NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_DP_INF_RAM_BE	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	90.0 % (27/30)	N.A.	N.A.	99.8 % (1638/1641)
G_PARITY_TRUE	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (13/13)	N.A.	N.A.	100.0 % (105/105)
G_PARITY_FALSE	100.0 % (4/4)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(0).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP.I_TXTB_RAM	100.0 % (19/19)	100.0 % (12/12)	100.0 % (516/516)	100.0 % (15/15)	N.A.	N.A.	100.0 % (562/562)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208: txtb_port_b_data_out <= txtb_port_b_data_out_i;
Count: 143367
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 6708
Threshold: 1

Signal assignment statement on line 277:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 323
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 6385
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 55820806
Threshold: 1

Signal assignment statement on line 283:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 55753468
Threshold: 1

Signal assignment statement on line 285:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 67338
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 432465
Threshold: 1

Signal assignment statement on line 287:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 426668
Threshold: 1

Signal assignment statement on line 289:

289: mr_tst_control_twrstb;
Count: 5797
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 2207854
Threshold: 1

Signal assignment statement on line 291:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 2164750
Threshold: 1

Signal assignment statement on line 293:

293: mr_tst_wdata_tst_wdata;
Count: 43104
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 360318
Threshold: 1

Signal assignment statement on line 296:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 355072
Threshold: 1

Signal assignment statement on line 298:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 5246
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 145614
Threshold: 1

Signal assignment statement on line 300:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 2795
Threshold: 1

Signal assignment statement on line 302:

302: (others => '0');
Count: 142819
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	323	1
Bin	False	6385	1

	Evaluated to	Count	Threshold
Bin	True	55753468	1
Bin	False	67338	1

	Evaluated to	Count	Threshold
Bin	True	426668	1
Bin	False	5797	1

	Evaluated to	Count	Threshold
Bin	True	2164750	1
Bin	False	43104	1

	Evaluated to	Count	Threshold
Bin	True	355072	1
Bin	False	5246	1

	Evaluated to	Count	Threshold
Bin	True	2795	1
Bin	False	142819	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	586	1
Bin	(31)	1	0	2187	1
Bin	(30)	0	1	587	1
Bin	(30)	1	0	2188	1
Bin	(29)	0	1	583	1
Bin	(29)	1	0	2184	1
Bin	(28)	0	1	671	1
Bin	(28)	1	0	2272	1
Bin	(27)	0	1	643	1
Bin	(27)	1	0	2244	1
Bin	(26)	0	1	642	1
Bin	(26)	1	0	2243	1
Bin	(25)	0	1	656	1
Bin	(25)	1	0	2257	1
Bin	(24)	0	1	650	1
Bin	(24)	1	0	2251	1
Bin	(23)	0	1	676	1
Bin	(23)	1	0	2277	1
Bin	(22)	0	1	660	1
Bin	(22)	1	0	2261	1
Bin	(21)	0	1	662	1
Bin	(21)	1	0	2263	1
Bin	(20)	0	1	654	1
Bin	(20)	1	0	2255	1
Bin	(19)	0	1	645	1
Bin	(19)	1	0	2246	1
Bin	(18)	0	1	666	1
Bin	(18)	1	0	2267	1
Bin	(17)	0	1	648	1
Bin	(17)	1	0	2249	1
Bin	(16)	0	1	610	1
Bin	(16)	1	0	2211	1
Bin	(15)	0	1	631	1
Bin	(15)	1	0	2232	1
Bin	(14)	0	1	626	1
Bin	(14)	1	0	2227	1
Bin	(13)	0	1	605	1
Bin	(13)	1	0	2206	1
Bin	(12)	0	1	629	1
Bin	(12)	1	0	2230	1
Bin	(11)	0	1	609	1
Bin	(11)	1	0	2210	1
Bin	(10)	0	1	618	1
Bin	(10)	1	0	2219	1
Bin	(9)	0	1	629	1
Bin	(9)	1	0	2230	1
Bin	(8)	0	1	616	1
Bin	(8)	1	0	2217	1
Bin	(7)	0	1	647	1
Bin	(7)	1	0	2248	1
Bin	(6)	0	1	644	1
Bin	(6)	1	0	2245	1
Bin	(5)	0	1	637	1
Bin	(5)	1	0	2238	1
Bin	(4)	0	1	616	1
Bin	(4)	1	0	2217	1
Bin	(3)	0	1	642	1
Bin	(3)	1	0	2243	1
Bin	(2)	0	1	634	1
Bin	(2)	1	0	2235	1
Bin	(1)	0	1	650	1
Bin	(1)	1	0	2251	1
Bin	(0)	0	1	621	1
Bin	(0)	1	0	2222	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8555	1
Bin	(31)	1	0	10106	1
Bin	(30)	0	1	8640	1
Bin	(30)	1	0	10190	1
Bin	(29)	0	1	8500	1
Bin	(29)	1	0	10051	1
Bin	(28)	0	1	22118	1
Bin	(28)	1	0	23588	1
Bin	(27)	0	1	17855	1
Bin	(27)	1	0	19312	1
Bin	(26)	0	1	22616	1
Bin	(26)	1	0	24093	1
Bin	(25)	0	1	18683	1
Bin	(25)	1	0	20151	1
Bin	(24)	0	1	22987	1
Bin	(24)	1	0	24455	1
Bin	(23)	0	1	19961	1
Bin	(23)	1	0	21424	1
Bin	(22)	0	1	22219	1
Bin	(22)	1	0	23678	1
Bin	(21)	0	1	20540	1
Bin	(21)	1	0	21992	1
Bin	(20)	0	1	21997	1
Bin	(20)	1	0	23466	1
Bin	(19)	0	1	20213	1
Bin	(19)	1	0	21644	1
Bin	(18)	0	1	23145	1
Bin	(18)	1	0	24595	1
Bin	(17)	0	1	13812	1
Bin	(17)	1	0	15316	1
Bin	(16)	0	1	13978	1
Bin	(16)	1	0	15483	1
Bin	(15)	0	1	13781	1
Bin	(15)	1	0	15293	1
Bin	(14)	0	1	13704	1
Bin	(14)	1	0	15206	1
Bin	(13)	0	1	13584	1
Bin	(13)	1	0	15097	1
Bin	(12)	0	1	13460	1
Bin	(12)	1	0	14966	1
Bin	(11)	0	1	14036	1
Bin	(11)	1	0	15546	1
Bin	(10)	0	1	15251	1
Bin	(10)	1	0	16708	1
Bin	(9)	0	1	25386	1
Bin	(9)	1	0	26719	1
Bin	(8)	0	1	14561	1
Bin	(8)	1	0	16067	1
Bin	(7)	0	1	34598	1
Bin	(7)	1	0	35793	1
Bin	(6)	0	1	24876	1
Bin	(6)	1	0	26166	1
Bin	(5)	0	1	19434	1
Bin	(5)	1	0	20895	1
Bin	(4)	0	1	15976	1
Bin	(4)	1	0	17472	1
Bin	(3)	0	1	26324	1
Bin	(3)	1	0	27687	1
Bin	(2)	0	1	28069	1
Bin	(2)	1	0	29388	1
Bin	(1)	0	1	26825	1
Bin	(1)	1	0	28189	1
Bin	(0)	0	1	35216	1
Bin	(0)	1	0	36410	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1826	1
Bin	1	0	3427	1

Signal:

TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	327782	1
Bin	(4)	1	0	27504978	1
Bin	(3)	0	1	579149	1
Bin	(3)	1	0	27253561	1
Bin	(2)	0	1	439626	1
Bin	(2)	1	0	27393606	1
Bin	(1)	0	1	27068140	1
Bin	(1)	1	0	766054	1
Bin	(0)	0	1	17683146	1
Bin	(0)	1	0	10152934	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	164928	1
Bin	1	0	166695	1

Signal:

TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	61070	1
Bin	(31)	1	0	1017447	1
Bin	(30)	0	1	64716	1
Bin	(30)	1	0	1013805	1
Bin	(29)	0	1	62919	1
Bin	(29)	1	0	1015622	1
Bin	(28)	0	1	89050	1
Bin	(28)	1	0	989515	1
Bin	(27)	0	1	81877	1
Bin	(27)	1	0	996672	1
Bin	(26)	0	1	75981	1
Bin	(26)	1	0	1002560	1
Bin	(25)	0	1	85014	1
Bin	(25)	1	0	993537	1
Bin	(24)	0	1	78816	1
Bin	(24)	1	0	999725	1
Bin	(23)	0	1	70152	1
Bin	(23)	1	0	1008421	1
Bin	(22)	0	1	105955	1
Bin	(22)	1	0	972598	1
Bin	(21)	0	1	74942	1
Bin	(21)	1	0	1003607	1
Bin	(20)	0	1	81292	1
Bin	(20)	1	0	997279	1
Bin	(19)	0	1	110049	1
Bin	(19)	1	0	968504	1
Bin	(18)	0	1	127716	1
Bin	(18)	1	0	950879	1
Bin	(17)	0	1	114337	1
Bin	(17)	1	0	964318	1
Bin	(16)	0	1	186755	1
Bin	(16)	1	0	891820	1
Bin	(15)	0	1	73513	1
Bin	(15)	1	0	1005046	1
Bin	(14)	0	1	85559	1
Bin	(14)	1	0	992996	1
Bin	(13)	0	1	77431	1
Bin	(13)	1	0	1001096	1
Bin	(12)	0	1	78080	1
Bin	(12)	1	0	1000467	1
Bin	(11)	0	1	100747	1
Bin	(11)	1	0	977812	1
Bin	(10)	0	1	117807	1
Bin	(10)	1	0	960730	1
Bin	(9)	0	1	169349	1
Bin	(9)	1	0	909216	1
Bin	(8)	0	1	151434	1
Bin	(8)	1	0	927117	1
Bin	(7)	0	1	126984	1
Bin	(7)	1	0	951617	1
Bin	(6)	0	1	113147	1
Bin	(6)	1	0	965452	1
Bin	(5)	0	1	106338	1
Bin	(5)	1	0	972253	1
Bin	(4)	0	1	161139	1
Bin	(4)	1	0	917416	1
Bin	(3)	0	1	132396	1
Bin	(3)	1	0	946159	1
Bin	(2)	0	1	158281	1
Bin	(2)	1	0	920320	1
Bin	(1)	0	1	226771	1
Bin	(1)	1	0	851845	1
Bin	(0)	0	1	190734	1
Bin	(0)	1	0	887958	1

Signal:

TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	27650	1
Bin	(4)	1	0	29251	1
Bin	(3)	0	1	4170	1
Bin	(3)	1	0	5771	1
Bin	(2)	0	1	47581	1
Bin	(2)	1	0	49182	1
Bin	(1)	0	1	39336	1
Bin	(1)	1	0	39339	1
Bin	(0)	0	1	105363	1
Bin	(0)	1	0	106961	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	8555	1
Bin	(31)	1	0	10106	1
Bin	(30)	0	1	8640	1
Bin	(30)	1	0	10190	1
Bin	(29)	0	1	8500	1
Bin	(29)	1	0	10051	1
Bin	(28)	0	1	22118	1
Bin	(28)	1	0	23588	1
Bin	(27)	0	1	17855	1
Bin	(27)	1	0	19312	1
Bin	(26)	0	1	22616	1
Bin	(26)	1	0	24093	1
Bin	(25)	0	1	18683	1
Bin	(25)	1	0	20151	1
Bin	(24)	0	1	22987	1
Bin	(24)	1	0	24455	1
Bin	(23)	0	1	19961	1
Bin	(23)	1	0	21424	1
Bin	(22)	0	1	22219	1
Bin	(22)	1	0	23678	1
Bin	(21)	0	1	20540	1
Bin	(21)	1	0	21992	1
Bin	(20)	0	1	21997	1
Bin	(20)	1	0	23466	1
Bin	(19)	0	1	20213	1
Bin	(19)	1	0	21644	1
Bin	(18)	0	1	23145	1
Bin	(18)	1	0	24595	1
Bin	(17)	0	1	13812	1
Bin	(17)	1	0	15316	1
Bin	(16)	0	1	13978	1
Bin	(16)	1	0	15483	1
Bin	(15)	0	1	13781	1
Bin	(15)	1	0	15293	1
Bin	(14)	0	1	13704	1
Bin	(14)	1	0	15206	1
Bin	(13)	0	1	13584	1
Bin	(13)	1	0	15097	1
Bin	(12)	0	1	13460	1
Bin	(12)	1	0	14966	1
Bin	(11)	0	1	14036	1
Bin	(11)	1	0	15546	1
Bin	(10)	0	1	15251	1
Bin	(10)	1	0	16708	1
Bin	(9)	0	1	25386	1
Bin	(9)	1	0	26719	1
Bin	(8)	0	1	14561	1
Bin	(8)	1	0	16067	1
Bin	(7)	0	1	34598	1
Bin	(7)	1	0	35793	1
Bin	(6)	0	1	24876	1
Bin	(6)	1	0	26166	1
Bin	(5)	0	1	19434	1
Bin	(5)	1	0	20895	1
Bin	(4)	0	1	15976	1
Bin	(4)	1	0	17472	1
Bin	(3)	0	1	26324	1
Bin	(3)	1	0	27687	1
Bin	(2)	0	1	28069	1
Bin	(2)	1	0	29388	1
Bin	(1)	0	1	26825	1
Bin	(1)	1	0	28189	1
Bin	(0)	0	1	35216	1
Bin	(0)	1	0	36410	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	323	1
Bin	1	0	1924	1

Signal:

PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	174	1
Bin	(20)	1	0	9020	1
Bin	(19)	0	1	10	1
Bin	(19)	1	0	9184	1
Bin	(18)	0	1	20	1
Bin	(18)	1	0	9174	1
Bin	(17)	0	1	200	1
Bin	(17)	1	0	8994	1
Bin	(16)	0	1	205	1
Bin	(16)	1	0	8989	1
Bin	(15)	0	1	263	1
Bin	(15)	1	0	8931	1
Bin	(14)	0	1	225	1
Bin	(14)	1	0	8969	1
Bin	(13)	0	1	194	1
Bin	(13)	1	0	9000	1
Bin	(12)	0	1	219	1
Bin	(12)	1	0	8975	1
Bin	(11)	0	1	444	1
Bin	(11)	1	0	8750	1
Bin	(10)	0	1	382	1
Bin	(10)	1	0	8812	1
Bin	(9)	0	1	524	1
Bin	(9)	1	0	8670	1
Bin	(8)	0	1	408	1
Bin	(8)	1	0	8786	1
Bin	(7)	0	1	565	1
Bin	(7)	1	0	8629	1
Bin	(6)	0	1	725	1
Bin	(6)	1	0	8469	1
Bin	(5)	0	1	1264	1
Bin	(5)	1	0	7930	1
Bin	(4)	0	1	2435	1
Bin	(4)	1	0	6759	1
Bin	(3)	0	1	4422	1
Bin	(3)	1	0	4772	1
Bin	(2)	0	1	5450	1
Bin	(2)	1	0	3744	1
Bin	(1)	0	1	3478	1
Bin	(1)	1	0	5716	1
Bin	(0)	0	1	3638	1
Bin	(0)	1	0	5556	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	13737	1
Bin	1	0	14193	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	17842	1
Bin	1	0	19443	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.G_TXT_BUF_COMP(0).G_TXT_BUF_EVEN.I_TXTB_EVEN_TOP.I_TXTB_RAM

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/txt_buffer/txtb_even_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

If statement on lines 277 to 280:

Signal assignment statement on line 277:

Signal assignment statement on line 280:

If statement on lines 283 to 285:

Signal assignment statement on line 283:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 287:

Signal assignment statement on line 289:

If statement on lines 291 to 293:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 296 to 298:

Signal assignment statement on line 296:

Signal assignment statement on line 298:

If statement on lines 300 to 302:

Signal assignment statement on line 300:

Signal assignment statement on line 302:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

"if" / "when" / "else" condition on line 283:

"if" / "when" / "else" condition on line 287:

"if" / "when" / "else" condition on line 291:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 300:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

"and" expression on lines 277 to 278:

Covered expressions:

"and" expression on lines 277 to 278:

"=" expression on line 277:

"=" expression on line 283:

"=" expression on line 287:

"=" expression on line 291:

"=" expression on line 296:

"=" expression on line 300:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: