NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
I_TX_SHIFT_REG	100.0 % (7/7)	100.0 % (8/8)	100.0 % (202/202)	100.0 % (6/6)	N.A.	N.A.	100.0 % (223/223)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_TX_SHIFT_REG	100.0 % (50/50)	100.0 % (44/44)	100.0 % (642/642)	100.0 % (80/80)	N.A.	N.A.	100.0 % (816/816)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 237 to 239:

237:    tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1') 
238:                    else 
239:                '0';

Count: 22982059
Threshold: 1

Signal assignment statement on line 237:

237: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')
Count: 2670025
Threshold: 1

Signal assignment statement on line 239:

239: '0';
Count: 20312034
Threshold: 1

If statement on lines 242 to 249:

242:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
243:                             tx_load_ext_id = '1' or 
...
248:                       else 
249:                   '0';

Count: 890086
Threshold: 1

Signal assignment statement on line 242:

242: tx_sr_pload <= '1' when (tx_load_base_id = '1' or
Count: 469835
Threshold: 1

Signal assignment statement on line 249:

249: '0';
Count: 420251
Threshold: 1

If statement on lines 252 to 254:

252:    tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else 
253:                crc_17 & "0000" when (crc_src = C_CRC17_SRC) else 
254:                        crc_21;

Count: 8830702
Threshold: 1

Signal assignment statement on line 252:

252: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else
Count: 1660835
Threshold: 1

Signal assignment statement on line 253:

253: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else
Count: 1082655
Threshold: 1

Signal assignment statement on line 254:

254: crc_21;
Count: 6087212
Threshold: 1

Sequential statement on lines 257 to 265:

257:    with bst_ctr select bst_ctr_grey <= 
258:        "001" when "001", 
...
264:        "100" when "111", 
265:        "000" when others;

Count: 298951
Threshold: 1

Signal assignment statement on line 258:

258: "001" when "001",
Count: 47742
Threshold: 1

Signal assignment statement on line 259:

259: "011" when "010",
Count: 43430
Threshold: 1

Signal assignment statement on line 260:

260: "010" when "011",
Count: 37917
Threshold: 1

Signal assignment statement on line 261:

261: "110" when "100",
Count: 33793
Threshold: 1

Signal assignment statement on line 262:

262: "111" when "101",
Count: 30293
Threshold: 1

Signal assignment statement on line 263:

263: "101" when "110",
Count: 28316
Threshold: 1

Signal assignment statement on line 264:

264: "100" when "111",
Count: 26519
Threshold: 1

Signal assignment statement on line 265:

265: "000" when others;
Count: 50941
Threshold: 1

Signal assignment statement on line 267:

267: bst_parity <= bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2);
Count: 298951
Threshold: 1

Signal assignment statement on line 269:

269: stuff_count <= bst_ctr_grey & bst_parity;
Count: 585493
Threshold: 1

Signal assignment statement on line 272:

272: tx_base_id <= tran_identifier(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
Count: 17650
Threshold: 1

Signal assignment statement on line 273:

273: tx_ext_id <= tran_identifier(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
Count: 9945
Threshold: 1

Signal assignment statement on lines 275 to 276:

275:    tran_word_swapped <= tran_word(7 downto 0)   & tran_word(15 downto 8) & 
276:                         tran_word(23 downto 16) & tran_word(31 downto 24);

Count: 161387
Threshold: 1

Signal assignment statement on line 283:

283: flip_mask <= (others => '0');
Count: 8744
Threshold: 1

If statement on lines 284 to 286:

284:        if (mr_mode_tstm = '1') then 
285:            flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1'; 
286:        end if;

Count: 8744
Threshold: 1

Signal assignment statement on line 285:

285: flip_mask(20 - to_integer(unsigned(tran_frame_test.tprm))) <= '1';
Count: 2815
Threshold: 1

If statement on lines 290 to 292:

290:    tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1') 
291:                                             else 
292:                                      tx_crc;

Count: 6839860
Threshold: 1

Signal assignment statement on line 290:

290: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')
Count: 64598
Threshold: 1

Signal assignment statement on line 292:

292: tx_crc;
Count: 6775262
Threshold: 1

If statement on lines 295 to 297:

295:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1') 
296:                                                                     else 
297:                                                         stuff_count;

Count: 592065
Threshold: 1

Signal assignment statement on line 295:

295:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

Count: 1969
Threshold: 1

Signal assignment statement on line 297:

297:                                                         stuff_count;

Count: 590096
Threshold: 1

If statement on lines 300 to 303:

300:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
301:                                                               mr_mode_tstm = '1') 
302:                                                         else 
303:                                                tran_dlc;

Count: 21425
Threshold: 1

Signal assignment statement on line 300:

300: tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and
Count: 220
Threshold: 1

Signal assignment statement on line 303:

303: tran_dlc;
Count: 21205
Threshold: 1

If statement on lines 313 to 320:

313:    tx_sr_pload_val <= 
314:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else 
...
319:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else 
320:                                        (others => '0');

Count: 8311315
Threshold: 1

Signal assignment statement on line 314:

314:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

Count: 51084
Threshold: 1

Signal assignment statement on line 315:

315:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

Count: 42334
Threshold: 1

Signal assignment statement on line 316:

316: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else
Count: 122262
Threshold: 1

Signal assignment statement on line 317:

317:                                       tran_word_swapped when (tx_load_data_word = '1') else

Count: 157121
Threshold: 1

Signal assignment statement on line 318:

318: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else
Count: 39904
Threshold: 1

Signal assignment statement on line 319:

319:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

Count: 57143
Threshold: 1

Signal assignment statement on line 320:

320: (others => '0');
Count: 7841467
Threshold: 1

If statement on lines 345 to 349:

345:    tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else 
346:                   RECESSIVE when (err_frm_req = '1') else 
347:                   DOMINANT when (tx_dominant = '1') else 
348:                   tx_sr_output when (tx_shift_ena = '1') else 
349:                   RECESSIVE;

Count: 1435576
Threshold: 1

Signal assignment statement on line 345:

345: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else
Count: 30645
Threshold: 1

Signal assignment statement on line 346:

346: RECESSIVE when (err_frm_req = '1') else
Count: 13325
Threshold: 1

Signal assignment statement on line 347:

347: DOMINANT when (tx_dominant = '1') else
Count: 125123
Threshold: 1

Signal assignment statement on line 348:

348: tx_sr_output when (tx_shift_ena = '1') else
Count: 1071795
Threshold: 1

Signal assignment statement on line 349:

349: RECESSIVE;
Count: 194688
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 237:

237: tx_sr_ce <= '1' when (tx_shift_ena = '1' and tx_trigger = '1')

	Evaluated to	Count	Threshold
Bin	True	2670025	1
Bin	False	20312034	1

"if" / "when" / "else" condition on lines 242 to 247:

242:    tx_sr_pload <= '1' when (tx_load_base_id = '1' or 
243:                             tx_load_ext_id = '1' or 
244:                             tx_load_dlc = '1' or 
245:                             tx_load_data_word = '1' or 
246:                             tx_load_stuff_count = '1' or 
247:                             tx_load_crc = '1')

	Evaluated to	Count	Threshold
Bin	True	469835	1
Bin	False	420251	1

"if" / "when" / "else" condition on line 252:

252: tx_crc <= crc_15 & "000000" when (crc_src = C_CRC15_SRC) else

	Evaluated to	Count	Threshold
Bin	True	1660835	1
Bin	False	7169867	1

"if" / "when" / "else" condition on line 253:

253: crc_17 & "0000" when (crc_src = C_CRC17_SRC) else

	Evaluated to	Count	Threshold
Bin	True	1082655	1
Bin	False	6087212	1

"case" / "with" / "select" choice on line 258:

258: "001" when "001",

	Choice of	Count	Threshold
Bin	`"001"`	47742	1

"case" / "with" / "select" choice on line 259:

259: "011" when "010",

	Choice of	Count	Threshold
Bin	`"010"`	43430	1

"case" / "with" / "select" choice on line 260:

260: "010" when "011",

	Choice of	Count	Threshold
Bin	`"011"`	37917	1

"case" / "with" / "select" choice on line 261:

261: "110" when "100",

	Choice of	Count	Threshold
Bin	`"100"`	33793	1

"case" / "with" / "select" choice on line 262:

262: "111" when "101",

	Choice of	Count	Threshold
Bin	`"101"`	30293	1

"case" / "with" / "select" choice on line 263:

263: "101" when "110",

	Choice of	Count	Threshold
Bin	`"110"`	28316	1

"case" / "with" / "select" choice on line 264:

264: "100" when "111",

	Choice of	Count	Threshold
Bin	`"111"`	26519	1

"case" / "with" / "select" choice on line 265:

265: "000" when others;

	Choice of	Count	Threshold
Bin	`others`	50941	1

"if" / "when" / "else" condition on line 284:

284: if (mr_mode_tstm = '1') then

	Evaluated to	Count	Threshold
Bin	True	2815	1
Bin	False	5929	1

"if" / "when" / "else" condition on line 290:

290: tx_crc_flipped <= (tx_crc xor flip_mask) when (tran_frame_test.fcrc = '1')

	Evaluated to	Count	Threshold
Bin	True	64598	1
Bin	False	6775262	1

"if" / "when" / "else" condition on line 295:

295:    stuff_count_flipped <= (stuff_count xor flip_mask(20 downto 17)) when (tran_frame_test.fstc = '1')

	Evaluated to	Count	Threshold
Bin	True	1969	1
Bin	False	590096	1

"if" / "when" / "else" condition on lines 300 to 301:

300:    tran_dlc_swapped <= tran_frame_test.tprm(3 downto 0) when (tran_frame_test.sdlc = '1' and 
301:                                                               mr_mode_tstm = '1')

	Evaluated to	Count	Threshold
Bin	True	220	1
Bin	False	21205	1

"if" / "when" / "else" condition on line 314:

314:                    tx_base_id & "000000000000000000000" when (tx_load_base_id = '1') else

	Evaluated to	Count	Threshold
Bin	True	51084	1
Bin	False	8260231	1

"if" / "when" / "else" condition on line 315:

315:                            tx_ext_id & "00000000000000" when (tx_load_ext_id = '1') else

	Evaluated to	Count	Threshold
Bin	True	42334	1
Bin	False	8217897	1

"if" / "when" / "else" condition on line 316:

316: tran_dlc_swapped & "0000000000000000000000000000" when (tx_load_dlc = '1') else

	Evaluated to	Count	Threshold
Bin	True	122262	1
Bin	False	8095635	1

"if" / "when" / "else" condition on line 317:

317:                                       tran_word_swapped when (tx_load_data_word = '1') else

	Evaluated to	Count	Threshold
Bin	True	157121	1
Bin	False	7938514	1

"if" / "when" / "else" condition on line 318:

318: stuff_count_flipped & "0000000000000000000000000000" when (tx_load_stuff_count = '1') else

	Evaluated to	Count	Threshold
Bin	True	39904	1
Bin	False	7898610	1

"if" / "when" / "else" condition on line 319:

319:                          tx_crc_flipped & "00000000000" when (tx_load_crc = '1') else

	Evaluated to	Count	Threshold
Bin	True	57143	1
Bin	False	7841467	1

"if" / "when" / "else" condition on line 345:

345: tx_data_nbs <= DOMINANT when (err_frm_req = '1' and is_err_active = '1') else

	Evaluated to	Count	Threshold
Bin	True	30645	1
Bin	False	1404931	1

"if" / "when" / "else" condition on line 346:

346: RECESSIVE when (err_frm_req = '1') else

	Evaluated to	Count	Threshold
Bin	True	13325	1
Bin	False	1391606	1

"if" / "when" / "else" condition on line 347:

347: DOMINANT when (tx_dominant = '1') else

	Evaluated to	Count	Threshold
Bin	True	125123	1
Bin	False	1266483	1

"if" / "when" / "else" condition on line 348:

348: tx_sr_output when (tx_shift_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	1071795	1
Bin	False	194688	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TSTM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_BASE_ID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_EXT_ID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_DLC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_DATA_WORD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_STUFF_COUNT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_LOAD_CRC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_SHIFT_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_DOMINANT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CRC_SRC

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CRC_15

	Element	From	To	Threshold	Excluded due to
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CRC_17

	Element	From	To	Threshold	Excluded due to
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CRC_21

	Element	From	To	Threshold	Excluded due to
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

ERR_FRM_REQ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BST_CTR

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRAN_IDENTIFIER

	Element	From	To	Threshold	Excluded due to
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRAN_WORD

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TRAN_DLC

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

TX_DATA_NBS

	From	To	Count	Threshold
Bin	0	1	648446	1
Bin	1	0	646847	1

Port:

TRAN_FRAME_TEST

	Element	From	To	Count	Threshold
Bin	FSTC	0	1	270	1
Bin	FSTC	1	0	1871	1
Bin	FCRC	0	1	100	1
Bin	FCRC	1	0	1701	1
Bin	SDLC	0	1	270	1
Bin	SDLC	1	0	1871	1
Bin	TPRM(4)	0	1	58	1
Bin	TPRM(4)	1	0	3273	1
Bin	TPRM(3)	0	1	189	1
Bin	TPRM(3)	1	0	1838	1
Bin	TPRM(2)	0	1	209	1
Bin	TPRM(2)	1	0	1858	1
Bin	TPRM(1)	0	1	431	1
Bin	TPRM(1)	1	0	2080	1
Bin	TPRM(0)	0	1	653	1
Bin	TPRM(0)	1	0	2302	1

Signal:

TX_SR_OUTPUT

	From	To	Count	Threshold
Bin	0	1	524626	1
Bin	1	0	526226	1

Signal:

TX_SR_CE

	From	To	Count	Threshold
Bin	0	1	2670025	1
Bin	1	0	2671626	1

Signal:

TX_SR_PLOAD

	From	To	Count	Threshold
Bin	0	1	417049	1
Bin	1	0	418650	1

Signal:

TX_SR_PLOAD_VAL

	Element	From	To	Count	Threshold
Bin	(31)	0	1	104661	1
Bin	(31)	1	0	106262	1
Bin	(30)	0	1	105699	1
Bin	(30)	1	0	107300	1
Bin	(29)	0	1	112420	1
Bin	(29)	1	0	114021	1
Bin	(28)	0	1	118657	1
Bin	(28)	1	0	120258	1
Bin	(27)	0	1	82605	1
Bin	(27)	1	0	84206	1
Bin	(26)	0	1	84438	1
Bin	(26)	1	0	86039	1
Bin	(25)	0	1	82910	1
Bin	(25)	1	0	84511	1
Bin	(24)	0	1	86754	1
Bin	(24)	1	0	88355	1
Bin	(23)	0	1	83006	1
Bin	(23)	1	0	84607	1
Bin	(22)	0	1	84698	1
Bin	(22)	1	0	86299	1
Bin	(21)	0	1	86553	1
Bin	(21)	1	0	88154	1
Bin	(20)	0	1	60751	1
Bin	(20)	1	0	62352	1
Bin	(19)	0	1	59407	1
Bin	(19)	1	0	61008	1
Bin	(18)	0	1	64378	1
Bin	(18)	1	0	65979	1
Bin	(17)	0	1	59440	1
Bin	(17)	1	0	61041	1
Bin	(16)	0	1	48267	1
Bin	(16)	1	0	49868	1
Bin	(15)	0	1	44390	1
Bin	(15)	1	0	45991	1
Bin	(14)	0	1	36205	1
Bin	(14)	1	0	37806	1
Bin	(13)	0	1	26827	1
Bin	(13)	1	0	28428	1
Bin	(12)	0	1	28407	1
Bin	(12)	1	0	30008	1
Bin	(11)	0	1	25943	1
Bin	(11)	1	0	27544	1
Bin	(10)	0	1	26705	1
Bin	(10)	1	0	28306	1
Bin	(9)	0	1	24420	1
Bin	(9)	1	0	26021	1
Bin	(8)	0	1	25716	1
Bin	(8)	1	0	27317	1
Bin	(7)	0	1	23846	1
Bin	(7)	1	0	25447	1
Bin	(6)	0	1	25335	1
Bin	(6)	1	0	26936	1
Bin	(5)	0	1	22959	1
Bin	(5)	1	0	24560	1
Bin	(4)	0	1	25663	1
Bin	(4)	1	0	27264	1
Bin	(3)	0	1	23410	1
Bin	(3)	1	0	25011	1
Bin	(2)	0	1	25922	1
Bin	(2)	1	0	27523	1
Bin	(1)	0	1	24007	1
Bin	(1)	1	0	25608	1
Bin	(0)	0	1	26459	1
Bin	(0)	1	0	28060	1

Signal:

TX_BASE_ID

	Element	From	To	Count	Threshold
Bin	(10)	0	1	3839	1
Bin	(10)	1	0	5438	1
Bin	(9)	0	1	3881	1
Bin	(9)	1	0	5482	1
Bin	(8)	0	1	3779	1
Bin	(8)	1	0	5379	1
Bin	(7)	0	1	4116	1
Bin	(7)	1	0	5715	1
Bin	(6)	0	1	3866	1
Bin	(6)	1	0	5466	1
Bin	(5)	0	1	4114	1
Bin	(5)	1	0	5714	1
Bin	(4)	0	1	3807	1
Bin	(4)	1	0	5406	1
Bin	(3)	0	1	4112	1
Bin	(3)	1	0	5710	1
Bin	(2)	0	1	3866	1
Bin	(2)	1	0	5466	1
Bin	(1)	0	1	4130	1
Bin	(1)	1	0	5729	1
Bin	(0)	0	1	3817	1
Bin	(0)	1	0	5415	1

Signal:

TX_EXT_ID

	Element	From	To	Count	Threshold
Bin	(17)	0	1	1749	1
Bin	(17)	1	0	3350	1
Bin	(16)	0	1	1735	1
Bin	(16)	1	0	3336	1
Bin	(15)	0	1	1750	1
Bin	(15)	1	0	3351	1
Bin	(14)	0	1	1697	1
Bin	(14)	1	0	3298	1
Bin	(13)	0	1	1711	1
Bin	(13)	1	0	3312	1
Bin	(12)	0	1	1662	1
Bin	(12)	1	0	3263	1
Bin	(11)	0	1	1733	1
Bin	(11)	1	0	3334	1
Bin	(10)	0	1	1658	1
Bin	(10)	1	0	3259	1
Bin	(9)	0	1	1721	1
Bin	(9)	1	0	3322	1
Bin	(8)	0	1	1700	1
Bin	(8)	1	0	3301	1
Bin	(7)	0	1	1770	1
Bin	(7)	1	0	3371	1
Bin	(6)	0	1	1740	1
Bin	(6)	1	0	3341	1
Bin	(5)	0	1	1750	1
Bin	(5)	1	0	3351	1
Bin	(4)	0	1	1735	1
Bin	(4)	1	0	3336	1
Bin	(3)	0	1	1753	1
Bin	(3)	1	0	3354	1
Bin	(2)	0	1	1727	1
Bin	(2)	1	0	3328	1
Bin	(1)	0	1	1749	1
Bin	(1)	1	0	3350	1
Bin	(0)	0	1	1722	1
Bin	(0)	1	0	3323	1

Signal:

TX_CRC

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1775185	1
Bin	(20)	1	0	1776782	1
Bin	(19)	0	1	1689557	1
Bin	(19)	1	0	1691155	1
Bin	(18)	0	1	1699130	1
Bin	(18)	1	0	1700731	1
Bin	(17)	0	1	1714191	1
Bin	(17)	1	0	1715787	1
Bin	(16)	0	1	1712594	1
Bin	(16)	1	0	1714193	1
Bin	(15)	0	1	1713165	1
Bin	(15)	1	0	1714763	1
Bin	(14)	0	1	1719804	1
Bin	(14)	1	0	1721402	1
Bin	(13)	0	1	1730203	1
Bin	(13)	1	0	1731803	1
Bin	(12)	0	1	1652384	1
Bin	(12)	1	0	1653983	1
Bin	(11)	0	1	1675948	1
Bin	(11)	1	0	1677545	1
Bin	(10)	0	1	1725039	1
Bin	(10)	1	0	1726639	1
Bin	(9)	0	1	1710076	1
Bin	(9)	1	0	1711675	1
Bin	(8)	0	1	1712212	1
Bin	(8)	1	0	1713808	1
Bin	(7)	0	1	1736479	1
Bin	(7)	1	0	1738079	1
Bin	(6)	0	1	1695664	1
Bin	(6)	1	0	1697264	1
Bin	(5)	0	1	1415248	1
Bin	(5)	1	0	1416846	1
Bin	(4)	0	1	1426177	1
Bin	(4)	1	0	1427775	1
Bin	(3)	0	1	1228835	1
Bin	(3)	1	0	1230436	1
Bin	(2)	0	1	1229856	1
Bin	(2)	1	0	1231457	1
Bin	(1)	0	1	1233425	1
Bin	(1)	1	0	1235026	1
Bin	(0)	0	1	1238273	1
Bin	(0)	1	0	1239874	1

Signal:

TX_CRC_FLIPPED

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1775235	1
Bin	(20)	1	0	1776832	1
Bin	(19)	0	1	1689607	1
Bin	(19)	1	0	1691205	1
Bin	(18)	0	1	1699180	1
Bin	(18)	1	0	1700781	1
Bin	(17)	0	1	1714241	1
Bin	(17)	1	0	1715837	1
Bin	(16)	0	1	1712644	1
Bin	(16)	1	0	1714243	1
Bin	(15)	0	1	1713215	1
Bin	(15)	1	0	1714813	1
Bin	(14)	0	1	1719854	1
Bin	(14)	1	0	1721452	1
Bin	(13)	0	1	1730253	1
Bin	(13)	1	0	1731853	1
Bin	(12)	0	1	1652434	1
Bin	(12)	1	0	1654033	1
Bin	(11)	0	1	1675998	1
Bin	(11)	1	0	1677595	1
Bin	(10)	0	1	1725089	1
Bin	(10)	1	0	1726689	1
Bin	(9)	0	1	1710126	1
Bin	(9)	1	0	1711725	1
Bin	(8)	0	1	1712262	1
Bin	(8)	1	0	1713858	1
Bin	(7)	0	1	1736529	1
Bin	(7)	1	0	1738129	1
Bin	(6)	0	1	1695714	1
Bin	(6)	1	0	1697314	1
Bin	(5)	0	1	1415298	1
Bin	(5)	1	0	1416896	1
Bin	(4)	0	1	1426227	1
Bin	(4)	1	0	1427825	1
Bin	(3)	0	1	1228837	1
Bin	(3)	1	0	1230438	1
Bin	(2)	0	1	1229858	1
Bin	(2)	1	0	1231459	1
Bin	(1)	0	1	1233427	1
Bin	(1)	1	0	1235028	1
Bin	(0)	0	1	1238275	1
Bin	(0)	1	0	1239876	1

Signal:

BST_CTR_GREY

	Element	From	To	Count	Threshold
Bin	(2)	0	1	118921	1
Bin	(2)	1	0	178429	1
Bin	(1)	0	1	145433	1
Bin	(1)	1	0	151917	1
Bin	(0)	0	1	149781	1
Bin	(0)	1	0	147569	1

Signal:

BST_PARITY

	From	To	Count	Threshold
Bin	0	1	142471	1
Bin	1	0	144071	1

Signal:

STUFF_COUNT

	Element	From	To	Count	Threshold
Bin	(3)	0	1	33793	1
Bin	(3)	1	0	35393	1
Bin	(2)	0	1	43430	1
Bin	(2)	1	0	45029	1
Bin	(1)	0	1	78035	1
Bin	(1)	1	0	79634	1
Bin	(0)	0	1	142471	1
Bin	(0)	1	0	144071	1

Signal:

FLIP_MASK

	Element	From	To	Count	Threshold
Bin	(20)	0	1	1464	1
Bin	(20)	1	0	3822	1
Bin	(19)	0	1	146	1
Bin	(19)	1	0	5140	1
Bin	(18)	0	1	124	1
Bin	(18)	1	0	5162	1
Bin	(17)	0	1	106	1
Bin	(17)	1	0	5180	1
Bin	(16)	0	1	65	1
Bin	(16)	1	0	5221	1
Bin	(15)	0	1	59	1
Bin	(15)	1	0	5227	1
Bin	(14)	0	1	64	1
Bin	(14)	1	0	5222	1
Bin	(13)	0	1	62	1
Bin	(13)	1	0	5224	1
Bin	(12)	0	1	71	1
Bin	(12)	1	0	5215	1
Bin	(11)	0	1	73	1
Bin	(11)	1	0	5213	1
Bin	(10)	0	1	69	1
Bin	(10)	1	0	5217	1
Bin	(9)	0	1	62	1
Bin	(9)	1	0	5224	1
Bin	(8)	0	1	58	1
Bin	(8)	1	0	5228	1
Bin	(7)	0	1	58	1
Bin	(7)	1	0	5228	1
Bin	(6)	0	1	62	1
Bin	(6)	1	0	5224	1
Bin	(5)	0	1	58	1
Bin	(5)	1	0	5228	1
Bin	(4)	0	1	50	1
Bin	(4)	1	0	5236	1
Bin	(3)	0	1	2	1
Bin	(3)	1	0	5284	1
Bin	(2)	0	1	2	1
Bin	(2)	1	0	5284	1
Bin	(1)	0	1	2	1
Bin	(1)	1	0	5284	1
Bin	(0)	0	1	2	1
Bin	(0)	1	0	5284	1

Signal:

STUFF_COUNT_FLIPPED

	Element	From	To	Count	Threshold
Bin	(3)	0	1	34013	1
Bin	(3)	1	0	35613	1
Bin	(2)	0	1	43502	1
Bin	(2)	1	0	45101	1
Bin	(1)	0	1	78100	1
Bin	(1)	1	0	79699	1
Bin	(0)	0	1	142508	1
Bin	(0)	1	0	144108	1

Signal:

TRAN_DLC_SWAPPED

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1608	1
Bin	(3)	1	0	3208	1
Bin	(2)	0	1	2052	1
Bin	(2)	1	0	3652	1
Bin	(1)	0	1	2013	1
Bin	(1)	1	0	3614	1
Bin	(0)	0	1	3669	1
Bin	(0)	1	0	5270	1

Signal:

TRAN_WORD_SWAPPED

	Element	From	To	Count	Threshold
Bin	(31)	0	1	36273	1
Bin	(31)	1	0	37874	1
Bin	(30)	0	1	28429	1
Bin	(30)	1	0	30030	1
Bin	(29)	0	1	21116	1
Bin	(29)	1	0	22717	1
Bin	(28)	0	1	18302	1
Bin	(28)	1	0	19903	1
Bin	(27)	0	1	27203	1
Bin	(27)	1	0	28804	1
Bin	(26)	0	1	28957	1
Bin	(26)	1	0	30558	1
Bin	(25)	0	1	29125	1
Bin	(25)	1	0	30726	1
Bin	(24)	0	1	36252	1
Bin	(24)	1	0	37853	1
Bin	(23)	0	1	15609	1
Bin	(23)	1	0	17210	1
Bin	(22)	0	1	15444	1
Bin	(22)	1	0	17045	1
Bin	(21)	0	1	15185	1
Bin	(21)	1	0	16786	1
Bin	(20)	0	1	15097	1
Bin	(20)	1	0	16698	1
Bin	(19)	0	1	16120	1
Bin	(19)	1	0	17721	1
Bin	(18)	0	1	17647	1
Bin	(18)	1	0	19248	1
Bin	(17)	0	1	26763	1
Bin	(17)	1	0	28364	1
Bin	(16)	0	1	16193	1
Bin	(16)	1	0	17794	1
Bin	(15)	0	1	23084	1
Bin	(15)	1	0	24685	1
Bin	(14)	0	1	26541	1
Bin	(14)	1	0	28142	1
Bin	(13)	0	1	23341	1
Bin	(13)	1	0	24942	1
Bin	(12)	0	1	26369	1
Bin	(12)	1	0	27970	1
Bin	(11)	0	1	22949	1
Bin	(11)	1	0	24550	1
Bin	(10)	0	1	27560	1
Bin	(10)	1	0	29161	1
Bin	(9)	0	1	15363	1
Bin	(9)	1	0	16964	1
Bin	(8)	0	1	15654	1
Bin	(8)	1	0	17255	1
Bin	(7)	0	1	8701	1
Bin	(7)	1	0	10302	1
Bin	(6)	0	1	8651	1
Bin	(6)	1	0	10252	1
Bin	(5)	0	1	8418	1
Bin	(5)	1	0	10019	1
Bin	(4)	0	1	26185	1
Bin	(4)	1	0	27786	1
Bin	(3)	0	1	20423	1
Bin	(3)	1	0	22024	1
Bin	(2)	0	1	26634	1
Bin	(2)	1	0	28235	1
Bin	(1)	0	1	21726	1
Bin	(1)	1	0	23327	1
Bin	(0)	0	1	27533	1
Bin	(0)	1	0	29134	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 237:

 tx_shift_ena = '1' and tx_trigger = '1' 
 <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	8762013	1
Bin	True	False	2727417	1
Bin	True	True	2670025	1

"=" expression on line 237:

tx_shift_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	17584617	1
Bin	True	5397442	1

"=" expression on line 237:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11550021	1
Bin	True	11432038	1

"or" expression on lines 242 to 247:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1' or tx_load_stuff_count = '1' or tx_load_crc = '1' 
 <----------------------------------------------------------LHS----------------------------------------------------------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	420251	1
Bin	False	True	57143	1
Bin	True	False	412692	1

"or" expression on lines 242 to 246:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1' or tx_load_stuff_count = '1' 
 <--------------------------------------------LHS-------------------------------------------->    <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	477394	1
Bin	False	True	39904	1
Bin	True	False	372788	1

"or" expression on lines 242 to 245:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' or tx_load_data_word = '1' 
 <------------------------------LHS------------------------------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	517298	1
Bin	False	True	157121	1
Bin	True	False	215667	1

"or" expression on lines 242 to 244:

 tx_load_base_id = '1' or tx_load_ext_id = '1' or tx_load_dlc = '1' 
 <--------------------LHS-------------------->    <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	674419	1
Bin	False	True	122262	1
Bin	True	False	93405	1

"or" expression on lines 242 to 243:

 tx_load_base_id = '1' or tx_load_ext_id = '1' 
 <--------LHS-------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	796681	1
Bin	False	True	42334	1
Bin	True	False	51071	1

"=" expression on line 242:

tx_load_base_id = '1'

	Evaluated to	Count	Threshold
Bin	False	839015	1
Bin	True	51071	1

"=" expression on line 243:

tx_load_ext_id = '1'

	Evaluated to	Count	Threshold
Bin	False	847752	1
Bin	True	42334	1

"=" expression on line 244:

tx_load_dlc = '1'

	Evaluated to	Count	Threshold
Bin	False	767824	1
Bin	True	122262	1

"=" expression on line 245:

tx_load_data_word = '1'

	Evaluated to	Count	Threshold
Bin	False	732965	1
Bin	True	157121	1

"=" expression on line 246:

tx_load_stuff_count = '1'

	Evaluated to	Count	Threshold
Bin	False	850182	1
Bin	True	39904	1

"=" expression on line 247:

tx_load_crc = '1'

	Evaluated to	Count	Threshold
Bin	False	832943	1
Bin	True	57143	1

"xor" expression on line 267:

 bst_ctr_grey(0) xor bst_ctr_grey(1) xor bst_ctr_grey(2) 
 <---------------LHS--------------->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	92770	1
Bin	'0'	'1'	56812	1
Bin	'1'	'0'	85659	1
Bin	'1'	'1'	62109	1

"xor" expression on line 267:

 bst_ctr_grey(0) xor bst_ctr_grey(1) 
 <-----LHS----->     <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	75859	1
Bin	'0'	'1'	71710	1
Bin	'1'	'0'	76058	1
Bin	'1'	'1'	73723	1

"=" expression on line 284:

mr_mode_tstm = '1'

	Evaluated to	Count	Threshold
Bin	False	5929	1
Bin	True	2815	1

"=" expression on line 290:

tran_frame_test.fcrc = '1'

	Evaluated to	Count	Threshold
Bin	False	6775262	1
Bin	True	64598	1

"=" expression on line 295:

tran_frame_test.fstc = '1'

	Evaluated to	Count	Threshold
Bin	False	590096	1
Bin	True	1969	1

"and" expression on lines 300 to 301:

 tran_frame_test.sdlc = '1' and mr_mode_tstm = '1' 
 <----------LHS----------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	4366	1
Bin	True	False	50	1
Bin	True	True	220	1

"=" expression on line 300:

tran_frame_test.sdlc = '1'

	Evaluated to	Count	Threshold
Bin	False	21155	1
Bin	True	270	1

"=" expression on line 301:

mr_mode_tstm = '1'

	Evaluated to	Count	Threshold
Bin	False	16839	1
Bin	True	4586	1

"=" expression on line 314:

tx_load_base_id = '1'

	Evaluated to	Count	Threshold
Bin	False	8260231	1
Bin	True	51084	1

"=" expression on line 315:

tx_load_ext_id = '1'

	Evaluated to	Count	Threshold
Bin	False	8217897	1
Bin	True	42334	1

"=" expression on line 316:

tx_load_dlc = '1'

	Evaluated to	Count	Threshold
Bin	False	8095635	1
Bin	True	122262	1

"=" expression on line 317:

tx_load_data_word = '1'

	Evaluated to	Count	Threshold
Bin	False	7938514	1
Bin	True	157121	1

"=" expression on line 318:

tx_load_stuff_count = '1'

	Evaluated to	Count	Threshold
Bin	False	7898610	1
Bin	True	39904	1

"=" expression on line 319:

tx_load_crc = '1'

	Evaluated to	Count	Threshold
Bin	False	7841467	1
Bin	True	57143	1

"and" expression on line 345:

 err_frm_req = '1' and is_err_active = '1' 
 <------LHS------>     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	1232537	1
Bin	True	False	13325	1
Bin	True	True	30645	1

"=" expression on line 345:

err_frm_req = '1'

	Evaluated to	Count	Threshold
Bin	False	1391606	1
Bin	True	43970	1

"=" expression on line 345:

is_err_active = '1'

	Evaluated to	Count	Threshold
Bin	False	172394	1
Bin	True	1263182	1

"=" expression on line 346:

err_frm_req = '1'

	Evaluated to	Count	Threshold
Bin	False	1391606	1
Bin	True	13325	1

"=" expression on line 347:

tx_dominant = '1'

	Evaluated to	Count	Threshold
Bin	False	1266483	1
Bin	True	125123	1

"=" expression on line 348:

tx_shift_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	194688	1
Bin	True	1071795	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_TX_SHIFT_REG

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 237 to 239:

Signal assignment statement on line 237:

Signal assignment statement on line 239:

If statement on lines 242 to 249:

Signal assignment statement on line 242:

Signal assignment statement on line 249:

If statement on lines 252 to 254:

Signal assignment statement on line 252:

Signal assignment statement on line 253:

Signal assignment statement on line 254:

Sequential statement on lines 257 to 265:

Signal assignment statement on line 258:

Signal assignment statement on line 259:

Signal assignment statement on line 260:

Signal assignment statement on line 261:

Signal assignment statement on line 262:

Signal assignment statement on line 263:

Signal assignment statement on line 264:

Signal assignment statement on line 265:

Signal assignment statement on line 267:

Signal assignment statement on line 269:

Signal assignment statement on line 272:

Signal assignment statement on line 273:

Signal assignment statement on lines 275 to 276:

Signal assignment statement on line 283:

If statement on lines 284 to 286:

Signal assignment statement on line 285:

If statement on lines 290 to 292:

Signal assignment statement on line 290:

Signal assignment statement on line 292:

If statement on lines 295 to 297:

Signal assignment statement on line 295:

Signal assignment statement on line 297:

If statement on lines 300 to 303:

Signal assignment statement on line 300:

Signal assignment statement on line 303:

If statement on lines 313 to 320:

Signal assignment statement on line 314:

Signal assignment statement on line 315:

Signal assignment statement on line 316:

Signal assignment statement on line 317:

Signal assignment statement on line 318:

Signal assignment statement on line 319:

Signal assignment statement on line 320:

If statement on lines 345 to 349:

Signal assignment statement on line 345:

Signal assignment statement on line 346:

Signal assignment statement on line 347:

Signal assignment statement on line 348:

Signal assignment statement on line 349:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 237:

"if" / "when" / "else" condition on lines 242 to 247:

"if" / "when" / "else" condition on line 252:

"if" / "when" / "else" condition on line 253:

"case" / "with" / "select" choice on line 258:

"case" / "with" / "select" choice on line 259:

"case" / "with" / "select" choice on line 260:

"case" / "with" / "select" choice on line 261:

"case" / "with" / "select" choice on line 262:

"case" / "with" / "select" choice on line 263:

"case" / "with" / "select" choice on line 264:

"case" / "with" / "select" choice on line 265:

"if" / "when" / "else" condition on line 284:

"if" / "when" / "else" condition on line 290:

"if" / "when" / "else" condition on line 295:

"if" / "when" / "else" condition on lines 300 to 301:

"if" / "when" / "else" condition on line 314:

"if" / "when" / "else" condition on line 315:

"if" / "when" / "else" condition on line 316: