#----------------------------------------------------------- # Vivado v2025.2 (64-bit) # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 # SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 # Start of session at: Fri Apr 10 21:29:05 2026 # Process ID : 341854 # Current directory : /opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Vivado/ci_benchmark # Command line : vivado -mode tcl -source vivado_benchmark_small.tcl # Log file : /opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Vivado/ci_benchmark/vivado.log # Journal file : /opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Vivado/ci_benchmark/vivado.jou # Running On : fedora # Platform : unknown # Operating System : unknown # Processor Detail : AMD Ryzen Threadripper 9960X 24-Cores # CPU Frequency : 4510.894 MHz # CPU Physical cores : 24 # CPU Logical cores : 48 # Host memory : 134342 MB # Swap memory : 25568 MB # Total Virtual : 159910 MB # Available Virtual : 154841 MB #----------------------------------------------------------- source vivado_benchmark_small.tcl # source synth_core.tcl ## proc load_rtl {} { ## global PROJ_ROOT ## read_vhdl -library ctu_can_fd_rtl -verbose [glob $PROJ_ROOT/src/*/*/**.vhd] ## read_vhdl -library ctu_can_fd_rtl -verbose [glob $PROJ_ROOT/src/*/**.vhd] ## read_vhdl -library ctu_can_fd_rtl -verbose [glob $PROJ_ROOT/src/*.vhd] ## } ## proc form_generics {cfg_name} { ## global DESIGN_CONFIGS ## set CMD "" ## foreach CFG $DESIGN_CONFIGS { ## if {[dict get $CFG name] == $cfg_name} { ## dict for {PARAM VALUE} [dict get $CFG generics] { ## append CMD "-generic ${PARAM}=${VALUE} " ## } ## } ## } ## return "${CMD}" ## } ## proc run_synth {cfg_name} { ## global TOP ## global PART ## ## puts "Running synthesis of design configuration: ${cfg_name} ..." ## set GENERICS [form_generics $cfg_name] ## ## # First run only elaboration ## set CMD "synth_design -top ${TOP} -part ${PART} ${GENERICS} -rtl" ## eval $CMD ## ## # Needs to be configured post elaboration and prior to synthesis! ## config_timing_analysis -enable_preset_clear_arcs true ## set_property MAX_FANOUT 120 [get_cells *] ## ## # Now run full synthesis ## set CMD "synth_design -top ${TOP} -part ${PART} ${GENERICS}" ## eval $CMD ## ## # Do optimize to get also better results ## opt_design -resynth_seq_area ## } ## proc write_outputs {cfg_name} { ## global TOP ## ## exec rm -rf $cfg_name ## exec mkdir $cfg_name ## ## # Clock latency needed to do ideal clocks STA, needed for post-syn, as there is high ## # fanout from res_n, which ## set_clock_latency 2 [all_clocks] ## #udpate_timing ## ## report_timing_summary > $cfg_name/timing_summary.rpt ## report_utilization > $cfg_name/utilization.rpt ## report_utilization -hierarchical -hierarchical_percentages > $cfg_name/utilization_hierarchy.rpt ## ## write_vhdl -include_xilinx_libs -mode funcsim -verbose $cfg_name/$TOP.vhd ## write_verilog -include_xilinx_libs -mode funcsim $cfg_name/$TOP.v ## write_sdf -mode timesim -process_corner slow $cfg_name/$TOP\_slow.sdf ## write_sdf -mode timesim -process_corner fast $cfg_name/$TOP\_fast.sdf ## write_xdc $cfg_name/$TOP.xdc ## ## exec cp vivado.log $cfg_name ## } # source benchmark_configs.tcl ## set PART xc7k70tfbv676-1 ## set PROJECT_NAME CTU_CAN_FD_BENCHMARK ## set PROJ_ROOT ../../.. ## set TOP can_top_level ## set DESIGN_CONFIGS [list \ ## [ dict create \ ## name "small_design_config" \ ## generics \ ## [ dict create \ ## rx_buffer_size 32 \ ## txt_buffer_count 2 \ ## sup_filtA "1'b0" \ ## sup_filtB "1'b0" \ ## sup_filtC "1'b0" \ ## sup_range "1'b0" \ ## target_technology 1 \ ## sup_traffic_ctrs "1'b0" \ ## sup_test_registers "1'b0" \ ## sup_parity "1'b0" \ ## active_timestamp_bits 16 \ ## reset_buffer_rams "1'b0" \ ## ] ## ] \ ## [ dict create \ ## name "medium_design_config" \ ## generics \ ## [ dict create \ ## rx_buffer_size 128 \ ## txt_buffer_count 4 \ ## sup_filtA "1'b1" \ ## sup_filtB "1'b0" \ ## sup_filtC "1'b0" \ ## sup_range "1'b1" \ ## target_technology 1 \ ## sup_traffic_ctrs "1'b1" \ ## sup_test_registers "1'b1" \ ## sup_parity "1'b1" \ ## active_timestamp_bits 32 \ ## reset_buffer_rams "1'b0" \ ## ] ## ] \ ## [ dict create \ ## name "big_design_config" \ ## generics \ ## [ dict create \ ## rx_buffer_size 1024 \ ## txt_buffer_count 8 \ ## sup_filtA "1'b1" \ ## sup_filtB "1'b1" \ ## sup_filtC "1'b1" \ ## sup_range "1'b1" \ ## target_technology 1 \ ## sup_traffic_ctrs "1'b1" \ ## sup_test_registers "1'b1" \ ## sup_parity "1'b1" \ ## active_timestamp_bits 63 \ ## reset_buffer_rams "1'b0" \ ## ] ## ] \ ## ] # set_msg_config -id "Synth 8-6426" -new_severity "INFO" # load_rtl # read_xdc ../../Constraints/ctu_can_fd.sdc # global DESIGN_CONFIGS # set cfg [lindex $DESIGN_CONFIGS 0] # set cfg_name [dict get $cfg name] # run_synth $cfg_name Running synthesis of design configuration: small_design_config ... Command: synth_design -top can_top_level -part xc7k70tfbv676-1 -generic rx_buffer_size=32 -generic txt_buffer_count=2 -generic sup_filtA=1'b0 -generic sup_filtB=1'b0 -generic sup_filtC=1'b0 -generic sup_range=1'b0 -generic target_technology=1 -generic sup_traffic_ctrs=1'b0 -generic sup_test_registers=1'b0 -generic sup_parity=1'b0 -generic active_timestamp_bits=16 -generic reset_buffer_rams=1'b0 -rtl Starting synth_design INFO: [Device 21-403] Loading part xc7k70tfbv676-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 341872 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2403.074 ; gain = 480.875 ; free physical = 119544 ; free virtual = 146512 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'can_top_level' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd:207] Parameter rx_buffer_size bound to: 32 - type: integer Parameter txt_buffer_count bound to: 2 - type: integer Parameter sup_filtA bound to: 0 - type: bool Parameter sup_filtB bound to: 0 - type: bool Parameter sup_filtC bound to: 0 - type: bool Parameter sup_range bound to: 0 - type: bool Parameter sup_test_registers bound to: 0 - type: bool Parameter sup_traffic_ctrs bound to: 0 - type: bool Parameter sup_parity bound to: 0 - type: bool Parameter active_timestamp_bits bound to: 16 - type: integer Parameter reset_buffer_rams bound to: 0 - type: bool Parameter target_technology bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'rst_sync' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_sync.vhd:94] Parameter G_RESET_POLARITY bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'rst_sync' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_sync.vhd:94] INFO: [Synth 8-638] synthesizing module 'memory_registers' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd:303] Parameter G_SUP_FILTA bound to: 0 - type: bool Parameter G_SUP_FILTB bound to: 0 - type: bool Parameter G_SUP_FILTC bound to: 0 - type: bool Parameter G_SUP_RANGE bound to: 0 - type: bool Parameter G_SUP_TEST_REGISTERS bound to: 0 - type: bool Parameter G_SUP_TRAFFIC_CTRS bound to: 0 - type: bool Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUF_FRAME_CNT_WIDTH bound to: 4 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer Parameter G_INT_COUNT bound to: 12 - type: integer Parameter G_TRV_CTR_WIDTH bound to: 8 - type: integer Parameter G_TS_BITS bound to: 16 - type: integer Parameter G_DEVICE_ID bound to: 16'b1100101011111101 Parameter G_VERSION_MINOR bound to: 8'b00000111 Parameter G_VERSION_MAJOR bound to: 8'b00000010 Parameter G_TECHNOLOGY bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'clk_gate' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd:102] Parameter G_TECHNOLOGY bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'clk_gate' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd:102] INFO: [Synth 8-638] synthesizing module 'control_registers_reg_map' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:111] Parameter DATA_WIDTH bound to: 32 - type: integer Parameter ADDRESS_WIDTH bound to: 8 - type: integer Parameter REGISTERED_READ bound to: 1 - type: bool Parameter CLEAR_READ_DATA bound to: 0 - type: bool Parameter SUP_FILT_A bound to: 0 - type: bool Parameter SUP_TRAFFIC_CTRS bound to: 0 - type: bool Parameter SUP_RANGE bound to: 0 - type: bool Parameter SUP_FILT_C bound to: 0 - type: bool Parameter SUP_FILT_B bound to: 0 - type: bool Parameter address_width bound to: 6 - type: integer Parameter address_entries bound to: 39 - type: integer Parameter addr_vect bound to: 234'b100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000 Parameter registered_out bound to: 0 - type: bool INFO: [Synth 8-3491] module 'address_decoder' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd:83' bound to instance 'address_decoder_control_registers_comp' of component 'address_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:127] INFO: [Synth 8-638] synthesizing module 'address_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd:125] Parameter address_width bound to: 6 - type: integer Parameter address_entries bound to: 39 - type: integer Parameter addr_vect bound to: 234'b100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000 Parameter registered_out bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'address_decoder' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd:125] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'mode_rst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:146] INFO: [Synth 8-638] synthesizing module 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_bmm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:164] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_stm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:182] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_afm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:200] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_fde_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:218] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized2' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized2' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_tttm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:236] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_rom_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:254] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_acf_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:272] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_tstm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:290] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_rxbam_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:308] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_txbbm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:326] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_sam_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:344] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_erfm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:362] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_rtrle_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:380] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_rtrth_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:398] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized4' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized4' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_ilbp_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:416] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_ena_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:434] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_nisofd_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:452] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_pex_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:470] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_tbfbo_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:488] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_fdrf_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:506] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_pchke_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:524] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_rxrpmv_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:542] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_rrb_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:560] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_cdo_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:578] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_ercrst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:596] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_rxfcrst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:614] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_txfcrst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:632] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_cpexs_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:650] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_crxpe_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:668] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_ctxpe_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:686] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_ctxdpe_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:704] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_rxi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:722] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_txi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:740] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_ewli_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:758] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_doi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:776] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_fcsi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:794] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_ali_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:812] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_bei_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:830] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_ofi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:848] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_rxfi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:866] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_bsi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:884] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_rbnei_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:902] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_txbhci_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:920] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_set_int_ena_set_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:938] INFO: [Synth 8-638] synthesizing module 'memory_reg_os__parameterized2' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os__parameterized2' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_set_int_ena_set_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:956] INFO: [Synth 8-638] synthesizing module 'memory_reg_os__parameterized4' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os__parameterized4' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_clr_int_ena_clr_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:974] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_clr_int_ena_clr_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:992] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_set_int_mask_set_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1010] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_set_int_mask_set_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1028] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_clr_int_mask_clr_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1046] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_clr_int_mask_clr_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1064] Parameter data_width bound to: 7 - type: integer Parameter reset_value bound to: 7'b0000101 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_prop_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1082] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 7 - type: integer Parameter reset_value bound to: 7'b0000101 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph1_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1101] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized1' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized1' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00001 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph1_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1120] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized3' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00001 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized3' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b101 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph2_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1139] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized5' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b101 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized5' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph2_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1158] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized7' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized7' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b01010 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_brp_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1177] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized9' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b01010 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized9' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_brp_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1196] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00010 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_sjw_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1215] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized11' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00010 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized11' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 6 - type: integer Parameter reset_value bound to: 6'b000011 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_prop_fd_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1234] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized13' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 6 - type: integer Parameter reset_value bound to: 6'b000011 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized13' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph1_fd_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1253] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0001 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph1_fd_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1272] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized15' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0001 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized15' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b011 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph2_fd_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1291] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized17' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b011 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized17' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 2 - type: integer Parameter reset_value bound to: 2'b00 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph2_fd_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1310] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized19' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 2 - type: integer Parameter reset_value bound to: 2'b00 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized19' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00100 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_brp_fd_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1329] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized21' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00100 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized21' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_brp_fd_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1348] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00010 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_sjw_fd_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1367] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b01100000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'ewl_ew_limit_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1386] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized23' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b01100000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized23' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b10000000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'erp_erp_limit_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1405] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized25' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b10000000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized25' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'ctr_pres_ctpv_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1424] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized27' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized27' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'ctr_pres_ctpv_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1443] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized29' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized29' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_ptx_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1462] INFO: [Synth 8-638] synthesizing module 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os_lock' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_prx_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1481] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_enorm_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1500] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_efd_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1519] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fanb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2170] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fane_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2188] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fafb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2206] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fafe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2224] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbnb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2242] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbne_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2260] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbfb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2278] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbfe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2296] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcnb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2314] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcne_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2332] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcfb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2350] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcfe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2368] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frnb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2386] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frne_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2404] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frfb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2422] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frfe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2440] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'rx_settings_rtsop_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2458] Parameter data_width bound to: 32 - type: integer INFO: [Synth 8-3491] module 'read_access_signaller' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd:81' bound to instance 'rx_data_access_signaller_comp' of component 'read_access_signaller' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2476] INFO: [Synth 8-638] synthesizing module 'read_access_signaller' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd:112] Parameter data_width bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'read_access_signaller' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd:112] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'tx_command_txce_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2493] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'tx_command_txcr_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2511] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'tx_command_txca_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2529] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'tx_command_txb1_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2547] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'tx_command_txb2_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2565] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized6' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized6' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized8' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized8' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00001010 INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized31' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00001010 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized31' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 2 - type: integer Parameter reset_value bound to: 2'b00 INFO: [Synth 8-256] done synthesizing module 'control_registers_reg_map' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:111] INFO: [Synth 8-638] synthesizing module 'rst_reg' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd:106] Parameter G_RESET_POLARITY bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'dff_arst' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'dff_arst' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] INFO: [Synth 8-638] synthesizing module 'mux2' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/mux2.vhd:103] INFO: [Synth 8-256] done synthesizing module 'mux2' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/mux2.vhd:103] INFO: [Synth 8-256] done synthesizing module 'rst_reg' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd:106] INFO: [Synth 8-256] done synthesizing module 'memory_registers' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd:303] INFO: [Synth 8-638] synthesizing module 'rx_buffer' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer.vhd:260] Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer Parameter G_RX_BUF_FRAME_CNT_WIDTH bound to: 4 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_RX_BUF_RAM bound to: 0 - type: bool Parameter G_TECHNOLOGY bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'rx_buffer_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_fsm.vhd:148] INFO: [Synth 8-256] done synthesizing module 'rx_buffer_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_fsm.vhd:148] INFO: [Synth 8-638] synthesizing module 'rx_buffer_pointers' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_pointers.vhd:165] Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'rx_buffer_pointers' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_pointers.vhd:165] INFO: [Synth 8-638] synthesizing module 'rx_buffer_ram' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd:153] Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_RX_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'dp_inf_ram' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram.vhd:124] Parameter G_WORD_WIDTH bound to: 32 - type: integer Parameter G_DEPTH bound to: 32 - type: integer Parameter G_ADDRESS_WIDTH bound to: 5 - type: integer Parameter G_SYNC_READ bound to: 1 - type: bool Parameter G_RESETABLE bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'dp_inf_ram' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram.vhd:124] INFO: [Synth 8-256] done synthesizing module 'rx_buffer_ram' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd:153] INFO: [Synth 8-256] done synthesizing module 'rx_buffer' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer.vhd:260] INFO: [Synth 8-638] synthesizing module 'txt_buffer_even' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd:198] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer Parameter G_ID bound to: 0 - type: integer Parameter G_TECHNOLOGY bound to: 1 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'txt_buffer_ram' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] Parameter G_ID bound to: 0 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'dp_inf_ram_be' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd:125] Parameter G_WORD_WIDTH bound to: 32 - type: integer Parameter G_DEPTH bound to: 21 - type: integer Parameter G_ADDRESS_WIDTH bound to: 5 - type: integer Parameter G_SYNC_READ bound to: 1 - type: bool Parameter G_RESETABLE bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'dp_inf_ram_be' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd:125] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_ram' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] INFO: [Synth 8-638] synthesizing module 'txt_buffer_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd:154] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd:154] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_even' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd:198] INFO: [Synth 8-638] synthesizing module 'txt_buffer_odd' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd:204] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer Parameter G_ID bound to: 1 - type: integer Parameter G_TECHNOLOGY bound to: 1 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'txt_buffer_ram__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] Parameter G_ID bound to: 1 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'txt_buffer_ram__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_odd' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd:204] INFO: [Synth 8-638] synthesizing module 'tx_arbitrator' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator.vhd:210] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'priority_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/priority_decoder.vhd:118] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'priority_decoder' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/priority_decoder.vhd:118] INFO: [Synth 8-638] synthesizing module 'tx_arbitrator_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator_fsm.vhd:179] INFO: [Synth 8-256] done synthesizing module 'tx_arbitrator_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator_fsm.vhd:179] INFO: [Synth 8-256] done synthesizing module 'tx_arbitrator' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator.vhd:210] INFO: [Synth 8-638] synthesizing module 'frame_filters' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd:200] Parameter G_SUP_FILTA bound to: 0 - type: bool Parameter G_SUP_FILTB bound to: 0 - type: bool Parameter G_SUP_FILTC bound to: 0 - type: bool Parameter G_SUP_RANGE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'bit_filter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd:114] Parameter G_WIDTH bound to: 29 - type: integer Parameter G_IS_PRESENT bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'bit_filter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd:114] INFO: [Synth 8-638] synthesizing module 'range_filter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd:116] Parameter G_WIDTH bound to: 29 - type: integer Parameter G_IS_PRESENT bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'range_filter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd:116] INFO: [Synth 8-256] done synthesizing module 'frame_filters' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd:200] INFO: [Synth 8-638] synthesizing module 'int_manager' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_manager.vhd:193] Parameter G_INT_COUNT bound to: 12 - type: integer Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'int_module' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_module.vhd:142] INFO: [Synth 8-256] done synthesizing module 'int_module' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_module.vhd:142] INFO: [Synth 8-256] done synthesizing module 'int_manager' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_manager.vhd:193] INFO: [Synth 8-638] synthesizing module 'can_core' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd:354] Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer Parameter G_CTRL_CTR_WIDTH bound to: 9 - type: integer Parameter G_RETR_LIM_CTR_WIDTH bound to: 4 - type: integer Parameter G_ERR_VALID_PIPELINE bound to: 1 - type: bool Parameter G_CRC15_POL bound to: 16'b1100010110011001 Parameter G_CRC17_POL bound to: 20'b00110110100001011011 Parameter G_CRC21_POL bound to: 24'b001100000010100010011001 Parameter G_SUP_TRAFFIC_CTRS bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'protocol_control' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd:442] Parameter G_CTRL_CTR_WIDTH bound to: 9 - type: integer Parameter G_RETR_LIM_CTR_WIDTH bound to: 4 - type: integer Parameter G_ERR_VALID_PIPELINE bound to: 1 - type: bool INFO: [Synth 8-638] synthesizing module 'endian_swapper' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/endian_swapper.vhd:113] Parameter G_SWAP_GEN bound to: 1 - type: bool Parameter G_WORD_SIZE bound to: 4 - type: integer Parameter G_GROUP_SIZE bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'endian_swapper' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/endian_swapper.vhd:113] INFO: [Synth 8-638] synthesizing module 'protocol_control_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd:503] INFO: [Synth 8-638] synthesizing module 'dlc_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd:99] INFO: [Synth 8-256] done synthesizing module 'dlc_decoder' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd:99] INFO: [Synth 8-256] done synthesizing module 'protocol_control_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd:503] INFO: [Synth 8-638] synthesizing module 'control_counter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/control_counter.vhd:155] Parameter G_CTRL_CTR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'control_counter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/control_counter.vhd:155] INFO: [Synth 8-638] synthesizing module 'reintegration_counter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/reintegration_counter.vhd:117] INFO: [Synth 8-256] done synthesizing module 'reintegration_counter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/reintegration_counter.vhd:117] INFO: [Synth 8-638] synthesizing module 'retransmitt_counter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/retransmitt_counter.vhd:131] Parameter G_RETR_LIM_CTR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'retransmitt_counter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/retransmitt_counter.vhd:131] INFO: [Synth 8-638] synthesizing module 'err_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_detector.vhd:212] Parameter G_ERR_VALID_PIPELINE bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'err_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_detector.vhd:212] INFO: [Synth 8-638] synthesizing module 'tx_shift_reg' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd:193] INFO: [Synth 8-638] synthesizing module 'shift_reg_preload' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_preload.vhd:119] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RESET_VALUE bound to: 0 - type: integer Parameter G_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'shift_reg_preload' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_preload.vhd:119] INFO: [Synth 8-256] done synthesizing module 'tx_shift_reg' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd:193] INFO: [Synth 8-638] synthesizing module 'rx_shift_reg' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd:201] INFO: [Synth 8-638] synthesizing module 'shift_reg_byte' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd:124] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RESET_VALUE bound to: 32'b00000000000000000000000000000000 Parameter G_NUM_BYTES bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'shift_reg_byte' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd:124] INFO: [Synth 8-256] done synthesizing module 'rx_shift_reg' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd:201] INFO: [Synth 8-256] done synthesizing module 'protocol_control' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd:442] INFO: [Synth 8-638] synthesizing module 'operation_control' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/operation_control.vhd:135] INFO: [Synth 8-256] done synthesizing module 'operation_control' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/operation_control.vhd:135] INFO: [Synth 8-638] synthesizing module 'fault_confinement' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd:196] INFO: [Synth 8-638] synthesizing module 'fault_confinement_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_fsm.vhd:146] INFO: [Synth 8-256] done synthesizing module 'fault_confinement_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_fsm.vhd:146] INFO: [Synth 8-638] synthesizing module 'err_counters' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_counters.vhd:160] INFO: [Synth 8-256] done synthesizing module 'err_counters' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_counters.vhd:160] INFO: [Synth 8-638] synthesizing module 'fault_confinement_rules' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_rules.vhd:153] INFO: [Synth 8-256] done synthesizing module 'fault_confinement_rules' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_rules.vhd:153] INFO: [Synth 8-256] done synthesizing module 'fault_confinement' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd:196] INFO: [Synth 8-638] synthesizing module 'can_crc' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd:177] Parameter G_CRC15_POL bound to: 16'b1100010110011001 Parameter G_CRC17_POL bound to: 20'b00110110100001011011 Parameter G_CRC21_POL bound to: 24'b001100000010100010011001 INFO: [Synth 8-638] synthesizing module 'crc_calc' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] Parameter G_CRC_WIDTH bound to: 15 - type: integer Parameter G_POLYNOMIAL bound to: 16'b1100010110011001 INFO: [Synth 8-256] done synthesizing module 'crc_calc' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] INFO: [Synth 8-638] synthesizing module 'crc_calc__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] Parameter G_CRC_WIDTH bound to: 17 - type: integer Parameter G_POLYNOMIAL bound to: 20'b00110110100001011011 INFO: [Synth 8-256] done synthesizing module 'crc_calc__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] INFO: [Synth 8-638] synthesizing module 'crc_calc__parameterized1' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] Parameter G_CRC_WIDTH bound to: 21 - type: integer Parameter G_POLYNOMIAL bound to: 24'b001100000010100010011001 INFO: [Synth 8-256] done synthesizing module 'crc_calc__parameterized1' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] INFO: [Synth 8-256] done synthesizing module 'can_crc' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd:177] INFO: [Synth 8-638] synthesizing module 'bit_stuffing' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd:139] INFO: [Synth 8-638] synthesizing module 'dff_arst_ce' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'dff_arst_ce' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] INFO: [Synth 8-638] synthesizing module 'dff_arst_ce__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'dff_arst_ce__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] INFO: [Synth 8-256] done synthesizing module 'bit_stuffing' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd:139] INFO: [Synth 8-638] synthesizing module 'bit_destuffing' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_destuffing.vhd:141] INFO: [Synth 8-638] synthesizing module 'dff_arst__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'dff_arst__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] INFO: [Synth 8-256] done synthesizing module 'bit_destuffing' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_destuffing.vhd:141] INFO: [Synth 8-638] synthesizing module 'trigger_mux' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/trigger_mux.vhd:175] Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'trigger_mux' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/trigger_mux.vhd:175] INFO: [Synth 8-256] done synthesizing module 'can_core' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd:354] INFO: [Synth 8-638] synthesizing module 'prescaler' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd:189] Parameter G_TSEG1_NBT_WIDTH bound to: 8 - type: integer Parameter G_TSEG2_NBT_WIDTH bound to: 6 - type: integer Parameter G_BRP_NBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_NBT_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_DBT_WIDTH bound to: 7 - type: integer Parameter G_TSEG2_DBT_WIDTH bound to: 5 - type: integer Parameter G_BRP_DBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_DBT_WIDTH bound to: 5 - type: integer Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'bit_time_cfg_capture' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_cfg_capture.vhd:174] Parameter G_TSEG1_NBT_WIDTH bound to: 8 - type: integer Parameter G_TSEG2_NBT_WIDTH bound to: 6 - type: integer Parameter G_BRP_NBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_NBT_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_DBT_WIDTH bound to: 7 - type: integer Parameter G_TSEG2_DBT_WIDTH bound to: 5 - type: integer Parameter G_BRP_DBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_DBT_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_time_cfg_capture' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_cfg_capture.vhd:174] INFO: [Synth 8-638] synthesizing module 'synchronisation_checker' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/synchronisation_checker.vhd:131] INFO: [Synth 8-256] done synthesizing module 'synchronisation_checker' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/synchronisation_checker.vhd:131] INFO: [Synth 8-638] synthesizing module 'bit_segment_meter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] Parameter G_SJW_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_WIDTH bound to: 8 - type: integer Parameter G_TSEG2_WIDTH bound to: 6 - type: integer Parameter G_BT_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_segment_meter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] INFO: [Synth 8-638] synthesizing module 'bit_time_counters' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] Parameter G_BT_WIDTH bound to: 8 - type: integer Parameter G_BRP_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_time_counters' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] INFO: [Synth 8-638] synthesizing module 'bit_segment_meter__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] Parameter G_SJW_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_WIDTH bound to: 7 - type: integer Parameter G_TSEG2_WIDTH bound to: 5 - type: integer Parameter G_BT_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_segment_meter__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] INFO: [Synth 8-638] synthesizing module 'bit_time_counters__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] Parameter G_BT_WIDTH bound to: 7 - type: integer Parameter G_BRP_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_time_counters__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] INFO: [Synth 8-638] synthesizing module 'segment_end_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd:141] INFO: [Synth 8-256] done synthesizing module 'segment_end_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd:141] INFO: [Synth 8-638] synthesizing module 'bit_time_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_fsm.vhd:127] INFO: [Synth 8-256] done synthesizing module 'bit_time_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_fsm.vhd:127] INFO: [Synth 8-638] synthesizing module 'trigger_generator' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/trigger_generator.vhd:150] Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'trigger_generator' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/trigger_generator.vhd:150] INFO: [Synth 8-256] done synthesizing module 'prescaler' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd:189] INFO: [Synth 8-638] synthesizing module 'bus_sampling' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd:198] Parameter G_SSP_DELAY_SAT_VAL bound to: 510 - type: integer Parameter G_TX_CACHE_DEPTH bound to: 8 - type: integer Parameter G_TX_CACHE_PTR_WIDTH bound to: 4 - type: integer Parameter G_TRV_CTR_WIDTH bound to: 8 - type: integer Parameter G_SSP_POS_WIDTH bound to: 9 - type: integer Parameter G_SSP_OFFSET_WIDTH bound to: 8 - type: integer Parameter G_SSP_CTRS_WIDTH bound to: 15 - type: integer INFO: [Synth 8-638] synthesizing module 'sig_sync' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/sig_sync.vhd:100] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RESET_VALUE bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'sig_sync' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/sig_sync.vhd:100] INFO: [Synth 8-638] synthesizing module 'trv_delay_measurement' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/trv_delay_meas.vhd:197] Parameter G_TRV_CTR_WIDTH bound to: 8 - type: integer Parameter G_SSP_POS_WIDTH bound to: 9 - type: integer Parameter G_SSP_OFFSET_WIDTH bound to: 8 - type: integer Parameter G_SSP_SATURATION_LVL bound to: 510 - type: integer INFO: [Synth 8-256] done synthesizing module 'trv_delay_measurement' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/trv_delay_meas.vhd:197] INFO: [Synth 8-638] synthesizing module 'data_edge_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/data_edge_detector.vhd:143] INFO: [Synth 8-256] done synthesizing module 'data_edge_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/data_edge_detector.vhd:143] INFO: [Synth 8-638] synthesizing module 'ssp_generator' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/ssp_generator.vhd:134] Parameter G_SSP_CTRS_WIDTH bound to: 15 - type: integer Parameter G_SSP_POS_WIDTH bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'ssp_generator' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/ssp_generator.vhd:134] INFO: [Synth 8-638] synthesizing module 'tx_data_cache' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/tx_data_cache.vhd:128] Parameter G_TX_CACHE_DEPTH bound to: 8 - type: integer Parameter G_TX_CACHE_PTR_WIDTH bound to: 4 - type: integer Parameter G_TX_CACHE_RST_VAL bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'tx_data_cache' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/tx_data_cache.vhd:128] INFO: [Synth 8-638] synthesizing module 'bit_err_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bit_err_detector.vhd:140] INFO: [Synth 8-256] done synthesizing module 'bit_err_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bit_err_detector.vhd:140] INFO: [Synth 8-638] synthesizing module 'sample_mux' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/sample_mux.vhd:125] INFO: [Synth 8-256] done synthesizing module 'sample_mux' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/sample_mux.vhd:125] INFO: [Synth 8-256] done synthesizing module 'bus_sampling' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd:198] INFO: [Synth 8-256] done synthesizing module 'can_top_level' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd:207] WARNING: [Synth 8-6014] Unused sequential element test_registers_cs_reg_reg was removed. [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd:403] WARNING: [Synth 8-3936] Found unconnected internal register 'mr_tst_dest_tst_addr_pad_reg' and it is trimmed from '16' to '5' bits. [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd:287] WARNING: [Synth 8-3936] Found unconnected internal register 'data_length_c_reg' and it is trimmed from '7' to '6' bits. [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd:931] WARNING: [Synth 8-7129] Port clk_sys in module fault_confinement_rules is either unconnected or has no load WARNING: [Synth 8-7129] Port tx_data in module err_detector is either unconnected or has no load WARNING: [Synth 8-7129] Port mr_command_rxfcrst in module can_core is either unconnected or has no load WARNING: [Synth 8-7129] Port mr_command_txfcrst in module can_core is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[28] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[27] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[26] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[25] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[24] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[23] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[22] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[21] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[20] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[19] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[18] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[17] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[16] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[15] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[14] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[13] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[12] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[11] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[10] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[9] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[8] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[7] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[6] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[5] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[4] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[3] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[2] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[1] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[0] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[28] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[27] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[26] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[25] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[24] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[23] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[22] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[21] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[20] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[19] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[18] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[17] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[16] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[15] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[14] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[13] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[12] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[11] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[10] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[9] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[8] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[7] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[6] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[5] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[4] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[3] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[2] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[1] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[0] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[28] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[27] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[26] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[25] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[24] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[23] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[22] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[21] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[20] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[19] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[18] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[17] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[16] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[15] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[14] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[13] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[12] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[11] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[10] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[9] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[8] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[7] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[6] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[5] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[4] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[3] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[2] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[1] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[0] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port enable in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[28] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[27] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[26] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[25] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[24] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[23] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[22] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[21] in module bit_filter is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2541.012 ; gain = 618.812 ; free physical = 119380 ; free virtual = 146350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2552.887 ; gain = 630.688 ; free physical = 119380 ; free virtual = 146350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2552.887 ; gain = 630.688 ; free physical = 119380 ; free virtual = 146350 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2552.895 ; gain = 0.000 ; free physical = 119550 ; free virtual = 146521 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc] Finished Parsing XDC File [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/can_top_level_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/can_top_level_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2678.352 ; gain = 0.000 ; free physical = 119572 ; free virtual = 146543 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2678.387 ; gain = 756.188 ; free physical = 119572 ; free virtual = 146542 312 Infos, 103 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2678.387 ; gain = 845.453 ; free physical = 119572 ; free virtual = 146542 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1827.110; main = 1827.110; forked = 0.000 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2678.355; main = 2678.355; forked = 0.000 Command: synth_design -top can_top_level -part xc7k70tfbv676-1 -generic rx_buffer_size=32 -generic txt_buffer_count=2 -generic sup_filtA=1'b0 -generic sup_filtB=1'b0 -generic sup_filtC=1'b0 -generic sup_range=1'b0 -generic target_technology=1 -generic sup_traffic_ctrs=1'b0 -generic sup_test_registers=1'b0 -generic sup_parity=1'b0 -generic active_timestamp_bits=16 -generic reset_buffer_rams=1'b0 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k70t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k70t' INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2686.391 ; gain = 7.941 ; free physical = 119373 ; free virtual = 146344 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'can_top_level' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd:207] Parameter rx_buffer_size bound to: 32 - type: integer Parameter txt_buffer_count bound to: 2 - type: integer Parameter sup_filtA bound to: 0 - type: bool Parameter sup_filtB bound to: 0 - type: bool Parameter sup_filtC bound to: 0 - type: bool Parameter sup_range bound to: 0 - type: bool Parameter sup_test_registers bound to: 0 - type: bool Parameter sup_traffic_ctrs bound to: 0 - type: bool Parameter sup_parity bound to: 0 - type: bool Parameter active_timestamp_bits bound to: 16 - type: integer Parameter reset_buffer_rams bound to: 0 - type: bool Parameter target_technology bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'rst_sync' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_sync.vhd:94] Parameter G_RESET_POLARITY bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'rst_sync' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_sync.vhd:94] INFO: [Synth 8-638] synthesizing module 'memory_registers' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd:303] Parameter G_SUP_FILTA bound to: 0 - type: bool Parameter G_SUP_FILTB bound to: 0 - type: bool Parameter G_SUP_FILTC bound to: 0 - type: bool Parameter G_SUP_RANGE bound to: 0 - type: bool Parameter G_SUP_TEST_REGISTERS bound to: 0 - type: bool Parameter G_SUP_TRAFFIC_CTRS bound to: 0 - type: bool Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUF_FRAME_CNT_WIDTH bound to: 4 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer Parameter G_INT_COUNT bound to: 12 - type: integer Parameter G_TRV_CTR_WIDTH bound to: 8 - type: integer Parameter G_TS_BITS bound to: 16 - type: integer Parameter G_DEVICE_ID bound to: 16'b1100101011111101 Parameter G_VERSION_MINOR bound to: 8'b00000111 Parameter G_VERSION_MAJOR bound to: 8'b00000010 Parameter G_TECHNOLOGY bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'clk_gate' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd:102] Parameter G_TECHNOLOGY bound to: 1 - type: integer INFO: [Synth 8-256] done synthesizing module 'clk_gate' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd:102] INFO: [Synth 8-638] synthesizing module 'control_registers_reg_map' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:111] Parameter DATA_WIDTH bound to: 32 - type: integer Parameter ADDRESS_WIDTH bound to: 8 - type: integer Parameter REGISTERED_READ bound to: 1 - type: bool Parameter CLEAR_READ_DATA bound to: 0 - type: bool Parameter SUP_FILT_A bound to: 0 - type: bool Parameter SUP_TRAFFIC_CTRS bound to: 0 - type: bool Parameter SUP_RANGE bound to: 0 - type: bool Parameter SUP_FILT_C bound to: 0 - type: bool Parameter SUP_FILT_B bound to: 0 - type: bool Parameter address_width bound to: 6 - type: integer Parameter address_entries bound to: 39 - type: integer Parameter addr_vect bound to: 234'b100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000 Parameter registered_out bound to: 0 - type: bool INFO: [Synth 8-3491] module 'address_decoder' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd:83' bound to instance 'address_decoder_control_registers_comp' of component 'address_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:127] INFO: [Synth 8-638] synthesizing module 'address_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd:125] Parameter address_width bound to: 6 - type: integer Parameter address_entries bound to: 39 - type: integer Parameter addr_vect bound to: 234'b100110100101100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000 Parameter registered_out bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'address_decoder' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd:125] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'mode_rst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:146] INFO: [Synth 8-638] synthesizing module 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_bmm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:164] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_stm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:182] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_afm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:200] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_fde_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:218] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized2' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized2' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_tttm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:236] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_rom_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:254] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_acf_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:272] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_tstm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:290] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_rxbam_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:308] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_txbbm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:326] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_sam_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:344] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'mode_erfm_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:362] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_rtrle_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:380] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_rtrth_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:398] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized4' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized4' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_ilbp_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:416] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_ena_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:434] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_nisofd_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:452] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_pex_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:470] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_tbfbo_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:488] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_fdrf_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:506] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'settings_pchke_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:524] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_rxrpmv_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:542] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_rrb_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:560] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_cdo_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:578] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_ercrst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:596] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_rxfcrst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:614] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_txfcrst_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:632] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_cpexs_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:650] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_crxpe_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:668] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_ctxpe_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:686] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'command_ctxdpe_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:704] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_rxi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:722] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_txi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:740] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_ewli_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:758] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_doi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:776] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_fcsi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:794] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_ali_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:812] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_bei_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:830] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_ofi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:848] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_rxfi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:866] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_bsi_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:884] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_rbnei_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:902] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_stat_txbhci_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:920] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_set_int_ena_set_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:938] INFO: [Synth 8-638] synthesizing module 'memory_reg_os__parameterized2' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os__parameterized2' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_set_int_ena_set_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:956] INFO: [Synth 8-638] synthesizing module 'memory_reg_os__parameterized4' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os__parameterized4' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:113] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_clr_int_ena_clr_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:974] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_ena_clr_int_ena_clr_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:992] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_set_int_mask_set_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1010] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_set_int_mask_set_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1028] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_clr_int_mask_clr_slice_1_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1046] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0000 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'int_mask_clr_int_mask_clr_slice_2_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1064] Parameter data_width bound to: 7 - type: integer Parameter reset_value bound to: 7'b0000101 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_prop_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1082] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 7 - type: integer Parameter reset_value bound to: 7'b0000101 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph1_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1101] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized1' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized1' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00001 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph1_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1120] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized3' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00001 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized3' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b101 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph2_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1139] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized5' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b101 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized5' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_ph2_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1158] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized7' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized7' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b01010 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_brp_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1177] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized9' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b01010 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized9' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_brp_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1196] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00010 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_sjw_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1215] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized11' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00010 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized11' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 6 - type: integer Parameter reset_value bound to: 6'b000011 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_prop_fd_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1234] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized13' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 6 - type: integer Parameter reset_value bound to: 6'b000011 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized13' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph1_fd_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1253] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0001 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph1_fd_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1272] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized15' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 4 - type: integer Parameter reset_value bound to: 4'b0001 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized15' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b011 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph2_fd_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1291] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized17' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b011 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized17' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 2 - type: integer Parameter reset_value bound to: 2'b00 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_ph2_fd_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1310] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized19' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 2 - type: integer Parameter reset_value bound to: 2'b00 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized19' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00100 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_brp_fd_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1329] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized21' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00100 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized21' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_brp_fd_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1348] Parameter data_width bound to: 5 - type: integer Parameter reset_value bound to: 5'b00010 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'btr_fd_sjw_fd_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1367] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b01100000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'ewl_ew_limit_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1386] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized23' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b01100000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized23' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b10000000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'erp_erp_limit_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1405] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized25' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b10000000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized25' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'ctr_pres_ctpv_slice_1_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1424] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized27' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00000000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized27' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:81' bound to instance 'ctr_pres_ctpv_slice_2_reg_comp' of component 'memory_reg_rw_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1443] INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized29' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized29' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_ptx_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1462] INFO: [Synth 8-638] synthesizing module 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'memory_reg_os_lock' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:118] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_prx_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1481] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_enorm_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1500] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os_lock' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os_lock.vhd:81' bound to instance 'ctr_pres_efd_reg_comp' of component 'memory_reg_os_lock' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:1519] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fanb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2170] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fane_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2188] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fafb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2206] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b1 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fafe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2224] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbnb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2242] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbne_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2260] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbfb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2278] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fbfe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2296] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcnb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2314] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcne_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2332] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcfb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2350] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_fcfe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2368] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frnb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2386] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frne_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2404] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frfb_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2422] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'filter_control_frfe_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2440] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'rx_settings_rtsop_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2458] Parameter data_width bound to: 32 - type: integer INFO: [Synth 8-3491] module 'read_access_signaller' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd:81' bound to instance 'rx_data_access_signaller_comp' of component 'read_access_signaller' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2476] INFO: [Synth 8-638] synthesizing module 'read_access_signaller' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd:112] Parameter data_width bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'read_access_signaller' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/read_access_signaler.vhd:112] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'tx_command_txce_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2493] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'tx_command_txcr_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2511] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_os' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_os.vhd:81' bound to instance 'tx_command_txca_reg_comp' of component 'memory_reg_os' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2529] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'tx_command_txb1_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2547] Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 INFO: [Synth 8-3491] module 'memory_reg_rw' declared at '/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:81' bound to instance 'tx_command_txb2_reg_comp' of component 'memory_reg_rw' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:2565] INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 1 - type: integer Parameter reset_value bound to: 1'b0 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b001 INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized6' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b001 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized6' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-638] synthesizing module 'memory_reg_rw__parameterized8' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw__parameterized8' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw.vhd:113] Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 3 - type: integer Parameter reset_value bound to: 3'b000 Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00001010 INFO: [Synth 8-638] synthesizing module 'memory_reg_rw_lock__parameterized31' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 8 - type: integer Parameter reset_value bound to: 8'b00001010 INFO: [Synth 8-256] done synthesizing module 'memory_reg_rw_lock__parameterized31' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd:118] Parameter data_width bound to: 2 - type: integer Parameter reset_value bound to: 2'b00 INFO: [Synth 8-256] done synthesizing module 'control_registers_reg_map' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/control_registers_reg_map.vhd:111] INFO: [Synth 8-638] synthesizing module 'rst_reg' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd:106] Parameter G_RESET_POLARITY bound to: 1'b0 INFO: [Synth 8-638] synthesizing module 'dff_arst' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'dff_arst' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] INFO: [Synth 8-638] synthesizing module 'mux2' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/mux2.vhd:103] INFO: [Synth 8-256] done synthesizing module 'mux2' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/mux2.vhd:103] INFO: [Synth 8-256] done synthesizing module 'rst_reg' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd:106] INFO: [Synth 8-256] done synthesizing module 'memory_registers' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd:303] INFO: [Synth 8-638] synthesizing module 'rx_buffer' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer.vhd:260] Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer Parameter G_RX_BUF_FRAME_CNT_WIDTH bound to: 4 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_RX_BUF_RAM bound to: 0 - type: bool Parameter G_TECHNOLOGY bound to: 1 - type: integer INFO: [Synth 8-638] synthesizing module 'rx_buffer_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_fsm.vhd:148] INFO: [Synth 8-256] done synthesizing module 'rx_buffer_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_fsm.vhd:148] INFO: [Synth 8-638] synthesizing module 'rx_buffer_pointers' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_pointers.vhd:165] Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'rx_buffer_pointers' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_pointers.vhd:165] INFO: [Synth 8-638] synthesizing module 'rx_buffer_ram' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd:153] Parameter G_RX_BUFF_SIZE bound to: 32 - type: integer Parameter G_RX_BUFF_PTR_WIDTH bound to: 5 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_RX_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'dp_inf_ram' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram.vhd:124] Parameter G_WORD_WIDTH bound to: 32 - type: integer Parameter G_DEPTH bound to: 32 - type: integer Parameter G_ADDRESS_WIDTH bound to: 5 - type: integer Parameter G_SYNC_READ bound to: 1 - type: bool Parameter G_RESETABLE bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'dp_inf_ram' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram.vhd:124] INFO: [Synth 8-256] done synthesizing module 'rx_buffer_ram' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd:153] INFO: [Synth 8-256] done synthesizing module 'rx_buffer' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer.vhd:260] INFO: [Synth 8-638] synthesizing module 'txt_buffer_even' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd:198] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer Parameter G_ID bound to: 0 - type: integer Parameter G_TECHNOLOGY bound to: 1 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'txt_buffer_ram' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] Parameter G_ID bound to: 0 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'dp_inf_ram_be' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd:125] Parameter G_WORD_WIDTH bound to: 32 - type: integer Parameter G_DEPTH bound to: 21 - type: integer Parameter G_ADDRESS_WIDTH bound to: 5 - type: integer Parameter G_SYNC_READ bound to: 1 - type: bool Parameter G_RESETABLE bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'dp_inf_ram_be' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd:125] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_ram' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] INFO: [Synth 8-638] synthesizing module 'txt_buffer_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd:154] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd:154] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_even' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_even.vhd:198] INFO: [Synth 8-638] synthesizing module 'txt_buffer_odd' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd:204] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer Parameter G_ID bound to: 1 - type: integer Parameter G_TECHNOLOGY bound to: 1 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'txt_buffer_ram__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] Parameter G_ID bound to: 1 - type: integer Parameter G_SUP_PARITY bound to: 0 - type: bool Parameter G_RESET_TXT_BUF_RAM bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'txt_buffer_ram__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd:156] INFO: [Synth 8-256] done synthesizing module 'txt_buffer_odd' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd:204] INFO: [Synth 8-638] synthesizing module 'tx_arbitrator' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator.vhd:210] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'priority_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/priority_decoder.vhd:118] Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'priority_decoder' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/priority_decoder.vhd:118] INFO: [Synth 8-638] synthesizing module 'tx_arbitrator_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator_fsm.vhd:179] INFO: [Synth 8-256] done synthesizing module 'tx_arbitrator_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator_fsm.vhd:179] INFO: [Synth 8-256] done synthesizing module 'tx_arbitrator' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/tx_arbitrator/tx_arbitrator.vhd:210] INFO: [Synth 8-638] synthesizing module 'frame_filters' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd:200] Parameter G_SUP_FILTA bound to: 0 - type: bool Parameter G_SUP_FILTB bound to: 0 - type: bool Parameter G_SUP_FILTC bound to: 0 - type: bool Parameter G_SUP_RANGE bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'bit_filter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd:114] Parameter G_WIDTH bound to: 29 - type: integer Parameter G_IS_PRESENT bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'bit_filter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd:114] INFO: [Synth 8-638] synthesizing module 'range_filter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd:116] Parameter G_WIDTH bound to: 29 - type: integer Parameter G_IS_PRESENT bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'range_filter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/range_filter.vhd:116] INFO: [Synth 8-256] done synthesizing module 'frame_filters' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd:200] INFO: [Synth 8-638] synthesizing module 'int_manager' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_manager.vhd:193] Parameter G_INT_COUNT bound to: 12 - type: integer Parameter G_TXT_BUFFER_COUNT bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'int_module' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_module.vhd:142] INFO: [Synth 8-256] done synthesizing module 'int_module' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_module.vhd:142] INFO: [Synth 8-256] done synthesizing module 'int_manager' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/interrupt_manager/int_manager.vhd:193] INFO: [Synth 8-638] synthesizing module 'can_core' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd:354] Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer Parameter G_CTRL_CTR_WIDTH bound to: 9 - type: integer Parameter G_RETR_LIM_CTR_WIDTH bound to: 4 - type: integer Parameter G_ERR_VALID_PIPELINE bound to: 1 - type: bool Parameter G_CRC15_POL bound to: 16'b1100010110011001 Parameter G_CRC17_POL bound to: 20'b00110110100001011011 Parameter G_CRC21_POL bound to: 24'b001100000010100010011001 Parameter G_SUP_TRAFFIC_CTRS bound to: 0 - type: bool INFO: [Synth 8-638] synthesizing module 'protocol_control' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd:442] Parameter G_CTRL_CTR_WIDTH bound to: 9 - type: integer Parameter G_RETR_LIM_CTR_WIDTH bound to: 4 - type: integer Parameter G_ERR_VALID_PIPELINE bound to: 1 - type: bool INFO: [Synth 8-638] synthesizing module 'endian_swapper' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/endian_swapper.vhd:113] Parameter G_SWAP_GEN bound to: 1 - type: bool Parameter G_WORD_SIZE bound to: 4 - type: integer Parameter G_GROUP_SIZE bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'endian_swapper' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/endian_swapper.vhd:113] INFO: [Synth 8-638] synthesizing module 'protocol_control_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd:503] INFO: [Synth 8-638] synthesizing module 'dlc_decoder' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd:99] INFO: [Synth 8-256] done synthesizing module 'dlc_decoder' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd:99] INFO: [Synth 8-256] done synthesizing module 'protocol_control_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd:503] INFO: [Synth 8-638] synthesizing module 'control_counter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/control_counter.vhd:155] Parameter G_CTRL_CTR_WIDTH bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'control_counter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/control_counter.vhd:155] INFO: [Synth 8-638] synthesizing module 'reintegration_counter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/reintegration_counter.vhd:117] INFO: [Synth 8-256] done synthesizing module 'reintegration_counter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/reintegration_counter.vhd:117] INFO: [Synth 8-638] synthesizing module 'retransmitt_counter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/retransmitt_counter.vhd:131] Parameter G_RETR_LIM_CTR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'retransmitt_counter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/retransmitt_counter.vhd:131] INFO: [Synth 8-638] synthesizing module 'err_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_detector.vhd:212] Parameter G_ERR_VALID_PIPELINE bound to: 1 - type: bool INFO: [Synth 8-256] done synthesizing module 'err_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_detector.vhd:212] INFO: [Synth 8-638] synthesizing module 'tx_shift_reg' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd:193] INFO: [Synth 8-638] synthesizing module 'shift_reg_preload' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_preload.vhd:119] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RESET_VALUE bound to: 0 - type: integer Parameter G_WIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'shift_reg_preload' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_preload.vhd:119] INFO: [Synth 8-256] done synthesizing module 'tx_shift_reg' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/tx_shift_reg.vhd:193] INFO: [Synth 8-638] synthesizing module 'rx_shift_reg' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd:201] INFO: [Synth 8-638] synthesizing module 'shift_reg_byte' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd:124] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RESET_VALUE bound to: 32'b00000000000000000000000000000000 Parameter G_NUM_BYTES bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'shift_reg_byte' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_byte.vhd:124] INFO: [Synth 8-256] done synthesizing module 'rx_shift_reg' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd:201] INFO: [Synth 8-256] done synthesizing module 'protocol_control' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd:442] INFO: [Synth 8-638] synthesizing module 'operation_control' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/operation_control.vhd:135] INFO: [Synth 8-256] done synthesizing module 'operation_control' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/operation_control.vhd:135] INFO: [Synth 8-638] synthesizing module 'fault_confinement' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd:196] INFO: [Synth 8-638] synthesizing module 'fault_confinement_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_fsm.vhd:146] INFO: [Synth 8-256] done synthesizing module 'fault_confinement_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_fsm.vhd:146] INFO: [Synth 8-638] synthesizing module 'err_counters' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_counters.vhd:160] INFO: [Synth 8-256] done synthesizing module 'err_counters' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/err_counters.vhd:160] INFO: [Synth 8-638] synthesizing module 'fault_confinement_rules' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_rules.vhd:153] INFO: [Synth 8-256] done synthesizing module 'fault_confinement_rules' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_rules.vhd:153] INFO: [Synth 8-256] done synthesizing module 'fault_confinement' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd:196] INFO: [Synth 8-638] synthesizing module 'can_crc' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd:177] Parameter G_CRC15_POL bound to: 16'b1100010110011001 Parameter G_CRC17_POL bound to: 20'b00110110100001011011 Parameter G_CRC21_POL bound to: 24'b001100000010100010011001 INFO: [Synth 8-638] synthesizing module 'crc_calc' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] Parameter G_CRC_WIDTH bound to: 15 - type: integer Parameter G_POLYNOMIAL bound to: 16'b1100010110011001 INFO: [Synth 8-256] done synthesizing module 'crc_calc' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] INFO: [Synth 8-638] synthesizing module 'crc_calc__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] Parameter G_CRC_WIDTH bound to: 17 - type: integer Parameter G_POLYNOMIAL bound to: 20'b00110110100001011011 INFO: [Synth 8-256] done synthesizing module 'crc_calc__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] INFO: [Synth 8-638] synthesizing module 'crc_calc__parameterized1' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] Parameter G_CRC_WIDTH bound to: 21 - type: integer Parameter G_POLYNOMIAL bound to: 24'b001100000010100010011001 INFO: [Synth 8-256] done synthesizing module 'crc_calc__parameterized1' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd:131] INFO: [Synth 8-256] done synthesizing module 'can_crc' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd:177] INFO: [Synth 8-638] synthesizing module 'bit_stuffing' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd:139] INFO: [Synth 8-638] synthesizing module 'dff_arst_ce' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'dff_arst_ce' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] INFO: [Synth 8-638] synthesizing module 'dff_arst_ce__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'dff_arst_ce__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst_ce.vhd:103] INFO: [Synth 8-256] done synthesizing module 'bit_stuffing' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd:139] INFO: [Synth 8-638] synthesizing module 'bit_destuffing' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_destuffing.vhd:141] INFO: [Synth 8-638] synthesizing module 'dff_arst__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RST_VAL bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'dff_arst__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/dff_arst.vhd:100] INFO: [Synth 8-256] done synthesizing module 'bit_destuffing' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/bit_destuffing.vhd:141] INFO: [Synth 8-638] synthesizing module 'trigger_mux' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/trigger_mux.vhd:175] Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'trigger_mux' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/trigger_mux.vhd:175] INFO: [Synth 8-256] done synthesizing module 'can_core' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd:354] INFO: [Synth 8-638] synthesizing module 'prescaler' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd:189] Parameter G_TSEG1_NBT_WIDTH bound to: 8 - type: integer Parameter G_TSEG2_NBT_WIDTH bound to: 6 - type: integer Parameter G_BRP_NBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_NBT_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_DBT_WIDTH bound to: 7 - type: integer Parameter G_TSEG2_DBT_WIDTH bound to: 5 - type: integer Parameter G_BRP_DBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_DBT_WIDTH bound to: 5 - type: integer Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer INFO: [Synth 8-638] synthesizing module 'bit_time_cfg_capture' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_cfg_capture.vhd:174] Parameter G_TSEG1_NBT_WIDTH bound to: 8 - type: integer Parameter G_TSEG2_NBT_WIDTH bound to: 6 - type: integer Parameter G_BRP_NBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_NBT_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_DBT_WIDTH bound to: 7 - type: integer Parameter G_TSEG2_DBT_WIDTH bound to: 5 - type: integer Parameter G_BRP_DBT_WIDTH bound to: 8 - type: integer Parameter G_SJW_DBT_WIDTH bound to: 5 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_time_cfg_capture' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_cfg_capture.vhd:174] INFO: [Synth 8-638] synthesizing module 'synchronisation_checker' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/synchronisation_checker.vhd:131] INFO: [Synth 8-256] done synthesizing module 'synchronisation_checker' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/synchronisation_checker.vhd:131] INFO: [Synth 8-638] synthesizing module 'bit_segment_meter' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] Parameter G_SJW_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_WIDTH bound to: 8 - type: integer Parameter G_TSEG2_WIDTH bound to: 6 - type: integer Parameter G_BT_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_segment_meter' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] INFO: [Synth 8-638] synthesizing module 'bit_time_counters' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] Parameter G_BT_WIDTH bound to: 8 - type: integer Parameter G_BRP_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_time_counters' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] INFO: [Synth 8-638] synthesizing module 'bit_segment_meter__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] Parameter G_SJW_WIDTH bound to: 5 - type: integer Parameter G_TSEG1_WIDTH bound to: 7 - type: integer Parameter G_TSEG2_WIDTH bound to: 5 - type: integer Parameter G_BT_WIDTH bound to: 7 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_segment_meter__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_segment_meter.vhd:266] INFO: [Synth 8-638] synthesizing module 'bit_time_counters__parameterized0' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] Parameter G_BT_WIDTH bound to: 7 - type: integer Parameter G_BRP_WIDTH bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'bit_time_counters__parameterized0' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd:135] INFO: [Synth 8-638] synthesizing module 'segment_end_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd:141] INFO: [Synth 8-256] done synthesizing module 'segment_end_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/segment_end_detector.vhd:141] INFO: [Synth 8-638] synthesizing module 'bit_time_fsm' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_fsm.vhd:127] INFO: [Synth 8-256] done synthesizing module 'bit_time_fsm' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_fsm.vhd:127] INFO: [Synth 8-638] synthesizing module 'trigger_generator' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/trigger_generator.vhd:150] Parameter G_SAMPLE_TRIGGER_COUNT bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'trigger_generator' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/trigger_generator.vhd:150] INFO: [Synth 8-256] done synthesizing module 'prescaler' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd:189] INFO: [Synth 8-638] synthesizing module 'bus_sampling' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd:198] Parameter G_SSP_DELAY_SAT_VAL bound to: 510 - type: integer Parameter G_TX_CACHE_DEPTH bound to: 8 - type: integer Parameter G_TX_CACHE_PTR_WIDTH bound to: 4 - type: integer Parameter G_TRV_CTR_WIDTH bound to: 8 - type: integer Parameter G_SSP_POS_WIDTH bound to: 9 - type: integer Parameter G_SSP_OFFSET_WIDTH bound to: 8 - type: integer Parameter G_SSP_CTRS_WIDTH bound to: 15 - type: integer INFO: [Synth 8-638] synthesizing module 'sig_sync' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/sig_sync.vhd:100] Parameter G_RESET_POLARITY bound to: 1'b0 Parameter G_RESET_VALUE bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'sig_sync' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/common_blocks/sig_sync.vhd:100] INFO: [Synth 8-638] synthesizing module 'trv_delay_measurement' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/trv_delay_meas.vhd:197] Parameter G_TRV_CTR_WIDTH bound to: 8 - type: integer Parameter G_SSP_POS_WIDTH bound to: 9 - type: integer Parameter G_SSP_OFFSET_WIDTH bound to: 8 - type: integer Parameter G_SSP_SATURATION_LVL bound to: 510 - type: integer INFO: [Synth 8-256] done synthesizing module 'trv_delay_measurement' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/trv_delay_meas.vhd:197] INFO: [Synth 8-638] synthesizing module 'data_edge_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/data_edge_detector.vhd:143] INFO: [Synth 8-256] done synthesizing module 'data_edge_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/data_edge_detector.vhd:143] INFO: [Synth 8-638] synthesizing module 'ssp_generator' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/ssp_generator.vhd:134] Parameter G_SSP_CTRS_WIDTH bound to: 15 - type: integer Parameter G_SSP_POS_WIDTH bound to: 9 - type: integer INFO: [Synth 8-256] done synthesizing module 'ssp_generator' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/ssp_generator.vhd:134] INFO: [Synth 8-638] synthesizing module 'tx_data_cache' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/tx_data_cache.vhd:128] Parameter G_TX_CACHE_DEPTH bound to: 8 - type: integer Parameter G_TX_CACHE_PTR_WIDTH bound to: 4 - type: integer Parameter G_TX_CACHE_RST_VAL bound to: 1'b1 INFO: [Synth 8-256] done synthesizing module 'tx_data_cache' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/tx_data_cache.vhd:128] INFO: [Synth 8-638] synthesizing module 'bit_err_detector' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bit_err_detector.vhd:140] INFO: [Synth 8-256] done synthesizing module 'bit_err_detector' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bit_err_detector.vhd:140] INFO: [Synth 8-638] synthesizing module 'sample_mux' [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/sample_mux.vhd:125] INFO: [Synth 8-256] done synthesizing module 'sample_mux' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/sample_mux.vhd:125] INFO: [Synth 8-256] done synthesizing module 'bus_sampling' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd:198] INFO: [Synth 8-256] done synthesizing module 'can_top_level' (0#1) [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd:207] WARNING: [Synth 8-6014] Unused sequential element test_registers_cs_reg_reg was removed. [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd:403] WARNING: [Synth 8-3936] Found unconnected internal register 'mr_tst_dest_tst_addr_pad_reg' and it is trimmed from '16' to '5' bits. [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/rx_buffer/rx_buffer_ram.vhd:287] WARNING: [Synth 8-3936] Found unconnected internal register 'data_length_c_reg' and it is trimmed from '7' to '6' bits. [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd:931] WARNING: [Synth 8-7129] Port clk_sys in module fault_confinement_rules is either unconnected or has no load WARNING: [Synth 8-7129] Port tx_data in module err_detector is either unconnected or has no load WARNING: [Synth 8-7129] Port mr_command_rxfcrst in module can_core is either unconnected or has no load WARNING: [Synth 8-7129] Port mr_command_txfcrst in module can_core is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[28] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[27] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[26] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[25] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[24] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[23] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[22] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[21] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[20] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[19] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[18] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[17] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[16] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[15] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[14] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[13] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[12] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[11] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[10] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[9] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[8] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[7] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[6] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[5] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[4] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[3] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[2] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[1] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_upp_th[0] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[28] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[27] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[26] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[25] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[24] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[23] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[22] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[21] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[20] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[19] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[18] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[17] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[16] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[15] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[14] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[13] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[12] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[11] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[10] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[9] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[8] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[7] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[6] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[5] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[4] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[3] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[2] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[1] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_low_th[0] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[28] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[27] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[26] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[25] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[24] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[23] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[22] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[21] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[20] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[19] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[18] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[17] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[16] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[15] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[14] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[13] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[12] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[11] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[10] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[9] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[8] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[7] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[6] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[5] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[4] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[3] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[2] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[1] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_input[0] in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port enable in module range_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[28] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[27] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[26] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[25] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[24] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[23] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[22] in module bit_filter is either unconnected or has no load WARNING: [Synth 8-7129] Port filter_mask[21] in module bit_filter is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2747.355 ; gain = 68.906 ; free physical = 119287 ; free virtual = 146258 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2759.230 ; gain = 80.781 ; free physical = 119287 ; free virtual = 146258 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2759.230 ; gain = 80.781 ; free physical = 119287 ; free virtual = 146258 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2759.230 ; gain = 0.000 ; free physical = 119287 ; free virtual = 146258 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc] Finished Parsing XDC File [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/can_top_level_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/can_top_level_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2833.949 ; gain = 0.000 ; free physical = 119305 ; free virtual = 146276 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2833.984 ; gain = 0.000 ; free physical = 119306 ; free virtual = 146277 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2833.984 ; gain = 155.535 ; free physical = 119323 ; free virtual = 146294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k70tfbv676-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2833.984 ; gain = 155.535 ; free physical = 119323 ; free virtual = 146294 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2833.984 ; gain = 155.535 ; free physical = 119323 ; free virtual = 146294 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'curr_state_reg' in module 'rx_buffer_fsm' INFO: [Synth 8-802] inferred FSM for state register 'curr_state_reg' in module 'txt_buffer_fsm' INFO: [Synth 8-802] inferred FSM for state register 'curr_state_reg' in module 'tx_arbitrator_fsm' INFO: [Synth 8-802] inferred FSM for state register 'curr_state_reg' in module 'operation_control' INFO: [Synth 8-802] inferred FSM for state register 'curr_state_reg' in module 'fault_confinement_fsm' INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'bit_time_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s_rxb_idle | 000000000001 | 0000 s_rxb_store_frame_format | 000000000010 | 0001 s_rxb_store_identifier | 000000000100 | 0010 s_rxb_skip_ts_low | 000000001000 | 0011 s_rxb_skip_ts_high | 000000010000 | 0100 s_rxb_store_data | 000000100000 | 0111 s_rxb_store_end_ts_low | 000001000000 | 0101 s_rxb_store_end_ts_high | 000010000000 | 0110 s_rxb_store_err_frame_format | 000100000000 | 1000 s_rxb_store_err_identifier | 001000000000 | 1001 s_rxb_store_err_ts_low | 010000000000 | 1010 s_rxb_store_err_ts_high | 100000000000 | 1011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'curr_state_reg' using encoding 'one-hot' in module 'rx_buffer_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s_txt_empty | 010 | 000 s_txt_ready | 001 | 001 s_txt_tx_prog | 111 | 010 s_txt_ab_prog | 110 | 011 s_txt_failed | 101 | 101 s_txt_parity_err | 000 | 111 s_txt_ok | 011 | 100 s_txt_aborted | 100 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'curr_state_reg' using encoding 'sequential' in module 'txt_buffer_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s_arb_idle | 000 | 000 s_arb_sel_low_ts | 001 | 001 s_arb_sel_upp_ts | 010 | 010 s_arb_sel_ftw | 011 | 101 s_arb_sel_ffw | 100 | 011 s_arb_sel_idw | 101 | 100 s_arb_validated | 110 | 110 s_arb_locked | 111 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'curr_state_reg' using encoding 'sequential' in module 'tx_arbitrator_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s_oc_off | 00 | 00 s_oc_idle | 01 | 01 s_oc_receiver | 10 | 11 s_oc_transmitter | 11 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'curr_state_reg' using encoding 'sequential' in module 'operation_control' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s_fc_bus_off | 00 | 10 s_fc_err_active | 01 | 00 s_fc_err_passive | 10 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'curr_state_reg' using encoding 'sequential' in module 'fault_confinement_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- s_bt_reset | 001 | 10 s_bt_tseg1 | 010 | 00 s_bt_tseg2 | 100 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'one-hot' in module 'bit_time_fsm' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2833.984 ; gain = 155.535 ; free physical = 119306 ; free virtual = 146279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 16 Bit Adders := 1 2 Input 15 Bit Adders := 2 2 Input 9 Bit Adders := 6 3 Input 9 Bit Adders := 1 2 Input 8 Bit Adders := 6 3 Input 8 Bit Adders := 3 2 Input 7 Bit Adders := 2 3 Input 7 Bit Adders := 2 2 Input 6 Bit Adders := 6 2 Input 5 Bit Adders := 6 2 Input 4 Bit Adders := 4 2 Input 3 Bit Adders := 4 +---XORs : 2 Input 21 Bit XORs := 2 2 Input 17 Bit XORs := 1 2 Input 15 Bit XORs := 1 2 Input 4 Bit XORs := 1 3 Input 1 Bit XORs := 2 2 Input 1 Bit XORs := 3 +---Registers : 64 Bit Registers := 1 32 Bit Registers := 6 29 Bit Registers := 2 21 Bit Registers := 1 17 Bit Registers := 1 16 Bit Registers := 2 15 Bit Registers := 2 9 Bit Registers := 6 8 Bit Registers := 13 7 Bit Registers := 2 6 Bit Registers := 3 5 Bit Registers := 10 4 Bit Registers := 9 3 Bit Registers := 6 2 Bit Registers := 2 1 Bit Registers := 317 +---RAMs : 1024 Bit (32 X 32 bit) RAMs := 1 672 Bit (21 X 32 bit) RAMs := 2 +---Muxes : 2 Input 39 Bit Muxes := 1 2 Input 32 Bit Muxes := 24 2 Input 21 Bit Muxes := 5 2 Input 17 Bit Muxes := 2 2 Input 16 Bit Muxes := 3 2 Input 15 Bit Muxes := 4 12 Input 12 Bit Muxes := 1 2 Input 12 Bit Muxes := 7 2 Input 9 Bit Muxes := 10 3 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 13 2 Input 7 Bit Muxes := 15 8 Input 7 Bit Muxes := 3 2 Input 6 Bit Muxes := 10 3 Input 6 Bit Muxes := 2 12 Input 5 Bit Muxes := 1 2 Input 5 Bit Muxes := 27 5 Input 5 Bit Muxes := 1 3 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 28 3 Input 4 Bit Muxes := 6 12 Input 4 Bit Muxes := 2 8 Input 4 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 85 5 Input 3 Bit Muxes := 4 3 Input 3 Bit Muxes := 4 6 Input 3 Bit Muxes := 4 8 Input 3 Bit Muxes := 10 34 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 6 7 Input 3 Bit Muxes := 2 2 Input 2 Bit Muxes := 34 3 Input 2 Bit Muxes := 5 4 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 240 12 Input 1 Bit Muxes := 3 4 Input 1 Bit Muxes := 7 3 Input 1 Bit Muxes := 7 8 Input 1 Bit Muxes := 12 5 Input 1 Bit Muxes := 1 39 Input 1 Bit Muxes := 19 6 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2858.965 ; gain = 180.516 ; free physical = 119298 ; free virtual = 146281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +---------------------+--------------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +---------------------+--------------------------+---------------+----------------+ |protocol_control_fsm | bit_err_disable_receiver | 64x1 | LUT | |protocol_control_fsm | bit_err_disable_receiver | 64x1 | LUT | +---------------------+--------------------------+---------------+----------------+ Block RAM: Preliminary Mapping Report (see note below) +------------------------------------------------------------+-------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------------------------------------------------------+-------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |rx_buffer_inst | rx_buffer_ram_inst/dp_inf_ram_inst/ram_rst_false_gen.ram_memory_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |\txt_buf_comp_gen[0].txt_buf_even_gen.txt_buffer_even_inst | txt_buffer_ram_inst/dp_inf_ram_be_inst/ram_rst_false_gen.ram_memory_reg | 21 x 32(READ_FIRST) | W | | 21 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |\txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst | txt_buffer_ram_inst/dp_inf_ram_be_inst/ram_rst_false_gen.ram_memory_reg | 21 x 32(READ_FIRST) | W | | 21 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +------------------------------------------------------------+-------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2858.965 ; gain = 180.516 ; free physical = 119312 ; free virtual = 146295 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 2941.691 ; gain = 263.242 ; free physical = 119237 ; free virtual = 146219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +------------------------------------------------------------+-------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------------------------------------------------------+-------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |rx_buffer_inst | rx_buffer_ram_inst/dp_inf_ram_inst/ram_rst_false_gen.ram_memory_reg | 32 x 32(READ_FIRST) | W | | 32 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |\txt_buf_comp_gen[0].txt_buf_even_gen.txt_buffer_even_inst | txt_buffer_ram_inst/dp_inf_ram_be_inst/ram_rst_false_gen.ram_memory_reg | 21 x 32(READ_FIRST) | W | | 21 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |\txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst | txt_buffer_ram_inst/dp_inf_ram_be_inst/ram_rst_false_gen.ram_memory_reg | 21 x 32(READ_FIRST) | W | | 21 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +------------------------------------------------------------+-------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance rx_buffer_inst/rx_buffer_ram_inst/dp_inf_ram_inst/ram_rst_false_gen.ram_memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance txt_buf_comp_gen[0].txt_buf_even_gen.txt_buffer_even_inst/txt_buffer_ram_inst/dp_inf_ram_be_inst/ram_rst_false_gen.ram_memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst/txt_buffer_ram_inst/dp_inf_ram_be_inst/ram_rst_false_gen.ram_memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2941.691 ; gain = 263.242 ; free physical = 119237 ; free virtual = 146219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 3067.504 ; gain = 389.055 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 3067.504 ; gain = 389.055 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 3067.504 ; gain = 389.055 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 3067.504 ; gain = 389.055 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3071.473 ; gain = 393.023 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3071.473 ; gain = 393.023 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |CARRY4 | 71| |3 |LUT1 | 18| |4 |LUT2 | 297| |5 |LUT3 | 218| |6 |LUT4 | 335| |7 |LUT5 | 416| |8 |LUT6 | 870| |9 |MUXF7 | 65| |10 |MUXF8 | 6| |11 |RAMB18E1 | 3| |12 |FDCE | 868| |13 |FDPE | 89| |14 |IBUF | 117| |15 |OBUF | 38| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3071.473 ; gain = 393.023 ; free physical = 119153 ; free virtual = 146136 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 392 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 3071.473 ; gain = 318.270 ; free physical = 119153 ; free virtual = 146136 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 3071.480 ; gain = 393.023 ; free physical = 119153 ; free virtual = 146136 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3071.480 ; gain = 0.000 ; free physical = 119320 ; free virtual = 146303 INFO: [Netlist 29-17] Analyzing 145 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc] Finished Parsing XDC File [/opt/actions-runner/_work/ctu-can-regression/ctu-can-regression/synthesis/Constraints/ctu_can_fd.sdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.281 ; gain = 0.000 ; free physical = 119285 ; free virtual = 146268 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Synth Design complete | Checksum: a9086142 INFO: [Common 17-83] Releasing license: Synthesis 645 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 3153.316 ; gain = 474.930 ; free physical = 119285 ; free virtual = 146268 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2310.349; main = 2310.349; forked = 346.159 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4554.758; main = 3153.285; forked = 1645.773 Command: opt_design -resynth_seq_area Attempting to get a license for feature 'Implementation' and/or device 'xc7k70t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k70t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3153.316 ; gain = 0.000 ; free physical = 119288 ; free virtual = 146270 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 21e5b6144 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.316 ; gain = 0.000 ; free physical = 119292 ; free virtual = 146275 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 21e5b6144 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3153.316 ; gain = 0.000 ; free physical = 119292 ; free virtual = 146275 Phase 1 Initialization | Checksum: 21e5b6144 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3153.316 ; gain = 0.000 ; free physical = 119292 ; free virtual = 146275 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Detect if minReqCache needed Phase 2.1 Detect if minReqCache needed | Checksum: 21e5b6144 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3153.316 ; gain = 0.000 ; free physical = 119292 ; free virtual = 146275 Phase 2.2 Timer Update INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2.2 Timer Update | Checksum: 21e5b6144 Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.63 . Memory (MB): peak = 3207.094 ; gain = 53.777 ; free physical = 119279 ; free virtual = 146262 Phase 2.3 Timing Data Collection Phase 2.3 Timing Data Collection | Checksum: 21e5b6144 Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.63 . Memory (MB): peak = 3207.094 ; gain = 53.777 ; free physical = 119279 ; free virtual = 146262 Phase 2 Timer Update And Timing Data Collection | Checksum: 21e5b6144 Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.64 . Memory (MB): peak = 3207.094 ; gain = 53.777 ; free physical = 119279 ; free virtual = 146262 Phase 3 Resynthesis INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-74] Optimized 1 modules. INFO: [Opt 31-75] Optimized module 'rx_buffer_fsm'. INFO: [Opt 31-1566] Pulled 6 inverters resulting in an inversion of 45 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.922 ; gain = 0.000 ; free physical = 117811 ; free virtual = 144794 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.922 ; gain = 0.000 ; free physical = 118638 ; free virtual = 145621 Phase 3 Resynthesis | Checksum: 1b11eec45 Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.922 ; gain = 61.605 ; free physical = 118638 ; free virtual = 145621 Resynthesis | Checksum: 1b11eec45 INFO: [Opt 31-389] Phase Resynthesis created 87 cells and removed 91 cells Phase 4 Post Processing Netlist Phase 4 Post Processing Netlist | Checksum: 1b11eec45 Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.922 ; gain = 61.605 ; free physical = 118638 ; free virtual = 145621 Post Processing Netlist | Checksum: 1b11eec45 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 5 Finalization Phase 5.1 Finalizing Design Cores and Updating Shapes Phase 5.1 Finalizing Design Cores and Updating Shapes | Checksum: fda330bf Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.922 ; gain = 61.605 ; free physical = 118638 ; free virtual = 145621 Phase 5.2 Verifying Netlist Connectivity Phase 5.2 Verifying Netlist Connectivity | Checksum: fda330bf Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.922 ; gain = 61.605 ; free physical = 118638 ; free virtual = 145621 Phase 5 Finalization | Checksum: fda330bf Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.922 ; gain = 61.605 ; free physical = 118638 ; free virtual = 145621 Opt_design Change Summary ========================= --------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | --------------------------------------------------------------------------------------------------------------------- | Resynthesis | 87 | 91 | 0 | | Post Processing Netlist | 0 | 0 | 0 | --------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: fda330bf Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 3214.922 ; gain = 61.605 ; free physical = 118638 ; free virtual = 145621 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3214.922 ; gain = 0.000 ; free physical = 118639 ; free virtual = 145622 INFO: [Common 17-83] Releasing license: Implementation 663 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully # write_outputs $cfg_name INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Fri Apr 10 21:29:43 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary | Design : can_top_level | Device : 7k70t-fbv676 | Speed File : -1 PRODUCTION 1.12 2017-02-17 | Design State : Optimized --------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (2) 6. checking no_output_delay (3) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (2) ------------------------------ There are 0 input ports with no input delay specified. There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (3) ------------------------------- There are 0 ports with no output delay specified. There are 3 ports with no output delay but user has a false path constraint (MEDIUM) There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 2.503 0.000 0 2870 0.206 0.000 0 2870 4.650 0.000 0 966 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- SYS_CLK {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- SYS_CLK 3.224 0.000 0 1914 0.206 0.000 0 1914 4.650 0.000 0 966 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** SYS_CLK SYS_CLK 2.503 0.000 0 956 0.616 0.000 0 956 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: SYS_CLK To Clock: SYS_CLK Setup : 0 Failing Endpoints, Worst Slack 3.224ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.206ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 4.650ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.224ns (required time - arrival time) Source: timestamp[1] (input port clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]/D (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: SYS_CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (SYS_CLK rise@10.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 4.277ns (logic 1.694ns (39.599%) route 2.584ns (60.401%)) Logic Levels: 11 (CARRY4=4 IBUF=1 LUT4=2 LUT5=1 LUT6=3) Input Delay: 2.500ns Clock Path Skew: 2.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.000ns = ( 12.000 - 10.000 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r ideal clock network latency 2.000 2.000 input delay 2.500 4.500 0.000 4.500 r timestamp[1] (IN) net (fo=0) 0.000 4.500 timestamp[1] IBUF (Prop_ibuf_I_O) 0.830 5.330 r timestamp_IBUF[1]_inst/O net (fo=4, unplaced) 0.584 5.913 tx_arbitrator_inst/tx_arbitrator_fsm_inst/timestamp_IBUF[1] LUT4 (Prop_lut4_I0_O) 0.066 5.979 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_105/O net (fo=1, unplaced) 0.000 5.979 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_105_n_0 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.353 6.332 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_81/CO[3] net (fo=1, unplaced) 0.000 6.332 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_81_n_0 CARRY4 (Prop_carry4_CI_CO[3]) 0.060 6.392 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_58/CO[3] net (fo=1, unplaced) 0.000 6.392 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_58_n_0 CARRY4 (Prop_carry4_CI_CO[3]) 0.060 6.452 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_36/CO[3] net (fo=1, unplaced) 0.000 6.452 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_36_n_0 CARRY4 (Prop_carry4_CI_CO[3]) 0.060 6.512 f tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_20/CO[3] net (fo=2, unplaced) 0.594 7.106 txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst/txt_buffer_fsm_inst/FSM_sequential_curr_state[2]_i_4__1[0] LUT4 (Prop_lut4_I2_O) 0.053 7.159 f txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst/txt_buffer_fsm_inst/FSM_sequential_curr_state[2]_i_11__1/O net (fo=5, unplaced) 0.368 7.527 tx_arbitrator_inst/tx_arbitrator_fsm_inst/timestamp_valid LUT6 (Prop_lut6_I4_O) 0.053 7.580 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_24/O net (fo=1, unplaced) 0.340 7.920 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_24_n_0 LUT6 (Prop_lut6_I5_O) 0.053 7.973 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_14__0/O net (fo=1, unplaced) 0.340 8.313 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_14__0_n_0 LUT6 (Prop_lut6_I0_O) 0.053 8.366 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_5__1/O net (fo=3, unplaced) 0.358 8.724 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_5__1_n_0 LUT5 (Prop_lut5_I3_O) 0.053 8.777 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[0]_i_1__1/O net (fo=1, unplaced) 0.000 8.777 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[0]_i_1__1_n_0 FDCE r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]/D ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 10.000 10.000 r 0.000 10.000 r clk_sys (IN) ideal clock network latency 2.000 12.000 net (fo=0) 0.000 12.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 12.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 12.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 12.000 r clk_sys_IBUF_BUFG_inst/O net (fo=965, unplaced) 0.000 12.000 tx_arbitrator_inst/tx_arbitrator_fsm_inst/clk_sys_IBUF_BUFG FDCE r tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]/C clock pessimism 0.000 12.000 clock uncertainty -0.035 11.965 FDCE (Setup_fdce_C_D) 0.037 12.002 tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0] ------------------------------------------------------------------- required time 12.002 arrival time -8.777 ------------------------------------------------------------------- slack 3.224 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.206ns (arrival time - required time) Source: tx_arbitrator_inst/last_txtb_index_reg[0]/C (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: tx_arbitrator_inst/last_txtb_index_reg[0]/D (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: SYS_CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (SYS_CLK rise@0.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 0.271ns (logic 0.164ns (60.596%) route 0.107ns (39.404%)) Logic Levels: 1 (LUT6=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=965, unplaced) 0.000 2.000 tx_arbitrator_inst/clk_sys_IBUF_BUFG FDCE r tx_arbitrator_inst/last_txtb_index_reg[0]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.100 2.100 r tx_arbitrator_inst/last_txtb_index_reg[0]/Q net (fo=2, unplaced) 0.107 2.207 tx_arbitrator_inst/tx_arbitrator_fsm_inst/last_txtb_index[0] LUT6 (Prop_lut6_I5_O) 0.064 2.271 r tx_arbitrator_inst/tx_arbitrator_fsm_inst/last_txtb_index[0]_i_1/O net (fo=1, unplaced) 0.000 2.271 tx_arbitrator_inst/tx_arbitrator_fsm_inst_n_17 FDCE r tx_arbitrator_inst/last_txtb_index_reg[0]/D ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=965, unplaced) 0.000 2.000 tx_arbitrator_inst/clk_sys_IBUF_BUFG FDCE r tx_arbitrator_inst/last_txtb_index_reg[0]/C clock pessimism 0.000 2.000 FDCE (Hold_fdce_C_D) 0.065 2.065 tx_arbitrator_inst/last_txtb_index_reg[0] ------------------------------------------------------------------- required time -2.065 arrival time 2.271 ------------------------------------------------------------------- slack 0.206 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: SYS_CLK Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_sys } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 10.000 7.505 rx_buffer_inst/rx_buffer_ram_inst/dp_inf_ram_inst/ram_rst_false_gen.ram_memory_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/C High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/C --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: SYS_CLK To Clock: SYS_CLK Setup : 0 Failing Endpoints, Worst Slack 2.503ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.616ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.503ns (required time - arrival time) Source: scan_enable (input port clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/CLR (recovery check against rising-edge clock SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (SYS_CLK rise@10.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 2.203ns (logic 0.883ns (40.066%) route 1.321ns (59.934%)) Logic Levels: 2 (IBUF=1 LUT3=1) Input Delay: 5.000ns Clock Path Skew: 2.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.000ns = ( 12.000 - 10.000 ) Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r ideal clock network latency 2.000 2.000 input delay 5.000 7.000 0.000 7.000 r scan_enable (IN) net (fo=0) 0.000 7.000 scan_enable IBUF (Prop_ibuf_I_O) 0.830 7.830 r scan_enable_IBUF_inst/O net (fo=10, unplaced) 0.584 8.413 memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/scan_enable_IBUF LUT3 (Prop_lut3_I1_O) 0.053 8.466 f memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/FSM_onehot_curr_state[11]_i_3/O net (fo=531, unplaced) 0.737 9.203 bus_sampling_inst/bit_err_detector_inst/bit_err_ssp_capt_q_reg_0 FDCE f bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/CLR ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 10.000 10.000 r 0.000 10.000 r clk_sys (IN) ideal clock network latency 2.000 12.000 net (fo=0) 0.000 12.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 12.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 12.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 12.000 r clk_sys_IBUF_BUFG_inst/O net (fo=965, unplaced) 0.000 12.000 bus_sampling_inst/bit_err_detector_inst/clk_sys_IBUF_BUFG FDCE r bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/C clock pessimism 0.000 12.000 clock uncertainty -0.035 11.965 FDCE (Recov_fdce_C_CLR) -0.258 11.707 bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg ------------------------------------------------------------------- required time 11.707 arrival time -9.203 ------------------------------------------------------------------- slack 2.503 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.616ns (arrival time - required time) Source: rst_sync_inst/rst_reg/C (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: memory_registers_inst/control_registers_cs_reg_reg/CLR (removal check against rising-edge clock SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (SYS_CLK rise@0.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 0.545ns (logic 0.164ns (30.112%) route 0.381ns (69.888%)) Logic Levels: 1 (LUT1=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=965, unplaced) 0.000 2.000 rst_sync_inst/clk_sys_IBUF_BUFG FDCE r rst_sync_inst/rst_reg/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.100 2.100 r rst_sync_inst/rst_reg/Q net (fo=11, unplaced) 0.121 2.221 rst_sync_inst/res_n_out LUT1 (Prop_lut1_I0_O) 0.064 2.285 f rst_sync_inst/reg_q_i_2__0/O net (fo=3, unplaced) 0.259 2.545 memory_registers_inst/reg_q_reg_3 FDCE f memory_registers_inst/control_registers_cs_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=965, unplaced) 0.000 2.000 memory_registers_inst/clk_sys_IBUF_BUFG FDCE r memory_registers_inst/control_registers_cs_reg_reg/C clock pessimism 0.000 2.000 FDCE (Remov_fdce_C_CLR) -0.071 1.929 memory_registers_inst/control_registers_cs_reg_reg ------------------------------------------------------------------- required time -1.929 arrival time 2.545 ------------------------------------------------------------------- slack 0.616 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Fri Apr 10 21:29:43 2026 | Host : fedora running 64-bit unknown | Command : report_utilization | Design : can_top_level | Device : xc7k70tfbv676-1 | Speed File : -1 | Design State : Optimized --------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type 2. Memory 3. DSP 4. IO and GT Specific 5. Clocking 6. Specific Feature 7. Primitives 8. Black Boxes 9. Instantiated Netlists 1. Slice Logic -------------- +-------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+------+-------+------------+-----------+-------+ | Slice LUTs* | 1785 | 0 | 0 | 41000 | 4.35 | | LUT as Logic | 1785 | 0 | 0 | 41000 | 4.35 | | LUT as Memory | 0 | 0 | 0 | 13400 | 0.00 | | Slice Registers | 959 | 0 | 0 | 82000 | 1.17 | | Register as Flip Flop | 959 | 0 | 0 | 82000 | 1.17 | | Register as Latch | 0 | 0 | 0 | 82000 | 0.00 | | F7 Muxes | 65 | 0 | 0 | 20500 | 0.32 | | F8 Muxes | 6 | 0 | 0 | 10250 | 0.06 | | Unique Control Sets | 80 | | 0 | 10250 | 0.78 | +-------------------------+------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. Warning! LUT value is adjusted to account for LUT combining. Warning! For any ECO changes, please run place_design if there are unplaced instances ** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. 1.1 Summary of Registers by Type -------------------------------- +-------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +-------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 89 | Yes | - | Set | | 870 | Yes | - | Reset | | 0 | Yes | Set | - | | 0 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. Memory --------- +-------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------+------+-------+------------+-----------+-------+ | Block RAM Tile | 1.5 | 0 | 0 | 135 | 1.11 | | RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 | | RAMB18 | 3 | 0 | 0 | 270 | 1.11 | | RAMB18E1 only | 3 | | | | | +-------------------+------+-------+------------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 3. DSP ------ +-----------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------+------+-------+------------+-----------+-------+ | DSPs | 0 | 0 | 0 | 240 | 0.00 | +-----------+------+-------+------------+-----------+-------+ 4. IO and GT Specific --------------------- +-----------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------------------+------+-------+------------+-----------+-------+ | Bonded IOB | 155 | 0 | 0 | 300 | 51.67 | | Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 | | Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 | | PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 6 | 0.00 | | OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 | | IN_FIFO | 0 | 0 | 0 | 24 | 0.00 | | IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 | | IBUFDS | 0 | 0 | 0 | 288 | 0.00 | | GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 | | GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 | | ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 | | IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 | | ILOGIC | 0 | 0 | 0 | 300 | 0.00 | | OLOGIC | 0 | 0 | 0 | 300 | 0.00 | +-----------------------------+------+-------+------------+-----------+-------+ 5. Clocking ----------- +------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------+------+-------+------------+-----------+-------+ | BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | | BUFIO | 0 | 0 | 0 | 24 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 | | PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 | | BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | | BUFHCE | 0 | 0 | 0 | 96 | 0.00 | | BUFR | 0 | 0 | 0 | 24 | 0.00 | +------------+------+-------+------------+-----------+-------+ 6. Specific Feature ------------------- +-------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------+------+-------+------------+-----------+-------+ | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | | PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | | XADC | 0 | 0 | 0 | 1 | 0.00 | +-------------+------+-------+------------+-----------+-------+ 7. Primitives ------------- +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ | FDCE | 870 | Flop & Latch | | LUT6 | 867 | LUT | | LUT5 | 419 | LUT | | LUT4 | 335 | LUT | | LUT2 | 295 | LUT | | LUT3 | 219 | LUT | | IBUF | 117 | IO | | FDPE | 89 | Flop & Latch | | CARRY4 | 71 | CarryLogic | | MUXF7 | 65 | MuxFx | | OBUF | 38 | IO | | LUT1 | 13 | LUT | | MUXF8 | 6 | MuxFx | | RAMB18E1 | 3 | Block Memory | | BUFG | 1 | Clock | +----------+------+---------------------+ 8. Black Boxes -------------- +----------+------+ | Ref Name | Used | +----------+------+ 9. Instantiated Netlists ------------------------ +----------+------+ | Ref Name | Used | +----------+------+ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Fri Apr 10 21:29:43 2026 | Host : fedora running 64-bit unknown | Command : report_utilization -hierarchical -hierarchical_percentages | Design : can_top_level | Device : xc7k70tfbv676-1 | Speed File : -1 | Design State : Optimized --------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-----------------------------------------------------------+---------------------------+-------------+-------------+----------+----------+------------+----------+----------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-----------------------------------------------------------+---------------------------+-------------+-------------+----------+----------+------------+----------+----------+------------+ | can_top_level | (top) | 1785(4.35%) | 1785(4.35%) | 0(0.00%) | 0(0.00%) | 959(1.17%) | 0(0.00%) | 3(1.11%) | 0(0.00%) | | (can_top_level) | (top) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bus_sampling_inst | bus_sampling | 99(0.24%) | 99(0.24%) | 0(0.00%) | 0(0.00%) | 84(0.10%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | ssp_generator_inst | ssp_generator | 61(0.15%) | 61(0.15%) | 0(0.00%) | 0(0.00%) | 33(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | can_core_inst | can_core | 775(1.89%) | 775(1.89%) | 0(0.00%) | 0(0.00%) | 327(0.40%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | can_crc_inst | can_crc | 56(0.14%) | 56(0.14%) | 0(0.00%) | 0(0.00%) | 53(0.06%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | fault_confinement_inst | fault_confinement | 165(0.40%) | 165(0.40%) | 0(0.00%) | 0(0.00%) | 58(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (err_counters_inst) | err_counters | 148(0.36%) | 148(0.36%) | 0(0.00%) | 0(0.00%) | 54(0.07%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_control_inst | protocol_control | 496(1.21%) | 496(1.21%) | 0(0.00%) | 0(0.00%) | 190(0.23%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | protocol_control_fsm_inst | protocol_control_fsm | 408(1.00%) | 408(1.00%) | 0(0.00%) | 0(0.00%) | 35(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_shift_reg_inst | rx_shift_reg | 30(0.07%) | 30(0.07%) | 0(0.00%) | 0(0.00%) | 75(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | int_manager_inst | int_manager | 84(0.20%) | 84(0.20%) | 0(0.00%) | 0(0.00%) | 37(0.05%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | memory_registers_inst | memory_registers | 274(0.67%) | 274(0.67%) | 0(0.00%) | 0(0.00%) | 198(0.24%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | control_registers_reg_map_comp | control_registers_reg_map | 270(0.66%) | 270(0.66%) | 0(0.00%) | 0(0.00%) | 195(0.24%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | prescaler_inst | prescaler | 146(0.36%) | 146(0.36%) | 0(0.00%) | 0(0.00%) | 74(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | bit_time_fsm_inst | bit_time_fsm | 56(0.14%) | 56(0.14%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_buffer_inst | rx_buffer | 197(0.48%) | 197(0.48%) | 0(0.00%) | 0(0.00%) | 122(0.15%) | 0(0.00%) | 1(0.37%) | 0(0.00%) | | (rx_buffer_inst) | rx_buffer | 6(0.01%) | 6(0.01%) | 0(0.00%) | 0(0.00%) | 77(0.09%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_buffer_fsm_inst | rx_buffer_fsm | 96(0.23%) | 96(0.23%) | 0(0.00%) | 0(0.00%) | 12(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | rx_buffer_pointers_inst | rx_buffer_pointers | 60(0.15%) | 60(0.15%) | 0(0.00%) | 0(0.00%) | 32(0.04%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_arbitrator_inst | tx_arbitrator | 115(0.28%) | 115(0.28%) | 0(0.00%) | 0(0.00%) | 104(0.13%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | (tx_arbitrator_inst) | tx_arbitrator | 46(0.11%) | 46(0.11%) | 0(0.00%) | 0(0.00%) | 100(0.12%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | tx_arbitrator_fsm_inst | tx_arbitrator_fsm | 69(0.17%) | 69(0.17%) | 0(0.00%) | 0(0.00%) | 4(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | | txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst | txt_buffer_odd | 88(0.21%) | 88(0.21%) | 0(0.00%) | 0(0.00%) | 6(0.01%) | 0(0.00%) | 1(0.37%) | 0(0.00%) | | txt_buffer_fsm_inst | txt_buffer_fsm | 85(0.21%) | 85(0.21%) | 0(0.00%) | 0(0.00%) | 3(0.01%) | 0(0.00%) | 0(0.00%) | 0(0.00%) | +-----------------------------------------------------------+---------------------------+-------------+-------------+----------+----------+------------+----------+----------+------------+ INFO: [Vivado 12-4103] The output of -include_unisim and -include_xilinx_libs does not include secure primitives. Please incorporate them manually. INFO: [Vivado 12-4103] The output of -include_unisim and -include_xilinx_libs does not include secure primitives. Please incorporate them manually.