INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date         : Fri Apr 10 21:29:43 2026
| Host         : fedora running 64-bit unknown
| Command      : report_timing_summary
| Design       : can_top_level
| Device       : 7k70t-fbv676
| Speed File   : -1  PRODUCTION 1.12 2017-02-17
| Design State : Optimized
---------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (2)
6. checking no_output_delay (3)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (2)
------------------------------
 There are 0 input ports with no input delay specified.

 There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM)


6. checking no_output_delay (3)
-------------------------------
 There are 0 ports with no output delay specified.

 There are 3 ports with no output delay but user has a false path constraint (MEDIUM)

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      2.503        0.000                      0                 2870        0.206        0.000                      0                 2870        4.650        0.000                       0                   966  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock    Waveform(ns)       Period(ns)      Frequency(MHz)
-----    ------------       ----------      --------------
SYS_CLK  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
SYS_CLK             3.224        0.000                      0                 1914        0.206        0.000                      0                 1914        4.650        0.000                       0                   966  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**  SYS_CLK            SYS_CLK                  2.503        0.000                      0                  956        0.616        0.000                      0                  956  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  SYS_CLK
  To Clock:  SYS_CLK

Setup :            0  Failing Endpoints,  Worst Slack        3.224ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.206ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.650ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.224ns  (required time - arrival time)
  Source:                 timestamp[1]
                            (input port clocked by SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             SYS_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (SYS_CLK rise@10.000ns - SYS_CLK rise@0.000ns)
  Data Path Delay:        4.277ns  (logic 1.694ns (39.599%)  route 2.584ns (60.401%))
  Logic Levels:           11  (CARRY4=4 IBUF=1 LUT4=2 LUT5=1 LUT6=3)
  Input Delay:            2.500ns
  Clock Path Skew:        2.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.000ns = ( 12.000 - 10.000 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock SYS_CLK rise edge)    0.000     0.000 r  
                         ideal clock network latency
                                                      2.000     2.000    
                         input delay                  2.500     4.500    
                                                      0.000     4.500 r  timestamp[1] (IN)
                         net (fo=0)                   0.000     4.500    timestamp[1]
                         IBUF (Prop_ibuf_I_O)         0.830     5.330 r  timestamp_IBUF[1]_inst/O
                         net (fo=4, unplaced)         0.584     5.913    tx_arbitrator_inst/tx_arbitrator_fsm_inst/timestamp_IBUF[1]
                         LUT4 (Prop_lut4_I0_O)        0.066     5.979 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_105/O
                         net (fo=1, unplaced)         0.000     5.979    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_105_n_0
                         CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.353     6.332 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_81/CO[3]
                         net (fo=1, unplaced)         0.000     6.332    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_81_n_0
                         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.060     6.392 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_58/CO[3]
                         net (fo=1, unplaced)         0.000     6.392    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_58_n_0
                         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.060     6.452 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_36/CO[3]
                         net (fo=1, unplaced)         0.000     6.452    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_36_n_0
                         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.060     6.512 f  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[2]_i_20/CO[3]
                         net (fo=2, unplaced)         0.594     7.106    txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst/txt_buffer_fsm_inst/FSM_sequential_curr_state[2]_i_4__1[0]
                         LUT4 (Prop_lut4_I2_O)        0.053     7.159 f  txt_buf_comp_gen[1].txt_buf_odd_gen.txt_buffer_odd_inst/txt_buffer_fsm_inst/FSM_sequential_curr_state[2]_i_11__1/O
                         net (fo=5, unplaced)         0.368     7.527    tx_arbitrator_inst/tx_arbitrator_fsm_inst/timestamp_valid
                         LUT6 (Prop_lut6_I4_O)        0.053     7.580 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_24/O
                         net (fo=1, unplaced)         0.340     7.920    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_24_n_0
                         LUT6 (Prop_lut6_I5_O)        0.053     7.973 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_14__0/O
                         net (fo=1, unplaced)         0.340     8.313    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_14__0_n_0
                         LUT6 (Prop_lut6_I0_O)        0.053     8.366 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_5__1/O
                         net (fo=3, unplaced)         0.358     8.724    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[2]_i_5__1_n_0
                         LUT5 (Prop_lut5_I3_O)        0.053     8.777 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[0]_i_1__1/O
                         net (fo=1, unplaced)         0.000     8.777    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state[0]_i_1__1_n_0
                         FDCE                                         r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock SYS_CLK rise edge)   10.000    10.000 r  
                                                      0.000    10.000 r  clk_sys (IN)
                         ideal clock network latency
                                                      2.000    12.000    
                         net (fo=0)                   0.000    12.000    clk_sys
                         IBUF (Prop_ibuf_I_O)         0.000    12.000 r  clk_sys_IBUF_inst/O
                         net (fo=1, unplaced)         0.000    12.000    clk_sys_IBUF
                         BUFG (Prop_bufg_I_O)         0.000    12.000 r  clk_sys_IBUF_BUFG_inst/O
                         net (fo=965, unplaced)       0.000    12.000    tx_arbitrator_inst/tx_arbitrator_fsm_inst/clk_sys_IBUF_BUFG
                         FDCE                                         r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]/C
                         clock pessimism              0.000    12.000    
                         clock uncertainty           -0.035    11.965    
                         FDCE (Setup_fdce_C_D)        0.037    12.002    tx_arbitrator_inst/tx_arbitrator_fsm_inst/FSM_sequential_curr_state_reg[0]
  -------------------------------------------------------------------
                         required time                         12.002    
                         arrival time                          -8.777    
  -------------------------------------------------------------------
                         slack                                  3.224    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.206ns  (arrival time - required time)
  Source:                 tx_arbitrator_inst/last_txtb_index_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            tx_arbitrator_inst/last_txtb_index_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             SYS_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (SYS_CLK rise@0.000ns - SYS_CLK rise@0.000ns)
  Data Path Delay:        0.271ns  (logic 0.164ns (60.596%)  route 0.107ns (39.404%))
  Logic Levels:           1  (LUT6=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock SYS_CLK rise edge)    0.000     0.000 r  
                                                      0.000     0.000 r  clk_sys (IN)
                         ideal clock network latency
                                                      2.000     2.000    
                         net (fo=0)                   0.000     2.000    clk_sys
                         IBUF (Prop_ibuf_I_O)         0.000     2.000 r  clk_sys_IBUF_inst/O
                         net (fo=1, unplaced)         0.000     2.000    clk_sys_IBUF
                         BUFG (Prop_bufg_I_O)         0.000     2.000 r  clk_sys_IBUF_BUFG_inst/O
                         net (fo=965, unplaced)       0.000     2.000    tx_arbitrator_inst/clk_sys_IBUF_BUFG
                         FDCE                                         r  tx_arbitrator_inst/last_txtb_index_reg[0]/C
  -------------------------------------------------------------------    -------------------
                         FDCE (Prop_fdce_C_Q)         0.100     2.100 r  tx_arbitrator_inst/last_txtb_index_reg[0]/Q
                         net (fo=2, unplaced)         0.107     2.207    tx_arbitrator_inst/tx_arbitrator_fsm_inst/last_txtb_index[0]
                         LUT6 (Prop_lut6_I5_O)        0.064     2.271 r  tx_arbitrator_inst/tx_arbitrator_fsm_inst/last_txtb_index[0]_i_1/O
                         net (fo=1, unplaced)         0.000     2.271    tx_arbitrator_inst/tx_arbitrator_fsm_inst_n_17
                         FDCE                                         r  tx_arbitrator_inst/last_txtb_index_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock SYS_CLK rise edge)    0.000     0.000 r  
                                                      0.000     0.000 r  clk_sys (IN)
                         ideal clock network latency
                                                      2.000     2.000    
                         net (fo=0)                   0.000     2.000    clk_sys
                         IBUF (Prop_ibuf_I_O)         0.000     2.000 r  clk_sys_IBUF_inst/O
                         net (fo=1, unplaced)         0.000     2.000    clk_sys_IBUF
                         BUFG (Prop_bufg_I_O)         0.000     2.000 r  clk_sys_IBUF_BUFG_inst/O
                         net (fo=965, unplaced)       0.000     2.000    tx_arbitrator_inst/clk_sys_IBUF_BUFG
                         FDCE                                         r  tx_arbitrator_inst/last_txtb_index_reg[0]/C
                         clock pessimism              0.000     2.000    
                         FDCE (Hold_fdce_C_D)         0.065     2.065    tx_arbitrator_inst/last_txtb_index_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.065    
                         arrival time                           2.271    
  -------------------------------------------------------------------
                         slack                                  0.206    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         SYS_CLK
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clk_sys }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location  Pin
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.495         10.000      7.505                rx_buffer_inst/rx_buffer_ram_inst/dp_inf_ram_inst/ram_rst_false_gen.ram_memory_reg/CLKARDCLK
Low Pulse Width   Slow    FDCE/C              n/a            0.350         5.000       4.650                bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/C
High Pulse Width  Slow    FDCE/C              n/a            0.350         5.000       4.650                bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/C



---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  SYS_CLK
  To Clock:  SYS_CLK

Setup :            0  Failing Endpoints,  Worst Slack        2.503ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.616ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.503ns  (required time - arrival time)
  Source:                 scan_enable
                            (input port clocked by SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/CLR
                            (recovery check against rising-edge clock SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (SYS_CLK rise@10.000ns - SYS_CLK rise@0.000ns)
  Data Path Delay:        2.203ns  (logic 0.883ns (40.066%)  route 1.321ns (59.934%))
  Logic Levels:           2  (IBUF=1 LUT3=1)
  Input Delay:            5.000ns
  Clock Path Skew:        2.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.000ns = ( 12.000 - 10.000 ) 
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock SYS_CLK rise edge)    0.000     0.000 r  
                         ideal clock network latency
                                                      2.000     2.000    
                         input delay                  5.000     7.000    
                                                      0.000     7.000 r  scan_enable (IN)
                         net (fo=0)                   0.000     7.000    scan_enable
                         IBUF (Prop_ibuf_I_O)         0.830     7.830 r  scan_enable_IBUF_inst/O
                         net (fo=10, unplaced)        0.584     8.413    memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/scan_enable_IBUF
                         LUT3 (Prop_lut3_I1_O)        0.053     8.466 f  memory_registers_inst/global_rst_rst_reg_inst/rx_shift_res_reg_inst/FSM_onehot_curr_state[11]_i_3/O
                         net (fo=531, unplaced)       0.737     9.203    bus_sampling_inst/bit_err_detector_inst/bit_err_ssp_capt_q_reg_0
                         FDCE                                         f  bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock SYS_CLK rise edge)   10.000    10.000 r  
                                                      0.000    10.000 r  clk_sys (IN)
                         ideal clock network latency
                                                      2.000    12.000    
                         net (fo=0)                   0.000    12.000    clk_sys
                         IBUF (Prop_ibuf_I_O)         0.000    12.000 r  clk_sys_IBUF_inst/O
                         net (fo=1, unplaced)         0.000    12.000    clk_sys_IBUF
                         BUFG (Prop_bufg_I_O)         0.000    12.000 r  clk_sys_IBUF_BUFG_inst/O
                         net (fo=965, unplaced)       0.000    12.000    bus_sampling_inst/bit_err_detector_inst/clk_sys_IBUF_BUFG
                         FDCE                                         r  bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg/C
                         clock pessimism              0.000    12.000    
                         clock uncertainty           -0.035    11.965    
                         FDCE (Recov_fdce_C_CLR)     -0.258    11.707    bus_sampling_inst/bit_err_detector_inst/bit_err_q_reg
  -------------------------------------------------------------------
                         required time                         11.707    
                         arrival time                          -9.203    
  -------------------------------------------------------------------
                         slack                                  2.503    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.616ns  (arrival time - required time)
  Source:                 rst_sync_inst/rst_reg/C
                            (rising edge-triggered cell FDCE clocked by SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            memory_registers_inst/control_registers_cs_reg_reg/CLR
                            (removal check against rising-edge clock SYS_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (SYS_CLK rise@0.000ns - SYS_CLK rise@0.000ns)
  Data Path Delay:        0.545ns  (logic 0.164ns (30.112%)  route 0.381ns (69.888%))
  Logic Levels:           1  (LUT1=1)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock SYS_CLK rise edge)    0.000     0.000 r  
                                                      0.000     0.000 r  clk_sys (IN)
                         ideal clock network latency
                                                      2.000     2.000    
                         net (fo=0)                   0.000     2.000    clk_sys
                         IBUF (Prop_ibuf_I_O)         0.000     2.000 r  clk_sys_IBUF_inst/O
                         net (fo=1, unplaced)         0.000     2.000    clk_sys_IBUF
                         BUFG (Prop_bufg_I_O)         0.000     2.000 r  clk_sys_IBUF_BUFG_inst/O
                         net (fo=965, unplaced)       0.000     2.000    rst_sync_inst/clk_sys_IBUF_BUFG
                         FDCE                                         r  rst_sync_inst/rst_reg/C
  -------------------------------------------------------------------    -------------------
                         FDCE (Prop_fdce_C_Q)         0.100     2.100 r  rst_sync_inst/rst_reg/Q
                         net (fo=11, unplaced)        0.121     2.221    rst_sync_inst/res_n_out
                         LUT1 (Prop_lut1_I0_O)        0.064     2.285 f  rst_sync_inst/reg_q_i_2__0/O
                         net (fo=3, unplaced)         0.259     2.545    memory_registers_inst/reg_q_reg_3
                         FDCE                                         f  memory_registers_inst/control_registers_cs_reg_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock SYS_CLK rise edge)    0.000     0.000 r  
                                                      0.000     0.000 r  clk_sys (IN)
                         ideal clock network latency
                                                      2.000     2.000    
                         net (fo=0)                   0.000     2.000    clk_sys
                         IBUF (Prop_ibuf_I_O)         0.000     2.000 r  clk_sys_IBUF_inst/O
                         net (fo=1, unplaced)         0.000     2.000    clk_sys_IBUF
                         BUFG (Prop_bufg_I_O)         0.000     2.000 r  clk_sys_IBUF_BUFG_inst/O
                         net (fo=965, unplaced)       0.000     2.000    memory_registers_inst/clk_sys_IBUF_BUFG
                         FDCE                                         r  memory_registers_inst/control_registers_cs_reg_reg/C
                         clock pessimism              0.000     2.000    
                         FDCE (Remov_fdce_C_CLR)     -0.071     1.929    memory_registers_inst/control_registers_cs_reg_reg
  -------------------------------------------------------------------
                         required time                         -1.929    
                         arrival time                           2.545    
  -------------------------------------------------------------------
                         slack                                  0.616    





