File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_rules.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Fault confinement rules.
71: --
72: -- Purpose:
73: -- Implement fault confinement rules for incrementing and decrementing Fault
74: -- confinement error counters. Controlled by Protocol control via standardized
75: -- interface as described in ISO 11898-1 2015.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: entity fault_confinement_rules is
90: port (
91: -------------------------------------------------------------------------------------------
92: -- Clock
93: -------------------------------------------------------------------------------------------
94: -- System clock, only for PSL assertions
95: clk_sys : in std_logic;
96:
97: -------------------------------------------------------------------------------------------
98: -- Operation control interface
99: -------------------------------------------------------------------------------------------
100: -- Unit is transmitter
101: is_transmitter : in std_logic;
102:
103: -- Unit is receiver
104: is_receiver : in std_logic;
105:
106: -------------------------------------------------------------------------------------------
107: -- Protocol Control interface
108: -------------------------------------------------------------------------------------------
109: -- Error is detected
110: err_detected : in std_logic;
111:
112: -- Error counter should remain unchanged
113: err_ctrs_unchanged : in std_logic;
114:
115: -- Primary Error
116: primary_err : in std_logic;
117:
118: -- Active Error Flag or Overload flag is being tranmsmitted
119: act_err_ovr_flag : in std_logic;
120:
121: -- Error delimiter too late
122: err_delim_late : in std_logic;
123:
124: -- Transmission of frame valid
125: tran_valid : in std_logic;
126:
127: -- Decrement receive Error counter
128: decrement_rec : in std_logic;
129:
130: -- Bit Error in passive error flag after ACK error
131: bit_err_after_ack_err : in std_logic;
132:
133: -------------------------------------------------------------------------------------------
134: -- Memory registers interface
135: -------------------------------------------------------------------------------------------
136: mr_mode_rom : in std_logic;
137:
138: -------------------------------------------------------------------------------------------
139: -- Output signals to error counters
140: -------------------------------------------------------------------------------------------
141: -- Increment Error counter by 1
142: inc_one : out std_logic;
143:
144: -- Increment Error counter by 8
145: inc_eight : out std_logic;
146:
147: -- Decrement Error counter by 1
148: dec_one : out std_logic
149: );
150: end entity;
151:
152: architecture rtl of fault_confinement_rules is
153:
154: signal inc_one_i : std_logic;
155: signal inc_eight_i : std_logic;
156:
157: begin
158:
159: -----------------------------------------------------------------------------------------------
160: -- Increment RX Error counter by 1 when Receiver detects an error which is not during Active
161: -- Error flag or Overload flag!
162: -----------------------------------------------------------------------------------------------
163: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')
164: else
165: '0';
166:
167: -----------------------------------------------------------------------------------------------
168: -- Increment by 8:
169: -- - Receiver detects DOMINANT bit as first bit after sending and Error flag (rule "b")
170: -- - Transmitter/Receiver detect a bit error while sending Active Error flag or an Overload
171: -- flag! Note that other than bit error can't be signalled in Error Flag on 'err_detected'!
172: -- (rules "d" and "e")
173: -- - Transmitter sends Error flag but non of the exceptions are valid (rule "c")
174: -- - Error delimiter comes too late (more than 14 consecutive bits), (rule "f")
175: -- - ACK Error followed by bit error during passive error frame!
176: -----------------------------------------------------------------------------------------------
177: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else
178: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else
179: '1' when (is_transmitter = '1' and
180: err_detected = '1' and
181: err_ctrs_unchanged = '0') else
182: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else
183: '0';
184:
185: -----------------------------------------------------------------------------------------------
186: -- Decrement by 1 when either transmission or reception is valid
187: -----------------------------------------------------------------------------------------------
188: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')
189: else
190: '0';
191:
192: -----------------------------------------------------------------------------------------------
193: -- Gating by ROM mode. In ROM mode, Error counters shall not increment.
194: -- Decrement does not need to be gated since the counter will stay at 0!
195: -----------------------------------------------------------------------------------------------
196: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)
197: else
198: '0';
199: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)
200: else
201: '0';
202:
203: end architecture;