File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/reintegration_counter.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Re-integration counter.
71: --
72: -- Purpose:
73: -- Counts number of ocurrences of 11 consecutive bits to measure re-integration
74: -- after unit went bus-off. Controlled by Protocol control FSM.
75: --------------------------------------------------------------------------------
76:
77: Library ieee;
78: use ieee.std_logic_1164.all;
79: use ieee.numeric_std.ALL;
80:
81: Library ctu_can_fd_rtl;
82: use ctu_can_fd_rtl.can_constants_pkg.all;
83: use ctu_can_fd_rtl.can_types_pkg.all;
84:
85: use ctu_can_fd_rtl.CAN_FD_register_map.all;
86: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
87:
88: entity reintegration_counter is
89: port (
90: -------------------------------------------------------------------------------------------
91: -- Clock and Asynchronous Reset
92: -------------------------------------------------------------------------------------------
93: clk_sys : in std_logic;
94: res_n : in std_logic;
95:
96: -------------------------------------------------------------------------------------------
97: -- Control signals
98: -------------------------------------------------------------------------------------------
99: -- Clear (synchronous)
100: reinteg_ctr_clr : in std_logic;
101:
102: -- Enable counting (with RX Trigger)
103: reinteg_ctr_enable : in std_logic;
104:
105: -- RX Trigger
106: rx_trigger : in std_logic;
107:
108: -------------------------------------------------------------------------------------------
109: -- Status signals
110: -------------------------------------------------------------------------------------------
111: -- Integration counter expired.
112: reinteg_ctr_expired : out std_logic
113: );
114: end entity;
115:
116: architecture rtl of reintegration_counter is
117:
118: -- Retransmitt limit counter
119: signal reinteg_ctr_d : unsigned(7 downto 0);
120: signal reinteg_ctr_q : unsigned(7 downto 0);
121:
122: -- Clock enable
123: signal reinteg_ctr_ce : std_logic;
124:
125: begin
126:
127: -- Next value
128: reinteg_ctr_d <= (others => '0') when (reinteg_ctr_clr = '1')
129: else
130: reinteg_ctr_q + 1;
131:
132: -- Clock enable
133: reinteg_ctr_ce <= '1' when (reinteg_ctr_clr = '1' or
134: (reinteg_ctr_enable = '1' and rx_trigger = '1'))
135: else
136: '0';
137:
138: -- Counter is expired when 128 is reached (counted 129 * 11 bits)
139: reinteg_ctr_expired <= '1' when (reinteg_ctr_q = 128)
140: else
141: '0';
142:
143: -----------------------------------------------------------------------------------------------
144: -- Counter register
145: -----------------------------------------------------------------------------------------------
146: retr_ctr_reg_proc : process(clk_sys, res_n)
147: begin
148: if (res_n = '0') then
149: reinteg_ctr_q <= (others => '0');
150: elsif (rising_edge(clk_sys)) then
151: if (reinteg_ctr_ce = '1') then
152: reinteg_ctr_q <= reinteg_ctr_d;
153: end if;
154: end if;
155: end process;
156:
157: end architecture;