File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/crc_calc.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Generic CRC calculation module.
71: --
72: -- Purpose:
73: -- Calculates CRC sequence of generic length from Serial Data input. Processes
74: -- input data with trigger signal only when enabled. CRC value remains on
75: -- output when module is disabled. Upon start of calculation, CRC register
76: -- is loaded with initial value.
77: --------------------------------------------------------------------------------
78:
79: Library ieee;
80: use ieee.std_logic_1164.all;
81: use ieee.numeric_std.ALL;
82:
83: Library ctu_can_fd_rtl;
84: use ctu_can_fd_rtl.can_constants_pkg.all;
85: use ctu_can_fd_rtl.can_types_pkg.all;
86:
87: use ctu_can_fd_rtl.CAN_FD_register_map.all;
88: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
89:
90: entity crc_calc is
91: generic (
92: -- Width of CRC sequence
93: G_CRC_WIDTH : natural;
94:
95: -- CRC Polynomial
96: G_POLYNOMIAL : std_logic_vector
97: );
98: port (
99: -------------------------------------------------------------------------------------------
100: -- System clock and Asynchronous Reset
101: -------------------------------------------------------------------------------------------
102: clk_sys : in std_logic;
103: res_n : in std_logic;
104:
105: -------------------------------------------------------------------------------------------
106: -- CRC Calculation control
107: -------------------------------------------------------------------------------------------
108: -- Serial data input for CRC calculation
109: data_in : in std_logic;
110:
111: -- Trigger to sample the input data
112: trig : in std_logic;
113:
114: -- CRC calculation enabled
115: enable : in std_logic;
116:
117: -- MSB of Initialization vector for CRC calculation
118: init_vect_msb : in std_logic;
119:
120: -- Load CRC Initialization vector
121: load_init_vect : in std_logic;
122:
123: -------------------------------------------------------------------------------------------
124: -- CRC output
125: -------------------------------------------------------------------------------------------
126: crc : out std_logic_vector(G_CRC_WIDTH - 1 downto 0)
127: );
128: end entity;
129:
130: architecture rtl of crc_calc is
131:
132: -- CRC register
133: signal crc_q : std_logic_vector(G_CRC_WIDTH - 1 downto 0);
134:
135: -- Signal if next value of CRC should be shifted and XORed or only shifted!
136: signal crc_nxt : std_logic;
137:
138: -- Combinational value of next CRC value
139: signal crc_d : std_logic_vector(G_CRC_WIDTH - 1 downto 0);
140:
141: -- Clock enable for CRC register
142: signal crc_ce : std_logic;
143:
144: begin
145:
146: -----------------------------------------------------------------------------------------------
147: -- Calculation of next CRC value
148: -----------------------------------------------------------------------------------------------
149: crc_nxt <= data_in xor crc_q(G_CRC_WIDTH - 1);
150:
151: crc_d_decoder : process(init_vect_msb, load_init_vect, crc_nxt, crc_q)
152: begin
153: if (load_init_vect = '1') then
154: crc_d <= (others => '0');
155: crc_d(G_CRC_WIDTH - 1) <= init_vect_msb;
156: elsif (crc_nxt = '1') then
157: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0') xor
158: G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);
159: else
160: crc_d <= (crc_q(G_CRC_WIDTH - 2 downto 0) & '0');
161: end if;
162: end process;
163:
164: crc_ce <= '1' when (load_init_vect = '1') else
165: '1' when (enable = '1' and trig = '1') else
166: '0';
167:
168: -----------------------------------------------------------------------------------------------
169: -- CRC register
170: -----------------------------------------------------------------------------------------------
171: crc_reg_proc : process(res_n, clk_sys)
172: begin
173: if (res_n = '0') then
174: crc_q <= (others => '0');
175: elsif rising_edge(clk_sys) then
176: if (crc_ce = '1') then
177: crc_q <= crc_d;
178: end if;
179: end if;
180: end process crc_reg_proc;
181:
182: -- Register to output propagation.
183: crc <= crc_q;
184:
185: -----------------------------------------------------------------------------------------------
186: -- Assertions on input settings
187: -----------------------------------------------------------------------------------------------
188:
189: -- psl default clock is rising_edge(clk_sys);
190:
191: -- psl no_simul_load_and_calc_asrt : assert never
192: -- (enable = '1' and trig = '1' and load_init_vect = '1')
193: -- report "Can't load CRC init vector and execute CRC calculation at once!";
194:
195: end architecture;