File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/trigger_generator.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Trigger signals generator.
71: --
72: -- Purpose:
73: -- Trigger signals are active for one clock cycle. There are two trigger
74: -- types in CTU CAN FD implementation:
75: -- 1. RX Triggers - 2 Triggers - Pipeline stages: Destuff and Process
76: -- 2. TX Trigger - 1 Trigger - Pipeline stage: Stuff
77: -- TX trigger is active at the start of bit time and it is used to transmitt
78: -- Data. RX trigger is active in last cycle of TSEG1 and it represents
79: -- sample point! Both triggers are always aligned with Time Quanta!
80: -- Trigger signals are then used for data processing pipeline in CAN
81: -- Datapath (e.g. Bit Stuffing, Bit Destuffing, Processing by CAN Core).
82: -- Trigger signals are demonstrated in following diagram:
83: --
84: -- +------+--------------+-----------+----------+
85: -- | SYNC | PROP | PH1 | PH2 |
86: -- +------+--------------+-----------+----------+
87: -- TX __¯¯____________________________________________¯¯____
88: -- ______________________________________________________
89: -- ____________________________________¯¯________________
90: -- RX ______________________________________¯¯______________
91: -- ______________________________________________________
92: -- Clock _¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_¯_
93:
94: -- Note that trigger signal sequence should always be completed. Due to
95: -- Hard Synchronisation mechanism, Trigger request for e.g. TX Trigger might
96: -- occur still during pipelined RX Trigger signal active. This occurs when
97: -- Hard synchronisation occurs just one clock cycle after Sample point.
98: -- The main task of trigger generator is to generate Triggers from Trigger
99: -- Requests. If a trigger request occurs during previous trigger active,
100: -- Trigger generator buffers the request and processes it only after the
101: -- previous trigger sequence ends. Overall length of bit is maintained, only
102: -- next TX trigger is throttled by one clock cycle.
103: --
104: --------------------------------------------------------------------------------
105:
106: Library ieee;
107: use ieee.std_logic_1164.all;
108: use ieee.numeric_std.ALL;
109:
110: Library ctu_can_fd_rtl;
111: use ctu_can_fd_rtl.can_constants_pkg.all;
112: use ctu_can_fd_rtl.can_types_pkg.all;
113:
114: use ctu_can_fd_rtl.CAN_FD_register_map.all;
115: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
116:
117: entity trigger_generator is
118: generic (
119: -- Number of signals in Sample trigger
120: G_SAMPLE_TRIGGER_COUNT : natural range 2 to 8
121: );
122: port(
123: -------------------------------------------------------------------------------------------
124: -- Clock and Asynchronous reset
125: -------------------------------------------------------------------------------------------
126: clk_sys : in std_logic;
127: res_n : in std_logic;
128:
129: -------------------------------------------------------------------------------------------
130: -- Control signal
131: -------------------------------------------------------------------------------------------
132: -- RX Trigger request (Sample point)
133: rx_trig_req : in std_logic;
134:
135: -- TX Trigger request (Sync)
136: tx_trig_req : in std_logic;
137:
138: -------------------------------------------------------------------------------------------
139: -- Trigger outputs
140: -------------------------------------------------------------------------------------------
141: -- RX Triggers (Two in two following clock cycles)
142: rx_triggers : out std_logic_vector(G_SAMPLE_TRIGGER_COUNT - 1 downto 0);
143:
144: -- TX Trigger
145: tx_trigger : out std_logic
146: );
147: end entity;
148:
149: architecture rtl of trigger_generator is
150:
151: -- Register to create delayed version of Sample Trigger by one clock cycle.
152: signal rx_trig_req_q : std_logic;
153:
154: -----------------------------------------------------------------------------------------------
155: -- Trigger request flag. Set when a request for Sync trigger arrives and another Sample is
156: -- still in progress
157: -----------------------------------------------------------------------------------------------
158: signal tx_trig_req_flag_d : std_logic;
159: signal tx_trig_req_flag_q : std_logic;
160: signal tx_trig_req_flag_dq : std_logic;
161:
162: begin
163:
164: -----------------------------------------------------------------------------------------------
165: -- Sync trigger capture register
166: -----------------------------------------------------------------------------------------------
167: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else
168: '0' when (rx_trig_req_q = '0') else
169: tx_trig_req_flag_q;
170:
171: tx_trig_req_flag_proc : process(clk_sys, res_n)
172: begin
173: if (res_n = '0') then
174: tx_trig_req_flag_q <= '0';
175: elsif (rising_edge(clk_sys)) then
176: tx_trig_req_flag_q <= tx_trig_req_flag_d;
177: end if;
178: end process;
179:
180: tx_trig_req_flag_dq <= tx_trig_req or tx_trig_req_flag_q;
181:
182: -----------------------------------------------------------------------------------------------
183: -- Register to create delayed version of RX Trigger (for processing by Protocol Control)
184: -----------------------------------------------------------------------------------------------
185: rx_trig_reg_proc : process(clk_sys, res_n)
186: begin
187: if (res_n = '0') then
188: rx_trig_req_q <= '0';
189: elsif (rising_edge(clk_sys)) then
190: rx_trig_req_q <= rx_trig_req;
191: end if;
192: end process;
193:
194:
195: -----------------------------------------------------------------------------------------------
196: -- RX Trigger, driven directly. Since Sync Trigger lasts only one clock cycle, and trigger
197: -- request might never occur at once, we don't have to do any capturing!
198: -----------------------------------------------------------------------------------------------
199: rx_triggers(1) <= rx_trig_req;
200: rx_triggers(0) <= rx_trig_req_q;
201:
202: -----------------------------------------------------------------------------------------------
203: -- TX Trigger is active when either direct trigger or flag is active. But it must be gated when
204: -- RX Trigger 1 is active. In this case TX Trigger request flag was set and TX Trigger will be
205: -- shifted by one clock cycle.
206: -----------------------------------------------------------------------------------------------
207: tx_trigger <= '0' when (rx_trig_req_q = '1') else
208: tx_trig_req_flag_dq;
209:
210: -----------------------------------------------------------------------------------------------
211: -----------------------------------------------------------------------------------------------
212: -- Assertions
213: -----------------------------------------------------------------------------------------------
214: -----------------------------------------------------------------------------------------------
215:
216: -- psl default clock is rising_edge(clk_sys);
217:
218: -----------------------------------------------------------------------------------------------
219: -- Sync request and Sample request should never be active at the same time.
220: -- This should be handled by Scanner FSM.
221: --
222: -- psl sync_sample_trig_no_simul_asrt : assert never
223: -- (rx_trig_req = '1' and tx_trig_req = '1')
224: -- report "Sync and Sample trigger should no be requested at once!";
225: -----------------------------------------------------------------------------------------------
226:
227: end architecture rtl;