File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/shift_reg_preload.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Shift register with asynchronous reset and synchronous pre-load.
71: -- Shifts-in always zero.
72: --------------------------------------------------------------------------------
73:
74: Library ieee;
75: use ieee.std_logic_1164.all;
76:
77: entity shift_reg_preload is
78: generic (
79: -- Reset polarity
80: G_RESET_POLARITY : std_logic;
81:
82: -- Reset value
83: G_RESET_VALUE : std_logic_vector;
84:
85: -- Shift register width
86: G_WIDTH : natural
87: );
88: port (
89: -------------------------------------------------------------------------------------------
90: -- Clock and reset
91: -------------------------------------------------------------------------------------------
92: clk : in std_logic;
93: res_n : in std_logic;
94:
95: -------------------------------------------------------------------------------------------
96: -- Control signals
97: -------------------------------------------------------------------------------------------
98: -- Pre-load shift register
99: preload : in std_logic;
100:
101: -- Value to be pre-load to the shift register
102: preload_val : in std_logic_vector(G_WIDTH - 1 downto 0);
103:
104: -- When enabled, shifted each clock, when disabled, register maintains its state.
105: enable : in std_logic;
106:
107: -------------------------------------------------------------------------------------------
108: -- Status signals
109: -------------------------------------------------------------------------------------------
110: -- Shift register value
111: reg_stat : out std_logic_vector(G_WIDTH - 1 downto 0);
112:
113: -- Shift register output
114: reg_output : out std_logic
115: );
116: end shift_reg_preload;
117:
118: architecture rtl of shift_reg_preload is
119:
120: -- Internal shift register DFFs
121: signal shift_regs : std_logic_vector(G_WIDTH - 1 downto 0);
122:
123: begin
124:
125: -----------------------------------------------------------------------------------------------
126: -- Calculation of next shift register value
127: -----------------------------------------------------------------------------------------------
128: reg_output <= shift_regs(G_WIDTH - 1);
129:
130: -----------------------------------------------------------------------------------------------
131: -- Implementation of a shift register
132: -----------------------------------------------------------------------------------------------
133: shift_down_proc : process (res_n, clk)
134: begin
135: if (res_n = G_RESET_POLARITY) then
136: shift_regs <= G_RESET_VALUE;
137:
138: elsif (rising_edge(clk)) then
139: if (preload = '1') then
140: shift_regs <= preload_val;
141: elsif (enable = '1') then
142: shift_regs <= shift_regs(G_WIDTH - 2 downto 0) & '0';
143: end if;
144: end if;
145: end process;
146:
147: -----------------------------------------------------------------------------------------------
148: -- Propagation of shift register to the outputs
149: -----------------------------------------------------------------------------------------------
150: reg_stat <= shift_regs;
151:
152: -----------------------------------------------------------------------------------------------
153: -- Assertion for correct length of reset value
154: -----------------------------------------------------------------------------------------------
155: -- coverage off
156: assert (G_RESET_VALUE'length = G_WIDTH) report "Invalid length of shift " &
157: "register reset value" severity error;
158: -- coverage on
159:
160: end rtl;