File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/bit_destuffing.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bit Destuffing.
71: --
72: -- Purpose:
73: -- Performs bit destuffing from received data stream. Operates in Destuff
74: -- pipeline stage with Bit Destuffing trigger. Length of Bit Destuffing rule
75: -- is controlled by Protocol control FSM. Implements regular bit stuffing,
76: -- as well as Fixed bit stuffing. Upon transition from non-fixed to fixed bit
77: -- stuffing, inserts an extra stuff bit.
78: -- Detects stuff error if n+1-th bit is not opposite of previous processed bit.
79: -- Indicates that bit was destuffed when n bits of equal polarity are processed.
80: -- Processing of input data always take one clock cycle (output is DFF). When
81: -- circuit is disabled, it only propagates data from input to output with Bit
82: -- Destuffing Trigger and does not detect Stuff Error, neither performs Bit
83: -- destuffing. Counts number of destuffed bits modulo 8.
84: --------------------------------------------------------------------------------
85:
86: Library ieee;
87: use ieee.std_logic_1164.all;
88: use ieee.numeric_std.ALL;
89:
90: Library ctu_can_fd_rtl;
91: use ctu_can_fd_rtl.can_constants_pkg.all;
92: use ctu_can_fd_rtl.can_types_pkg.all;
93:
94: use ctu_can_fd_rtl.CAN_FD_register_map.all;
95: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
96:
97: entity bit_destuffing is
98: port (
99: -------------------------------------------------------------------------------------------
100: -- Clock and Asynchronous reset
101: -------------------------------------------------------------------------------------------
102: clk_sys : in std_logic;
103: res_n : in std_logic;
104:
105: -------------------------------------------------------------------------------------------
106: -- Data-path
107: -------------------------------------------------------------------------------------------
108: -- Data input (from Bus Sampling)
109: data_in : in std_logic;
110:
111: -- Data output (to Protocol Control)
112: data_out : out std_logic;
113:
114: -------------------------------------------------------------------------------------------
115: -- Control signals
116: -------------------------------------------------------------------------------------------
117: -- Bit Destuffing Trigger (in Sample point, from Prescaler).
118: bds_trigger : in std_logic;
119:
120: -- Bit Destuffing is enabled.
121: destuff_enable : in std_logic;
122:
123: -- Bit destuffing type (0-Normal, 1-Fixed)
124: fixed_stuff : in std_logic;
125:
126: -------------------------------------------------------------------------------------------
127: -- Status Outpus
128: -------------------------------------------------------------------------------------------
129: -- Stuff error detected (more equal consecutive bits than length of stuff rule.
130: stuff_err : out std_logic;
131:
132: -- Data output is not valid, actual bit is stuff bit.
133: destuffed : out std_logic;
134:
135: -- Number of de-stuffed bits with normal bit stuffing method
136: dst_ctr : out std_logic_vector(2 downto 0)
137: );
138: end entity;
139:
140: architecture rtl of bit_destuffing is
141:
142: -- Stuff bit should be discarded
143: signal discard_stuff_bit : std_logic;
144:
145: -- Change from non-fixed to fixed bit stuffing occured
146: signal non_fix_to_fix_chng : std_logic;
147:
148: -- Number of equal consecutive bits on input is equal to length of stuff
149: -- rule
150: signal stuff_lvl_reached : std_logic;
151:
152: -- Stuff rule is violated -> Stuff error.
153: signal stuff_rule_violate : std_logic;
154:
155: -- Previous value of enable - register
156: signal enable_prev : std_logic;
157:
158: -- Previous value of fixed stuff - register
159: signal fixed_prev_q : std_logic;
160: signal fixed_prev_d : std_logic;
161:
162: -- Counter with number of equal consecutive bits on input
163: signal same_bits_d : unsigned(2 downto 0);
164: signal same_bits_q : unsigned(2 downto 0);
165: signal same_bits_add : unsigned(2 downto 0);
166: signal same_bits_erase : std_logic;
167:
168: -- Register with flag that bit was destuffed from serial stream
169: signal destuffed_q : std_logic;
170: signal destuffed_d : std_logic;
171:
172: -- Register with error flag signalling stuff error
173: signal stuff_err_q : std_logic;
174: signal stuff_err_d : std_logic;
175:
176: -- Counter of destuffed bits by non-fixed bit stuffing.
177: signal dst_ctr_q : unsigned(2 downto 0);
178: signal dst_ctr_d : unsigned(2 downto 0);
179: signal dst_ctr_add : unsigned(2 downto 0);
180:
181: -- Value of previous processed bit on the bus
182: signal prev_val_q : std_logic;
183: signal prev_val_d : std_logic;
184:
185: begin
186:
187: -----------------------------------------------------------------------------------------------
188: -- Registering previous value of enable input to detect 0->1 transition.
189: -----------------------------------------------------------------------------------------------
190: dff_ena_reg : entity ctu_can_fd_rtl.dff_arst
191: generic map (
192: G_RESET_POLARITY => '0',
193: G_RST_VAL => '0'
194: )
195: port map (
196: arst => res_n, -- IN
197: clk => clk_sys, -- IN
198: reg_d => destuff_enable, -- IN
199:
200: reg_q => enable_prev -- OUT
201: );
202:
203: -----------------------------------------------------------------------------------------------
204: -- Detection of change on fixed stuff settings upon mismatch between actual and registered
205: -- value of fixed stuff settings from previous bit.
206: -----------------------------------------------------------------------------------------------
207: non_fix_to_fix_chng <= '1' when (fixed_stuff = '1' and fixed_prev_q = '0')
208: else
209: '0';
210:
211: -----------------------------------------------------------------------------------------------
212: -- Number of stuff bits is reached when:
213: -- 1. Normal bit stuffing, number of same bits is equal to stuff rule length. Stuff bit is
214: -- already included in counting next consecutive bits of equal value (recursive behaviour).
215: -- 2. Fixed bit stuffing, number of same bits is equal to one more than rule length, since
216: -- stuff bit is not included then!
217: --
218: -- In both cases the "same_bits_q" is equal to 5, since for fixed stuffing the length of
219: -- stuff rule (4) compensates for recursivity of regular bit stuffing!
220: -----------------------------------------------------------------------------------------------
221: stuff_lvl_reached <= '1' when (same_bits_q = "101")
222: else
223: '0';
224:
225: -----------------------------------------------------------------------------------------------
226: -- Stuff bit should be discarded:
227: -- 1. Upon change of non-fixed to fixed bit stuffing
228: -- 2. Number of equal consecutive bits has reached length of stuff rule.
229: -----------------------------------------------------------------------------------------------
230: discard_stuff_bit <= '1' when (non_fix_to_fix_chng = '1' or stuff_lvl_reached = '1')
231: else
232: '0';
233:
234: -----------------------------------------------------------------------------------------------
235: -- Calculation of next value in fixed stuff register:
236: -- 1. Re-started upon 0->1 transition on "enable"
237: -- 2. Store "fixed_stuff" configuration when data are processed
238: -----------------------------------------------------------------------------------------------
239: fixed_prev_d <= '0' when (enable_prev = '0') else
240: fixed_stuff when (bds_trigger = '1') else
241: fixed_prev_q;
242:
243: -----------------------------------------------------------------------------------------------
244: -- Stuff rules is violated under following conditions:
245: -- 1. Actually processed bit should be discarded.
246: -- 2. Previously processed bit is equal to actual bit on input (N+1 bit is not different)
247: -- 3. Stuff error detection is enabled.
248: -----------------------------------------------------------------------------------------------
249: stuff_rule_violate <= '1' when (discard_stuff_bit = '1' and prev_val_q = data_in and
250: destuff_enable = '1')
251: else
252: '0';
253:
254: -----------------------------------------------------------------------------------------------
255: -- Registering previous value of fixed bit stuffing to detect first fixed stuff bit and insert
256: -- stuff bit in the beginning of CRC for CAN FD automatically!
257: -----------------------------------------------------------------------------------------------
258: dff_fixed_stuff_reg : entity ctu_can_fd_rtl.dff_arst_ce
259: generic map (
260: G_RESET_POLARITY => '0',
261: G_RST_VAL => '0'
262: )
263: port map (
264: arst => res_n, -- IN
265: clk => clk_sys, -- IN
266: reg_d => fixed_prev_d, -- IN
267: ce => destuff_enable, -- IN
268:
269: reg_q => fixed_prev_q -- OUT
270: );
271:
272: -----------------------------------------------------------------------------------------------
273: -- Combinationally incremented valued of counter with number of destuffed bits.
274: -----------------------------------------------------------------------------------------------
275: dst_ctr_add <= (dst_ctr_q + 1) mod 8;
276:
277: -----------------------------------------------------------------------------------------------
278: -- Counter with de-stuffed bits, next value:
279: -- 1. Erase upon edge on enable
280: -- 2. Increment when non-fixed stuff bit is inserted
281: -- 3. Keep otherwise
282: -----------------------------------------------------------------------------------------------
283: dst_ctr_d <= "000" when (enable_prev = '0')
284: else
285: dst_ctr_add when (bds_trigger = '1' and stuff_lvl_reached = '1' and
286: fixed_stuff = '0')
287: else
288: dst_ctr_q;
289:
290: -----------------------------------------------------------------------------------------------
291: -- Counter with number of de-stuffed bits - register assignment
292: -----------------------------------------------------------------------------------------------
293: dst_ctr_proc : process(clk_sys, res_n)
294: begin
295: if (res_n = '0') then
296: dst_ctr_q <= (others => '0');
297: elsif (rising_edge(clk_sys)) then
298: if (destuff_enable = '1') then
299: dst_ctr_q <= dst_ctr_d;
300: end if;
301: end if;
302: end process;
303:
304: -----------------------------------------------------------------------------------------------
305: -- Counter of equal consecutive bits should be erased:
306: -- 1. Circuit disabled, or just enabled (edge on enable)
307: -- 2. Stuff bit is just discarded.
308: -- 3. Bit is processed by non-fixed bit stuffing, but it differs from previous processed bit.
309: -----------------------------------------------------------------------------------------------
310: same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else
311: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
312: '1' when (bds_trigger = '1' and data_in /= prev_val_q and
313: fixed_stuff = '0') else
314: '0';
315:
316: -----------------------------------------------------------------------------------------------
317: -- Combinationally incremented value of counter of equal consecutive bits by 1.
318: -----------------------------------------------------------------------------------------------
319: same_bits_add <= (same_bits_q + 1) mod 8;
320:
321: -----------------------------------------------------------------------------------------------
322: -- Next value for counter of equal consecutive bits:
323: -- 1. Erase counter when signalled.
324: -- 2. Increment upon processing of bit.
325: -- 3. Keep its value otherwise.
326: -----------------------------------------------------------------------------------------------
327: same_bits_d <= "001" when (same_bits_erase = '1') else
328: same_bits_add when (bds_trigger = '1') else
329: same_bits_q;
330:
331: -----------------------------------------------------------------------------------------------
332: -- Counter of equal consecutive bits - register assignment.
333: -----------------------------------------------------------------------------------------------
334: same_bits_ctr_proc : process(clk_sys, res_n)
335: begin
336: if (res_n = '0') then
337: same_bits_q <= "001";
338: elsif (rising_edge(clk_sys)) then
339: same_bits_q <= same_bits_d;
340: end if;
341: end process;
342:
343: -----------------------------------------------------------------------------------------------
344: -- Destuffed flag - next value:
345: -- 1. Erase when circuit is disabled.
346: -- 2. Set when bit is processed and destuffed.
347: -- 3. Erase when bit is processed but should not be discarded.
348: -- 4. Keep value otherwise.
349: -----------------------------------------------------------------------------------------------
350: destuffed_d <= '0' when (destuff_enable = '0') else
351: '1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
352: '0' when (bds_trigger = '1') else
353: destuffed_q;
354:
355: -----------------------------------------------------------------------------------------------
356: -- Destuffed flag - register assignment
357: -----------------------------------------------------------------------------------------------
358: dff_destuffed_flag_reg : entity ctu_can_fd_rtl.dff_arst
359: generic map (
360: G_RESET_POLARITY => '0',
361: G_RST_VAL => '0'
362: )
363: port map (
364: arst => res_n, -- IN
365: clk => clk_sys, -- IN
366: reg_d => destuffed_d, -- IN
367:
368: reg_q => destuffed_q -- OUT
369: );
370:
371: -----------------------------------------------------------------------------------------------
372: -- Error register next value:
373: -- 1. Set when bit should be processed and stuff rule is violated.
374: -- 2. Cleared otherwise
375: -----------------------------------------------------------------------------------------------
376: stuff_err_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else
377: '0';
378:
379: -----------------------------------------------------------------------------------------------
380: -- Error register - register assignment
381: -----------------------------------------------------------------------------------------------
382: dff_err_reg : entity ctu_can_fd_rtl.dff_arst
383: generic map (
384: G_RESET_POLARITY => '0',
385: G_RST_VAL => '0'
386: )
387: port map (
388: arst => res_n, -- IN
389: clk => clk_sys, -- IN
390: reg_d => stuff_err_d, -- IN
391:
392: reg_q => stuff_err_q -- OUT
393: );
394:
395: -----------------------------------------------------------------------------------------------
396: -- Previously processed value - next value:
397: -- 1. Set to RECESSIVE upon edge on enable
398: -- 2. Set to RECESSIVE when non-fixed bit stuffing changes to fixed bit stuffing.
399: -----------------------------------------------------------------------------------------------
400: prev_val_d <= RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
401: data_in when (bds_trigger = '1') else
402: prev_val_q;
403:
404: -----------------------------------------------------------------------------------------------
405: -- Previously processed value - register assignment
406: -----------------------------------------------------------------------------------------------
407: dff_prev_val_reg : entity ctu_can_fd_rtl.dff_arst
408: generic map (
409: G_RESET_POLARITY => '0',
410: G_RST_VAL => RECESSIVE
411: )
412: port map (
413: arst => res_n, -- IN
414: clk => clk_sys, -- IN
415: reg_d => prev_val_d, -- IN
416:
417: reg_q => prev_val_q -- OUT
418: );
419:
420:
421: -----------------------------------------------------------------------------------------------
422: -- Sampling of data value to output during operation. One clock cycle of delay is inserted so
423: -- that next pipeline stage always processes the same data!
424: -----------------------------------------------------------------------------------------------
425: dff_data_out_val_reg : entity ctu_can_fd_rtl.dff_arst_ce
426: generic map (
427: G_RESET_POLARITY => '0',
428: G_RST_VAL => RECESSIVE
429: )
430: port map (
431: arst => res_n,
432: clk => clk_sys,
433:
434: reg_d => data_in,
435: ce => bds_trigger,
436: reg_q => data_out
437: );
438:
439: -----------------------------------------------------------------------------------------------
440: -- Propagation to output
441: -----------------------------------------------------------------------------------------------
442:
443: destuffed <= destuffed_q;
444: stuff_err <= stuff_err_q;
445: dst_ctr <= std_logic_vector(dst_ctr_q);
446:
447: end architecture;