File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/common/signal_delayer.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Purpose:
70: -- Delay a signal by non-static time.
71: -- Maintains a FIFO of (time&value) of event (change) on input signal
72: -- and replays it on the delayed signal with the specified delay.
73: --------------------------------------------------------------------------------
74: -- Revision History:
75: -- February 2018 First Implementation - Martin Jerabek
76: --------------------------------------------------------------------------------
77:
78: library ieee;
79: use ieee.std_logic_1164.all;
80:
81: entity signal_delayer_vec is
82: generic (
83: NSAMPLES : positive;
84: DWIDTH : positive
85: );
86: port (
87: input : in std_logic_vector(DWIDTH-1 downto 0);
88: delayed : out std_logic_vector(DWIDTH-1 downto 0);
89: delay : in time
90: );
91: end entity;
92:
93: architecture tb of signal_delayer_vec is
94: type data_type is array(0 to NSAMPLES-1) of time;
95: type dataval_type is array(0 to NSAMPLES-1) of std_logic_vector(DWIDTH-1 downto 0);
96: signal first : boolean := true;
97:
98: signal nonempty : boolean;
99: signal pop : boolean;-- sensitive to edge, not level!
100: signal top : time;
101: signal top_val : std_logic_vector(DWIDTH-1 downto 0);
102: begin
103: p_fifo: process
104: variable data : data_type;
105: variable dataval : dataval_type;
106: variable rdidx : natural := 0;
107: variable wridx : natural := 0;
108: begin
109: if first then
110: first <= false;
111: top_val <= input;
112: end if;
113: wait until (input'event or pop'event);
114: if input'event then
115: assert (wridx - rdidx) < NSAMPLES report "FIFO full!" severity failure;
116: data(wridx mod NSAMPLES) := now;
117: dataval(wridx mod NSAMPLES) := input;
118: wridx := wridx + 1;
119: elsif pop'event then
120: assert (wridx - rdidx) > 0 report "FIFO empty!" severity failure;
121: top_val <= dataval(rdidx mod NSAMPLES);
122: rdidx := rdidx + 1;
123: end if;
124: top <= data(rdidx mod NSAMPLES);
125: nonempty <= (wridx - rdidx) > 0;
126: wait for 0 ns;
127: end process;
128:
129: p_delay: process
130: variable towait : time;
131: variable first : boolean := true;
132: begin
133: if delay < 0 ns then
134: wait until delay >= 0 ns;
135: end if;
136: if first then
137: first := false;
138: delayed <= input;
139: end if;
140: if not nonempty then
141: wait until nonempty;
142: end if;
143: towait := top + delay - now;
144: --report "Waiting for " & time'image(towait);
145: wait for towait;
146: delayed <= top_val;
147: if not nonempty then
148: wait until nonempty;
149: end if;
150: pop <= not pop;
151: end process;
152: end;
153:
154: library ieee;
155: use ieee.std_logic_1164.all;
156:
157: entity signal_delayer is
158: generic (
159: NSAMPLES : positive
160: );
161: port (
162: input : in std_logic;
163: delayed : out std_logic;
164: delay : in time
165: );
166: end entity;
167:
168: architecture tb of signal_delayer is
169: signal input_v, delayed_v : std_logic_vector(0 downto 0);
170: begin
171: i_sdv: entity work.signal_delayer_vec
172: generic map (
173: NSAMPLES => NSAMPLES,
174: DWIDTH => 1
175: )
176: port map (
177: input => input_v,
178: delayed => delayed_v,
179: delay => delay
180: );
181: input_v <= (0 => input);
182: delayed <= delayed_v(0);
183: end architecture;