File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/trigger_mux.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Trigger multiplexor.
71: --
72: -- Purpose:
73: -- Creates trigger (clock enable) signals for pipeline stages within CAN Core.
74: -- Creates following trigger signals:
75: -- 1. Protocol control TX Trigger - Stuff pipeline stage. Gated when a bit
76: -- was stuffed.
77: -- 2. Protocol control RX Trigger - Process pipeline state. Gated when a
78: -- bit was destuffed.
79: -- 3. Bit stuffing trigger - Stuff pipeline stage.
80: -- 4. Bit destuffing trigger - Destuff pipeline stage
81: -- 5. CRC RX With bit stuffing trigger - Process pipeline stage. Gated
82: -- when fixed stuff bit is destuffed since CRC 17, 21 shall not be
83: -- calculated from fixed stuff bits.
84: -- 6. CRC RX No bit stuffing trigger - Process pipeline stage. Gated when
85: -- a bit is destuffed.
86: -- 7. CRC TX No bit stuffing trigger - Stuff pipeline stage. Gated when
87: -- a stuff bit was inserted after previous bit.
88: -- 7. CRC TX With bit stuffing trigger - Stuff pipeline stage + 1 clock
89: -- cycle. Gated when fixed stuff bit was inserted.
90: --------------------------------------------------------------------------------
91:
92: Library ieee;
93: use ieee.std_logic_1164.all;
94: use ieee.numeric_std.ALL;
95:
96: Library ctu_can_fd_rtl;
97: use ctu_can_fd_rtl.can_constants_pkg.all;
98: use ctu_can_fd_rtl.can_types_pkg.all;
99:
100: use ctu_can_fd_rtl.CAN_FD_register_map.all;
101: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
102:
103: entity trigger_mux is
104: generic (
105: -- Number of Sample Triggers
106: G_SAMPLE_TRIGGER_COUNT : natural
107: );
108: port (
109: -------------------------------------------------------------------------------------------
110: -- Clock and Asynchronous reset
111: -------------------------------------------------------------------------------------------
112: clk_sys :in std_logic;
113: res_n :in std_logic;
114:
115: -------------------------------------------------------------------------------------------
116: -- Input triggers
117: -------------------------------------------------------------------------------------------
118: -- RX Triggers
119: rx_triggers :in std_logic_vector(G_SAMPLE_TRIGGER_COUNT - 1 downto 0);
120:
121: -- TX Trigger
122: tx_trigger :in std_logic;
123:
124: -------------------------------------------------------------------------------------------
125: -- Control signals
126: -------------------------------------------------------------------------------------------
127: -- Stuff bit is inserted, Protocol control operation to be halted for one bit time
128: data_halt :in std_logic;
129:
130: -- Data output is not valid, actual bit is stuff bit.
131: destuffed :in std_logic;
132:
133: -- Fixed bit stuffing method is used
134: fixed_stuff :in std_logic;
135:
136: -- Bit Destuffing Data input
137: bds_data_in :in std_logic;
138:
139: -------------------------------------------------------------------------------------------
140: -- Output triggers
141: -------------------------------------------------------------------------------------------
142: -- Protocol control TX Trigger
143: pc_tx_trigger :out std_logic;
144:
145: -- Protocol control RX Trigger
146: pc_rx_trigger :out std_logic;
147:
148: -- Bit Stuffing Trigger
149: bst_trigger :out std_logic;
150:
151: -- Bit De-Stuffing Trigger
152: bds_trigger :out std_logic;
153:
154: -- CRC Trigger RX - No bit stuffing
155: crc_trig_rx_nbs :out std_logic;
156:
157: -- CRC Trigger TX - No bit stuffing
158: crc_trig_tx_nbs :out std_logic;
159:
160: -- CRC Trigger RX - With bit stuffing
161: crc_trig_rx_wbs :out std_logic;
162:
163: -- CRC Trigger TX - With bit stuffing
164: crc_trig_tx_wbs :out std_logic;
165:
166: -------------------------------------------------------------------------------------------
167: -- Status signals
168: -------------------------------------------------------------------------------------------
169: -- CRC RX With Bit Stuffing - Data input
170: crc_data_rx_wbs :out std_logic
171: );
172: end entity;
173:
174: architecture rtl of trigger_mux is
175:
176: signal tx_trigger_q : std_logic;
177:
178: begin
179:
180: -----------------------------------------------------------------------------------------------
181: -- Protocol control triggers:
182: -- 1. Protocol control trigger (TX) - shifts TX Shift register, is enabled when stuff bit is
183: -- not inserted! Active in Stuff pipeline stage.
184: -- 2. Protocol control trigger (RX) - shifts RX Shift register, is enabled when stuff bit is
185: -- not destuffed! Active in Process pipeline stage.
186: -----------------------------------------------------------------------------------------------
187: pc_tx_trigger <= '1' when (tx_trigger = '1' and data_halt = '0')
188: else
189: '0';
190:
191: pc_rx_trigger <= '1' when (rx_triggers(0) = '1' and destuffed = '0')
192: else
193: '0';
194:
195: -----------------------------------------------------------------------------------------------
196: -- Bit stuffing/destuffing triggers:
197: -- 1. Bit Stuffing Trigger (TX) - Processes data on Bit stuffing input, active in Stuff
198: -- pipeline stage.
199: -- 2. Bit Destuffing Trigger (RX) - Processes data on Bit Destuffin input, active in Destuff
200: -- pipeline stage.
201: -----------------------------------------------------------------------------------------------
202: bst_trigger <= tx_trigger;
203: bds_trigger <= rx_triggers(1);
204:
205: -----------------------------------------------------------------------------------------------
206: -- CRC Triggers for CRC 15 (CRC without stuff bits):
207: -- 1. CRC RX NBS - Trigger for CRC15 from RX data without bit stuffing. Trigger must be gated
208: -- when bit was destuffed, because CRC15 for CAN 2.0 frames shall not take stuff bits into
209: -- account! Active in Process pipeline stage.
210: -- 2. CRC TX NBS - Trigger for CRC15 from TX data without bit stuffing. Must be gated when
211: -- stuff bit is inserted! Active in Stuff pipeline stage.
212: -----------------------------------------------------------------------------------------------
213: crc_trig_rx_nbs <= '1' when (rx_triggers(0) = '1' and destuffed = '0')
214: else
215: '0';
216:
217: crc_trig_tx_nbs <= '1' when (tx_trigger = '1' and data_halt = '0')
218: else
219: '0';
220:
221: -----------------------------------------------------------------------------------------------
222: -- CRC Trigger for CRC 17, 21 (with bit stuffing):
223: -- 1. CRC TX WBS - Trigger for CRC17, CRC21 from TX Data with bit stuffing. This trigger must
224: -- be gated for fixed stuff bits since CRC17, CRC21 shall not contain fixed stuff bits!
225: -- Active one clock cycle after Stuff pipeline stage.
226: -- 2. CRC RX WBS - Trigger for CRC17, CRC21 from RX Data with bit stuffing. Fixed stuff bits
227: -- must be left out! Active in Process pipeline stage. (see next comment).
228: -----------------------------------------------------------------------------------------------
229: crc_trig_tx_wbs_reg : entity ctu_can_fd_rtl.dff_arst
230: generic map(
231: G_RESET_POLARITY => '0',
232: G_RST_VAL => '0'
233: )
234: port map(
235: arst => res_n, -- IN
236: clk => clk_sys, -- IN
237: reg_d => tx_trigger, -- IN
238:
239: reg_q => tx_trigger_q -- OUT
240: );
241:
242: crc_trig_tx_wbs <= '0' when (fixed_stuff = '1' and data_halt = '1') else
243: '1' when (tx_trigger_q = '1') else
244: '0';
245:
246: -----------------------------------------------------------------------------------------------
247: -- We must gate fixed stuff bit for CRC from RX With Bit Stuffing. But we don't know if it is
248: -- stuff bit in Stuff pipeline stage. So we must delay the information to Process pipeline
249: -- stage. We sample the data (Bit Destuffing input) to avoid possible change, and calculate the
250: -- CRC with rx_trigger(0) (in Process pipeline stage).
251: -----------------------------------------------------------------------------------------------
252: crc_data_rx_wbs_reg : entity ctu_can_fd_rtl.dff_arst_ce
253: generic map(
254: G_RESET_POLARITY => '0',
255: G_RST_VAL => '0'
256: )
257: port map(
258: arst => res_n, -- IN
259: clk => clk_sys, -- IN
260: reg_d => bds_data_in, -- IN
261: ce => rx_triggers(1), -- IN
262:
263: reg_q => crc_data_rx_wbs -- OUT
264: );
265:
266: crc_trig_rx_wbs <= '0' when (fixed_stuff = '1' and destuffed = '1') else
267: '1' when (rx_triggers(0) = '1') else
268: '0';
269:
270: end architecture;