File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/bus_traffic_counters.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bus traffic counters.
71: --
72: -- Purpose:
73: -- Counts number of transmitted and received frames on CAN Bus.
74: --------------------------------------------------------------------------------
75:
76: Library ieee;
77: use ieee.std_logic_1164.all;
78: use ieee.numeric_std.ALL;
79:
80: Library ctu_can_fd_rtl;
81: use ctu_can_fd_rtl.can_constants_pkg.all;
82: use ctu_can_fd_rtl.can_types_pkg.all;
83:
84: use ctu_can_fd_rtl.CAN_FD_register_map.all;
85: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
86:
87: entity bus_traffic_counters is
88: port (
89: -------------------------------------------------------------------------------------------
90: -- System clock and Asynchronous Reset
91: -------------------------------------------------------------------------------------------
92: clk_sys : in std_logic;
93: res_n : in std_logic;
94:
95: -------------------------------------------------------------------------------------------
96: -- DFT support
97: -------------------------------------------------------------------------------------------
98: scan_enable : in std_logic;
99:
100: -------------------------------------------------------------------------------------------
101: -- Control signals
102: -------------------------------------------------------------------------------------------
103:
104: -- Frame transmission valid
105: tran_valid : in std_logic;
106:
107: -- Frame reception valid
108: rec_valid : in std_logic;
109:
110: -------------------------------------------------------------------------------------------
111: -- Memory registers interface
112: -------------------------------------------------------------------------------------------
113: mr_command_rxfcrst : in std_logic;
114: mr_command_txfcrst : in std_logic;
115:
116: -------------------------------------------------------------------------------------------
117: -- Counter values
118: -------------------------------------------------------------------------------------------
119: -- TX Traffic counter
120: tx_frame_ctr : out std_logic_vector(31 downto 0);
121:
122: -- RX Traffic counter
123: rx_frame_ctr : out std_logic_vector(31 downto 0)
124: );
125: end entity;
126:
127: architecture rtl of bus_traffic_counters is
128:
129: signal tx_frame_ctr_i : std_logic_vector(31 downto 0);
130: signal rx_frame_ctr_i : std_logic_vector(31 downto 0);
131:
132: -- Selected value to increment
133: signal sel_value : unsigned(31 downto 0);
134:
135: -- Incremented value by 1
136: signal inc_value : unsigned(31 downto 0);
137:
138: -- Reset signals for counters (registered, to avoid glitches)
139: signal tx_ctr_rst_n_d : std_logic;
140: signal tx_ctr_rst_n_q_scan : std_logic;
141:
142: signal rx_ctr_rst_n_d : std_logic;
143: signal rx_ctr_rst_n_q_scan : std_logic;
144:
145: signal tran_valid_q : std_logic;
146: signal rec_valid_q : std_logic;
147:
148: begin
149:
150: -----------------------------------------------------------------------------------------------
151: -- Register increment command (to relax timing through the counter!)
152: -----------------------------------------------------------------------------------------------
153: increment_reg_proc : process(clk_sys, res_n)
154: begin
155: if (res_n = '0') then
156: tran_valid_q <= '0';
157: rec_valid_q <= '0';
158: elsif rising_edge(clk_sys) then
159: tran_valid_q <= tran_valid;
160: rec_valid_q <= rec_valid;
161: end if;
162: end process;
163:
164: tx_frame_ctr <= tx_frame_ctr_i;
165: rx_frame_ctr <= rx_frame_ctr_i;
166:
167: -- Multiplexor between TX and RX value to increment
168: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1')
169: else
170: unsigned(rx_frame_ctr_i);
171:
172: -- Incremented value of either TX or RX counter
173: inc_value <= sel_value + 1;
174:
175: -----------------------------------------------------------------------------------------------
176: -- Reset registers
177: -----------------------------------------------------------------------------------------------
178: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1')
179: else
180: '1';
181:
182: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1')
183: else
184: '1';
185:
186: -----------------------------------------------------------------------------------------------
187: -- Reset pipeline registers
188: -----------------------------------------------------------------------------------------------
189: tx_ctr_reg_rst_inst : entity ctu_can_fd_rtl.rst_reg
190: generic map (
191: G_RESET_POLARITY => '0'
192: )
193: port map(
194: -- Clock and Reset
195: clk => clk_sys, -- IN
196: arst => res_n, -- IN
197:
198: -- Flip flop input / output
199: d => tx_ctr_rst_n_d, -- IN
200: q => tx_ctr_rst_n_q_scan, -- OUT
201:
202: -- Scan mode control
203: scan_enable => scan_enable -- IN
204: );
205:
206: rx_ctr_reg_rst_inst : entity ctu_can_fd_rtl.rst_reg
207: generic map (
208: G_RESET_POLARITY => '0'
209: )
210: port map(
211: -- Clock and Reset
212: clk => clk_sys, -- IN
213: arst => res_n, -- IN
214:
215: -- Flip flop input / output
216: d => rx_ctr_rst_n_d, -- IN
217: q => rx_ctr_rst_n_q_scan, -- OUT
218:
219: -- Scan mode control
220: scan_enable => scan_enable -- IN
221: );
222:
223: -----------------------------------------------------------------------------------------------
224: -- TX Counter register
225: -----------------------------------------------------------------------------------------------
226: tx_ctr_proc : process(clk_sys, tx_ctr_rst_n_q_scan)
227: begin
228: if (tx_ctr_rst_n_q_scan = '0') then
229: tx_frame_ctr_i <= (others => '0');
230: elsif rising_edge(clk_sys) then
231: if (tran_valid_q = '1') then
232: tx_frame_ctr_i <= std_logic_vector(inc_value);
233: end if;
234: end if;
235: end process;
236:
237: -----------------------------------------------------------------------------------------------
238: -- RX Counter register
239: -----------------------------------------------------------------------------------------------
240: rx_ctr_proc : process(clk_sys, rx_ctr_rst_n_q_scan)
241: begin
242: if (rx_ctr_rst_n_q_scan = '0') then
243: rx_frame_ctr_i <= (others => '0');
244: elsif rising_edge(clk_sys) then
245: if (rec_valid_q = '1') then
246: rx_frame_ctr_i <= std_logic_vector(inc_value);
247: end if;
248: end if;
249: end process;
250:
251: -----------------------------------------------------------------------------------------------
252: -- Assertions
253: -----------------------------------------------------------------------------------------------
254: -- psl default clock is rising_edge(clk_sys);
255:
256: -- psl no_simul_inc_tx_rx_asrt : assert never
257: -- (tran_valid = '1' and rec_valid = '1')
258: -- report "Simultaneous increment of TX and RX error traffic counter";
259:
260: end architecture;