File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_rx_buffer.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Functional coverage for RX Buffer
71: --
72: --------------------------------------------------------------------------------
73: -- Revision History:
74: -- 27.4.2025 Created file
75: --------------------------------------------------------------------------------
76:
77: Library ctu_can_fd_tb;
78: context ctu_can_fd_tb.ieee_context;
79: context ctu_can_fd_tb.tb_common_context;
80: context ctu_can_fd_tb.rtl_context;
81:
82: use ctu_can_fd_tb.clk_gen_agent_pkg.all;
83: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
84:
85: entity func_cov_rx_buffer is
86: generic (
87: -- RX Buffer size
88: G_RX_BUFF_SIZE : natural range 32 to 4096
89: );
90: port (
91: -- DUT clock
92: clk : in std_logic
93: );
94: end entity;
95:
96: architecture tb of func_cov_rx_buffer is
97:
98: -----------------------------------------------------------------------------------------------
99: -- Aliases to "rx_buffer" top
100: -----------------------------------------------------------------------------------------------
101:
102: alias data_overrun_i is
103: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.data_overrun_i : std_logic >>;
104:
105: alias data_overrun_flg is
106: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.data_overrun_flg : std_logic >>;
107:
108: alias read_increment is
109: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.read_increment : std_logic >>;
110:
111: alias read_counter_q is
112: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.read_counter_q : unsigned(4 downto 0) >>;
113:
114: alias commit_rx_frame is
115: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.commit_rx_frame : std_logic >>;
116:
117: alias write_raw_intent is
118: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.write_raw_intent : std_logic >>;
119:
120: alias mr_rx_settings_rtsop is
121: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.mr_rx_settings_rtsop : std_logic >>;
122:
123: alias rec_is_rtr is
124: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.rec_is_rtr : std_logic >>;
125:
126: alias rec_dlc is
127: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.rec_dlc : std_logic_vector(3 downto 0) >>;
128:
129: alias rx_parity_error is
130: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.rx_parity_error : std_logic >>;
131:
132: alias mr_command_crxpe is
133: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.mr_command_crxpe : std_logic >>;
134:
135: -----------------------------------------------------------------------------------------------
136: -- Aliases to "rx_buffer_pointers" top
137: -----------------------------------------------------------------------------------------------
138: alias C_FREE_MEM_WIDTH is
139: << constant .tb_top_ctu_can_fd.dut.rx_buffer_inst.rx_buffer_pointers_inst.C_FREE_MEM_WIDTH : natural >>;
140:
141: alias rx_mem_free_raw is
142: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.rx_buffer_pointers_inst.rx_mem_free_raw : unsigned(C_FREE_MEM_WIDTH-1 downto 0) >>;
143:
144: alias rx_mem_free_i is
145: << signal .tb_top_ctu_can_fd.dut.rx_buffer_inst.rx_buffer_pointers_inst.rx_mem_free_i : std_logic_vector(C_FREE_MEM_WIDTH-1 downto 0) >>;
146:
147:
148: begin
149:
150: -- psl default clock is rising_edge(clk);
151:
152: -----------------------------------------------------------------------------------------------
153: -- Corner-cases
154: -----------------------------------------------------------------------------------------------
155: --
156: -- psl rx_buf_overrun_flags_cov :
157: -- cover {data_overrun_i = '1' and data_overrun_flg = '1'};
158: --
159: -- psl rx_buf_commit_and_read_cov :
160: -- cover {read_increment = '1' and read_counter_q = "00001" and commit_rx_frame = '1'}
161: -- report "RX Buffer Commit and Frame read finish - Simultaneous!";
162: --
163: -- psl rx_buf_write_and_read_cov :
164: -- cover {write_raw_intent = '1' and read_increment = '1'};
165: --
166: -- psl rx_buf_read_after_write_cov :
167: -- cover {write_raw_intent = '1'; read_increment = '1'};
168: --
169: -- psl rx_buf_write_after_read_cov :
170: -- cover {read_increment = '1'; write_raw_intent = '1'};
171: --
172: -- psl rx_buf_sof_timestamp :
173: -- cover {mr_rx_settings_rtsop = RTS_BEG and commit_rx_frame = '1'};
174: --
175: -- psl rx_buf_eof_timestamp :
176: -- cover {mr_rx_settings_rtsop = RTS_END and commit_rx_frame = '1'};
177: --
178: -- psl rx_buf_burst_read_short_cov :
179: -- cover {(read_increment = '1')[*4]};
180: --
181: -- psl rx_buf_burst_read_max_cov :
182: -- cover {(read_increment = '1')[*16]};
183: -- Note: SW reads the frame like so: Read metadata one by one and then 16 data words.
184: -- Therefore highest burst achievable is 16 with current TB!
185: --
186:
187: -----------------------------------------------------------------------------------------------
188: -- Received frame types
189: -----------------------------------------------------------------------------------------------
190:
191: -- psl rx_buf_store_rtr_cov :
192: -- cover {rec_is_rtr = '1' and commit_rx_frame = '1'};
193: --
194: -- psl rx_buf_store_empty_frame_cov :
195: -- cover {rec_dlc = "0000" and rec_is_rtr = '0' and commit_rx_frame = '1'};
196: --
197: -- psl rx_buf_store_1_byte_frame_cov :
198: -- cover {rec_dlc = "0001" and rec_is_rtr = '0' and commit_rx_frame = '1'};
199: --
200: -- psl rx_buf_store_2_byte_frame_cov :
201: -- cover {rec_dlc = "0010" and rec_is_rtr = '0' and commit_rx_frame = '1'};
202: --
203: -- psl rx_buf_store_3_byte_frame_cov :
204: -- cover {rec_dlc = "0011" and rec_is_rtr = '0' and commit_rx_frame = '1'};
205: --
206: -- psl rx_buf_store_4_byte_frame_cov :
207: -- cover {rec_dlc = "0100" and rec_is_rtr = '0' and commit_rx_frame = '1'};
208: --
209: -- psl rx_buf_store_5_byte_frame_cov :
210: -- cover {rec_dlc = "0101" and rec_is_rtr = '0' and commit_rx_frame = '1'};
211: --
212: -- psl rx_buf_store_8_byte_frame_cov :
213: -- cover {rec_dlc = "1000" and rec_is_rtr = '0' and commit_rx_frame = '1'};
214: --
215: -- psl rx_buf_store_64_byte_frame_cov :
216: -- cover {rec_dlc = "1111" and rec_is_rtr = '0' and commit_rx_frame = '1'};
217: --
218: -- In the cycle where mr_command_crxpe is active, the rx_parity_error is cleared.
219: -- Since memory bus is driven in between falling edges, and functional coverage
220: -- is sampled with delayed clock, we can't detect case where rx_parity_error = '1'
221: -- and mr_command_crxpe = '1' simultaneously. Thus we detect falling edge due to
222: -- clear!
223: -- psl rx_parity_err_clr_cov :
224: -- cover {rx_parity_error = '1'; rx_parity_error = '0' and mr_command_crxpe = '1'};
225:
226:
227: -----------------------------------------------------------------------------------------------
228: -- Pointers
229: -----------------------------------------------------------------------------------------------
230:
231: -- psl rx_no_raw_mem_free_cov :
232: -- cover {to_integer(unsigned(rx_mem_free_raw)) = 0};
233: --
234: -- psl rx_all_raw_mem_free_cov :
235: -- cover {to_integer(unsigned(rx_mem_free_raw)) = G_RX_BUFF_SIZE};
236: --
237: -- psl rx_no_int_mem_free_cov :
238: -- cover {to_integer(unsigned(rx_mem_free_i)) = 0};
239: --
240: -- psl rx_all_int_mem_free_cov :
241: -- cover {to_integer(unsigned(rx_mem_free_i)) = G_RX_BUFF_SIZE};
242: --
243:
244:
245: end architecture;