File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/test_probe_agent/test_probe_agent.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Test probe agent - Allows checking internal signals of CTU CAN FD which
71: -- were brought to "test_probe" top.
72: --
73: -- TODO: Once GHDL supports external names, we can remove the test-probe
74: -- from CTU CAN FD Top, and mirror on internal signal value!
75: --
76: --------------------------------------------------------------------------------
77: -- Revision History:
78: -- 27.3.2021 Created file
79: --------------------------------------------------------------------------------
80:
81: Library ctu_can_fd_tb;
82: context ctu_can_fd_tb.ieee_context;
83: context ctu_can_fd_tb.rtl_context;
84: context ctu_can_fd_tb.tb_common_context;
85:
86: use ctu_can_fd_tb.test_probe_agent_pkg.all;
87: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
88:
89:
90: entity test_probe_agent is
91: port (
92: -- VIP test control / status signals
93: dut_test_probe : in t_ctu_can_fd_test_probe;
94: test_node_test_probe : in t_ctu_can_fd_test_probe ;
95:
96: -- DFT support of VIP
97: dut_scan_enable : out std_logic;
98: test_node_scan_enable : out std_logic
99: );
100: end entity;
101:
102: architecture tb of test_probe_agent is
103:
104: signal dut_scan_enable_i : std_logic := '0';
105: signal test_node_scan_enable_i : std_logic := '0';
106:
107: begin
108:
109: ---------------------------------------------------------------------------
110: -- Comunication receiver process
111: ---------------------------------------------------------------------------
112: receiver_proc : process
113: variable cmd : integer;
114: variable reply_code : integer;
115:
116: variable node : integer;
117:
118: variable tmp_bool : boolean;
119: variable tmp_logic : std_logic;
120:
121: -----------------------------------------------------------------------
122: -- This implemenation suffers from lower performance, than simple
123: -- "wait until", however, it does not exit when signal it waits on
124: -- changes only for delta-cycle since it is output of combinatorial
125: -- logic!
126: -----------------------------------------------------------------------
127: procedure wait_signal_delta_glitch_free(
128: signal sig : in std_logic
129: ) is
130: begin
131: while true loop
132: wait until sig = '1';
133: wait for 1 ps;
134: if (sig = '1') then
135: exit;
136: end if;
137: end loop;
138: end procedure;
139: begin
140: receive_start(default_channel, C_TEST_PROBE_AGENT_ID);
141:
142: -- Command is sent as message type
143: cmd := com_channel_data.get_msg_code;
144: reply_code := C_REPLY_CODE_OK;
145:
146: -- Read node on whose test probe to wait
147: node := com_channel_data.get_param;
148:
149: case cmd is
150: when TEST_PROBE_AGNT_WAIT_SAMPLE_NO_STUFF =>
151: if (node = 0) then
152: wait_signal_delta_glitch_free(dut_test_probe.rx_trigger_nbs);
153: else
154: wait_signal_delta_glitch_free(test_node_test_probe.rx_trigger_nbs);
155: end if;
156:
157: when TEST_PROBE_AGNT_WAIT_SAMPLE_STUFF =>
158: if (node = 0) then
159: wait_signal_delta_glitch_free(dut_test_probe.rx_trigger_wbs);
160: else
161: wait_signal_delta_glitch_free(test_node_test_probe.rx_trigger_wbs);
162: end if;
163:
164: when TEST_PROBE_AGNT_WAIT_SYNC =>
165: if (node = 0) then
166: wait_signal_delta_glitch_free(dut_test_probe.tx_trigger);
167: else
168: wait_signal_delta_glitch_free(test_node_test_probe.tx_trigger);
169: end if;
170:
171: when TEST_PROBE_AGNT_SCAN_CONFIGURE =>
172: tmp_bool := com_channel_data.get_param;
173:
174: if tmp_bool then
175: tmp_logic := '1';
176: else
177: tmp_logic := '0';
178: end if;
179:
180: if (node = 0) then
181: dut_scan_enable_i <= tmp_logic;
182: else
183: test_node_scan_enable_i <= tmp_logic;
184: end if;
185:
186: when others =>
187: info_m("Invalid message type: " & integer'image(cmd));
188: reply_code := C_REPLY_CODE_ERR;
189:
190: end case;
191: receive_finish(default_channel, reply_code);
192: end process;
193:
194: dut_scan_enable <= dut_scan_enable_i;
195: test_node_scan_enable <= test_node_scan_enable_i;
196:
197: end architecture;