File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_cfg_capture.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bit Time config capture
71: --
72: -- Purpose:
73: -- Re-calculates Bit time settings as defined in Memory registers (SYNC, PROP,
74: -- PH1, PH2), to internal representation of Prescaler (TSEG1 and TSEG2).
75: -- TSEG1 = SYNC + PROP + PH1, is captured at moment when core is turned on to
76: -- avoid long combinational paths. TSEG2, SJW, BRP are passed directly, only
77: -- width is accustomized.
78: --------------------------------------------------------------------------------
79:
80: Library ieee;
81: use ieee.std_logic_1164.all;
82: use ieee.numeric_std.ALL;
83:
84: Library ctu_can_fd_rtl;
85: use ctu_can_fd_rtl.can_constants_pkg.all;
86: use ctu_can_fd_rtl.can_types_pkg.all;
87:
88: use ctu_can_fd_rtl.CAN_FD_register_map.all;
89: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
90:
91: entity bit_time_cfg_capture is
92: generic (
93: -- TSEG1 Width - Nominal Bit Time
94: G_TSEG1_NBT_WIDTH : natural;
95:
96: -- TSEG2 Width - Nominal Bit Time
97: G_TSEG2_NBT_WIDTH : natural;
98:
99: -- Baud rate prescaler Width - Nominal Bit Time
100: G_BRP_NBT_WIDTH : natural;
101:
102: -- Synchronisation Jump width Width - Nominal Bit Time
103: G_SJW_NBT_WIDTH : natural;
104:
105: -- TSEG1 Width - Data Bit Time
106: G_TSEG1_DBT_WIDTH : natural;
107:
108: -- TSEG2 Width - Data Bit Time
109: G_TSEG2_DBT_WIDTH : natural;
110:
111: -- Baud rate prescaler width - Data Bit Time
112: G_BRP_DBT_WIDTH : natural;
113:
114: -- Synchronisation Jump Width width - Data Bit Time
115: G_SJW_DBT_WIDTH : natural
116: );
117: port (
118: -------------------------------------------------------------------------------------------
119: -- Clock and Asynchronous reset
120: -------------------------------------------------------------------------------------------
121: clk_sys : in std_logic;
122: res_n : in std_logic;
123:
124: -------------------------------------------------------------------------------------------
125: -- Memory Registers interface
126: -------------------------------------------------------------------------------------------
127: mr_settings_ena : in std_logic;
128:
129: mr_btr_prop : in std_logic_vector(6 downto 0);
130: mr_btr_ph1 : in std_logic_vector(5 downto 0);
131: mr_btr_ph2 : in std_logic_vector(5 downto 0);
132: mr_btr_brp : in std_logic_vector(7 downto 0);
133: mr_btr_sjw : in std_logic_vector(4 downto 0);
134:
135: mr_btr_fd_prop_fd : in std_logic_vector(5 downto 0);
136: mr_btr_fd_ph1_fd : in std_logic_vector(4 downto 0);
137: mr_btr_fd_ph2_fd : in std_logic_vector(4 downto 0);
138: mr_btr_fd_brp_fd : in std_logic_vector(7 downto 0);
139: mr_btr_fd_sjw_fd : in std_logic_vector(4 downto 0);
140:
141: -------------------------------------------------------------------------------------------
142: -- Output values
143: -------------------------------------------------------------------------------------------
144: -- Time segment 1 - Nominal Bit Time
145: tseg1_nbt : out std_logic_vector(G_TSEG1_NBT_WIDTH - 1 downto 0);
146:
147: -- Time segment 2 - Nominal Bit Time
148: tseg2_nbt : out std_logic_vector(G_TSEG2_NBT_WIDTH - 1 downto 0);
149:
150: -- Baud Rate Prescaler - Nominal Bit Time
151: brp_nbt : out std_logic_vector(G_BRP_NBT_WIDTH - 1 downto 0);
152:
153: -- Synchronisation Jump Width - Nominal Bit Time
154: sjw_nbt : out std_logic_vector(G_SJW_NBT_WIDTH - 1 downto 0);
155:
156: -- Time segment 1 - Data Bit Time
157: tseg1_dbt : out std_logic_vector(G_TSEG1_DBT_WIDTH - 1 downto 0);
158:
159: -- Time segment 2 - Data Bit Time
160: tseg2_dbt : out std_logic_vector(G_TSEG2_DBT_WIDTH - 1 downto 0);
161:
162: -- Baud Rate Prescaler - Data Bit Time
163: brp_dbt : out std_logic_vector(G_BRP_DBT_WIDTH - 1 downto 0);
164:
165: -- Synchronisation Jump Width - Data Bit Time
166: sjw_dbt : out std_logic_vector(G_SJW_DBT_WIDTH - 1 downto 0);
167:
168: -- Signal to load the expected segment length by Bit time counters
169: start_edge : out std_logic
170: );
171: end entity;
172:
173: architecture rtl of bit_time_cfg_capture is
174:
175: -----------------------------------------------------------------------------------------------
176: -- Next values for configuration.
177: -----------------------------------------------------------------------------------------------
178: signal tseg1_nbt_d : std_logic_vector(G_TSEG1_NBT_WIDTH - 1 downto 0);
179: signal tseg1_dbt_d : std_logic_vector(G_TSEG1_DBT_WIDTH - 1 downto 0);
180:
181: constant sync_length : unsigned(7 downto 0) := x"01";
182:
183: -----------------------------------------------------------------------------------------------
184: -- Edge detection after enabling the core
185: -----------------------------------------------------------------------------------------------
186: signal mr_settings_ena_reg : std_logic;
187: signal mr_settings_ena_reg_2 : std_logic;
188:
189: -- Capture signal
190: signal capture : std_logic;
191:
192: begin
193:
194: -----------------------------------------------------------------------------------------------
195: -- SETTINGS[ENA] edge detection
196: -----------------------------------------------------------------------------------------------
197: settings_ena_reg_proc : process(res_n, clk_sys)
198: begin
199: if (res_n = '0') then
200: mr_settings_ena_reg <= '0';
201: mr_settings_ena_reg_2 <= '0';
202: elsif (rising_edge(clk_sys)) then
203: mr_settings_ena_reg <= mr_settings_ena;
204: mr_settings_ena_reg_2 <= mr_settings_ena_reg;
205: end if;
206: end process;
207:
208: -- Capture the configuration upon enabbling of the core.
209: capture <= '1' when (mr_settings_ena = '1' and mr_settings_ena_reg = '0') else
210: '0';
211:
212: -- Start edge is generated one clock cycle after the capture so that resynchronisation will
213: -- capture correct values already!
214: start_edge <= '1' when (mr_settings_ena_reg_2 = '0' and mr_settings_ena_reg = '1') else
215: '0';
216:
217: -----------------------------------------------------------------------------------------------
218: -- Time segment 2
219: -----------------------------------------------------------------------------------------------
220: tseg2_nbt <= std_logic_vector(resize(unsigned(mr_btr_ph2), G_TSEG2_NBT_WIDTH));
221: tseg2_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_ph2_fd),G_TSEG2_DBT_WIDTH));
222:
223: -----------------------------------------------------------------------------------------------
224: -- Synchronisation jump width
225: -----------------------------------------------------------------------------------------------
226: sjw_nbt <= std_logic_vector(resize(unsigned(mr_btr_sjw), G_SJW_NBT_WIDTH));
227: sjw_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_sjw_fd), G_SJW_DBT_WIDTH));
228:
229: -----------------------------------------------------------------------------------------------
230: -- Baud rate prescaler
231: -----------------------------------------------------------------------------------------------
232: brp_nbt <= std_logic_vector(resize(unsigned(mr_btr_brp), G_BRP_NBT_WIDTH));
233: brp_dbt <= std_logic_vector(resize(unsigned(mr_btr_fd_brp_fd), G_BRP_DBT_WIDTH));
234:
235: -----------------------------------------------------------------------------------------------
236: -- Calculation of next values for TSEG1 capture registers
237: -----------------------------------------------------------------------------------------------
238: tseg1_nbt_d <= std_logic_vector(
239: resize(unsigned(mr_btr_prop), G_TSEG1_NBT_WIDTH) +
240: resize(unsigned(mr_btr_ph1), G_TSEG1_NBT_WIDTH) +
241: resize(sync_length, G_TSEG1_NBT_WIDTH));
242:
243: tseg1_dbt_d <= std_logic_vector(
244: resize(unsigned(mr_btr_fd_prop_fd), G_TSEG1_DBT_WIDTH) +
245: resize(unsigned(mr_btr_fd_ph1_fd), G_TSEG1_DBT_WIDTH) +
246: resize(sync_length, G_TSEG1_DBT_WIDTH));
247:
248: -----------------------------------------------------------------------------------------------
249: -- Capture registers for TSEG1
250: -----------------------------------------------------------------------------------------------
251: brp_capt_proc : process(res_n, clk_sys)
252: begin
253: if (res_n = '0') then
254: -- Matching reset values to what is in Memory registers.
255: -- This is to make assertions which check valid bit time config
256: -- happy, no impact on functionality!
257: tseg1_nbt <= std_logic_vector(to_unsigned(9, G_TSEG1_NBT_WIDTH));
258: tseg1_dbt <= std_logic_vector(to_unsigned(7, G_TSEG1_DBT_WIDTH));
259: elsif (rising_edge(clk_sys)) then
260: if (capture = '1') then
261: tseg1_nbt <= tseg1_nbt_d;
262: tseg1_dbt <= tseg1_dbt_d;
263: end if;
264: end if;
265: end process;
266:
267: end architecture;