File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/endian_swapper.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Endian swapper
71: --
72: -- Purpose:
73: -- Swaps endianity of input vector. Size of byte (group) is configurable. Word
74: -- size and selection by generic or input signal is configurable. Output is
75: -- combinatorial.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81: use ieee.math_real.ALL;
82:
83: Library ctu_can_fd_rtl;
84: use ctu_can_fd_rtl.can_constants_pkg.all;
85: use ctu_can_fd_rtl.can_types_pkg.all;
86:
87: use ctu_can_fd_rtl.CAN_FD_register_map.all;
88: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
89:
90: entity endian_swapper is
91: generic (
92:
93: -- When true, output word is endian swapped as long as "swap_by_signal" is true.
94: -- Otherwise it has no meaning.
95: G_SWAP_GEN : boolean;
96:
97: -- Size of word (in groups)
98: G_WORD_SIZE : natural;
99:
100: -- Size of group (in bits)
101: G_GROUP_SIZE : natural
102: );
103: port (
104: -- Data input
105: input : in std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
106:
107: -- Data output
108: output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0)
109: );
110: end entity;
111:
112: architecture rtl of endian_swapper is
113:
114: -- Endian swapped input word
115: signal swapped : std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
116:
117: begin
118:
119: -----------------------------------------------------------------------------------------------
120: -- Endian swap implementation
121: -----------------------------------------------------------------------------------------------
122: swap_proc : process(input)
123: variable l_ind_orig : natural;
124: variable u_ind_orig : natural;
125: variable l_ind_swap : natural;
126: variable u_ind_swap : natural;
127: variable i_inv : natural;
128: begin
129: for i in 0 to G_WORD_SIZE - 1 loop
130: l_ind_orig := i * G_GROUP_SIZE;
131: u_ind_orig := (i + 1) * G_GROUP_SIZE - 1;
132: i_inv := G_WORD_SIZE - i - 1;
133: l_ind_swap := i_inv * G_GROUP_SIZE;
134: u_ind_swap := (i_inv + 1) * G_GROUP_SIZE - 1;
135: swapped(u_ind_swap downto l_ind_swap) <=
136: input(u_ind_orig downto l_ind_orig);
137: end loop;
138: end process;
139:
140: -----------------------------------------------------------------------------------------------
141: -- Swapping by generic
142: -----------------------------------------------------------------------------------------------
143:
144: -- Swap
145: swap_by_generic_true_gen : if (G_SWAP_GEN) generate
146: output <= swapped;
147: end generate swap_by_generic_true_gen;
148:
149: -- Don't Swap
150: swap_by_generic_false_gen : if (not G_SWAP_GEN) generate
151: output <= input;
152: end generate swap_by_generic_false_gen;
153:
154: end architecture;