File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_prescaler_nbt.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Functional coverage for Prescaler
71: --
72: --------------------------------------------------------------------------------
73: -- Revision History:
74: -- 27.4.2025 Created file
75: --------------------------------------------------------------------------------
76:
77: Library ctu_can_fd_tb;
78: context ctu_can_fd_tb.ieee_context;
79: context ctu_can_fd_tb.tb_common_context;
80: context ctu_can_fd_tb.rtl_context;
81:
82: use ctu_can_fd_tb.clk_gen_agent_pkg.all;
83: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
84:
85: entity func_cov_prescaler_nbt is
86: port (
87: -- DUT clock
88: clk : in std_logic
89: );
90: end entity;
91:
92: architecture tb of func_cov_prescaler_nbt is
93:
94: alias is_tseg1 is
95: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.is_tseg1 : std_logic >>;
96:
97: alias is_tseg2 is
98: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.is_tseg2 : std_logic >>;
99:
100: alias exp_seg_length_ce is
101: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.exp_seg_length_ce : std_logic >>;
102:
103: alias use_basic_segm_length is
104: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.use_basic_segm_length : std_logic >>;
105:
106: alias phase_err is
107: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.phase_err : unsigned(7 downto 0) >>;
108:
109: alias sjw is
110: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.sjw : std_logic_vector(4 downto 0) >>;
111:
112: alias exit_segm_req is
113: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.exit_segm_req : std_logic >>;
114:
115: alias exit_ph2_immediate is
116: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.exit_ph2_immediate : std_logic >>;
117:
118: alias exit_segm_regular_tseg1 is
119: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.exit_segm_regular_tseg1 : std_logic >>;
120:
121: alias exit_segm_regular_tseg2 is
122: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.bit_segment_meter_nbt_inst.exit_segm_regular_tseg2 : std_logic >>;
123:
124: alias resync_edge_valid is
125: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.resync_edge_valid : std_logic >>;
126:
127: begin
128:
129: -- psl default clock is rising_edge(clk);
130:
131: -- Positive resynchronization with E < SJW
132: -- psl nbt_pos_resync_e_less_than_sjw_cov : cover
133: -- {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1'
134: -- and resync_edge_valid = '1' and
135: -- (to_integer(unsigned(phase_err)) < to_integer(unsigned(sjw)))};
136:
137: -- Positive resynchronization with E > SJW
138: -- psl nbt_pos_resync_e_more_than_sjw_cov : cover
139: -- {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1'
140: -- and resync_edge_valid = '1' and
141: -- (to_integer(unsigned(phase_err)) > to_integer(unsigned(sjw)))};
142:
143: -- Positive resynchronization with E = SJW
144: -- psl nbt_pos_resync_e_equal_sjw_cov : cover
145: -- {exp_seg_length_ce = '1' and use_basic_segm_length = '0' and is_tseg1 = '1'
146: -- and resync_edge_valid = '1' and
147: -- (to_integer(unsigned(phase_err)) = to_integer(unsigned(sjw)))};
148:
149: -- Negative resynchronization with E < SJW
150: -- psl nbt_neg_resync_e_less_than_sjw_cov : cover
151: -- {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and
152: -- (to_integer(unsigned(phase_err)) < to_integer(unsigned(sjw)))};
153:
154: -- Negative resynchronization with E > SJW
155: -- psl nbt_neg_resync_e_more_than_sjw_cov : cover
156: -- {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and
157: -- (to_integer(unsigned(phase_err)) > to_integer(unsigned(sjw)))};
158:
159: -- Negative resynchronization with E = SJW
160: -- psl nbt_neg_resync_e_equal_sjw_cov : cover
161: -- {exp_seg_length_ce = '1' and resync_edge_valid = '1' and is_tseg2 = '1' and
162: -- (to_integer(unsigned(phase_err)) = to_integer(unsigned(sjw)))};
163:
164: -- psl nbt_exit_segm_immediate_cov : cover
165: -- {exit_segm_req = '1' and exit_ph2_immediate = '1'};
166:
167: -- psl nbt_exit_segm_regular_tseg1_cov : cover
168: -- {exit_segm_req = '1' and exit_segm_regular_tseg1 = '1' and exit_segm_regular_tseg2 = '0'};
169:
170: -- psl nbt_exit_segm_regular_tseg2_cov : cover
171: -- {exit_segm_req = '1' and exit_segm_regular_tseg1 = '0' and exit_segm_regular_tseg2 = '1'};
172:
173: end architecture;