File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_fsm.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Fault confinement FSM.
71: --
72: -- Purpose:
73: -- Implements Fault confinement state of a node. State is changed when Error
74: -- Counters reach according threshold. Error warning limit interrupt is
75: -- supported. Error warning limit and Error passive threshold are configurable
76: -- from Driving Bus. Protocol control sets node to error active upon the end
77: -- of Intefration and Re-integration.
78: --------------------------------------------------------------------------------
79:
80: Library ieee;
81: use ieee.std_logic_1164.all;
82: use ieee.numeric_std.ALL;
83:
84: Library ctu_can_fd_rtl;
85: use ctu_can_fd_rtl.can_constants_pkg.all;
86: use ctu_can_fd_rtl.can_types_pkg.all;
87:
88: use ctu_can_fd_rtl.CAN_FD_register_map.all;
89: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
90:
91: entity fault_confinement_fsm is
92: port (
93: -------------------------------------------------------------------------------------------
94: -- Clock and Asynchronous Reset
95: -------------------------------------------------------------------------------------------
96: clk_sys : in std_logic;
97: res_n : in std_logic;
98:
99: -------------------------------------------------------------------------------------------
100: -- Control signals
101: -------------------------------------------------------------------------------------------
102: -- Set unit to be error active
103: set_err_active : in std_logic;
104:
105: -------------------------------------------------------------------------------------------
106: -- Memory registers interface
107: -------------------------------------------------------------------------------------------
108: mr_ewl_ew_limit : in std_logic_vector(7 downto 0);
109: mr_erp_erp_limit : in std_logic_vector(7 downto 0);
110:
111: mr_status_ewl : out std_logic;
112:
113: -------------------------------------------------------------------------------------------
114: -- Error counters
115: -------------------------------------------------------------------------------------------
116: -- TX Error counter
117: tx_err_ctr : in std_logic_vector(8 downto 0);
118:
119: -- RX Error counter
120: rx_err_ctr : in std_logic_vector(8 downto 0);
121:
122: -------------------------------------------------------------------------------------------
123: -- Fault confinement State indication
124: -------------------------------------------------------------------------------------------
125: -- Unit is error active
126: is_err_active : out std_logic;
127:
128: -- Unit is error passive
129: is_err_passive : out std_logic;
130:
131: -- Unit is Bus-off
132: is_bus_off : out std_logic;
133:
134: -------------------------------------------------------------------------------------------
135: -- Status outputs
136: -------------------------------------------------------------------------------------------
137: -- Fault confinement state changed
138: fcs_changed : out std_logic;
139:
140: -- Error warning limit was reached
141: err_warning_limit_pulse : out std_logic
142: );
143: end entity;
144:
145: architecture rtl of fault_confinement_fsm is
146:
147: signal tx_err_ctr_mt_erp : std_logic;
148: signal rx_err_ctr_mt_erp : std_logic;
149:
150: signal tx_err_ctr_mt_ewl : std_logic;
151: signal rx_err_ctr_mt_ewl : std_logic;
152:
153: signal tx_err_ctr_mt_255 : std_logic;
154:
155: -- Error warning limit register (to detect change)
156: signal err_warning_limit_d : std_logic;
157: signal err_warning_limit_q : std_logic;
158:
159: -----------------------------------------------------------------------------------------------
160: -- Fault confinement FSM
161: -----------------------------------------------------------------------------------------------
162: signal curr_state : t_fault_conf_state;
163: signal next_state : t_fault_conf_state;
164:
165: begin
166:
167: -- TX Error counter more than Error Passive Limit
168: tx_err_ctr_mt_erp <= '1' when (unsigned(tx_err_ctr) >= unsigned(mr_erp_erp_limit))
169: else
170: '0';
171:
172: -- RX Error counter more than Error Passive Limit
173: rx_err_ctr_mt_erp <= '1' when (unsigned(rx_err_ctr) >= unsigned(mr_erp_erp_limit))
174: else
175: '0';
176:
177: -- TX Error counter more than 255
178: tx_err_ctr_mt_255 <= '1' when (unsigned(tx_err_ctr) > 255)
179: else
180: '0';
181:
182: -- TX Error counter more than Error Warning Limit
183: tx_err_ctr_mt_ewl <= '1' when (unsigned(tx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit)))
184: else
185: '0';
186:
187: -- RX Error counter more than Error Warning Limit
188: rx_err_ctr_mt_ewl <= '1' when (unsigned(rx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit)))
189: else
190: '0';
191:
192: err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1')
193: else
194: '0';
195:
196: -----------------------------------------------------------------------------------------------
197: -- Error warning limit register
198: -----------------------------------------------------------------------------------------------
199: ewl_reg_proc : process(res_n, clk_sys)
200: begin
201: if (res_n = '0') then
202: err_warning_limit_q <= '0';
203: elsif (rising_edge(clk_sys)) then
204: err_warning_limit_q <= err_warning_limit_d;
205: end if;
206: end process;
207:
208: err_warning_limit_pulse <= '1' when (err_warning_limit_d /= err_warning_limit_q)
209: else
210: '0';
211:
212: mr_status_ewl <= err_warning_limit_d;
213:
214: -----------------------------------------------------------------------------------------------
215: -- Next state process
216: -----------------------------------------------------------------------------------------------
217: fc_fsm_next_state_proc : process(curr_state, tx_err_ctr_mt_255,
218: tx_err_ctr_mt_erp, rx_err_ctr_mt_erp, set_err_active)
219: begin
220: next_state <= curr_state;
221:
222: case curr_state is
223: when s_fc_err_active =>
224: if (tx_err_ctr_mt_erp = '1' or rx_err_ctr_mt_erp = '1') then
225: next_state <= s_fc_err_passive;
226: end if;
227:
228: when s_fc_err_passive =>
229: if (tx_err_ctr_mt_255 = '1') then
230: next_state <= s_fc_bus_off;
231: elsif (tx_err_ctr_mt_erp = '0' and rx_err_ctr_mt_erp = '0') then
232: next_state <= s_fc_err_active;
233: end if;
234:
235: when s_fc_bus_off =>
236: if (set_err_active = '1') then
237: next_state <= s_fc_err_active;
238: end if;
239: end case;
240:
241: end process;
242:
243: -----------------------------------------------------------------------------------------------
244: -- State register
245: -----------------------------------------------------------------------------------------------
246: fault_conf_state_reg : process(clk_sys, res_n)
247: begin
248: if (res_n = '0') then
249: curr_state <= s_fc_bus_off;
250: elsif (rising_edge(clk_sys)) then
251: curr_state <= next_state;
252: end if;
253: end process;
254:
255: -----------------------------------------------------------------------------------------------
256: -- Current state
257: -----------------------------------------------------------------------------------------------
258: fc_fsm_curr_state_proc : process(curr_state)
259: begin
260: is_err_active <= '0';
261: is_err_passive <= '0';
262: is_bus_off <= '0';
263:
264: case curr_state is
265: when s_fc_err_active =>
266: is_err_active <= '1';
267:
268: when s_fc_err_passive =>
269: is_err_passive <= '1';
270:
271: when s_fc_bus_off =>
272: is_bus_off <= '1';
273: end case;
274: end process;
275:
276: -- Fault confinement state changed when current state is not equal to next state.
277: fcs_changed <= '1' when (curr_state /= next_state) else
278: '0';
279:
280: end architecture;