File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/ssp_generator.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Secondary Sampling point generator.
71: --
72: -- Purpose:
73: -- Create SSP by delaying TX trigger. First TX Trigger after bit-rate switch
74: -- is delayed by SSP Offset, each next by length of bit time. Length of bit
75: -- time is measured in multiples of clock cycles.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: entity ssp_generator is
90: generic(
91: -- Width of SSP generator counters (BTMC, SSPC)
92: G_SSP_CTRS_WIDTH : natural;
93:
94: -- Width of SSP position
95: G_SSP_POS_WIDTH : natural
96: );
97: port(
98: -------------------------------------------------------------------------------------------
99: -- Clock and Async reset
100: -------------------------------------------------------------------------------------------
101: clk_sys :in std_logic;
102: res_n :in std_logic;
103:
104: -------------------------------------------------------------------------------------------
105: -- Control signals
106: -------------------------------------------------------------------------------------------
107: -- Reset Bit time measurement counter
108: btmc_reset :in std_logic;
109:
110: -- Start Measurement of data bit time (in TX Trigger)
111: dbt_measure_start :in std_logic;
112:
113: -- First SSP generated (in ESI bit)
114: gen_first_ssp :in std_logic;
115:
116: -- SSP offset
117: ssp_delay :in std_logic_vector(G_SSP_POS_WIDTH - 1 downto 0);
118:
119: -- SSP enable (SSP trigger gated when disabled)
120: ssp_enable :in std_logic;
121:
122: -------------------------------------------------------------------------------------------
123: -- Trigger signals
124: -------------------------------------------------------------------------------------------
125: -- TX Trigger
126: tx_trigger :in std_logic;
127:
128: -- RX Trigger
129: sample_sec :out std_logic
130: );
131: end entity;
132:
133: architecture rtl of ssp_generator is
134:
135: -- Bit time measuremend counter
136: signal btmc_d : std_logic_vector(G_SSP_CTRS_WIDTH - 1 downto 0);
137: signal btmc_q : std_logic_vector(G_SSP_CTRS_WIDTH - 1 downto 0);
138: signal btmc_add : std_logic_vector(G_SSP_CTRS_WIDTH - 1 downto 0);
139: signal btmc_ce : std_logic;
140:
141: -- Measurement running flag
142: signal btmc_meas_running_d : std_logic;
143: signal btmc_meas_running_q : std_logic;
144:
145: -- SSP counter
146: signal sspc_d : unsigned(G_SSP_CTRS_WIDTH - 1 downto 0);
147: signal sspc_q : unsigned(G_SSP_CTRS_WIDTH - 1 downto 0);
148: signal sspc_ce : std_logic;
149: signal sspc_expired : std_logic;
150: signal sspc_threshold : unsigned(G_SSP_CTRS_WIDTH - 1 downto 0);
151: signal sspc_add : unsigned(G_SSP_CTRS_WIDTH - 1 downto 0);
152:
153: constant C_SSPC_RST_VAL : unsigned(G_SSP_CTRS_WIDTH - 1 downto 0) := to_unsigned(1, G_SSP_CTRS_WIDTH);
154:
155: -- First SSP flag
156: signal first_ssp_d : std_logic;
157: signal first_ssp_q : std_logic;
158:
159: -- SSP running flag
160: signal sspc_ena_d : std_logic;
161: signal sspc_ena_q : std_logic;
162:
163: begin
164:
165: -------------------------------------------------------------------------------------------
166: -- Bit time measurement control:
167: -- 1. Reset on measurement restart.
168: -- 2. Start when commanded by Protocol control (ESI bit) and TX Trigger occurs!
169: -- 3. Stop on next TX Trigger (measurement should not be set then)
170: -------------------------------------------------------------------------------------------
171: btmc_meas_running_d <= '0' when (btmc_reset = '1') else
172: '1' when (dbt_measure_start = '1' and tx_trigger = '1') else
173: '0' when (tx_trigger = '1') else
174: btmc_meas_running_q;
175:
176: btmc_meas_flag_proc : process(clk_sys, res_n)
177: begin
178: if (res_n = '0') then
179: btmc_meas_running_q <= '0';
180: elsif (rising_edge(clk_sys)) then
181: btmc_meas_running_q <= btmc_meas_running_d;
182: end if;
183: end process;
184:
185: -------------------------------------------------------------------------------------------
186: -- Bit time counter measurement:
187: -- 1. Reset
188: -- 2. Increment when measurement is running
189: -- 3. Keep value otherwise
190: -------------------------------------------------------------------------------------------
191: btmc_d <= (others => '0') when (btmc_reset = '1') else
192: btmc_add when (btmc_meas_running_q = '1') else
193: btmc_q;
194:
195: btmc_add <= std_logic_vector(unsigned(btmc_q) + 1);
196:
197: btmc_ce <= '1' when (btmc_d /= btmc_q) else
198: '0';
199:
200: btmc_proc : process(clk_sys, res_n)
201: begin
202: if (res_n = '0') then
203: btmc_q <= (others => '0');
204: elsif (rising_edge(clk_sys)) then
205: if (btmc_ce = '1') then
206: btmc_q <= btmc_d;
207: end if;
208: end if;
209: end process;
210:
211: -------------------------------------------------------------------------------------------
212: -- First SSP flag:
213: -- 1. Set in TX trigger of ESI (first SSP delay starts).
214: -- 2. Cleared when first SSP is reached.
215: -------------------------------------------------------------------------------------------
216: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else
217: '0' when (sspc_expired = '1') else
218: first_ssp_q;
219:
220: first_ssp_flag_proc : process(clk_sys, res_n)
221: begin
222: if (res_n = '0') then
223: first_ssp_q <= '0';
224: elsif (rising_edge(clk_sys)) then
225: first_ssp_q <= first_ssp_d;
226: end if;
227: end process;
228:
229:
230: -------------------------------------------------------------------------------------------
231: -- SSP counting:
232: -- 1. Enable on TX Trigger of ESI
233: -- 2. Disable when SSP gets disabled
234: -------------------------------------------------------------------------------------------
235: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else
236: '0' when (ssp_enable = '0') else
237: sspc_ena_q;
238:
239: sspc_run_flag_proc : process(clk_sys, res_n)
240: begin
241: if (res_n = '0') then
242: sspc_ena_q <= '0';
243: elsif (rising_edge(clk_sys)) then
244: sspc_ena_q <= sspc_ena_d;
245: end if;
246: end process;
247:
248: -------------------------------------------------------------------------------------------
249: -------------------------------------------------------------------------------------------
250: -- SSP Counter
251: -------------------------------------------------------------------------------------------
252: -------------------------------------------------------------------------------------------
253:
254: -------------------------------------------------------------------------------------------
255: -- SSP measurement threshold:
256: -- 1. Count till SSP offset in first SSP.
257: -- 2. Count till bit time length in further SSPs (measured by BTMC)
258: -------------------------------------------------------------------------------------------
259: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')
260: else
261: unsigned(btmc_q);
262:
263: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else
264: '0';
265:
266: sspc_add <= sspc_q + 1;
267:
268: -------------------------------------------------------------------------------------------
269: -- SSP counter:
270: -- 1. Reset before, or when expired (auto reset)
271: -- 2. Count when enabled
272: -------------------------------------------------------------------------------------------
273: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else
274: sspc_add when (sspc_ena_q = '1') else
275: sspc_q;
276:
277: sspc_ce <= '1' when (sspc_d /= sspc_q) else
278: '0';
279:
280: sspc_proc : process(clk_sys, res_n)
281: begin
282: if (res_n = '0') then
283: sspc_q <= C_SSPC_RST_VAL;
284: elsif (rising_edge(clk_sys)) then
285: if (sspc_ce = '1') then
286: sspc_q <= sspc_d;
287: end if;
288: end if;
289: end process;
290:
291: -------------------------------------------------------------------------------------------
292: -- Generation of SSP trigger
293: -------------------------------------------------------------------------------------------
294: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else
295: '0';
296:
297: -------------------------------------------------------------------------------------------
298: -- Assertions
299: -------------------------------------------------------------------------------------------
300: -- psl default clock is rising_edge(clk_sys);
301:
302: -- psl no_sspc_overflow : assert never
303: -- (unsigned(sspc_d) < unsigned(sspc_q)) and (btmc_reset = '0' and sspc_expired = '0')
304: -- report "SSPC overflow";
305:
306: -- psl no_btmc_overflow : assert never
307: -- ((unsigned(btmc_d) < unsigned(btmc_q)) and (btmc_reset /= '1'))
308: -- report "BTMC overflow";
309:
310: end architecture;