File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/sample_mux.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Sample multiplexor.
71: --
72: -- Purpose:
73: -- Maintains a value sampled in previous sample point. This is then used
74: -- by other modules within Bus sampling.
75: --------------------------------------------------------------------------------
76:
77: Library ieee;
78: use ieee.std_logic_1164.all;
79: use ieee.numeric_std.ALL;
80:
81: Library ctu_can_fd_rtl;
82: use ctu_can_fd_rtl.can_constants_pkg.all;
83: use ctu_can_fd_rtl.can_types_pkg.all;
84:
85: use ctu_can_fd_rtl.CAN_FD_register_map.all;
86: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
87:
88: entity sample_mux is
89: port (
90: -------------------------------------------------------------------------------------------
91: -- Clock and Async reset
92: -------------------------------------------------------------------------------------------
93: clk_sys :in std_logic;
94: res_n :in std_logic;
95:
96: -------------------------------------------------------------------------------------------
97: -- Control signals
98: -------------------------------------------------------------------------------------------
99: -- Sample control (nominal, data, secondary)
100: sp_control :in std_logic_vector(1 downto 0);
101:
102: -- RX Trigger
103: rx_trigger :in std_logic;
104:
105: -- RX Trigger - Secondary Sampling
106: sample_sec :in std_logic;
107:
108: -------------------------------------------------------------------------------------------
109: -- Memory registers interface
110: -------------------------------------------------------------------------------------------
111: mr_settings_ena :in std_logic;
112:
113: -------------------------------------------------------------------------------------------
114: -- Datapath
115: -------------------------------------------------------------------------------------------
116: -- RX Data (synchronised)
117: data_rx_synced :in std_logic;
118:
119: -- Sampled value of RX pin in Sample point (DFF output)
120: prev_sample :out std_logic
121: );
122: end entity;
123:
124: architecture rtl of sample_mux is
125:
126: -- Internal sample signal (muxed for NBT, DBT and SAMPLE)
127: signal sample : std_logic;
128:
129: -- Bit error detected value
130: signal prev_sample_d : std_logic;
131: signal prev_sample_q : std_logic;
132:
133: begin
134:
135: -------------------------------------------------------------------------------------------
136: -- Sample point multiplexor
137: -------------------------------------------------------------------------------------------
138: sample <= sample_sec when (sp_control = SECONDARY_SAMPLE) else
139: rx_trigger;
140:
141: -------------------------------------------------------------------------------------------
142: -- Previous sample register
143: -------------------------------------------------------------------------------------------
144: prev_sample_d <= data_rx_synced when (sample = '1') else
145: prev_sample_q;
146:
147: sample_prev_req_proc : process(clk_sys, res_n)
148: begin
149: if (res_n = '0') then
150: prev_sample_q <= RECESSIVE;
151: elsif (rising_edge(clk_sys)) then
152: if (mr_settings_ena = '1') then
153: prev_sample_q <= prev_sample_d;
154: end if;
155: end if;
156: end process;
157:
158: -------------------------------------------------------------------------------------------
159: -- Internal signal to output propagation
160: -------------------------------------------------------------------------------------------
161: prev_sample <= prev_sample_q;
162:
163: end architecture;