File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/feature_test_agent/feature_test_agent.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Feature test agent. Executes feature tests.
71: --
72: -- Feature test agent is started by test controller agent, when test_type
73: -- is configured to "feature". Feature test agent resets DUT, configures it,
74: -- enables it, runs test sequence.
75: --
76: --------------------------------------------------------------------------------
77: -- Revision History:
78: -- 11.3.2021 Created file
79: --------------------------------------------------------------------------------
80:
81: Library ctu_can_fd_tb;
82: context ctu_can_fd_tb.ieee_context;
83: context ctu_can_fd_tb.tb_common_context;
84: context ctu_can_fd_tb.rtl_context;
85: context ctu_can_fd_tb.tb_agents_context;
86:
87: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
88:
89: entity feature_test_agent is
90: generic(
91: -- Test details
92: test_name : string;
93: test_type : string;
94:
95: -- DUT config
96: cfg_sys_clk_period : string;
97:
98: -- Bit timing cofnig used in; compliance tests
99: cfg_brp : natural;
100: cfg_prop : natural;
101: cfg_ph_1 : natural;
102: cfg_ph_2 : natural;
103: cfg_sjw : natural;
104: cfg_brp_fd : natural;
105: cfg_prop_fd : natural;
106: cfg_ph_1_fd : natural;
107: cfg_ph_2_fd : natural;
108: cfg_sjw_fd : natural;
109:
110: -- Secondary sample point config
111: cfg_ssp_src : natural;
112: cfg_ssp_offset : natural
113: );
114: port(
115: -----------------------------------------------------------------------
116: -- Test node connections
117: -----------------------------------------------------------------------
118: clk_sys : in std_logic;
119: res_n : in std_logic;
120:
121: write_data : in std_logic_vector(31 DOWNTO 0);
122: read_data : out std_logic_vector(31 DOWNTO 0);
123: adress : in std_logic_vector(15 DOWNTO 0);
124: scs : in std_logic;
125: srd : in std_logic;
126: swr : in std_logic;
127: sbe : in std_logic_vector(3 DOWNTO 0);
128:
129: -- CAN bus from/to DUT
130: dut_can_tx : in std_logic;
131: dut_can_rx : out std_logic;
132:
133: -- Test Nodes test probe output
134: test_node_test_probe : out t_ctu_can_fd_test_probe;
135: test_node_scan_enable : in std_logic
136: );
137: end entity;
138:
139:
140: architecture tb of feature_test_agent is
141:
142: signal bus_level : std_logic;
143:
144: -- Test node signals
145: signal test_node_can_tx : std_logic;
146: signal test_node_can_rx : std_logic;
147:
148: -- Signals with 1 ps delay (close to delta celay only)
149: signal dut_can_tx_delta_delay : std_logic;
150: signal test_node_can_tx_delta_delay : std_logic;
151:
152: -- Delayed CAN bus signals
153: signal dut_can_tx_delayed : std_logic := '1';
154: signal test_node_can_tx_delayed : std_logic := '1';
155:
156: -- Forcing bus level value (ANDed bus level)
157: signal force_bus_level_i : boolean := false;
158: signal force_bus_level_value : std_logic := '0';
159:
160: -- Inverting bus value compared
161: signal flip_bus_level_i : boolean := false;
162:
163: -- Forcing CAN RX of only single node
164: signal force_can_rx_dut : boolean := false;
165: signal force_can_rx_test_node : boolean := false;
166: signal force_can_rx_value : std_logic := '0';
167:
168: -- Transceiver delays (on can_tx signal)
169: signal can_tx_delay_dut : time := 1 ns;
170: signal can_tx_delay_test_node : time := 1 ns;
171:
172: -- ANDed TX (expected bus level upon regular transmission)
173: signal anded_tx : std_logic;
174:
175: begin
176:
177: ---------------------------------------------------------------------------
178: -- Test node
179: ---------------------------------------------------------------------------
180: test_node_inst : entity ctu_can_fd_rtl.can_top_level
181: generic map(
182: -- Keep config hard-coded, it is enough that DUT is configurable!
183: rx_buffer_size => 256, -- Size to receive 8 frames is needed
184: txt_buffer_count => 4,
185: sup_filtA => false,
186: sup_filtB => false,
187: sup_filtC => false,
188: sup_range => false,
189: sup_traffic_ctrs => true,
190: target_technology => C_TECH_ASIC
191: )
192: port map(
193: -- Clock and Asynchronous reset
194: clk_sys => clk_sys,
195: res_n => res_n,
196:
197: -- DFT support
198: scan_enable => test_node_scan_enable,
199:
200: -- Memory interface
201: data_in => write_data,
202: data_out => read_data,
203: adress => adress,
204: scs => scs,
205: srd => srd,
206: swr => swr,
207: sbe => sbe,
208:
209: -- Interrupt Interface - not needed for test node
210: int => open,
211:
212: -- CAN Bus Interface
213: can_tx => test_node_can_tx,
214: can_rx => test_node_can_rx,
215:
216: -- Test probe, timestamp, not needed for test node!
217: test_probe => test_node_test_probe,
218: timestamp => (OTHERS => '1')
219: );
220:
221: ---------------------------------------------------------------------------
222: -- Comunication receiver process
223: ---------------------------------------------------------------------------
224: receiver_proc : process
225: variable cmd : integer;
226: variable reply_code : integer;
227: variable tmp : integer;
228: variable tmp_logic : std_logic;
229: begin
230: receive_start(default_channel, C_FEATURE_TEST_AGENT_ID);
231:
232: -- Command is sent as message type
233: cmd := com_channel_data.get_msg_code;
234: reply_code := C_REPLY_CODE_OK;
235:
236: case cmd is
237: when FEATURE_TEST_AGNT_FORCE_BUS =>
238: force_bus_level_value <= com_channel_data.get_param;
239: force_bus_level_i <= true;
240:
241: when FEATURE_TEST_AGNT_RELEASE_BUS =>
242: force_bus_level_i <= false;
243: flip_bus_level_i <= false;
244:
245: when FEATURE_TEST_AGNT_FORCE_CAN_RX =>
246: tmp := com_channel_data.get_param;
247: force_can_rx_value <= com_channel_data.get_param;
248: if (tmp = 0) then
249: force_can_rx_dut <= true;
250: else
251: force_can_rx_test_node <= true;
252: end if;
253:
254: when FEATURE_TEST_AGNT_RELEASE_CAN_RX =>
255: force_can_rx_dut <= false;
256: force_can_rx_test_node <= false;
257:
258: when FEATURE_TEST_AGNT_SET_TRV_DELAY =>
259: tmp := com_channel_data.get_param;
260: if (tmp = 0) then
261: can_tx_delay_dut <= com_channel_data.get_param;
262: else
263: can_tx_delay_test_node <= com_channel_data.get_param;
264: end if;
265:
266: when FEATURE_TEST_AGNT_CHECK_BUS_LEVEL =>
267: tmp_logic := com_channel_data.get_param;
268: check_m(tmp_logic = bus_level, FEATURE_TEST_AGENT_TAG &
269: "Bus level value shoul be:" & std_logic'image(tmp_logic));
270:
271: when FEATURE_TEST_AGNT_CHECK_CAN_TX =>
272: tmp := com_channel_data.get_param;
273: tmp_logic := com_channel_data.get_param;
274: if (tmp = 0) then
275: check_m(tmp_logic = dut_can_tx, "DUT CAN TX");
276: else
277: check_m(tmp_logic = test_node_can_tx, "Test node CAN TX");
278: end if;
279:
280: when FEATURE_TEST_AGNT_GET_CAN_TX =>
281: tmp := com_channel_data.get_param;
282: if (tmp = 0) then
283: com_channel_data.set_param(dut_can_tx);
284: else
285: com_channel_data.set_param(test_node_can_tx);
286: end if;
287:
288: when FEATURE_TEST_AGNT_GET_CAN_RX =>
289: tmp := com_channel_data.get_param;
290: if (tmp = 0) then
291: com_channel_data.set_param(dut_can_rx);
292: else
293: com_channel_data.set_param(test_node_can_rx);
294: end if;
295:
296: when FEATURE_TEST_AGNT_FLIP_BUS =>
297: flip_bus_level_i <= true;
298:
299: when others =>
300: info_m("Invalid message type: " & integer'image(cmd));
301: reply_code := C_REPLY_CODE_ERR;
302:
303: end case;
304: receive_finish(default_channel, reply_code);
305: end process;
306:
307: ---------------------------------------------------------------------------
308: -- Signal delaying
309: ---------------------------------------------------------------------------
310: i_tx_delay_dut : entity ctu_can_fd_tb.signal_delayer
311: generic map (
312: NSAMPLES => 32
313: )
314: port map (
315: input => dut_can_tx_delta_delay,
316: delay => can_tx_delay_dut,
317: delayed => dut_can_tx_delayed
318: );
319:
320: i_tx_delay_test_node : entity ctu_can_fd_tb.signal_delayer
321: generic map (
322: NSAMPLES => 32
323: )
324: port map (
325: input => test_node_can_tx_delta_delay,
326: delay => can_tx_delay_test_node,
327: delayed => test_node_can_tx_delayed
328: );
329:
330: ---------------------------------------------------------------------------
331: -- On RTL, can_tx is 'U' at time zero, and it gets defined value when
332: -- res_n is asserted. Thus 'U' -> 1 event occurs in non-zero time.
333: -- On Xilinx gate level sims, having res_n = 'U' first few nanoseconds of
334: -- simulation does cause output of flop in reset synchronizer to be '0',
335: -- not 'U'. Thus synchronized reset is '0' from time 0, and there is no
336: -- event on it when res_n input gets asserted non-'U' value! This causes
337: -- can_tx to be set to '1' from time 0 of simulation. As consequence of
338: -- this, signal delayer will ignore the first event on can_tx in time 0,
339: -- and will keep its output at 0!
340: ---------------------------------------------------------------------------
341: dut_can_tx_delta_delay <= dut_can_tx after 1 ps;
342: test_node_can_tx_delta_delay <= test_node_can_tx after 1 ps;
343:
344: ---------------------------------------------------------------------------
345: -- Bus level and RX signal of each node
346: ---------------------------------------------------------------------------
347: anded_tx <= dut_can_tx_delayed and test_node_can_tx_delayed;
348:
349: bus_level <= force_bus_level_value when force_bus_level_i else
350: not (anded_tx) when flip_bus_level_i else
351: anded_tx;
352:
353: dut_can_rx <= force_can_rx_value when force_can_rx_dut else
354: bus_level;
355:
356: test_node_can_rx <= force_can_rx_value when force_can_rx_test_node else
357: bus_level;
358:
359: ---------------------------------------------------------------------------
360: ---------------------------------------------------------------------------
361: -- Test control process
362: --
363: -- Waits on start request from Test controller agent and runs a test.
364: ---------------------------------------------------------------------------
365: ---------------------------------------------------------------------------
366: test_process : process
367: variable bus_timing : t_ctu_bit_time_cfg :=(
368: tq_nbt => cfg_brp,
369: tq_dbt => cfg_brp_fd,
370: prop_nbt => cfg_prop,
371: ph1_nbt => cfg_ph_1,
372: ph2_nbt => cfg_ph_2,
373: sjw_nbt => cfg_sjw,
374: prop_dbt => cfg_prop_fd,
375: ph1_dbt => cfg_ph_1_fd,
376: ph2_dbt => cfg_ph_2_fd,
377: sjw_dbt => cfg_sjw_fd
378: );
379: begin
380: wait until feature_start = '1';
381:
382: -- Pre-set test to be "passed", any error will make it fail
383: ctu_vip_test_result.set_result(true);
384:
385: -- Initialize TXT Buffer memories
386: info_m("***************************************************************");
387: info_m("Clearing TXT Buffer memories!");
388: info_m("***************************************************************");
389: info_m("DUT node:");
390: ctu_init_txtb_mems(DUT_NODE, default_channel);
391: info_m("Test node:");
392: ctu_init_txtb_mems(TEST_NODE, default_channel);
393:
394: -- Configure bit timing
395: ctu_set_bit_time_cfg(bus_timing, DUT_NODE, default_channel);
396: ctu_set_bit_time_cfg(bus_timing, TEST_NODE, default_channel);
397:
398: -- Configure secondary sample point
399: ctu_set_ssp(t_ctu_ssp_kind'val(cfg_ssp_src),
400: std_logic_vector(to_unsigned(cfg_ssp_offset, 8)),
401: DUT_NODE, default_channel);
402:
403: ctu_set_ssp(t_ctu_ssp_kind'val(cfg_ssp_src),
404: std_logic_vector(to_unsigned(cfg_ssp_offset, 8)),
405: TEST_NODE, default_channel);
406:
407: -- Set default retransmitt limit to 0 (Failed frames are not retransmited)
408: ctu_set_retr_limit(true, 0, DUT_NODE, default_channel);
409: ctu_set_retr_limit(true, 0, TEST_NODE, default_channel);
410:
411: -- Enable CAN controllers
412: ctu_turn(true, DUT_NODE, default_channel);
413: ctu_turn(true, TEST_NODE, default_channel);
414: info_m("Controllers are ON");
415:
416: -- Wait till integration is over in both nodes
417: ctu_wait_err_active(DUT_NODE, default_channel);
418: ctu_wait_err_active(TEST_NODE, default_channel);
419: info_m("Bus integration finished");
420:
421: -- Execute feature test
422: exec_feature_test(test_name, default_channel);
423:
424: -- Signal test is done.
425: feature_result <= ctu_vip_test_result.get_result;
426: wait for 0 ns;
427: feature_done <= '1';
428: wait until feature_start = '0';
429: feature_done <= '0';
430: wait for 0 ns;
431:
432: end process;
433:
434: end architecture;