File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/tb_top_vunit_ctu_can_fd.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- CTU CAN FD main testbench top
71: --
72: --------------------------------------------------------------------------------
73: -- Revision History:
74: -- 26.1.2021 Created file
75: --------------------------------------------------------------------------------
76:
77: -- Only top level uses Vunit. This allows keeping CTU CAN FD VIP Vunit-less,
78: -- when integrating RTL and VIP into other TB!
79: library vunit_lib;
80: context vunit_lib.vunit_context;
81:
82: -- Common contexts
83: Library ctu_can_fd_tb;
84: context ctu_can_fd_tb.ieee_context;
85: context ctu_can_fd_tb.tb_common_context;
86: context ctu_can_fd_tb.tb_agents_context;
87: context ctu_can_fd_tb.rtl_context;
88:
89: entity tb_top_ctu_can_fd is
90: generic(
91: -- Test-bench specific stuff
92: runner_cfg : string := runner_cfg_default;
93: test_name : string := "device_id";
94: test_type : string := "feature"; -- "feature", "compliance" or "reference"
95: log_level : t_log_verbosity := verbosity_info;
96: func_cov_en : boolean := true;
97:
98: iterations : natural := 1;
99: timeout : string := "10 ms";
100:
101: is_force_supported : boolean := true;
102:
103: -- Reference test iterations
104: reference_iterations : natural range 1 to 1000 := 10;
105:
106: -- Clock configuration of DUT
107: cfg_sys_clk_period : string := "10 ns";
108:
109: -- Finish on report Error
110: finish_on_error : natural := 0;
111:
112: -- Bit timing config of DUT on CAN bus (used by compliance tests)
113: cfg_brp : natural := 4;
114: cfg_prop : natural := 0;
115: cfg_ph_1 : natural := 1;
116: cfg_ph_2 : natural := 1;
117: cfg_sjw : natural := 2;
118: cfg_brp_fd : natural := 1;
119: cfg_prop_fd : natural := 3;
120: cfg_ph_1_fd : natural := 1;
121: cfg_ph_2_fd : natural := 2;
122: cfg_sjw_fd : natural := 2;
123:
124: -- Secondary sample point config
125: cfg_ssp_src : natural := 0;
126: cfg_ssp_offset : natural := 10;
127:
128: -- DUT configuration
129: rx_buffer_size : natural := 64;
130: txt_buffer_count : natural range 2 to 8 := 8;
131: sup_filtA : boolean := true;
132: sup_filtB : boolean := true;
133: sup_filtC : boolean := true;
134: sup_range : boolean := true;
135: sup_traffic_ctrs : boolean := true;
136: sup_parity : boolean := true;
137: target_technology : natural := C_TECH_ASIC;
138: reset_buffer_rams : boolean := false;
139:
140: -- Seed
141: seed : natural := 0
142: );
143: end entity;
144:
145: architecture tb of tb_top_ctu_can_fd is
146:
147: -- DUT interface
148: signal clk_sys : std_logic;
149: signal res_n : std_logic;
150:
151: signal write_data : std_logic_vector(31 DOWNTO 0);
152: signal read_data : std_logic_vector(31 DOWNTO 0);
153: signal address : std_logic_vector(15 DOWNTO 0);
154: signal scs : std_logic;
155: signal swr : std_logic;
156: signal srd : std_logic;
157: signal sbe : std_logic_vector(3 DOWNTO 0);
158:
159: signal int : std_logic;
160:
161: signal can_tx : std_logic;
162: signal can_rx : std_logic;
163:
164: signal timestamp : std_logic_vector(63 DOWNTO 0);
165: signal test_probe : t_ctu_can_fd_test_probe;
166:
167: -- Test control
168: signal test_start : std_logic := '0';
169: signal test_done : std_logic := '0';
170: signal test_success : std_logic := '0'; -- 0 fail / 1 success
171:
172: signal scan_enable : std_logic;
173:
174: component ctu_can_fd_vip is
175: generic(
176: -- Test details
177: test_name : string;
178: test_type : string;
179: func_cov_en : boolean;
180:
181: -- DUT configuration
182: rx_buffer_size : natural;
183: txt_buffer_count : natural range 2 to 8 := 8;
184:
185: -- DUT Clock period
186: cfg_sys_clk_period : string;
187: finish_on_error : natural;
188:
189: -- Bit timing cofnig used in; compliance tests
190: cfg_brp : natural;
191: cfg_prop : natural;
192: cfg_ph_1 : natural;
193: cfg_ph_2 : natural;
194: cfg_sjw : natural;
195: cfg_brp_fd : natural;
196: cfg_prop_fd : natural;
197: cfg_ph_1_fd : natural;
198: cfg_ph_2_fd : natural;
199: cfg_sjw_fd : natural;
200:
201: -- Secondary sample point config
202: cfg_ssp_src : natural;
203: cfg_ssp_offset : natural;
204:
205: -- Seed
206: seed : natural := 0;
207:
208: -- Reference test iterations
209: reference_iterations : natural range 1 to 1000 := 10
210: );
211: port(
212: -- Test control
213: test_start : in std_logic;
214: test_done : out std_logic := '0';
215: test_success : out std_logic := '0';
216:
217: -- DUT interface
218: clk_sys : out std_logic;
219: res_n : out std_logic;
220:
221: scan_enable : out std_logic;
222:
223: write_data : out std_logic_vector(31 DOWNTO 0);
224: read_data : in std_logic_vector(31 DOWNTO 0);
225: adress : out std_logic_vector(15 DOWNTO 0);
226: scs : out std_logic;
227: srd : out std_logic;
228: swr : out std_logic;
229: sbe : out std_logic_vector(3 DOWNTO 0);
230:
231: int : in std_logic;
232:
233: can_tx : in std_logic;
234: can_rx : out std_logic;
235:
236: test_probe : in t_ctu_can_fd_test_probe;
237: timestamp : out std_logic_vector(63 DOWNTO 0)
238: );
239: end component;
240:
241: begin
242:
243: ---------------------------------------------------------------------------
244: -- DUT (Use RAM-like memory bus)
245: ---------------------------------------------------------------------------
246: dut : entity ctu_can_fd_rtl.can_top_level
247: generic map(
248: rx_buffer_size => rx_buffer_size,
249: txt_buffer_count => txt_buffer_count,
250: sup_filtA => sup_filtA,
251: sup_filtB => sup_filtB,
252: sup_filtC => sup_filtC,
253: sup_range => sup_range,
254: sup_traffic_ctrs => sup_traffic_ctrs,
255: sup_parity => sup_parity,
256: target_technology => target_technology,
257: reset_buffer_rams => reset_buffer_rams
258: )
259: port map(
260: -- Clock and Asynchronous reset
261: clk_sys => clk_sys,
262: res_n => res_n,
263:
264: -- DFT support
265: scan_enable => scan_enable,
266:
267: -- Memory interface
268: data_in => write_data,
269: data_out => read_data,
270: adress => address,
271: scs => scs,
272: srd => srd,
273: swr => swr,
274: sbe => sbe,
275:
276: -- Interrupt Interface
277: int => int,
278:
279: -- CAN Bus Interface
280: can_tx => can_tx,
281: can_rx => can_rx,
282:
283: -- Test probe
284: test_probe => test_probe,
285:
286: -- Timestamp for time based transmission / reception
287: timestamp => timestamp
288: );
289:
290:
291: ---------------------------------------------------------------------------
292: -- CTU CAN FD VIP
293: ---------------------------------------------------------------------------
294: ctu_can_fd_vip_inst : ctu_can_fd_vip
295: generic map(
296: test_name => test_name,
297: test_type => test_type,
298: func_cov_en => func_cov_en,
299:
300: rx_buffer_size => rx_buffer_size,
301: txt_buffer_count => txt_buffer_count,
302:
303: cfg_sys_clk_period => cfg_sys_clk_period,
304: finish_on_error => finish_on_error,
305:
306: cfg_brp => cfg_brp,
307: cfg_prop => cfg_prop,
308: cfg_ph_1 => cfg_ph_1,
309: cfg_ph_2 => cfg_ph_2,
310: cfg_sjw => cfg_sjw,
311: cfg_brp_fd => cfg_brp_fd,
312: cfg_prop_fd => cfg_prop_fd,
313: cfg_ph_1_fd => cfg_ph_1_fd,
314: cfg_ph_2_fd => cfg_ph_2_fd,
315: cfg_sjw_fd => cfg_sjw_fd,
316:
317: cfg_ssp_src => cfg_ssp_src,
318: cfg_ssp_offset => cfg_ssp_offset,
319:
320: seed => seed,
321: reference_iterations => reference_iterations
322: )
323: port map(
324: -- Test control
325: test_start => test_start,
326: test_done => test_done,
327: test_success => test_success,
328:
329: -----------------------------------------------------------------------
330: -- DUT interface
331: -----------------------------------------------------------------------
332:
333: -- Clock, reset
334: clk_sys => clk_sys,
335: res_n => res_n,
336:
337: -- DFT support
338: scan_enable => scan_enable,
339:
340: -- Memory bus
341: write_data => write_data,
342: read_data => read_data,
343: adress => address,
344: scs => scs,
345: srd => srd,
346: swr => swr,
347: sbe => sbe,
348:
349: -- Interrupt
350: int => int,
351:
352: -- CAN bus
353: can_tx => can_tx,
354: can_rx => can_rx,
355:
356: -- Test interface
357: test_probe => test_probe,
358:
359: -- Timestamp
360: timestamp => timestamp
361: );
362:
363:
364: ---------------------------------------------------------------------------
365: -- Vunit manager - controls CTU CAN FD VIP
366: ---------------------------------------------------------------------------
367: vunit_manager_proc : process
368: begin
369: test_runner_setup(runner, runner_cfg);
370: wait for 10 ns;
371:
372: info_m("***************************************************************");
373: info_m("CTU CAN FD main testbench");
374: info_m("");
375: info_m("Test configuration:");
376: info_m(" Test type: " & test_type);
377: info_m(" Test name: " & test_name);
378: info_m(" No. of iterations: " & integer'image(iterations));
379: info_m(" System clock period: " & cfg_sys_clk_period);
380: info_m(" Log level: " & t_log_verbosity'image(log_level));
381: info_m(" Seed: " & integer'image(seed));
382: info_m(" Reference test iterations: " & integer'image(reference_iterations));
383: info_m(" Timeout: " & timeout);
384: info_m(" Finish on error: " & integer'image(finish_on_error));
385: info_m(" Force support: " & boolean'image(is_force_supported));
386: info_m("");
387: info_m("DUT configuration:");
388: info_m(" RX buffer size: " & integer'image(rx_buffer_size));
389: info_m(" TXT Buffer count: " & integer'image(txt_buffer_count));
390: info_m(" Filter A: " & boolean'image(sup_filtA));
391: info_m(" Filter B: " & boolean'image(sup_filtB));
392: info_m(" Filter C: " & boolean'image(sup_filtC));
393: info_m(" Range filter: " & boolean'image(sup_range));
394: info_m(" Traffic counters: " & boolean'image(sup_traffic_ctrs));
395: info_m(" Target technology: " & integer'image(target_technology));
396: info_m(" Reset Buffer RAMS: " & boolean'image(reset_buffer_rams));
397: info_m("");
398: info_m("Bit timing settings (Nominal):");
399: info_m(" BRP: " & integer'image(cfg_brp));
400: info_m(" PH1: " & integer'image(cfg_ph_1));
401: info_m(" PROP: " & integer'image(cfg_prop));
402: info_m(" PH2: " & integer'image(cfg_ph_2));
403: info_m(" SJW: " & integer'image(cfg_sjw));
404: info_m("");
405: info_m("Bit timing settings (Data):");
406: info_m(" BRP: " & integer'image(cfg_brp_fd));
407: info_m(" PH1: " & integer'image(cfg_ph_1_fd));
408: info_m(" PROP: " & integer'image(cfg_prop_fd));
409: info_m(" PH2: " & integer'image(cfg_ph_2_fd));
410: info_m(" SJW: " & integer'image(cfg_sjw_fd));
411: info_m("Secondary sample point:");
412: info_m(" Source: " & integer'image(cfg_ssp_src));
413: info_m(" Offset: " & integer'image(cfg_ssp_offset));
414: info_m("");
415: info_m("***************************************************************");
416:
417: show(get_logger(default_checker), display_handler, pass);
418: set_log_verbosity(log_level, global_verbosity);
419:
420: tb_force.set_force_supported(is_force_supported);
421:
422: for i in 1 to iterations loop
423: info_m("***************************************************************");
424: info_m(" Iteration nr: " & integer'image(i));
425: info_m("***************************************************************");
426:
427: -- Execute test
428: test_start <= '1';
429: wait until test_done = '1';
430: wait for 1 ns;
431:
432: -- Propagate fail to Vunit if test signals it failed
433: -- true indicates fail (exit code 1)
434: if (test_success = '0') then
435: test_runner_cleanup(runner, true);
436: end if;
437:
438: -- Finish handshake
439: test_start <= '0';
440: wait until test_done = '0';
441: wait for 10 ns;
442: end loop;
443:
444: -- Finish succesfully
445: test_runner_cleanup(runner);
446: std.env.finish;
447: end process;
448:
449: ---------------------------------------------------------------------------
450: -- Spawn watchdog
451: ---------------------------------------------------------------------------
452: watchdog: if time'value(timeout) > 0 ns generate
453: test_runner_watchdog(runner, time'value(timeout));
454: end generate;
455:
456: end architecture;