File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bit_err_detector.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bit error detector.
71: --
72: -- Purpose:
73: -- Detects bit error in:
74: -- 1. Regular sampling point (compares actual TX data to actual RX data),
75: -- in Nominal Bit Rate.
76: -- 2. Secondary sampling point (compares actual RX data to delayed TX data),
77: -- in Data Bit-Rate of Transmitter (Secondary sampling).
78: --------------------------------------------------------------------------------
79:
80: Library ieee;
81: use ieee.std_logic_1164.all;
82: use ieee.numeric_std.ALL;
83:
84: Library ctu_can_fd_rtl;
85: use ctu_can_fd_rtl.can_constants_pkg.all;
86: use ctu_can_fd_rtl.can_types_pkg.all;
87:
88: use ctu_can_fd_rtl.CAN_FD_register_map.all;
89: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
90:
91: entity bit_err_detector is
92: port (
93: -------------------------------------------------------------------------------------------
94: -- Clock and Async reset
95: -------------------------------------------------------------------------------------------
96: clk_sys :in std_logic;
97: res_n :in std_logic;
98:
99: -------------------------------------------------------------------------------------------
100: -- Control signals from CAN core
101: -------------------------------------------------------------------------------------------
102: -- Sample control
103: sp_control :in std_logic_vector(1 downto 0);
104:
105: -- RX Trigger
106: rx_trigger :in std_logic;
107:
108: -- RX Trigger - Secondary Sample
109: sample_sec :in std_logic;
110:
111: -- Bit error enable
112: bit_err_enable :in std_logic;
113:
114: -------------------------------------------------------------------------------------------
115: -- Memory registers interface
116: -------------------------------------------------------------------------------------------
117: mr_settings_ena :in std_logic;
118:
119: -------------------------------------------------------------------------------------------
120: -- TX / RX Datapath
121: -------------------------------------------------------------------------------------------
122: -- Actually transmitted data on CAN bus
123: data_tx :in std_logic;
124:
125: -- Delayed transmitted data (for detection in secondary sampling point)
126: data_tx_delayed :in std_logic;
127:
128: -- RX Data (Synchronised)
129: data_rx_synced :in std_logic;
130:
131: -------------------------------------------------------------------------------------------
132: -- Status outputs
133: -------------------------------------------------------------------------------------------
134: -- Bit error detected
135: bit_err : out std_logic
136: );
137: end entity;
138:
139: architecture rtl of bit_err_detector is
140:
141: -- Bit error detected value
142: signal bit_err_d : std_logic;
143: signal bit_err_q : std_logic;
144:
145: -- Capture register for Secondary sampling point bit error
146: signal bit_err_ssp_capt_d : std_logic;
147: signal bit_err_ssp_capt_q : std_logic;
148:
149: -- Valid Bit error detected by Secondary sampling
150: signal bit_err_ssp_valid : std_logic;
151: signal bit_err_ssp_condition : std_logic;
152:
153: -- Valid Bit Error detected by regular sampling
154: signal bit_err_norm_valid : std_logic;
155:
156: begin
157:
158: -------------------------------------------------------------------------------------------
159: -- Condition for SSP bit error is valid when TX Data cache output is not equal to CAN RX
160: -- in the moment of SSP!
161: -------------------------------------------------------------------------------------------
162: bit_err_ssp_condition <= '1' when (data_tx_delayed /= data_rx_synced and
163: sample_sec = '1' and
164: bit_err_enable = '1')
165: else
166: '0';
167:
168: -------------------------------------------------------------------------------------------
169: -- Capture register for secondary sampling point bit error:
170: -- 1. Clear upon next regular sample point.
171: -- 2. Set when Bit error is detected by secondary sampling point.
172: -------------------------------------------------------------------------------------------
173: bit_err_ssp_capt_d <= '0' when (rx_trigger = '1') else
174: '1' when (bit_err_ssp_condition = '1') else
175: bit_err_ssp_capt_q;
176:
177: bit_error_ssp_capt_reg_proc : process(clk_sys, res_n)
178: begin
179: if (res_n = '0') then
180: bit_err_ssp_capt_q <= '0';
181: elsif (rising_edge(clk_sys)) then
182: bit_err_ssp_capt_q <= bit_err_ssp_capt_d;
183: end if;
184: end process;
185:
186: -------------------------------------------------------------------------------------------
187: -- Bit Error for SSP is processed in Sample point (RX Trigger). We must look at capture
188: -- register (bit_err_ssp_capt_q) and also SSP condition because SSP might occur at the same
189: -- cycle as RX Trigger and in this case bit error is processed immediately and not captured!
190: -------------------------------------------------------------------------------------------
191: bit_err_ssp_valid <= '1' when (sp_control = SECONDARY_SAMPLE and rx_trigger = '1' and
192: (bit_err_ssp_capt_q = '1' or bit_err_ssp_condition = '1'))
193: else
194: '0';
195:
196: bit_err_norm_valid <= '1' when (sp_control /= SECONDARY_SAMPLE and
197: data_rx_synced /= data_tx and
198: rx_trigger = '1' and
199: bit_err_enable = '1')
200: else
201: '0';
202:
203: -------------------------------------------------------------------------------------------
204: -- Expected data is not equal to actual data in sample point -> Bit Error!
205: -------------------------------------------------------------------------------------------
206: bit_err_d <= '0' when (mr_settings_ena = CTU_CAN_DISABLED) else
207: '1' when (bit_err_ssp_valid = '1') else
208: '1' when (bit_err_norm_valid = '1') else
209: '0';
210:
211: -------------------------------------------------------------------------------------------
212: -- Bit error register
213: -------------------------------------------------------------------------------------------
214: bit_err_reg_proc : process(clk_sys, res_n)
215: begin
216: if (res_n = '0') then
217: bit_err_q <= '0';
218: elsif (rising_edge(clk_sys)) then
219: bit_err_q <= bit_err_d;
220: end if;
221: end process;
222:
223: -- Propagation to output
224: bit_err <= bit_err_q;
225:
226: end architecture;