File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_txt_buffer_even.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Functional coverage for a single TXT Buffer
71: --
72: --------------------------------------------------------------------------------
73: -- Revision History:
74: -- 1.6.2025 Created file
75: --------------------------------------------------------------------------------
76:
77: Library ctu_can_fd_tb;
78: context ctu_can_fd_tb.ieee_context;
79: context ctu_can_fd_tb.tb_common_context;
80: context ctu_can_fd_tb.rtl_context;
81:
82: use ctu_can_fd_tb.clk_gen_agent_pkg.all;
83: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
84:
85: entity func_cov_txt_buffer_even is
86: generic (
87: G_TXT_BUFFER_INDEX : natural
88: );
89: port (
90: -- DUT clock
91: clk : in std_logic
92: );
93: end entity;
94:
95: architecture tb of func_cov_txt_buffer_even is
96:
97: -----------------------------------------------------------------------------------------------
98: -- Aliases to "txt_buffer" top
99: -----------------------------------------------------------------------------------------------
100: alias mr_tx_command_txcr is
101: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.mr_tx_command_txcr : std_logic >>;
102:
103: alias mr_tx_command_txce is
104: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.mr_tx_command_txce : std_logic >>;
105:
106: alias mr_tx_command_txca is
107: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.mr_tx_command_txca : std_logic >>;
108:
109: alias mr_tx_command_txbi is
110: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.mr_tx_command_txbi : std_logic >>;
111:
112: alias txtb_hw_cmd is
113: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txtb_hw_cmd : t_txtb_hw_cmd >>;
114:
115: alias txtb_hw_cmd_cs is
116: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txtb_hw_cmd_cs : std_logic >>;
117:
118: -----------------------------------------------------------------------------------------------
119: -- Aliases to "txt_buffer_fsm"
120: -----------------------------------------------------------------------------------------------
121: alias curr_state is
122: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txt_buffer_fsm_inst.curr_state : t_txt_buf_state >>;
123:
124: alias next_state is
125: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txt_buffer_fsm_inst.next_state : t_txt_buf_state >>;
126:
127: alias txtb_parity_error_valid is
128: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txt_buffer_fsm_inst.txtb_parity_error_valid : std_logic >>;
129:
130: alias abort_applied is
131: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.abort_applied : std_logic >>;
132:
133: alias txt_fsm_ce is
134: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txt_buffer_fsm_inst.txt_fsm_ce : std_logic >>;
135:
136: alias txtb_hw_cmd_i is
137: << signal .tb_top_ctu_can_fd.dut.txt_buf_comp_gen(G_TXT_BUFFER_INDEX).txt_buf_even_gen.txt_buffer_even_inst.txt_buffer_fsm_inst.txtb_hw_cmd : t_txtb_hw_cmd >>;
138:
139: begin
140:
141: -- psl default clock is rising_edge(clk);
142:
143: -------------------------------------------------------------------------------------------
144: -- Each SW command active
145: -------------------------------------------------------------------------------------------
146:
147: -- psl txtb_set_ready_cov : cover {mr_tx_command_txcr = '1' and mr_tx_command_txbi = '1'};
148: -- psl txtb_set_empty_cov : cover {mr_tx_command_txce = '1' and mr_tx_command_txbi = '1'};
149: -- psl txtb_set_abort_cov : cover {mr_tx_command_txca = '1' and mr_tx_command_txbi = '1'};
150:
151: -------------------------------------------------------------------------------------------
152: -- HW Commands
153: -------------------------------------------------------------------------------------------
154:
155: -- psl txtb_hw_lock : cover {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1'};
156: -- psl txtb_hw_valid : cover {txtb_hw_cmd.valid = '1' and txtb_hw_cmd_cs = '1'};
157: -- psl txtb_hw_err : cover {txtb_hw_cmd.err = '1' and txtb_hw_cmd_cs = '1'};
158: -- psl txtb_hw_arbl : cover {txtb_hw_cmd.arbl = '1' and txtb_hw_cmd_cs = '1'};
159: -- psl txtb_hw_failed : cover {txtb_hw_cmd.failed = '1' and txtb_hw_cmd_cs = '1'};
160:
161: -------------------------------------------------------------------------------------------
162: -- Parity error during each possible state
163: -------------------------------------------------------------------------------------------
164:
165: -- psl txtb_perr_txt_ready_cov : cover
166: -- {curr_state = s_txt_ready and txtb_parity_error_valid = '1'};
167:
168: -- psl txtb_perr_txt_tx_prog_cov : cover
169: -- {curr_state = s_txt_tx_prog and txtb_parity_error_valid = '1'};
170:
171: -- psl txtb_perr_txt_ab_prog_cov : cover
172: -- {curr_state = s_txt_ab_prog and txtb_parity_error_valid = '1'};
173:
174: -------------------------------------------------------------------------------------------
175: -- Simultaneous HW and SW Commands
176: -------------------------------------------------------------------------------------------
177: --
178: -- psl txtb_hw_sw_cmd_txt_ready_hazard_cov : cover
179: -- {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1' and abort_applied = '1' and
180: -- curr_state = s_txt_ready};
181: --
182: -- psl txtb_hw_sw_cmd_txt_tx_prog_hazard_cov : cover
183: -- {((txtb_hw_cmd_i.valid = '1' or txtb_hw_cmd_i.err = '1' or
184: -- txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.failed = '1') and
185: -- abort_applied = '1' and curr_state = s_txt_tx_prog)};
186:
187: -------------------------------------------------------------------------------------------
188: -- Corner-case transitions of FSM
189: -------------------------------------------------------------------------------------------
190: --
191: -- psl txtb_ready_to_abt_in_progress_cov : cover
192: -- {curr_state = s_txt_ready and next_state = s_txt_ab_prog and txt_fsm_ce = '1'};
193: --
194: -- psl txtb_abt_in_progress_to_parity_error_cov : cover
195: -- {curr_state = s_txt_ab_prog and next_state = s_txt_parity_err and txt_fsm_ce = '1'};
196: --
197: -- psl txtb_tx_in_progress_to_aborted_cov : cover
198: -- {curr_state = s_txt_tx_prog and next_state = s_txt_aborted and txt_fsm_ce = '1'};
199:
200: end architecture;