File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/retransmitt_counter.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Retransmitt counter.
71: --
72: -- Purpose:
73: -- Counts number of retransmissions on a TX frame from single TXT Buffer.
74: -- Signals reaching Retransmitt limit to Protocol Control FSM. Cleared when
75: -- selected TXT Buffer changes or transmission was succesfull. Incremented by
76: -- 1 when Error frame occurs or Arbitration is lost.
77: --------------------------------------------------------------------------------
78:
79: Library ieee;
80: use ieee.std_logic_1164.all;
81: use ieee.numeric_std.ALL;
82:
83: Library ctu_can_fd_rtl;
84: use ctu_can_fd_rtl.can_constants_pkg.all;
85: use ctu_can_fd_rtl.can_types_pkg.all;
86:
87: use ctu_can_fd_rtl.CAN_FD_register_map.all;
88: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
89:
90: entity retransmitt_counter is
91: generic (
92: -- Width of Retransmitt limit counter
93: G_RETR_LIM_CTR_WIDTH : natural
94: );
95: port (
96: -------------------------------------------------------------------------------------------
97: -- Clock and Asynchronous Reset
98: -------------------------------------------------------------------------------------------
99: clk_sys : in std_logic;
100: res_n : in std_logic;
101:
102: -------------------------------------------------------------------------------------------
103: -- Control signals
104: -------------------------------------------------------------------------------------------
105: -- Selected TXT Buffer changed in comparison to previous transmission
106: txtb_changed : in std_logic;
107:
108: -- Clear the counter
109: retr_ctr_clear : in std_logic;
110:
111: -- Increment the counter by 1
112: retr_ctr_add : in std_logic;
113:
114: -------------------------------------------------------------------------------------------
115: -- Memory registers interface
116: -------------------------------------------------------------------------------------------
117: mr_settings_rtrth : in std_logic_vector(G_RETR_LIM_CTR_WIDTH - 1 downto 0);
118:
119: -------------------------------------------------------------------------------------------
120: -- Status signals
121: -------------------------------------------------------------------------------------------
122: -- Retransmitt limit was reached
123: retr_limit_reached : out std_logic;
124:
125: -- Status of retransmit counter (for observation purpose)
126: retr_ctr : out std_logic_vector(G_RETR_LIM_CTR_WIDTH - 1 downto 0)
127: );
128: end entity;
129:
130: architecture rtl of retransmitt_counter is
131:
132: -- Retransmitt limit counter
133: signal retr_ctr_d : unsigned(G_RETR_LIM_CTR_WIDTH - 1 downto 0);
134: signal retr_ctr_q : unsigned(G_RETR_LIM_CTR_WIDTH - 1 downto 0);
135:
136: -- Clock enable
137: signal retr_ctr_ce : std_logic;
138:
139: begin
140:
141: -- Next value
142: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else
143: (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else
144: retr_ctr_q;
145:
146: -- Clock enable
147: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')
148: else
149: '0';
150:
151: -----------------------------------------------------------------------------------------------
152: -- Counter register
153: -----------------------------------------------------------------------------------------------
154: retr_ctr_reg_proc : process(clk_sys, res_n)
155: begin
156: if (res_n = '0') then
157: retr_ctr_q <= (others => '0');
158: elsif (rising_edge(clk_sys)) then
159: if (retr_ctr_ce = '1') then
160: retr_ctr_q <= retr_ctr_d;
161: end if;
162: end if;
163: end process;
164:
165: -- Retransmitt limit reached indication
166: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)
167: else
168: '0';
169:
170: -- Counter status propagation to output
171: retr_ctr <= std_logic_vector(retr_ctr_q);
172:
173: -----------------------------------------------------------------------------------------------
174: -- Assertions
175: -----------------------------------------------------------------------------------------------
176:
177: -- psl default clock is rising_edge(clk_sys);
178:
179: -- psl retr_ctr_simul_set_and_clear_asrt : assert never
180: -- (retr_ctr_add = '1' and retr_ctr_clear = '1');
181: -- report "Retransmitt counter, simultaneous increment and clear!";
182:
183: -- psl_retr_ctr_no_overflow : assert never
184: -- (retr_limit_reached = '1' and retr_ctr_add = '1')
185: -- report "Retransmitt counter overflow";
186:
187: end architecture;