File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/tx_data_cache.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- TX Data Cache.
71: --
72: -- Purpose:
73: -- Stores TX Data into FIFO buffer in time of regular sample point and read
74: -- at the time of secondary sample point. Output data are used for bit
75: -- error detection.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: entity tx_data_cache is
90: generic (
91: -- Depth of FIFO (Number of bits that can be stored)
92: G_TX_CACHE_DEPTH : natural range 4 to 32;
93:
94: -- Size of TX Data cache pointer
95: G_TX_CACHE_PTR_WIDTH : natural;
96:
97: -- FIFO reset value
98: G_TX_CACHE_RST_VAL : std_logic
99: );
100: port (
101: -------------------------------------------------------------------------------------------
102: -- Clock and Asynchronous reset
103: -------------------------------------------------------------------------------------------
104: clk_sys :in std_logic;
105: res_n :in std_logic;
106:
107: -------------------------------------------------------------------------------------------
108: -- Control signals
109: -------------------------------------------------------------------------------------------
110: -- Store input data
111: write :in std_logic;
112:
113: -- Read output data
114: read :in std_logic;
115:
116: -------------------------------------------------------------------------------------------
117: -- Data signals
118: -------------------------------------------------------------------------------------------
119: -- Data inputs
120: data_in :in std_logic;
121:
122: -- Data output
123: data_out :out std_logic
124: );
125: end entity;
126:
127: architecture rtl of tx_data_cache is
128:
129: -- Cache Memory (FIFO in DFFs)
130: signal tx_cache_mem : std_logic_vector(G_TX_CACHE_DEPTH - 1 downto 0);
131:
132: -- Write Pointer
133: signal write_pointer_q : unsigned(G_TX_CACHE_PTR_WIDTH - 1 downto 0);
134: signal write_pointer_d : unsigned(G_TX_CACHE_PTR_WIDTH - 1 downto 0);
135:
136: -- Read pointer
137: signal read_pointer_q : unsigned(G_TX_CACHE_PTR_WIDTH - 1 downto 0);
138: signal read_pointer_d : unsigned(G_TX_CACHE_PTR_WIDTH - 1 downto 0);
139:
140: begin
141:
142: -------------------------------------------------------------------------------------------
143: -- Combinationally incrementing write and read pointers
144: -------------------------------------------------------------------------------------------
145: write_pointer_d <= write_pointer_q + 1;
146: read_pointer_d <= read_pointer_q + 1;
147:
148:
149: -------------------------------------------------------------------------------------------
150: -- Incrementing the pointers upon read or write.
151: -------------------------------------------------------------------------------------------
152: write_ptr_proc : process(clk_sys, res_n)
153: begin
154: if (res_n = '0') then
155: write_pointer_q <= (others => '0');
156: elsif (rising_edge(clk_sys)) then
157: if (write = '1') then
158: write_pointer_q <= write_pointer_d;
159: end if;
160: end if;
161: end process;
162:
163:
164: read_ptr_proc : process(clk_sys, res_n)
165: begin
166: if (res_n = '0') then
167: read_pointer_q <= (others => '0');
168: elsif (rising_edge(clk_sys)) then
169: if (read = '1') then
170: read_pointer_q <= read_pointer_d;
171: end if;
172: end if;
173: end process;
174:
175:
176: -------------------------------------------------------------------------------------------
177: -- Storing data to FIFO.
178: -------------------------------------------------------------------------------------------
179: tx_cache_mem_proc : process(clk_sys, res_n)
180: begin
181: if (res_n = '0') then
182: tx_cache_mem <= (others => G_TX_CACHE_RST_VAL);
183: elsif (rising_edge(clk_sys)) then
184: if (write = '1') then
185: tx_cache_mem(to_integer(write_pointer_q(2 downto 0))) <= data_in;
186: end if;
187: end if;
188: end process;
189:
190:
191: -------------------------------------------------------------------------------------------
192: -- Reading data from FIFO combinationally.
193: -- We need to have the data available right away, not pipelined!
194: -------------------------------------------------------------------------------------------
195: data_out <= tx_cache_mem(to_integer(read_pointer_q(2 downto 0)));
196:
197: -------------------------------------------------------------------------------------------
198: -- Assertions on input signals
199: -------------------------------------------------------------------------------------------
200: -- psl default clock is rising_edge(clk_sys);
201:
202: -- psl no_fifo_overflow_asrt : assert never
203: -- ((read_pointer_q(3) /= write_pointer_q(3)) and
204: -- (read_pointer_q(2 downto 0) = write_pointer_q(2 downto 0)) and
205: -- (write = '1'))
206: -- report "TX Cache is full, there should be less than 8 bits on the fly!";
207:
208: -- psl no_empty_read : assert never
209: -- (read = '1' and write_pointer_q = read_pointer_q)
210: -- report "Read from empty TX CACHE";
211:
212: end architecture;