File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/operation_control.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Operation control FSM.
71: --
72: -- Purpose:
73: -- Controls operation state of the node (Transmitter, Receiver, Idle).
74: -- Controlled by Protocol control FSM.
75: --------------------------------------------------------------------------------
76:
77: Library ieee;
78: use ieee.std_logic_1164.all;
79: use ieee.numeric_std.ALL;
80:
81: Library ctu_can_fd_rtl;
82: use ctu_can_fd_rtl.can_constants_pkg.all;
83: use ctu_can_fd_rtl.can_types_pkg.all;
84:
85: use ctu_can_fd_rtl.CAN_FD_register_map.all;
86: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
87:
88: entity operation_control is
89: port (
90: -------------------------------------------------------------------------------------------
91: -- Clock and Asynchronous reset
92: -------------------------------------------------------------------------------------------
93: clk_sys : in std_logic;
94: res_n : in std_logic;
95:
96: -------------------------------------------------------------------------------------------
97: -- Prescaler Interface
98: -------------------------------------------------------------------------------------------
99: -- RX Trigger
100: rx_trigger : in std_logic;
101:
102: -------------------------------------------------------------------------------------------
103: -- Fault confinement Interface
104: -------------------------------------------------------------------------------------------
105: -- Unit is Bus-off
106: is_bus_off : in std_logic;
107:
108: -------------------------------------------------------------------------------------------
109: -- Protocol Control Interface
110: -------------------------------------------------------------------------------------------
111: -- Arbitration lost
112: arbitration_lost : in std_logic;
113:
114: -- Set unit to be transmitter (in SOF)
115: set_transmitter : in std_logic;
116:
117: -- Set unit to be receiver
118: set_receiver : in std_logic;
119:
120: -- Set unit to be idle
121: set_idle : in std_logic;
122:
123: -- Status outputs
124: is_transmitter : out std_logic;
125:
126: -- Unit is receiver
127: is_receiver : out std_logic;
128:
129: -- Unit is idle
130: is_idle : out std_logic
131: );
132: end entity;
133:
134: architecture rtl of operation_control is
135:
136: -- Operation control FSM
137: signal curr_state : t_operation_control_state;
138: signal next_state : t_operation_control_state;
139:
140: -- Unit is off the bus
141: signal go_to_off : std_logic;
142:
143: begin
144:
145: -----------------------------------------------------------------------------------------------
146: -- Unit should go to off when it turned Error Passive or when it is disabled. Gated by
147: -- RX Trigger (delayed till next sample point) to avoid transiting back to off directly after
148: -- the end of integration/reintegration.
149: -----------------------------------------------------------------------------------------------
150: go_to_off <= '1' when (is_bus_off = '1') and (rx_trigger = '1')
151: else
152: '0';
153:
154: -----------------------------------------------------------------------------------------------
155: -- Next state
156: -----------------------------------------------------------------------------------------------
157: next_state_proc : process(curr_state, set_idle, set_transmitter, set_receiver, arbitration_lost,
158: go_to_off)
159: begin
160: next_state <= curr_state;
161:
162: case curr_state is
163: when s_oc_off =>
164: if (set_idle = '1') then
165: next_state <= s_oc_idle;
166: end if;
167:
168: when s_oc_idle =>
169: if (go_to_off = '1') then
170: next_state <= s_oc_off;
171: elsif (set_transmitter = '1') then
172: next_state <= s_oc_transmitter;
173: elsif (set_receiver = '1') then
174: next_state <= s_oc_receiver;
175: end if;
176:
177: when s_oc_transmitter =>
178: if (go_to_off = '1') then
179: next_state <= s_oc_off;
180: elsif (set_idle = '1') then
181: next_state <= s_oc_idle;
182: elsif (set_receiver = '1' or arbitration_lost = '1') then
183: next_state <= s_oc_receiver;
184: end if;
185:
186: when s_oc_receiver =>
187: if (set_idle = '1') then
188: next_state <= s_oc_idle;
189: elsif (set_transmitter = '1') then
190: next_state <= s_oc_transmitter;
191: end if;
192: end case;
193:
194: end process;
195:
196: -----------------------------------------------------------------------------------------------
197: -- Current state
198: -----------------------------------------------------------------------------------------------
199: curr_state_proc : process(curr_state)
200: begin
201: is_idle <= '0';
202: is_transmitter <= '0';
203: is_receiver <= '0';
204:
205: case curr_state is
206: when s_oc_off =>
207: when s_oc_idle =>
208: is_idle <= '1';
209: when s_oc_transmitter =>
210: is_transmitter <= '1';
211: when s_oc_receiver =>
212: is_receiver <= '1';
213: end case;
214: end process;
215:
216: -----------------------------------------------------------------------------------------------
217: -- State register
218: -----------------------------------------------------------------------------------------------
219: state_reg_proc : process(clk_sys, res_n)
220: begin
221: if (res_n = '0') then
222: curr_state <= s_oc_off;
223: elsif (rising_edge(clk_sys)) then
224: curr_state <= next_state;
225: end if;
226: end process;
227:
228: -----------------------------------------------------------------------------------------------
229: -- Assertions
230: -----------------------------------------------------------------------------------------------
231: -- psl default clock is rising_edge(clk_sys);
232:
233: -- psl valid_arb_lost_asrt : assert never
234: -- (arbitration_lost = '1' and curr_state /= s_oc_transmitter)
235: -- report "Unit which is not transmitter lost arbitration";
236:
237: -- psl no_tx_rx_req_in_idle_asrt : assert never
238: -- (set_transmitter = '1' or set_receiver = '1') and (curr_state = s_oc_off)
239: -- report "Unit which is OFF can't be set to Transmitter or Receiver";
240:
241: -- psl no_simul_tx_rx_set_asrt : assert never
242: -- (set_transmitter = '1' and set_receiver = '1')
243: -- report "Unit can't be set to transmitter and receiver simultaneously!";
244:
245: -- psl no_simul_tx_idle_set_asrt : assert never
246: -- (set_transmitter = '1' and set_idle = '1')
247: -- report "Unit can't be set to transmitter and idle simultaneously!";
248:
249: -- psl never_to_off_as_receiver_asrt : assert never
250: -- (go_to_off = '1' and curr_state = s_oc_receiver)
251: -- report "Unit should not become Bus off while receiver!";
252:
253: end architecture;