File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/synchronisation_checker.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Synchronisation Checker.
71: --
72: -- Purpose:
73: -- Holds flag that Re-synchronisation or Hard synchronisation occured.
74: -- Valid Hard synchronisation or Re-synchronisation is signalled on the output.
75: -- Synchronisation flag is cleared in the end of TSEG1 (Sample point).
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: entity synchronisation_checker is
90: port (
91: -------------------------------------------------------------------------------------------
92: -- Clock and Asynchronous reset
93: -------------------------------------------------------------------------------------------
94: clk_sys : in std_logic;
95: res_n : in std_logic;
96:
97: -------------------------------------------------------------------------------------------
98: -- Control interface
99: -------------------------------------------------------------------------------------------
100: -- Synchronisation control (No synchronisation, Hard Synchronisation, Resynchronisation
101: sync_control : in std_logic_vector(1 downto 0);
102:
103: -- Synchronisation edge (from Bus sampling)
104: sync_edge : in std_logic;
105:
106: -- No re-synchronisation should be executed due to positive phase
107: -- error
108: no_pos_resync : in std_logic;
109:
110: -- End of segment
111: segment_end : in std_logic;
112:
113: -- Bit time FSM is in TSEG1
114: is_tseg1 : in std_logic;
115:
116: -- Bit time FSM is in TSEG2
117: is_tseg2 : in std_logic;
118:
119: -------------------------------------------------------------------------------------------
120: -- Status
121: -------------------------------------------------------------------------------------------
122: -- Resynchronisation edge is valid
123: resync_edge_valid : out std_logic;
124:
125: -- Hard synchronisation edge is valid
126: h_sync_edge_valid : out std_logic
127: );
128: end entity;
129:
130: architecture rtl of synchronisation_checker is
131:
132: -- Synchronisation edges
133: signal resync_edge : std_logic;
134: signal h_sync_edge : std_logic;
135: signal h_or_re_sync_edge : std_logic;
136:
137: -- Flag that synchronisation has occurred (either hard sync or re-sync)
138: signal sync_flag : std_logic;
139: signal sync_flag_ce : std_logic;
140: signal sync_flag_nxt : std_logic;
141:
142: begin
143:
144: -----------------------------------------------------------------------------------------------
145: -- Re-synchronisation, Hard synchronisation is distinguished by Sample control given by
146: -- Protocol Control.
147: -----------------------------------------------------------------------------------------------
148: resync_edge <= '1' when (sync_edge = '1' and sync_control = RE_SYNC) else
149: '0';
150:
151: h_sync_edge <= '1' when (sync_edge = '1' and sync_control = HARD_SYNC) else
152: '0';
153:
154: h_or_re_sync_edge <= '1' when (resync_edge = '1' or h_sync_edge = '1') else
155: '0';
156:
157: -----------------------------------------------------------------------------------------------
158: -- Synchronisation flag register.
159: -- 1. Set when Hard-sync or Resync occurs.
160: -- 2. Cleared in the end oof PH1 (sample point)
161: -- Takes care of not synchronising twice between two sample points.
162: -----------------------------------------------------------------------------------------------
163: sync_flag_ce <= '1' when (h_or_re_sync_edge = '1') else
164: '1' when (segment_end = '1' and is_tseg1 = '1') else
165: '0';
166:
167: sync_flag_nxt <= '1' when (h_or_re_sync_edge = '1') else
168: '0';
169:
170: sync_flag_proc : process(res_n, clk_sys)
171: begin
172: if (res_n = '0') then
173: sync_flag <= '0';
174: elsif (rising_edge(clk_sys)) then
175: if (sync_flag_ce = '1') then
176: sync_flag <= sync_flag_nxt;
177: end if;
178: end if;
179: end process;
180:
181: -----------------------------------------------------------------------------------------------
182: -- Re-synchronisation is valid when following conditions are met:
183: -- 1. There is resynchronisation edge
184: -- 2. Synchronisation flag dit not occur yet!
185: -- This has two sub-cases:
186: -- 1. TSEG2, any synchronisation
187: -- 2. TSEG1, only when 'no_pos_resync' is not set! This takes care of no synchronisation for
188: -- transmitter as result of positive phase error!
189: -----------------------------------------------------------------------------------------------
190: resync_edge_valid <= '1' when (resync_edge = '1' and sync_flag = '0' and
191: ((is_tseg2 = '1') or
192: (is_tseg1 = '1' and no_pos_resync = '0')))
193: else
194: '0';
195:
196: -----------------------------------------------------------------------------------------------
197: -- Hard synchronisation is valid at any time, only if there was no synchronisation before!
198: -----------------------------------------------------------------------------------------------
199: h_sync_edge_valid <= '0' when (no_pos_resync = '1' and is_tseg1 = '1') else
200: '1' when (h_sync_edge = '1' and sync_flag = '0') else
201: '0';
202:
203: end architecture rtl;