File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_prescaler.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Functional coverage for Prescaler
71: --
72: --------------------------------------------------------------------------------
73: -- Revision History:
74: -- 27.4.2025 Created file
75: --------------------------------------------------------------------------------
76:
77: Library ctu_can_fd_tb;
78: context ctu_can_fd_tb.ieee_context;
79: context ctu_can_fd_tb.tb_common_context;
80: context ctu_can_fd_tb.rtl_context;
81:
82: use ctu_can_fd_tb.clk_gen_agent_pkg.all;
83: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
84:
85: entity func_cov_prescaler is
86: port (
87: -- DUT clock
88: clk : in std_logic
89: );
90: end entity;
91:
92: architecture tb of func_cov_prescaler is
93:
94: -----------------------------------------------------------------------------------------------
95: -- Aliases to "prescaler" top
96: -----------------------------------------------------------------------------------------------
97:
98: alias sp_control is
99: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.sp_control : std_logic_vector(1 downto 0) >>;
100:
101: alias tseg1_nbt is
102: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.tseg1_nbt : std_logic_vector(7 downto 0) >>;
103:
104: alias tseg2_nbt is
105: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.tseg2_nbt : std_logic_vector(5 downto 0) >>;
106:
107: alias tseg1_dbt is
108: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.tseg1_dbt : std_logic_vector(6 downto 0) >>;
109:
110: alias tseg2_dbt is
111: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.tseg2_dbt : std_logic_vector(4 downto 0) >>;
112:
113: alias brp_nbt is
114: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.brp_nbt : std_logic_vector(7 downto 0) >>;
115:
116: alias brp_dbt is
117: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.brp_dbt : std_logic_vector(7 downto 0) >>;
118:
119: alias resync_edge_valid is
120: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.resync_edge_valid : std_logic >>;
121:
122: alias is_tseg1 is
123: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.is_tseg1 : std_logic >>;
124:
125: alias is_tseg2 is
126: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.is_tseg2 : std_logic >>;
127:
128: -----------------------------------------------------------------------------------------------
129: -- Aliases to "synchronisation_checker" top
130: -----------------------------------------------------------------------------------------------
131: alias sync_flag is
132: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.synchronisation_checker_inst.sync_flag : std_logic >>;
133:
134: alias h_sync_edge is
135: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.synchronisation_checker_inst.h_sync_edge : std_logic >>;
136:
137: alias resync_edge is
138: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.synchronisation_checker_inst.resync_edge : std_logic >>;
139:
140: alias h_sync_edge_valid is
141: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.synchronisation_checker_inst.h_sync_edge_valid : std_logic >>;
142:
143: -----------------------------------------------------------------------------------------------
144: -- Aliases to "trigger_generator" top
145: -----------------------------------------------------------------------------------------------
146:
147: alias rx_trig_req_q is
148: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.trigger_generator_inst.rx_trig_req_q : std_logic >>;
149:
150: alias tx_trig_req is
151: << signal .tb_top_ctu_can_fd.dut.prescaler_inst.trigger_generator_inst.tx_trig_req : std_logic >>;
152:
153: begin
154:
155: -- psl default clock is rising_edge(clk);
156:
157: -----------------------------------------------------------------------------------------------
158: -- Types of bit-rate / sample point
159: -----------------------------------------------------------------------------------------------
160:
161: -- psl nominal_sample_cov : cover
162: -- {sp_control = NOMINAL_SAMPLE};
163:
164: -- psl data_sample_cov : cover
165: -- {sp_control = DATA_SAMPLE};
166:
167: -- psl secondary_sample_cov : cover
168: -- {sp_control = SECONDARY_SAMPLE};
169:
170:
171: -----------------------------------------------------------------------------------------------
172: -- Minimal / Maximal bit rates
173: -----------------------------------------------------------------------------------------------
174:
175: -- psl minimal_bit_time_nbt_cov : cover
176: -- {to_integer(unsigned(tseg1_nbt)) = 5 and to_integer(unsigned(tseg2_nbt)) = 3
177: -- and to_integer(unsigned(brp_nbt)) = 1};
178:
179: -- psl minimal_bit_time_dbt_cov : cover
180: -- {to_integer(unsigned(tseg1_dbt)) = 3 and to_integer(unsigned(tseg2_dbt)) = 2
181: -- and to_integer(unsigned(brp_dbt)) = 1};
182:
183: -- psl maximal_bit_time_nbt_cov : cover
184: -- {to_integer(unsigned(tseg1_nbt)) = 191 and to_integer(unsigned(tseg2_nbt)) = 63};
185:
186: -- psl maximal_bit_time_dbt_cov : cover
187: -- {to_integer(unsigned(tseg1_dbt)) = 95 and to_integer(unsigned(tseg2_dbt)) = 31};
188:
189:
190: -----------------------------------------------------------------------------------------------
191: -- Various other bit rates
192: -----------------------------------------------------------------------------------------------
193:
194: -- psl brp_bin_1_1_cov : cover
195: -- {to_integer(unsigned(brp_nbt)) = 1 and to_integer(unsigned(brp_dbt)) = 1};
196:
197: -- psl brp_bin_2_1_cov : cover
198: -- {to_integer(unsigned(brp_nbt)) = 2 and to_integer(unsigned(brp_dbt)) = 1};
199:
200: -- psl brp_bin_3_1_cov : cover
201: -- {to_integer(unsigned(brp_nbt)) = 3 and to_integer(unsigned(brp_dbt)) = 1};
202:
203: -- psl brp_bin_4_1_cov : cover
204: -- {to_integer(unsigned(brp_nbt)) = 4 and to_integer(unsigned(brp_dbt)) = 1};
205:
206: -- psl brp_bin_4_3_cov : cover
207: -- {to_integer(unsigned(brp_nbt)) = 4 and to_integer(unsigned(brp_dbt)) = 3};
208:
209:
210: -----------------------------------------------------------------------------------------------
211: -- Maximal prescaler
212: -----------------------------------------------------------------------------------------------
213:
214: -- psl brp_nbt_max_cov : cover
215: -- {to_integer(unsigned(brp_nbt)) = 255};
216:
217: -- psl brp_dbt_max_cov : cover
218: -- {to_integer(unsigned(brp_dbt)) = 255};
219:
220:
221: -----------------------------------------------------------------------------------------------
222: -- Resynchronization
223: -----------------------------------------------------------------------------------------------
224:
225: -- Positive resynchronization in Nominal bit rate
226: -- psl pos_resync_in_nominal_bit_rate_cov : cover
227: -- {resync_edge_valid = '1' and is_tseg1 = '1' and sp_control = NOMINAL_SAMPLE};
228:
229: -- Negative resynchronization in Nominal bit rate!
230: -- psl neg_resync_in_nominal_bit_rate_cov : cover
231: -- {resync_edge_valid = '1' and is_tseg2 = '1' and sp_control = NOMINAL_SAMPLE};
232:
233: -- Negative resynchronization in Data bit rate
234: -- psl neg_resync_in_data_bit_rate_cov : cover
235: -- {resync_edge_valid = '1' and is_tseg2 = '1' and sp_control = DATA_SAMPLE};
236:
237: -- Positive resynchronization in Data bit rate
238: -- psl pos_resync_in_data_bit_rate_cov : cover
239: -- {resync_edge_valid = '1' and is_tseg1 = '1' and sp_control = DATA_SAMPLE};
240:
241:
242: -----------------------------------------------------------------------------------------------
243: -- Synchronization
244: -----------------------------------------------------------------------------------------------
245:
246: -- psl h_sync_ignored_due_to_previous_sync_cov : cover
247: -- {sync_flag = '1' and h_sync_edge = '1'};
248:
249: -- psl re_sync_ignored_due_to_previous_sync_cov : cover
250: -- {sync_flag = '1' and resync_edge = '1'};
251:
252: -- psl h_sync_in_tseg_1_cov : cover
253: -- {h_sync_edge_valid = '1' and is_tseg1 = '1'};
254:
255: -- psl h_sync_in_tseg_2_cov : cover
256: -- {h_sync_edge_valid = '1' and is_tseg2 = '1'};
257:
258: -- Hard synchronization in TSEG1
259: -- psl re_sync_in_tseg_1_cov : cover
260: -- {resync_edge_valid = '1' and is_tseg1 = '1'};
261:
262: -- psl re_sync_in_tseg_2_cov : cover
263: -- {resync_edge_valid = '1' and is_tseg2 = '1'};
264:
265:
266: -----------------------------------------------------------------------------------------------
267: -- Trigger generation
268: -----------------------------------------------------------------------------------------------
269:
270: -- psl tx_trigger_throttling_cov : cover
271: -- {rx_trig_req_q = '1' and tx_trig_req = '1'}
272: -- report "TX trigger throtlled!";
273:
274: end architecture;