File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_bus_sampling.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Functional coverage for Bus Sampling
71: --
72: --------------------------------------------------------------------------------
73: -- Revision History:
74: -- 27.4.2025 Created file
75: --------------------------------------------------------------------------------
76:
77: Library ctu_can_fd_tb;
78: context ctu_can_fd_tb.ieee_context;
79: context ctu_can_fd_tb.tb_common_context;
80: context ctu_can_fd_tb.rtl_context;
81:
82: use ctu_can_fd_tb.clk_gen_agent_pkg.all;
83: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
84:
85: entity func_cov_bus_sampling is
86: port (
87: -- DUT clock
88: clk : in std_logic
89: );
90: end entity;
91:
92: architecture tb of func_cov_bus_sampling is
93:
94: -----------------------------------------------------------------------------------------------
95: -- Aliases to "bus_sampling" top
96: -----------------------------------------------------------------------------------------------
97:
98: alias bit_err_ssp_valid is
99: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_valid : std_logic >>;
100:
101: alias bit_err_norm_valid is
102: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.bit_err_detector_inst.bit_err_norm_valid : std_logic >>;
103:
104: alias bit_err_ssp_capt_q is
105: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_capt_q : std_logic >>;
106:
107: alias bit_err_ssp_condition is
108: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_condition : std_logic >>;
109:
110: alias tq_edge is
111: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.tq_edge : std_logic >>;
112:
113: -----------------------------------------------------------------------------------------------
114: -- Aliases to "data_edge_detector" top
115: -----------------------------------------------------------------------------------------------
116:
117: alias rx_data_sync_prev is
118: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.data_edge_detector_inst.rx_data_sync_prev : std_logic >>;
119:
120: alias rx_data is
121: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.data_edge_detector_inst.rx_data : std_logic >>;
122:
123: alias prev_rx_sample is
124: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.data_edge_detector_inst.prev_rx_sample : std_logic >>;
125:
126: -----------------------------------------------------------------------------------------------
127: -- Aliases to "trv_delay_meas" top
128: -----------------------------------------------------------------------------------------------
129: alias mr_ssp_cfg_ssp_src is
130: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.trv_delay_measurement_inst.mr_ssp_cfg_ssp_src : std_logic_vector(1 downto 0) >>;
131:
132: alias tran_delay_meas is
133: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.trv_delay_measurement_inst.tran_delay_meas : std_logic >>;
134:
135: alias ssp_delay is
136: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay : std_logic_vector(C_SSP_POS_WIDTH-1 downto 0) >>;
137:
138: -----------------------------------------------------------------------------------------------
139: -- Aliases to "tx_data_cache" top
140: -----------------------------------------------------------------------------------------------
141: alias write_pointer_q is
142: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.tx_data_cache_inst.write_pointer_q : unsigned(3 downto 0) >>;
143:
144: alias read_pointer_q is
145: << signal .tb_top_ctu_can_fd.dut.bus_sampling_inst.tx_data_cache_inst.read_pointer_q : unsigned(3 downto 0) >>;
146:
147: begin
148:
149: -- psl default clock is rising_edge(clk);
150:
151: -----------------------------------------------------------------------------------------------
152: -- Bit Error detection
153: -----------------------------------------------------------------------------------------------
154:
155: -- psl bit_err_secondary_cov : cover
156: -- {bit_err_ssp_valid = '1' and bit_err_norm_valid = '0'};
157:
158: -- psl bit_err_secondary_capt_cov : cover
159: -- {bit_err_ssp_valid = '1' and bit_err_ssp_capt_q = '1' and bit_err_ssp_condition = '0'};
160:
161: -- psl bit_err_secondary_direct_cov : cover
162: -- {bit_err_ssp_valid = '1' and bit_err_ssp_capt_q = '0' and bit_err_ssp_condition = '1'};
163:
164:
165: -----------------------------------------------------------------------------------------------
166: -- Data edge detection
167: -----------------------------------------------------------------------------------------------
168:
169: -- psl sync_edge_but_prev_sample_the_same_cov : cover
170: -- {(rx_data_sync_prev /= rx_data) and (rx_data_sync_prev = RECESSIVE) and
171: -- (prev_rx_sample = rx_data) and (tq_edge = '1')};
172:
173:
174: -----------------------------------------------------------------------------------------------
175: -- Transceiver delay measureement
176: -----------------------------------------------------------------------------------------------
177:
178: -- psl ssp_meas_n_offset_cov : cover
179: -- {mr_ssp_cfg_ssp_src = SSP_SRC_MEAS_N_OFFSET and tran_delay_meas = '1'};
180:
181: -- psl ssp_offset_cov : cover
182: -- {mr_ssp_cfg_ssp_src = SSP_SRC_OFFSET and tran_delay_meas = '1'};
183:
184: -- psl ssp_no_ssp_cov : cover
185: -- {mr_ssp_cfg_ssp_src = SSP_SRC_NO_SSP and tran_delay_meas = '1'};
186: -- Note: Protocol control FSM actually requests the measurement of TRV delay
187: -- even if SSP is not used!
188:
189: -- psl ssp_offset_max_cov : cover
190: -- {ssp_delay = std_logic_vector(to_unsigned(C_SSP_DELAY_SAT_VAL, C_SSP_POS_WIDTH))};
191:
192:
193: -----------------------------------------------------------------------------------------------
194: -- TX Data cache
195: -----------------------------------------------------------------------------------------------
196:
197: -- psl tx_data_cache_one_bit_on_fly_cov : cover
198: -- {write_pointer_q = read_pointer_q + 1};
199:
200: -- psl tx_data_cache_two_bits_on_fly_cov : cover
201: -- {write_pointer_q = read_pointer_q + 2};
202:
203: -- psl tx_data_cache_three_bits_on_fly_cov : cover
204: -- {write_pointer_q = read_pointer_q + 3};
205:
206: -- psl tx_data_cache_four_bits_on_fly_cov : cover
207: -- {write_pointer_q = read_pointer_q + 4};
208:
209: -- psl tx_data_cache_five_bits_on_fly_cov : cover
210: -- {write_pointer_q = read_pointer_q + 5};
211:
212: -- psl tx_data_cache_six_bits_on_fly_cov : cover
213: -- {write_pointer_q = read_pointer_q + 6};
214:
215: -- psl tx_data_cache_seven_bits_on_fly_cov : cover
216: -- {write_pointer_q = read_pointer_q + 7};
217:
218: end architecture;