File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_fsm.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bit time FSM.
71: --
72: -- Purpose:
73: -- Determines segment of a Bit in which unit actually is (TSEG1, TSEG2).
74: -- Generates trigger requests:
75: -- TX Trigger request - Last cycle of TSEG2 (end of bit time).
76: -- RX Trigger request - Last cycle of TSEG1 (sample point).
77: --------------------------------------------------------------------------------
78:
79: Library ieee;
80: use ieee.std_logic_1164.all;
81: use ieee.numeric_std.ALL;
82:
83: Library ctu_can_fd_rtl;
84: use ctu_can_fd_rtl.can_constants_pkg.all;
85: use ctu_can_fd_rtl.can_types_pkg.all;
86:
87: use ctu_can_fd_rtl.CAN_FD_register_map.all;
88: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
89:
90: entity bit_time_fsm is
91: port (
92: -------------------------------------------------------------------------------------------
93: -- Clock and Asynchronous reset
94: -------------------------------------------------------------------------------------------
95: clk_sys : in std_logic;
96: res_n : in std_logic;
97:
98: -------------------------------------------------------------------------------------------
99: -- Memory registers interface
100: -------------------------------------------------------------------------------------------
101: mr_settings_ena : in std_logic;
102:
103: -------------------------------------------------------------------------------------------
104: -- Control interface
105: -------------------------------------------------------------------------------------------
106: -- Segment end (either due to re-sync, or reaching expected length)
107: segm_end : in std_logic;
108:
109: -------------------------------------------------------------------------------------------
110: -- Status signals
111: -------------------------------------------------------------------------------------------
112: -- Bit time FSM is in TSEG1
113: is_tseg1 : out std_logic;
114:
115: -- Bit time FSM is in TSEG2
116: is_tseg2 : out std_logic;
117:
118: -- Sample signal request (to sample point generator)
119: rx_trig_req : out std_logic;
120:
121: -- Sync signal request
122: tx_trig_req : out std_logic
123: );
124: end entity;
125:
126: architecture rtl of bit_time_fsm is
127:
128: -- Bit time FSM
129: signal current_state : t_bit_time;
130: signal next_state : t_bit_time;
131:
132: -- Bit time FSM clock enable
133: signal bt_fsm_ce : std_logic;
134:
135: begin
136:
137: -------------------------------------------------------------------------------------------
138: -- Next state process (combinational)
139: -------------------------------------------------------------------------------------------
140: next_state_proc : process(current_state, segm_end, mr_settings_ena)
141: begin
142: next_state <= current_state;
143:
144: if (mr_settings_ena = CTU_CAN_DISABLED) then
145: next_state <= s_bt_reset;
146: else
147: case current_state is
148: when s_bt_tseg1 =>
149: if (segm_end = '1') then
150: next_state <= s_bt_tseg2;
151: end if;
152: when s_bt_tseg2 =>
153: if (segm_end = '1') then
154: next_state <= s_bt_tseg1;
155: end if;
156: when s_bt_reset =>
157: next_state <= s_bt_tseg1;
158: end case;
159: end if;
160: end process;
161:
162: -------------------------------------------------------------------------------------------
163: -- Current state process (combinational)
164: -------------------------------------------------------------------------------------------
165: curr_state_proc : process(current_state, segm_end, mr_settings_ena)
166: begin
167: -- Default values
168: is_tseg1 <= '0';
169: is_tseg2 <= '0';
170: rx_trig_req <= '0';
171: tx_trig_req <= '0';
172:
173: case current_state is
174: when s_bt_reset =>
175: if (mr_settings_ena = CTU_CAN_ENABLED) then
176: tx_trig_req <= '1';
177: end if;
178:
179: when s_bt_tseg1 =>
180: is_tseg1 <= '1';
181: if (segm_end = '1') then
182: rx_trig_req <= '1';
183: end if;
184:
185: when s_bt_tseg2 =>
186: is_tseg2 <= '1';
187: if (segm_end = '1') then
188: tx_trig_req <= '1';
189: end if;
190:
191: end case;
192: end process;
193:
194: -------------------------------------------------------------------------------------------
195: -- State register assignment
196: -------------------------------------------------------------------------------------------
197: state_reg_proc : process(clk_sys, res_n)
198: begin
199: if (res_n = '0') then
200: current_state <= s_bt_reset;
201: elsif (rising_edge(clk_sys)) then
202: if (bt_fsm_ce = '1') then
203: current_state <= next_state;
204: end if;
205: end if;
206: end process;
207:
208: bt_fsm_ce <= '1' when (next_state /= current_state) else
209: '0';
210:
211: end architecture rtl;