File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/data_edge_detector.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Data edge detector.
71: --
72: -- Purpose:
73: -- Detection of edge on TX and RX data. Selectable DFF may be inserted on
74: -- output.
75: --
76: -- Edge on RX Data is signaled only when:
77: -- 1. Edge is detected on "rx_edge" input
78: -- 2. Previously sampled value of RX data is different from value after
79: -- the edge.
80: -- 3. Actual value of data is DOMINANT.
81: -- By these conditions it is satisfied that only RECESSIE to DOMINANT edge
82: -- with previous bit value detected as RECESSIVE is signalled. In CAN, this
83: -- is the only valid, HARD SYNCHRONISATION or RE-SYNCHRONISATION edge.
84: --
85: -- Edge on TX Data is signalled only when:
86: -- 1. There is an edge on TX Data.
87: -- 2. New TX-Data are dominant.
88: --
89: -- TX Edge is used for TRV DELAY measurement which is in EDL to R0 edge.
90: -- Thus only RECESSIVE to DOMINANT edge is needed.
91: --------------------------------------------------------------------------------
92:
93: Library ieee;
94: use ieee.std_logic_1164.all;
95: use ieee.numeric_std.ALL;
96:
97: Library ctu_can_fd_rtl;
98: use ctu_can_fd_rtl.can_constants_pkg.all;
99: use ctu_can_fd_rtl.can_types_pkg.all;
100:
101: use ctu_can_fd_rtl.CAN_FD_register_map.all;
102: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
103:
104: entity data_edge_detector is
105: port (
106: -------------------------------------------------------------------------------------------
107: -- Clock and Asynchronous reset
108: -------------------------------------------------------------------------------------------
109: clk_sys :in std_logic;
110: res_n :in std_logic;
111:
112: -------------------------------------------------------------------------------------------
113: -- Inputs
114: -------------------------------------------------------------------------------------------
115: -- TX Data from CAN Core
116: tx_data :in std_logic;
117:
118: -- RX Data (from CAN Bus)
119: rx_data :in std_logic;
120:
121: -- RX Data value from previous Sample point.
122: prev_rx_sample :in std_logic;
123:
124: -- Time quanta edge
125: tq_edge :in std_logic;
126:
127: -------------------------------------------------------------------------------------------
128: -- Outputs
129: -------------------------------------------------------------------------------------------
130: -- Edge detected on TX Data
131: tx_edge :out std_logic;
132:
133: -- Edge detected on RX Data
134: rx_edge :out std_logic;
135:
136: -- Synchronisation edge
137: sync_edge :out std_logic
138: );
139: end entity;
140:
141:
142: architecture rtl of data_edge_detector is
143:
144: -- Previous values on rx_data, tx_data inputs to detect edge
145: signal rx_data_prev : std_logic;
146: signal tx_data_prev : std_logic;
147: signal rx_data_sync_prev : std_logic;
148:
149: -- Internal value of output signals
150: signal rx_edge_i : std_logic;
151: signal tx_edge_i : std_logic;
152:
153: begin
154:
155: -------------------------------------------------------------------------------------------
156: -- Registering previous value of rx_data, tx_data to detect edge in the data stream
157: -------------------------------------------------------------------------------------------
158: data_reg_proc : process(clk_sys, res_n)
159: begin
160: if (res_n = '0') then
161: rx_data_prev <= RECESSIVE;
162: tx_data_prev <= RECESSIVE;
163: rx_data_sync_prev <= RECESSIVE;
164: elsif (rising_edge(clk_sys)) then
165: rx_data_prev <= rx_data;
166: tx_data_prev <= tx_data;
167:
168: if (tq_edge = '1') then
169: rx_data_sync_prev <= rx_data;
170: end if;
171: end if;
172: end process;
173:
174: -------------------------------------------------------------------------------------------
175: -- Valid TX Edge (Used to start transceiver delay measurement):
176: -- 1. Edge on tx_data
177: -- 2. RECESSIVE to DOMINANT
178: -------------------------------------------------------------------------------------------
179: tx_edge_i <= '1' when (tx_data_prev /= tx_data) and (tx_data_prev = RECESSIVE)
180: else
181: '0';
182:
183: -------------------------------------------------------------------------------------------
184: -- Valid RX Edge (used to stop transceiver delay measurement)
185: -- 1. Edge on rx_data
186: -- 2. RECESSIVE to DOMINANT
187: -------------------------------------------------------------------------------------------
188: rx_edge_i <= '1' when (rx_data_prev /= rx_data) and (rx_data_prev = RECESSIVE)
189: else
190: '0';
191:
192: -------------------------------------------------------------------------------------------
193: -- Synchronisation edge:
194: -- 1. Edge on RX data, aligned with Time Quanta
195: -- 2. Recessive to Dominant
196: -- 3. Data sampled in previous Sample point are different from actual
197: -- rx_data immediately after edge!
198: -- 4. Aligned with time quanta!
199: -------------------------------------------------------------------------------------------
200: sync_edge <= '1' when (rx_data_sync_prev /= rx_data) and
201: (rx_data_sync_prev = RECESSIVE) and
202: (prev_rx_sample /= rx_data) and
203: (tq_edge = '1')
204: else
205: '0';
206:
207: -------------------------------------------------------------------------------------------
208: -- Internal signals to output propagation
209: -------------------------------------------------------------------------------------------
210: rx_edge <= rx_edge_i;
211: tx_edge <= tx_edge_i;
212:
213: end architecture;