File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bit time counters.
71: --
72: -- Purpose:
73: -- Contains counters:
74: -- 1. Time Quanta counter.
75: -- 2. Segment counter.
76: --
77: -- Time Quanta counter counts duration of Time quanta segment and provides
78: --- Time Quanta edge signal. Segment counter counts with granularity of Time
79: -- Quanta and measures length of Bit segment (TSEG1, TSEG2).
80: --------------------------------------------------------------------------------
81:
82: Library ieee;
83: use ieee.std_logic_1164.all;
84: use ieee.numeric_std.ALL;
85:
86: Library ctu_can_fd_rtl;
87: use ctu_can_fd_rtl.can_constants_pkg.all;
88: use ctu_can_fd_rtl.can_types_pkg.all;
89:
90: use ctu_can_fd_rtl.CAN_FD_register_map.all;
91: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
92:
93: entity bit_time_counters is
94: generic (
95: -- Bit Time counter width
96: G_BT_WIDTH : natural;
97:
98: -- Baud rate prescaler width
99: G_BRP_WIDTH : natural
100: );
101: port(
102: -------------------------------------------------------------------------------------------
103: -- Clock and reset
104: -------------------------------------------------------------------------------------------
105: clk_sys : in std_logic;
106: res_n : in std_logic;
107:
108: -------------------------------------------------------------------------------------------
109: -- Control signals
110: -------------------------------------------------------------------------------------------
111: -- Baud rate Prescaler
112: brp : in std_logic_vector(G_BRP_WIDTH - 1 downto 0);
113:
114: -- Time Quanta Counter reset (synchronous)
115: tq_reset : in std_logic;
116:
117: -- Bit Time counter reset (synchronous)
118: bt_reset : in std_logic;
119:
120: -- Counters enabled
121: ctrs_en : in std_logic;
122:
123: -------------------------------------------------------------------------------------------
124: -- Status signals
125: -------------------------------------------------------------------------------------------
126: -- Time Quanta edge
127: tq_edge : out std_logic;
128:
129: -- Segment counter
130: segm_counter : out std_logic_vector(G_BT_WIDTH - 1 downto 0)
131: );
132: end entity;
133:
134: architecture rtl of bit_time_counters is
135:
136: -- Time Quanta Counter
137: signal tq_counter_d : std_logic_vector(G_BRP_WIDTH - 1 downto 0);
138: signal tq_counter_q : std_logic_vector(G_BRP_WIDTH - 1 downto 0);
139: signal tq_counter_expired : std_logic;
140:
141: constant C_TQ_RST : unsigned(G_BRP_WIDTH - 1 downto 0) := to_unsigned(1, G_BRP_WIDTH);
142:
143: signal tq_edge_i : std_logic;
144:
145: -- Bit Time counter
146: signal segm_counter_d : std_logic_vector(G_BT_WIDTH - 1 downto 0);
147: signal segm_counter_q : std_logic_vector(G_BT_WIDTH - 1 downto 0);
148: signal segm_counter_ce : std_logic;
149:
150: constant C_BT_ZEROES : std_logic_vector(G_BT_WIDTH - 1 downto 0) := (others => '0');
151:
152: begin
153:
154: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
155: else
156: '0';
157:
158: -------------------------------------------------------------------------------------------
159: -- Time quanta counter next value:
160: -- 1. Erase when reaching value of prescaler.
161: -- 2. Erase when re-started.
162: -- 3. Add 1 ohterwise!
163: -------------------------------------------------------------------------------------------
164: tq_counter_d <=
165: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
166: else
167: std_logic_vector(unsigned(tq_counter_q) + 1);
168:
169: tq_proc : process(clk_sys, res_n)
170: begin
171: if (res_n = '0') then
172: tq_counter_q <= std_logic_vector(C_TQ_RST);
173: elsif (rising_edge(clk_sys)) then
174: if (ctrs_en = '1') then
175: tq_counter_q <= tq_counter_d;
176: end if;
177: end if;
178: end process;
179:
180: -------------------------------------------------------------------------------------------
181: -- Time quanta edge
182: -------------------------------------------------------------------------------------------
183: tq_edge_i <= tq_counter_expired;
184:
185: -------------------------------------------------------------------------------------------
186: -- Segment counter
187: -------------------------------------------------------------------------------------------
188: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
189: std_logic_vector(unsigned(segm_counter_q) + 1);
190:
191: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
192: else
193: '0';
194:
195: segm_counter_proc : process(clk_sys, res_n)
196: begin
197: if (res_n = '0') then
198: segm_counter_q <= (others => '0');
199: elsif (rising_edge(clk_sys)) then
200: if (segm_counter_ce = '1') then
201: segm_counter_q <= segm_counter_d;
202: end if;
203: end if;
204: end process;
205:
206: -------------------------------------------------------------------------------------------
207: -- Internal signals to output propagation
208: -------------------------------------------------------------------------------------------
209: segm_counter <= segm_counter_q;
210: tq_edge <= tq_edge_i;
211:
212: end architecture rtl;