INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Mon Jul 20 14:12:13 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary | Design : ctu_can_fd_top | Device : 7k70t-fbv676 | Speed File : -1 PRODUCTION 1.12 2017-02-17 | Design State : Optimized --------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (3) 6. checking no_output_delay (3) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (3) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (3) ------------------------------- There are 0 ports with no output delay specified. There are 3 ports with no output delay but user has a false path constraint (MEDIUM) There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 2.629 0.000 0 3208 0.209 0.000 0 3208 4.650 0.000 0 1055 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- SYS_CLK {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- SYS_CLK 2.629 0.000 0 2167 0.209 0.000 0 2167 4.650 0.000 0 1055 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** SYS_CLK SYS_CLK 7.992 0.000 0 1041 0.618 0.000 0 1041 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: SYS_CLK To Clock: SYS_CLK Setup : 0 Failing Endpoints, Worst Slack 2.629ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.209ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 4.650ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.629ns (required time - arrival time) Source: i_mr_top/i_control_registers_reg_map/i_mode_txbbm_reg/g_bit[0].reg_value_r_reg[0]/C (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]/D (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: SYS_CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (SYS_CLK rise@10.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 7.373ns (logic 1.749ns (23.722%) route 5.624ns (76.278%)) Logic Levels: 17 (CARRY4=3 LUT4=3 LUT5=3 LUT6=8) Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 2.000 i_mr_top/i_control_registers_reg_map/i_mode_txbbm_reg/clk_sys_IBUF_BUFG FDCE r i_mr_top/i_control_registers_reg_map/i_mode_txbbm_reg/g_bit[0].reg_value_r_reg[0]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.269 2.269 f i_mr_top/i_control_registers_reg_map/i_mode_txbbm_reg/g_bit[0].reg_value_r_reg[0]/Q net (fo=21, unplaced) 0.593 2.862 i_mr_top/i_control_registers_reg_map/i_mode_txbbm_reg/g_bit[0].reg_value_r_reg[0]_0 LUT4 (Prop_lut4_I1_O) 0.165 3.027 f i_mr_top/i_control_registers_reg_map/i_mode_txbbm_reg/FSM_sequential_curr_state[2]_i_6__3/O net (fo=8, unplaced) 0.378 3.405 g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top/i_txtb_fsm/abort_applied LUT4 (Prop_lut4_I3_O) 0.053 3.458 r g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top/i_txtb_fsm/select_buf_index_reg[0]_i_4/O net (fo=3, unplaced) 0.358 3.816 i_mr_top/i_control_registers_reg_map/i_tx_priority_txt1p_reg/txtb_available[1] LUT6 (Prop_lut6_I4_O) 0.053 3.869 r i_mr_top/i_control_registers_reg_map/i_tx_priority_txt1p_reg/select_buf_index_reg[0]_i_6/O net (fo=4, unplaced) 0.364 4.233 i_mr_top/i_control_registers_reg_map/i_tx_priority_txt1p_reg/g_bit[2].reg_value_r_reg[2]_0 LUT4 (Prop_lut4_I3_O) 0.053 4.286 f i_mr_top/i_control_registers_reg_map/i_tx_priority_txt1p_reg/select_buf_index_reg[1]_i_10/O net (fo=2, unplaced) 0.532 4.818 i_mr_top/i_control_registers_reg_map/g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg/select_buf_index_reg_reg[1]_1 LUT6 (Prop_lut6_I1_O) 0.053 4.871 r i_mr_top/i_control_registers_reg_map/g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg/select_buf_index_reg[1]_i_7/O net (fo=2, unplaced) 0.351 5.222 i_mr_top/i_control_registers_reg_map/g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg/select_buf_index_reg[1]_i_7_n_0 LUT6 (Prop_lut6_I5_O) 0.053 5.275 r i_mr_top/i_control_registers_reg_map/g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg/select_buf_index_reg[1]_i_1/O net (fo=3, unplaced) 0.358 5.633 i_txarb_top/i_txarb_fsm/ts_low_internal_reg[31]_3[1] LUT5 (Prop_lut5_I0_O) 0.053 5.686 r i_txarb_top/i_txarb_fsm/tran_dlc_dbl_buf[3]_i_6/O net (fo=32, unplaced) 0.411 6.097 i_txarb_top/i_txarb_fsm/tran_dlc_dbl_buf[3]_i_6_n_0 LUT6 (Prop_lut6_I4_O) 0.053 6.150 r i_txarb_top/i_txarb_fsm/tran_identifier_com[4]_i_1/O net (fo=6, unplaced) 0.553 6.703 i_txarb_top/i_txarb_fsm/D[4] LUT6 (Prop_lut6_I1_O) 0.053 6.756 r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[0]_i_78/O net (fo=1, unplaced) 0.000 6.756 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[0]_i_78_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.310 7.066 r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]_i_53/CO[3] net (fo=1, unplaced) 0.000 7.066 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]_i_53_n_0 CARRY4 (Prop_carry4_CI_CO[3]) 0.060 7.126 r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]_i_30/CO[3] net (fo=1, unplaced) 0.000 7.126 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]_i_30_n_0 CARRY4 (Prop_carry4_CI_CO[2]) 0.149 7.275 f i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]_i_10/CO[2] net (fo=2, unplaced) 0.320 7.595 i_txarb_top/i_txarb_fsm/less_than10_in LUT5 (Prop_lut5_I4_O) 0.160 7.755 f i_txarb_top/i_txarb_fsm/fsm_wait_state_q_i_6/O net (fo=5, unplaced) 0.368 8.123 i_txarb_top/i_txarb_fsm/fsm_wait_state_q_i_6_n_0 LUT5 (Prop_lut5_I4_O) 0.053 8.176 f i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[2]_i_19/O net (fo=1, unplaced) 0.340 8.516 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[2]_i_19_n_0 LUT6 (Prop_lut6_I5_O) 0.053 8.569 r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[2]_i_12__2/O net (fo=1, unplaced) 0.340 8.909 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[2]_i_12__2_n_0 LUT6 (Prop_lut6_I5_O) 0.053 8.962 r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[2]_i_3__3/O net (fo=3, unplaced) 0.358 9.320 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[2]_i_3__3_n_0 LUT6 (Prop_lut6_I1_O) 0.053 9.373 r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[0]_i_1__3/O net (fo=1, unplaced) 0.000 9.373 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state[0]_i_1__3_n_0 FDCE r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]/D ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 10.000 10.000 r 0.000 10.000 r clk_sys (IN) ideal clock network latency 2.000 12.000 net (fo=0) 0.000 12.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 12.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 12.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 12.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 12.000 i_txarb_top/i_txarb_fsm/clk_sys_IBUF_BUFG FDCE r i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0]/C clock pessimism 0.000 12.000 clock uncertainty -0.035 11.965 FDCE (Setup_fdce_C_D) 0.037 12.002 i_txarb_top/i_txarb_fsm/FSM_sequential_curr_state_reg[0] ------------------------------------------------------------------- required time 12.002 arrival time -9.373 ------------------------------------------------------------------- slack 2.629 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.209ns (arrival time - required time) Source: i_mr_top/i_control_registers_reg_map/i_btr_fd_prop_fd_reg/g_bit[2].reg_value_r_reg[2]/C (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: i_btl_top/i_btl_cfg_capture/tseg1_dbt_reg[2]/D (rising edge-triggered cell FDPE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: SYS_CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (SYS_CLK rise@0.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 0.274ns (logic 0.164ns (59.943%) route 0.110ns (40.057%)) Logic Levels: 1 (LUT6=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 2.000 i_mr_top/i_control_registers_reg_map/i_btr_fd_prop_fd_reg/clk_sys_IBUF_BUFG FDCE r i_mr_top/i_control_registers_reg_map/i_btr_fd_prop_fd_reg/g_bit[2].reg_value_r_reg[2]/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.100 2.100 r i_mr_top/i_control_registers_reg_map/i_btr_fd_prop_fd_reg/g_bit[2].reg_value_r_reg[2]/Q net (fo=3, unplaced) 0.110 2.210 i_btl_top/i_btl_cfg_capture/mr_ctrl_out[btr_fd_prop_fd][2] LUT6 (Prop_lut6_I5_O) 0.064 2.274 r i_btl_top/i_btl_cfg_capture/tseg1_dbt[2]_i_1/O net (fo=1, unplaced) 0.000 2.274 i_btl_top/i_btl_cfg_capture/tseg1_dbt_d[2] FDPE r i_btl_top/i_btl_cfg_capture/tseg1_dbt_reg[2]/D ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 2.000 i_btl_top/i_btl_cfg_capture/clk_sys_IBUF_BUFG FDPE r i_btl_top/i_btl_cfg_capture/tseg1_dbt_reg[2]/C clock pessimism 0.000 2.000 FDPE (Hold_fdpe_C_D) 0.065 2.065 i_btl_top/i_btl_cfg_capture/tseg1_dbt_reg[2] ------------------------------------------------------------------- required time -2.065 arrival time 2.274 ------------------------------------------------------------------- slack 0.209 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: SYS_CLK Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_sys } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 10.000 7.505 g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_ram/i_dp_inf_ram_be/g_ram_rst_false.ram_memory_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/mr_tx_command_txca_q_reg/C High Pulse Width Slow FDCE/C n/a 0.350 5.000 4.650 g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/mr_tx_command_txca_q_reg/C --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: SYS_CLK To Clock: SYS_CLK Setup : 0 Failing Endpoints, Worst Slack 7.992ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.618ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.992ns (required time - arrival time) Source: i_mr_top/i_global_rst_rst_reg/i_rx_shift_res_reg/reg_q_reg/C (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_fsm/FSM_sequential_curr_state_reg[0]/CLR (recovery check against rising-edge clock SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (SYS_CLK rise@10.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 1.715ns (logic 0.422ns (24.606%) route 1.293ns (75.394%)) Logic Levels: 1 (LUT3=1) Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 2.000 i_mr_top/i_global_rst_rst_reg/i_rx_shift_res_reg/clk_sys_IBUF_BUFG FDCE r i_mr_top/i_global_rst_rst_reg/i_rx_shift_res_reg/reg_q_reg/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.269 2.269 r i_mr_top/i_global_rst_rst_reg/i_rx_shift_res_reg/reg_q_reg/Q net (fo=4, unplaced) 0.556 2.825 i_mr_top/i_global_rst_rst_reg/i_rx_shift_res_reg/reg_q_reg_0 LUT3 (Prop_lut3_I0_O) 0.153 2.978 f i_mr_top/i_global_rst_rst_reg/i_rx_shift_res_reg/FSM_onehot_curr_state[11]_i_3/O net (fo=540, unplaced) 0.737 3.715 g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_fsm/FSM_sequential_curr_state_reg[2]_5 FDCE f g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_fsm/FSM_sequential_curr_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 10.000 10.000 r 0.000 10.000 r clk_sys (IN) ideal clock network latency 2.000 12.000 net (fo=0) 0.000 12.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 12.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 12.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 12.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 12.000 g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_fsm/clk_sys_IBUF_BUFG FDCE r g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_fsm/FSM_sequential_curr_state_reg[0]/C clock pessimism 0.000 12.000 clock uncertainty -0.035 11.965 FDCE (Recov_fdce_C_CLR) -0.258 11.707 g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_fsm/FSM_sequential_curr_state_reg[0] ------------------------------------------------------------------- required time 11.707 arrival time -3.715 ------------------------------------------------------------------- slack 7.992 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.618ns (arrival time - required time) Source: i_rst_sync/rst_reg/C (rising edge-triggered cell FDCE clocked by SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: i_mr_top/control_registers_cs_reg_reg/CLR (removal check against rising-edge clock SYS_CLK {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (SYS_CLK rise@0.000ns - SYS_CLK rise@0.000ns) Data Path Delay: 0.547ns (logic 0.164ns (29.973%) route 0.383ns (70.027%)) Logic Levels: 1 (LUT1=1) Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 2.000 i_rst_sync/clk_sys_IBUF_BUFG FDCE r i_rst_sync/rst_reg/C ------------------------------------------------------------------- ------------------- FDCE (Prop_fdce_C_Q) 0.100 2.100 r i_rst_sync/rst_reg/Q net (fo=11, unplaced) 0.121 2.221 i_rst_sync/rst_n_out_OBUF LUT1 (Prop_lut1_I0_O) 0.064 2.285 f i_rst_sync/reg_q_i_2__0/O net (fo=4, unplaced) 0.262 2.547 i_mr_top/reg_q_reg_3 FDCE f i_mr_top/control_registers_cs_reg_reg/CLR ------------------------------------------------------------------- ------------------- (clock SYS_CLK rise edge) 0.000 0.000 r 0.000 0.000 r clk_sys (IN) ideal clock network latency 2.000 2.000 net (fo=0) 0.000 2.000 clk_sys IBUF (Prop_ibuf_I_O) 0.000 2.000 r clk_sys_IBUF_inst/O net (fo=1, unplaced) 0.000 2.000 clk_sys_IBUF BUFG (Prop_bufg_I_O) 0.000 2.000 r clk_sys_IBUF_BUFG_inst/O net (fo=1054, unplaced) 0.000 2.000 i_mr_top/clk_sys_IBUF_BUFG FDCE r i_mr_top/control_registers_cs_reg_reg/C clock pessimism 0.000 2.000 FDCE (Remov_fdce_C_CLR) -0.071 1.929 i_mr_top/control_registers_cs_reg_reg ------------------------------------------------------------------- required time -1.929 arrival time 2.547 ------------------------------------------------------------------- slack 0.618