// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 // Date : Mon Jul 20 14:12:14 2026 // Host : fedora running 64-bit unknown // Command : write_verilog -include_xilinx_libs -mode funcsim small_design_config/ctu_can_fd_top.v // Design : ctu_can_fd_top // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k70tfbv676-1 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps module bm_bit_err_detector (bit_err, bit_err_d2, bit_err_d0_out, clk_sys_IBUF_BUFG, bit_err_ssp_capt_q_reg_0, bit_err_ssp_condition, bit_err_ssp_capt_q_reg_1); output bit_err; output bit_err_d2; input bit_err_d0_out; input clk_sys_IBUF_BUFG; input bit_err_ssp_capt_q_reg_0; input bit_err_ssp_condition; input bit_err_ssp_capt_q_reg_1; wire bit_err; wire bit_err_d0_out; wire bit_err_d2; wire bit_err_ssp_capt_q; wire bit_err_ssp_capt_q_i_1_n_0; wire bit_err_ssp_capt_q_reg_0; wire bit_err_ssp_capt_q_reg_1; wire bit_err_ssp_condition; wire clk_sys_IBUF_BUFG; (* SOFT_HLUTNM = "soft_lutpair81" *) LUT2 #( .INIT(4'hE)) bit_err_q_i_4 (.I0(bit_err_ssp_capt_q), .I1(bit_err_ssp_condition), .O(bit_err_d2)); FDCE bit_err_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(bit_err_ssp_capt_q_reg_0), .D(bit_err_d0_out), .Q(bit_err)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'h54)) bit_err_ssp_capt_q_i_1 (.I0(bit_err_ssp_capt_q_reg_1), .I1(bit_err_ssp_condition), .I2(bit_err_ssp_capt_q), .O(bit_err_ssp_capt_q_i_1_n_0)); FDCE bit_err_ssp_capt_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(bit_err_ssp_capt_q_reg_0), .D(bit_err_ssp_capt_q_i_1_n_0), .Q(bit_err_ssp_capt_q)); endmodule module bm_data_edge_detector (tx_data_prev, rx_data_prev, sync_edge, rx_data_sync_prev, can_tx_OBUF, clk_sys_IBUF_BUFG, rx_data_sync_prev_reg_0, rx_data_prev_reg_0, rx_data_sync_prev_reg_1, rx_data_sync_prev_reg_2, rx_data_sync_prev_reg_3, prev_sample_q); output tx_data_prev; output rx_data_prev; output sync_edge; output rx_data_sync_prev; input can_tx_OBUF; input clk_sys_IBUF_BUFG; input rx_data_sync_prev_reg_0; input rx_data_prev_reg_0; input rx_data_sync_prev_reg_1; input rx_data_sync_prev_reg_2; input rx_data_sync_prev_reg_3; input prev_sample_q; wire can_tx_OBUF; wire clk_sys_IBUF_BUFG; wire prev_sample_q; wire rx_data_prev; wire rx_data_prev_reg_0; wire rx_data_sync_prev; wire rx_data_sync_prev_i_1_n_0; wire rx_data_sync_prev_reg_0; wire rx_data_sync_prev_reg_1; wire rx_data_sync_prev_reg_2; wire rx_data_sync_prev_reg_3; wire sync_edge; wire tx_data_prev; FDPE rx_data_prev_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(rx_data_prev_reg_0), .PRE(rx_data_sync_prev_reg_0), .Q(rx_data_prev)); LUT5 #( .INIT(32'hBABB8A88)) rx_data_sync_prev_i_1 (.I0(rx_data_prev_reg_0), .I1(rx_data_sync_prev_reg_1), .I2(rx_data_sync_prev_reg_2), .I3(rx_data_sync_prev_reg_3), .I4(rx_data_sync_prev), .O(rx_data_sync_prev_i_1_n_0)); FDPE rx_data_sync_prev_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(rx_data_sync_prev_i_1_n_0), .PRE(rx_data_sync_prev_reg_0), .Q(rx_data_sync_prev)); LUT6 #( .INIT(64'h0000BA0000000000)) sync_flag_i_2 (.I0(rx_data_sync_prev_reg_1), .I1(rx_data_sync_prev_reg_2), .I2(rx_data_sync_prev_reg_3), .I3(rx_data_sync_prev), .I4(rx_data_prev_reg_0), .I5(prev_sample_q), .O(sync_edge)); FDPE tx_data_prev_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(can_tx_OBUF), .PRE(rx_data_sync_prev_reg_0), .Q(tx_data_prev)); endmodule module bm_sample_mux (prev_sample_q_reg_0, prev_sample_q, prev_sample_q_reg_1, rx_data_sync_prev, \mr_ctrl_out[settings_ena] , prev_sample_q_reg_2, prev_sample_q_reg_3, sample_sec, clk_sys_IBUF_BUFG, prev_sample_q_reg_4); output prev_sample_q_reg_0; output prev_sample_q; input prev_sample_q_reg_1; input rx_data_sync_prev; input \mr_ctrl_out[settings_ena] ; input prev_sample_q_reg_2; input prev_sample_q_reg_3; input sample_sec; input clk_sys_IBUF_BUFG; input prev_sample_q_reg_4; wire clk_sys_IBUF_BUFG; wire \mr_ctrl_out[settings_ena] ; wire prev_sample_q; wire prev_sample_q_i_1_n_0; wire prev_sample_q_reg_0; wire prev_sample_q_reg_1; wire prev_sample_q_reg_2; wire prev_sample_q_reg_3; wire prev_sample_q_reg_4; wire rx_data_sync_prev; wire sample_sec; LUT3 #( .INIT(8'h9F)) \exp_seg_length_q[8]_i_7 (.I0(prev_sample_q), .I1(prev_sample_q_reg_1), .I2(rx_data_sync_prev), .O(prev_sample_q_reg_0)); LUT6 #( .INIT(64'hBBBFFFBF88800080)) prev_sample_q_i_1 (.I0(prev_sample_q_reg_1), .I1(\mr_ctrl_out[settings_ena] ), .I2(prev_sample_q_reg_2), .I3(prev_sample_q_reg_3), .I4(sample_sec), .I5(prev_sample_q), .O(prev_sample_q_i_1_n_0)); FDPE prev_sample_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(prev_sample_q_i_1_n_0), .PRE(prev_sample_q_reg_4), .Q(prev_sample_q)); endmodule module bm_ssp_generator (sspc_ena_q_reg_0, btmc_meas_running_q, CO, bit_err_ssp_condition, sample_sec, sspc_ena_q_reg_1, clk_sys_IBUF_BUFG, first_ssp_q_reg_0, btmc_meas_running_q_reg_0, data_tx_delayed, bit_err_ssp_capt_q_reg, bit_err_enable, \btmc_q_reg[0]_0 , Q, first_ssp_q0); output sspc_ena_q_reg_0; output btmc_meas_running_q; output [0:0]CO; output bit_err_ssp_condition; output sample_sec; input sspc_ena_q_reg_1; input clk_sys_IBUF_BUFG; input first_ssp_q_reg_0; input btmc_meas_running_q_reg_0; input data_tx_delayed; input bit_err_ssp_capt_q_reg; input bit_err_enable; input \btmc_q_reg[0]_0 ; input [8:0]Q; input first_ssp_q0; wire [0:0]CO; wire [8:0]Q; wire bit_err_enable; wire bit_err_ssp_capt_q_reg; wire bit_err_ssp_condition; wire btmc_ce; wire btmc_meas_running_q; wire btmc_meas_running_q_reg_0; wire [14:0]btmc_q; wire btmc_q0_carry__0_i_1_n_0; wire btmc_q0_carry__0_i_2_n_0; wire btmc_q0_carry_i_1_n_0; wire btmc_q0_carry_i_2_n_0; wire btmc_q0_carry_i_3_n_0; wire btmc_q0_carry_i_4_n_0; wire btmc_q0_carry_i_5_n_0; wire btmc_q0_carry_i_6_n_0; wire btmc_q0_carry_i_7_n_0; wire btmc_q0_carry_i_8_n_0; wire btmc_q0_carry_n_0; wire \btmc_q[0]_i_1_n_0 ; wire \btmc_q[10]_i_1_n_0 ; wire \btmc_q[11]_i_1_n_0 ; wire \btmc_q[12]_i_1_n_0 ; wire \btmc_q[13]_i_1_n_0 ; wire \btmc_q[14]_i_1_n_0 ; wire \btmc_q[1]_i_1_n_0 ; wire \btmc_q[2]_i_1_n_0 ; wire \btmc_q[3]_i_1_n_0 ; wire \btmc_q[3]_i_3_n_0 ; wire \btmc_q[4]_i_1_n_0 ; wire \btmc_q[5]_i_1_n_0 ; wire \btmc_q[6]_i_1_n_0 ; wire \btmc_q[7]_i_1_n_0 ; wire \btmc_q[8]_i_1_n_0 ; wire \btmc_q[9]_i_1_n_0 ; wire \btmc_q_reg[0]_0 ; wire \btmc_q_reg[11]_i_2_n_0 ; wire \btmc_q_reg[11]_i_2_n_4 ; wire \btmc_q_reg[11]_i_2_n_5 ; wire \btmc_q_reg[11]_i_2_n_6 ; wire \btmc_q_reg[11]_i_2_n_7 ; wire \btmc_q_reg[14]_i_2_n_5 ; wire \btmc_q_reg[14]_i_2_n_6 ; wire \btmc_q_reg[14]_i_2_n_7 ; wire \btmc_q_reg[3]_i_2_n_0 ; wire \btmc_q_reg[3]_i_2_n_4 ; wire \btmc_q_reg[3]_i_2_n_5 ; wire \btmc_q_reg[3]_i_2_n_6 ; wire \btmc_q_reg[3]_i_2_n_7 ; wire \btmc_q_reg[7]_i_2_n_0 ; wire \btmc_q_reg[7]_i_2_n_4 ; wire \btmc_q_reg[7]_i_2_n_5 ; wire \btmc_q_reg[7]_i_2_n_6 ; wire \btmc_q_reg[7]_i_2_n_7 ; wire clk_sys_IBUF_BUFG; wire data_tx_delayed; wire first_ssp_d0_carry__0_i_1_n_0; wire first_ssp_d0_carry__0_i_2_n_0; wire first_ssp_d0_carry__0_i_3_n_0; wire first_ssp_d0_carry__0_i_4_n_0; wire first_ssp_d0_carry__0_i_5_n_0; wire first_ssp_d0_carry__0_i_6_n_0; wire first_ssp_d0_carry__0_i_7_n_0; wire first_ssp_d0_carry__0_i_8_n_0; wire first_ssp_d0_carry_i_13_n_0; wire first_ssp_d0_carry_i_14_n_0; wire first_ssp_d0_carry_i_15_n_0; wire first_ssp_d0_carry_i_16_n_0; wire first_ssp_d0_carry_i_1_n_0; wire first_ssp_d0_carry_i_2_n_0; wire first_ssp_d0_carry_i_3_n_0; wire first_ssp_d0_carry_i_4_n_0; wire first_ssp_d0_carry_i_5_n_0; wire first_ssp_d0_carry_i_6_n_0; wire first_ssp_d0_carry_i_7_n_0; wire first_ssp_d0_carry_i_8_n_0; wire first_ssp_d0_carry_n_0; wire first_ssp_q; wire first_ssp_q0; wire first_ssp_q_i_1_n_0; wire first_ssp_q_reg_0; wire sample_sec; wire sel; wire sspc_ena_q_reg_0; wire sspc_ena_q_reg_1; wire sspc_q0_carry__0_i_1_n_0; wire sspc_q0_carry__0_i_2_n_5; wire sspc_q0_carry__0_i_2_n_6; wire sspc_q0_carry__0_i_2_n_7; wire sspc_q0_carry__0_i_3_n_0; wire sspc_q0_carry_i_10_n_0; wire sspc_q0_carry_i_11_n_0; wire sspc_q0_carry_i_12_n_0; wire sspc_q0_carry_i_1_n_0; wire sspc_q0_carry_i_2_n_0; wire sspc_q0_carry_i_3_n_0; wire sspc_q0_carry_i_4_n_0; wire sspc_q0_carry_i_5_n_0; wire sspc_q0_carry_i_5_n_4; wire sspc_q0_carry_i_5_n_5; wire sspc_q0_carry_i_5_n_6; wire sspc_q0_carry_i_5_n_7; wire sspc_q0_carry_i_6_n_0; wire sspc_q0_carry_i_7_n_0; wire sspc_q0_carry_i_7_n_4; wire sspc_q0_carry_i_7_n_5; wire sspc_q0_carry_i_7_n_6; wire sspc_q0_carry_i_7_n_7; wire sspc_q0_carry_i_8_n_0; wire sspc_q0_carry_i_9_n_0; wire sspc_q0_carry_i_9_n_4; wire sspc_q0_carry_i_9_n_5; wire sspc_q0_carry_i_9_n_6; wire sspc_q0_carry_i_9_n_7; wire sspc_q0_carry_n_0; wire \sspc_q[0]_i_2_n_0 ; wire \sspc_q[0]_i_3_n_0 ; wire \sspc_q[0]_i_4_n_0 ; wire \sspc_q[0]_i_5_n_0 ; wire \sspc_q[0]_i_6_n_0 ; wire \sspc_q[12]_i_2_n_0 ; wire \sspc_q[12]_i_3_n_0 ; wire \sspc_q[12]_i_4_n_0 ; wire \sspc_q[4]_i_2_n_0 ; wire \sspc_q[4]_i_3_n_0 ; wire \sspc_q[4]_i_4_n_0 ; wire \sspc_q[4]_i_5_n_0 ; wire \sspc_q[8]_i_2_n_0 ; wire \sspc_q[8]_i_3_n_0 ; wire \sspc_q[8]_i_4_n_0 ; wire \sspc_q[8]_i_5_n_0 ; wire [14:0]sspc_q_reg; wire \sspc_q_reg[0]_i_1_n_0 ; wire \sspc_q_reg[0]_i_1_n_4 ; wire \sspc_q_reg[0]_i_1_n_5 ; wire \sspc_q_reg[0]_i_1_n_6 ; wire \sspc_q_reg[0]_i_1_n_7 ; wire \sspc_q_reg[12]_i_1_n_5 ; wire \sspc_q_reg[12]_i_1_n_6 ; wire \sspc_q_reg[12]_i_1_n_7 ; wire \sspc_q_reg[4]_i_1_n_0 ; wire \sspc_q_reg[4]_i_1_n_4 ; wire \sspc_q_reg[4]_i_1_n_5 ; wire \sspc_q_reg[4]_i_1_n_6 ; wire \sspc_q_reg[4]_i_1_n_7 ; wire \sspc_q_reg[8]_i_1_n_0 ; wire \sspc_q_reg[8]_i_1_n_4 ; wire \sspc_q_reg[8]_i_1_n_5 ; wire \sspc_q_reg[8]_i_1_n_6 ; wire \sspc_q_reg[8]_i_1_n_7 ; wire [7:1]sspc_threshold; wire [2:0]NLW_btmc_q0_carry_CO_UNCONNECTED; wire [3:0]NLW_btmc_q0_carry_O_UNCONNECTED; wire [3:1]NLW_btmc_q0_carry__0_CO_UNCONNECTED; wire [3:0]NLW_btmc_q0_carry__0_O_UNCONNECTED; wire [2:0]\NLW_btmc_q_reg[11]_i_2_CO_UNCONNECTED ; wire [3:0]\NLW_btmc_q_reg[14]_i_2_CO_UNCONNECTED ; wire [3:3]\NLW_btmc_q_reg[14]_i_2_O_UNCONNECTED ; wire [2:0]\NLW_btmc_q_reg[3]_i_2_CO_UNCONNECTED ; wire [2:0]\NLW_btmc_q_reg[7]_i_2_CO_UNCONNECTED ; wire [2:0]NLW_first_ssp_d0_carry_CO_UNCONNECTED; wire [3:0]NLW_first_ssp_d0_carry_O_UNCONNECTED; wire [2:0]NLW_first_ssp_d0_carry__0_CO_UNCONNECTED; wire [3:0]NLW_first_ssp_d0_carry__0_O_UNCONNECTED; wire [2:0]NLW_sspc_q0_carry_CO_UNCONNECTED; wire [3:0]NLW_sspc_q0_carry_O_UNCONNECTED; wire [3:1]NLW_sspc_q0_carry__0_CO_UNCONNECTED; wire [3:0]NLW_sspc_q0_carry__0_O_UNCONNECTED; wire [3:0]NLW_sspc_q0_carry__0_i_2_CO_UNCONNECTED; wire [3:3]NLW_sspc_q0_carry__0_i_2_O_UNCONNECTED; wire [2:0]NLW_sspc_q0_carry_i_5_CO_UNCONNECTED; wire [2:0]NLW_sspc_q0_carry_i_7_CO_UNCONNECTED; wire [2:0]NLW_sspc_q0_carry_i_9_CO_UNCONNECTED; wire [2:0]\NLW_sspc_q_reg[0]_i_1_CO_UNCONNECTED ; wire [3:0]\NLW_sspc_q_reg[12]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_sspc_q_reg[12]_i_1_O_UNCONNECTED ; wire [2:0]\NLW_sspc_q_reg[4]_i_1_CO_UNCONNECTED ; wire [2:0]\NLW_sspc_q_reg[8]_i_1_CO_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair87" *) LUT5 #( .INIT(32'h60000000)) bit_err_ssp_capt_q_i_2 (.I0(data_tx_delayed), .I1(bit_err_ssp_capt_q_reg), .I2(CO), .I3(sspc_ena_q_reg_0), .I4(bit_err_enable), .O(bit_err_ssp_condition)); FDCE btmc_meas_running_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(first_ssp_q_reg_0), .D(btmc_meas_running_q_reg_0), .Q(btmc_meas_running_q)); CARRY4 btmc_q0_carry (.CI(1'b0), .CO({btmc_q0_carry_n_0,NLW_btmc_q0_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O(NLW_btmc_q0_carry_O_UNCONNECTED[3:0]), .S({btmc_q0_carry_i_1_n_0,btmc_q0_carry_i_2_n_0,btmc_q0_carry_i_3_n_0,btmc_q0_carry_i_4_n_0})); CARRY4 btmc_q0_carry__0 (.CI(btmc_q0_carry_n_0), .CO({NLW_btmc_q0_carry__0_CO_UNCONNECTED[3:1],btmc_ce}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O(NLW_btmc_q0_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,btmc_q0_carry__0_i_1_n_0})); LUT4 #( .INIT(16'h2D00)) btmc_q0_carry__0_i_1 (.I0(\btmc_q_reg[14]_i_2_n_7 ), .I1(\btmc_q_reg[0]_0 ), .I2(btmc_q[12]), .I3(btmc_q0_carry__0_i_2_n_0), .O(btmc_q0_carry__0_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT5 #( .INIT(32'h00903309)) btmc_q0_carry__0_i_2 (.I0(\btmc_q_reg[14]_i_2_n_6 ), .I1(btmc_q[13]), .I2(\btmc_q_reg[14]_i_2_n_5 ), .I3(\btmc_q_reg[0]_0 ), .I4(btmc_q[14]), .O(btmc_q0_carry__0_i_2_n_0)); LUT4 #( .INIT(16'h2D00)) btmc_q0_carry_i_1 (.I0(\btmc_q_reg[11]_i_2_n_6 ), .I1(\btmc_q_reg[0]_0 ), .I2(btmc_q[9]), .I3(btmc_q0_carry_i_5_n_0), .O(btmc_q0_carry_i_1_n_0)); LUT4 #( .INIT(16'h2D00)) btmc_q0_carry_i_2 (.I0(\btmc_q_reg[7]_i_2_n_5 ), .I1(\btmc_q_reg[0]_0 ), .I2(btmc_q[6]), .I3(btmc_q0_carry_i_6_n_0), .O(btmc_q0_carry_i_2_n_0)); LUT4 #( .INIT(16'h2D00)) btmc_q0_carry_i_3 (.I0(\btmc_q_reg[3]_i_2_n_4 ), .I1(\btmc_q_reg[0]_0 ), .I2(btmc_q[3]), .I3(btmc_q0_carry_i_7_n_0), .O(btmc_q0_carry_i_3_n_0)); LUT4 #( .INIT(16'h2D00)) btmc_q0_carry_i_4 (.I0(\btmc_q_reg[3]_i_2_n_7 ), .I1(\btmc_q_reg[0]_0 ), .I2(btmc_q[0]), .I3(btmc_q0_carry_i_8_n_0), .O(btmc_q0_carry_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT5 #( .INIT(32'h00903309)) btmc_q0_carry_i_5 (.I0(\btmc_q_reg[11]_i_2_n_5 ), .I1(btmc_q[10]), .I2(\btmc_q_reg[11]_i_2_n_4 ), .I3(\btmc_q_reg[0]_0 ), .I4(btmc_q[11]), .O(btmc_q0_carry_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT5 #( .INIT(32'h00903309)) btmc_q0_carry_i_6 (.I0(\btmc_q_reg[7]_i_2_n_4 ), .I1(btmc_q[7]), .I2(\btmc_q_reg[11]_i_2_n_7 ), .I3(\btmc_q_reg[0]_0 ), .I4(btmc_q[8]), .O(btmc_q0_carry_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT5 #( .INIT(32'h00903309)) btmc_q0_carry_i_7 (.I0(\btmc_q_reg[7]_i_2_n_7 ), .I1(btmc_q[4]), .I2(\btmc_q_reg[7]_i_2_n_6 ), .I3(\btmc_q_reg[0]_0 ), .I4(btmc_q[5]), .O(btmc_q0_carry_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT5 #( .INIT(32'h00903309)) btmc_q0_carry_i_8 (.I0(\btmc_q_reg[3]_i_2_n_6 ), .I1(btmc_q[1]), .I2(\btmc_q_reg[3]_i_2_n_5 ), .I3(\btmc_q_reg[0]_0 ), .I4(btmc_q[2]), .O(btmc_q0_carry_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT2 #( .INIT(4'h2)) \btmc_q[0]_i_1 (.I0(\btmc_q_reg[3]_i_2_n_7 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT2 #( .INIT(4'h2)) \btmc_q[10]_i_1 (.I0(\btmc_q_reg[11]_i_2_n_5 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT2 #( .INIT(4'h2)) \btmc_q[11]_i_1 (.I0(\btmc_q_reg[11]_i_2_n_4 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT2 #( .INIT(4'h2)) \btmc_q[12]_i_1 (.I0(\btmc_q_reg[14]_i_2_n_7 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[12]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT2 #( .INIT(4'h2)) \btmc_q[13]_i_1 (.I0(\btmc_q_reg[14]_i_2_n_6 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT2 #( .INIT(4'h2)) \btmc_q[14]_i_1 (.I0(\btmc_q_reg[14]_i_2_n_5 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT2 #( .INIT(4'h2)) \btmc_q[1]_i_1 (.I0(\btmc_q_reg[3]_i_2_n_6 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h2)) \btmc_q[2]_i_1 (.I0(\btmc_q_reg[3]_i_2_n_5 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h2)) \btmc_q[3]_i_1 (.I0(\btmc_q_reg[3]_i_2_n_4 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[3]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \btmc_q[3]_i_3 (.I0(btmc_q[0]), .I1(btmc_meas_running_q), .O(\btmc_q[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT2 #( .INIT(4'h2)) \btmc_q[4]_i_1 (.I0(\btmc_q_reg[7]_i_2_n_7 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT2 #( .INIT(4'h2)) \btmc_q[5]_i_1 (.I0(\btmc_q_reg[7]_i_2_n_6 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h2)) \btmc_q[6]_i_1 (.I0(\btmc_q_reg[7]_i_2_n_5 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT2 #( .INIT(4'h2)) \btmc_q[7]_i_1 (.I0(\btmc_q_reg[7]_i_2_n_4 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h2)) \btmc_q[8]_i_1 (.I0(\btmc_q_reg[11]_i_2_n_7 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT2 #( .INIT(4'h2)) \btmc_q[9]_i_1 (.I0(\btmc_q_reg[11]_i_2_n_6 ), .I1(\btmc_q_reg[0]_0 ), .O(\btmc_q[9]_i_1_n_0 )); FDCE \btmc_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[0]_i_1_n_0 ), .Q(btmc_q[0])); FDCE \btmc_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[10]_i_1_n_0 ), .Q(btmc_q[10])); FDCE \btmc_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[11]_i_1_n_0 ), .Q(btmc_q[11])); (* ADDER_THRESHOLD = "35" *) CARRY4 \btmc_q_reg[11]_i_2 (.CI(\btmc_q_reg[7]_i_2_n_0 ), .CO({\btmc_q_reg[11]_i_2_n_0 ,\NLW_btmc_q_reg[11]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\btmc_q_reg[11]_i_2_n_4 ,\btmc_q_reg[11]_i_2_n_5 ,\btmc_q_reg[11]_i_2_n_6 ,\btmc_q_reg[11]_i_2_n_7 }), .S(btmc_q[11:8])); FDCE \btmc_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[12]_i_1_n_0 ), .Q(btmc_q[12])); FDCE \btmc_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[13]_i_1_n_0 ), .Q(btmc_q[13])); FDCE \btmc_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[14]_i_1_n_0 ), .Q(btmc_q[14])); (* ADDER_THRESHOLD = "35" *) CARRY4 \btmc_q_reg[14]_i_2 (.CI(\btmc_q_reg[11]_i_2_n_0 ), .CO(\NLW_btmc_q_reg[14]_i_2_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_btmc_q_reg[14]_i_2_O_UNCONNECTED [3],\btmc_q_reg[14]_i_2_n_5 ,\btmc_q_reg[14]_i_2_n_6 ,\btmc_q_reg[14]_i_2_n_7 }), .S({1'b0,btmc_q[14:12]})); FDCE \btmc_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[1]_i_1_n_0 ), .Q(btmc_q[1])); FDCE \btmc_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[2]_i_1_n_0 ), .Q(btmc_q[2])); FDCE \btmc_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[3]_i_1_n_0 ), .Q(btmc_q[3])); (* ADDER_THRESHOLD = "35" *) CARRY4 \btmc_q_reg[3]_i_2 (.CI(1'b0), .CO({\btmc_q_reg[3]_i_2_n_0 ,\NLW_btmc_q_reg[3]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,btmc_q[0]}), .O({\btmc_q_reg[3]_i_2_n_4 ,\btmc_q_reg[3]_i_2_n_5 ,\btmc_q_reg[3]_i_2_n_6 ,\btmc_q_reg[3]_i_2_n_7 }), .S({btmc_q[3:1],\btmc_q[3]_i_3_n_0 })); FDCE \btmc_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[4]_i_1_n_0 ), .Q(btmc_q[4])); FDCE \btmc_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[5]_i_1_n_0 ), .Q(btmc_q[5])); FDCE \btmc_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[6]_i_1_n_0 ), .Q(btmc_q[6])); FDCE \btmc_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[7]_i_1_n_0 ), .Q(btmc_q[7])); (* ADDER_THRESHOLD = "35" *) CARRY4 \btmc_q_reg[7]_i_2 (.CI(\btmc_q_reg[3]_i_2_n_0 ), .CO({\btmc_q_reg[7]_i_2_n_0 ,\NLW_btmc_q_reg[7]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\btmc_q_reg[7]_i_2_n_4 ,\btmc_q_reg[7]_i_2_n_5 ,\btmc_q_reg[7]_i_2_n_6 ,\btmc_q_reg[7]_i_2_n_7 }), .S(btmc_q[7:4])); FDCE \btmc_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[8]_i_1_n_0 ), .Q(btmc_q[8])); FDCE \btmc_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(btmc_ce), .CLR(first_ssp_q_reg_0), .D(\btmc_q[9]_i_1_n_0 ), .Q(btmc_q[9])); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 first_ssp_d0_carry (.CI(1'b0), .CO({first_ssp_d0_carry_n_0,NLW_first_ssp_d0_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({first_ssp_d0_carry_i_1_n_0,first_ssp_d0_carry_i_2_n_0,first_ssp_d0_carry_i_3_n_0,first_ssp_d0_carry_i_4_n_0}), .O(NLW_first_ssp_d0_carry_O_UNCONNECTED[3:0]), .S({first_ssp_d0_carry_i_5_n_0,first_ssp_d0_carry_i_6_n_0,first_ssp_d0_carry_i_7_n_0,first_ssp_d0_carry_i_8_n_0})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 first_ssp_d0_carry__0 (.CI(first_ssp_d0_carry_n_0), .CO({CO,NLW_first_ssp_d0_carry__0_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({first_ssp_d0_carry__0_i_1_n_0,first_ssp_d0_carry__0_i_2_n_0,first_ssp_d0_carry__0_i_3_n_0,first_ssp_d0_carry__0_i_4_n_0}), .O(NLW_first_ssp_d0_carry__0_O_UNCONNECTED[3:0]), .S({first_ssp_d0_carry__0_i_5_n_0,first_ssp_d0_carry__0_i_6_n_0,first_ssp_d0_carry__0_i_7_n_0,first_ssp_d0_carry__0_i_8_n_0})); LUT3 #( .INIT(8'h8A)) first_ssp_d0_carry__0_i_1 (.I0(sspc_q_reg[14]), .I1(first_ssp_q), .I2(btmc_q[14]), .O(first_ssp_d0_carry__0_i_1_n_0)); LUT5 #( .INIT(32'hFF2FAA02)) first_ssp_d0_carry__0_i_2 (.I0(sspc_q_reg[12]), .I1(btmc_q[12]), .I2(btmc_q[13]), .I3(first_ssp_q), .I4(sspc_q_reg[13]), .O(first_ssp_d0_carry__0_i_2_n_0)); LUT5 #( .INIT(32'hFF2FAA02)) first_ssp_d0_carry__0_i_3 (.I0(sspc_q_reg[10]), .I1(btmc_q[10]), .I2(btmc_q[11]), .I3(first_ssp_q), .I4(sspc_q_reg[11]), .O(first_ssp_d0_carry__0_i_3_n_0)); LUT6 #( .INIT(64'hFFFF22FF0A0A0022)) first_ssp_d0_carry__0_i_4 (.I0(sspc_q_reg[8]), .I1(btmc_q[8]), .I2(Q[8]), .I3(btmc_q[9]), .I4(first_ssp_q), .I5(sspc_q_reg[9]), .O(first_ssp_d0_carry__0_i_4_n_0)); LUT3 #( .INIT(8'h4B)) first_ssp_d0_carry__0_i_5 (.I0(first_ssp_q), .I1(btmc_q[14]), .I2(sspc_q_reg[14]), .O(first_ssp_d0_carry__0_i_5_n_0)); LUT5 #( .INIT(32'h05059009)) first_ssp_d0_carry__0_i_6 (.I0(sspc_q_reg[12]), .I1(btmc_q[12]), .I2(sspc_q_reg[13]), .I3(btmc_q[13]), .I4(first_ssp_q), .O(first_ssp_d0_carry__0_i_6_n_0)); LUT5 #( .INIT(32'h05059009)) first_ssp_d0_carry__0_i_7 (.I0(sspc_q_reg[10]), .I1(btmc_q[10]), .I2(sspc_q_reg[11]), .I3(btmc_q[11]), .I4(first_ssp_q), .O(first_ssp_d0_carry__0_i_7_n_0)); LUT6 #( .INIT(64'h00990099A50000A5)) first_ssp_d0_carry__0_i_8 (.I0(sspc_q_reg[8]), .I1(Q[8]), .I2(btmc_q[8]), .I3(sspc_q_reg[9]), .I4(btmc_q[9]), .I5(first_ssp_q), .O(first_ssp_d0_carry__0_i_8_n_0)); LUT6 #( .INIT(64'h028AFFFF0000028A)) first_ssp_d0_carry_i_1 (.I0(sspc_q_reg[6]), .I1(first_ssp_q), .I2(btmc_q[6]), .I3(Q[6]), .I4(sspc_threshold[7]), .I5(sspc_q_reg[7]), .O(first_ssp_d0_carry_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT3 #( .INIT(8'hAC)) first_ssp_d0_carry_i_10 (.I0(Q[5]), .I1(btmc_q[5]), .I2(first_ssp_q), .O(sspc_threshold[5])); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT3 #( .INIT(8'hAC)) first_ssp_d0_carry_i_11 (.I0(Q[3]), .I1(btmc_q[3]), .I2(first_ssp_q), .O(sspc_threshold[3])); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT3 #( .INIT(8'hAC)) first_ssp_d0_carry_i_12 (.I0(Q[1]), .I1(btmc_q[1]), .I2(first_ssp_q), .O(sspc_threshold[1])); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'hE41B)) first_ssp_d0_carry_i_13 (.I0(first_ssp_q), .I1(btmc_q[7]), .I2(Q[7]), .I3(sspc_q_reg[7]), .O(first_ssp_d0_carry_i_13_n_0)); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT4 #( .INIT(16'hE41B)) first_ssp_d0_carry_i_14 (.I0(first_ssp_q), .I1(btmc_q[5]), .I2(Q[5]), .I3(sspc_q_reg[5]), .O(first_ssp_d0_carry_i_14_n_0)); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT4 #( .INIT(16'hE41B)) first_ssp_d0_carry_i_15 (.I0(first_ssp_q), .I1(btmc_q[3]), .I2(Q[3]), .I3(sspc_q_reg[3]), .O(first_ssp_d0_carry_i_15_n_0)); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT4 #( .INIT(16'hE41B)) first_ssp_d0_carry_i_16 (.I0(first_ssp_q), .I1(btmc_q[1]), .I2(Q[1]), .I3(sspc_q_reg[1]), .O(first_ssp_d0_carry_i_16_n_0)); LUT6 #( .INIT(64'h028AFFFF0000028A)) first_ssp_d0_carry_i_2 (.I0(sspc_q_reg[4]), .I1(first_ssp_q), .I2(btmc_q[4]), .I3(Q[4]), .I4(sspc_threshold[5]), .I5(sspc_q_reg[5]), .O(first_ssp_d0_carry_i_2_n_0)); LUT6 #( .INIT(64'h028AFFFF0000028A)) first_ssp_d0_carry_i_3 (.I0(sspc_q_reg[2]), .I1(first_ssp_q), .I2(btmc_q[2]), .I3(Q[2]), .I4(sspc_threshold[3]), .I5(sspc_q_reg[3]), .O(first_ssp_d0_carry_i_3_n_0)); LUT6 #( .INIT(64'h028AFFFF0000028A)) first_ssp_d0_carry_i_4 (.I0(sspc_q_reg[0]), .I1(first_ssp_q), .I2(btmc_q[0]), .I3(Q[0]), .I4(sspc_threshold[1]), .I5(sspc_q_reg[1]), .O(first_ssp_d0_carry_i_4_n_0)); LUT5 #( .INIT(32'h99A50000)) first_ssp_d0_carry_i_5 (.I0(sspc_q_reg[6]), .I1(Q[6]), .I2(btmc_q[6]), .I3(first_ssp_q), .I4(first_ssp_d0_carry_i_13_n_0), .O(first_ssp_d0_carry_i_5_n_0)); LUT5 #( .INIT(32'h99A50000)) first_ssp_d0_carry_i_6 (.I0(sspc_q_reg[4]), .I1(Q[4]), .I2(btmc_q[4]), .I3(first_ssp_q), .I4(first_ssp_d0_carry_i_14_n_0), .O(first_ssp_d0_carry_i_6_n_0)); LUT5 #( .INIT(32'h99A50000)) first_ssp_d0_carry_i_7 (.I0(sspc_q_reg[2]), .I1(Q[2]), .I2(btmc_q[2]), .I3(first_ssp_q), .I4(first_ssp_d0_carry_i_15_n_0), .O(first_ssp_d0_carry_i_7_n_0)); LUT5 #( .INIT(32'h99A50000)) first_ssp_d0_carry_i_8 (.I0(sspc_q_reg[0]), .I1(Q[0]), .I2(btmc_q[0]), .I3(first_ssp_q), .I4(first_ssp_d0_carry_i_16_n_0), .O(first_ssp_d0_carry_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'hAC)) first_ssp_d0_carry_i_9 (.I0(Q[7]), .I1(btmc_q[7]), .I2(first_ssp_q), .O(sspc_threshold[7])); LUT3 #( .INIT(8'hBA)) first_ssp_q_i_1 (.I0(first_ssp_q0), .I1(CO), .I2(first_ssp_q), .O(first_ssp_q_i_1_n_0)); FDCE first_ssp_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(first_ssp_q_reg_0), .D(first_ssp_q_i_1_n_0), .Q(first_ssp_q)); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT2 #( .INIT(4'h8)) prev_sample_q_i_3 (.I0(CO), .I1(sspc_ena_q_reg_0), .O(sample_sec)); FDCE sspc_ena_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(first_ssp_q_reg_0), .D(sspc_ena_q_reg_1), .Q(sspc_ena_q_reg_0)); CARRY4 sspc_q0_carry (.CI(1'b0), .CO({sspc_q0_carry_n_0,NLW_sspc_q0_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b1,1'b1,1'b1,1'b1}), .O(NLW_sspc_q0_carry_O_UNCONNECTED[3:0]), .S({sspc_q0_carry_i_1_n_0,sspc_q0_carry_i_2_n_0,sspc_q0_carry_i_3_n_0,sspc_q0_carry_i_4_n_0})); CARRY4 sspc_q0_carry__0 (.CI(sspc_q0_carry_n_0), .CO({NLW_sspc_q0_carry__0_CO_UNCONNECTED[3:1],sel}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O(NLW_sspc_q0_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,sspc_q0_carry__0_i_1_n_0})); LUT5 #( .INIT(32'h10EF0000)) sspc_q0_carry__0_i_1 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry__0_i_2_n_7), .I3(sspc_q_reg[12]), .I4(sspc_q0_carry__0_i_3_n_0), .O(sspc_q0_carry__0_i_1_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 sspc_q0_carry__0_i_2 (.CI(sspc_q0_carry_i_5_n_0), .CO(NLW_sspc_q0_carry__0_i_2_CO_UNCONNECTED[3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_sspc_q0_carry__0_i_2_O_UNCONNECTED[3],sspc_q0_carry__0_i_2_n_5,sspc_q0_carry__0_i_2_n_6,sspc_q0_carry__0_i_2_n_7}), .S({1'b0,sspc_q_reg[14:12]})); LUT6 #( .INIT(64'h1001000000EE10EF)) sspc_q0_carry__0_i_3 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry__0_i_2_n_6), .I3(sspc_q_reg[13]), .I4(sspc_q0_carry__0_i_2_n_5), .I5(sspc_q_reg[14]), .O(sspc_q0_carry__0_i_3_n_0)); LUT5 #( .INIT(32'h10EF0000)) sspc_q0_carry_i_1 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_5_n_6), .I3(sspc_q_reg[9]), .I4(sspc_q0_carry_i_6_n_0), .O(sspc_q0_carry_i_1_n_0)); LUT6 #( .INIT(64'h1001000000EE10EF)) sspc_q0_carry_i_10 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_7_n_7), .I3(sspc_q_reg[4]), .I4(sspc_q0_carry_i_7_n_6), .I5(sspc_q_reg[5]), .O(sspc_q0_carry_i_10_n_0)); LUT6 #( .INIT(64'h1001000000EE10EF)) sspc_q0_carry_i_11 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_9_n_6), .I3(sspc_q_reg[1]), .I4(sspc_q0_carry_i_9_n_5), .I5(sspc_q_reg[2]), .O(sspc_q0_carry_i_11_n_0)); LUT2 #( .INIT(4'h6)) sspc_q0_carry_i_12 (.I0(sspc_q_reg[0]), .I1(sspc_ena_q_reg_0), .O(sspc_q0_carry_i_12_n_0)); LUT5 #( .INIT(32'h10EF0000)) sspc_q0_carry_i_2 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_7_n_5), .I3(sspc_q_reg[6]), .I4(sspc_q0_carry_i_8_n_0), .O(sspc_q0_carry_i_2_n_0)); LUT5 #( .INIT(32'h10EF0000)) sspc_q0_carry_i_3 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_9_n_4), .I3(sspc_q_reg[3]), .I4(sspc_q0_carry_i_10_n_0), .O(sspc_q0_carry_i_3_n_0)); LUT5 #( .INIT(32'hFE010000)) sspc_q0_carry_i_4 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_9_n_7), .I3(sspc_q_reg[0]), .I4(sspc_q0_carry_i_11_n_0), .O(sspc_q0_carry_i_4_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 sspc_q0_carry_i_5 (.CI(sspc_q0_carry_i_7_n_0), .CO({sspc_q0_carry_i_5_n_0,NLW_sspc_q0_carry_i_5_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({sspc_q0_carry_i_5_n_4,sspc_q0_carry_i_5_n_5,sspc_q0_carry_i_5_n_6,sspc_q0_carry_i_5_n_7}), .S(sspc_q_reg[11:8])); LUT6 #( .INIT(64'h1001000000EE10EF)) sspc_q0_carry_i_6 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_5_n_5), .I3(sspc_q_reg[10]), .I4(sspc_q0_carry_i_5_n_4), .I5(sspc_q_reg[11]), .O(sspc_q0_carry_i_6_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 sspc_q0_carry_i_7 (.CI(sspc_q0_carry_i_9_n_0), .CO({sspc_q0_carry_i_7_n_0,NLW_sspc_q0_carry_i_7_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({sspc_q0_carry_i_7_n_4,sspc_q0_carry_i_7_n_5,sspc_q0_carry_i_7_n_6,sspc_q0_carry_i_7_n_7}), .S(sspc_q_reg[7:4])); LUT6 #( .INIT(64'h1001000000EE10EF)) sspc_q0_carry_i_8 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q0_carry_i_7_n_4), .I3(sspc_q_reg[7]), .I4(sspc_q0_carry_i_5_n_7), .I5(sspc_q_reg[8]), .O(sspc_q0_carry_i_8_n_0)); (* ADDER_THRESHOLD = "35" *) CARRY4 sspc_q0_carry_i_9 (.CI(1'b0), .CO({sspc_q0_carry_i_9_n_0,NLW_sspc_q0_carry_i_9_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,sspc_q_reg[0]}), .O({sspc_q0_carry_i_9_n_4,sspc_q0_carry_i_9_n_5,sspc_q0_carry_i_9_n_6,sspc_q0_carry_i_9_n_7}), .S({sspc_q_reg[3:1],sspc_q0_carry_i_12_n_0})); LUT3 #( .INIT(8'h10)) \sspc_q[0]_i_2 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_ena_q_reg_0), .O(\sspc_q[0]_i_2_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[0]_i_3 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[3]), .O(\sspc_q[0]_i_3_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[0]_i_4 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[2]), .O(\sspc_q[0]_i_4_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[0]_i_5 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[1]), .O(\sspc_q[0]_i_5_n_0 )); LUT4 #( .INIT(16'hEFFE)) \sspc_q[0]_i_6 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_ena_q_reg_0), .I3(sspc_q_reg[0]), .O(\sspc_q[0]_i_6_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[12]_i_2 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[14]), .O(\sspc_q[12]_i_2_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[12]_i_3 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[13]), .O(\sspc_q[12]_i_3_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[12]_i_4 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[12]), .O(\sspc_q[12]_i_4_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[4]_i_2 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[7]), .O(\sspc_q[4]_i_2_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[4]_i_3 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[6]), .O(\sspc_q[4]_i_3_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[4]_i_4 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[5]), .O(\sspc_q[4]_i_4_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[4]_i_5 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[4]), .O(\sspc_q[4]_i_5_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[8]_i_2 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[11]), .O(\sspc_q[8]_i_2_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[8]_i_3 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[10]), .O(\sspc_q[8]_i_3_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[8]_i_4 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[9]), .O(\sspc_q[8]_i_4_n_0 )); LUT3 #( .INIT(8'h10)) \sspc_q[8]_i_5 (.I0(\btmc_q_reg[0]_0 ), .I1(CO), .I2(sspc_q_reg[8]), .O(\sspc_q[8]_i_5_n_0 )); FDPE \sspc_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(sel), .D(\sspc_q_reg[0]_i_1_n_7 ), .PRE(first_ssp_q_reg_0), .Q(sspc_q_reg[0])); (* ADDER_THRESHOLD = "35" *) CARRY4 \sspc_q_reg[0]_i_1 (.CI(1'b0), .CO({\sspc_q_reg[0]_i_1_n_0 ,\NLW_sspc_q_reg[0]_i_1_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\sspc_q[0]_i_2_n_0 }), .O({\sspc_q_reg[0]_i_1_n_4 ,\sspc_q_reg[0]_i_1_n_5 ,\sspc_q_reg[0]_i_1_n_6 ,\sspc_q_reg[0]_i_1_n_7 }), .S({\sspc_q[0]_i_3_n_0 ,\sspc_q[0]_i_4_n_0 ,\sspc_q[0]_i_5_n_0 ,\sspc_q[0]_i_6_n_0 })); FDCE \sspc_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[8]_i_1_n_5 ), .Q(sspc_q_reg[10])); FDCE \sspc_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[8]_i_1_n_4 ), .Q(sspc_q_reg[11])); FDCE \sspc_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[12]_i_1_n_7 ), .Q(sspc_q_reg[12])); (* ADDER_THRESHOLD = "35" *) CARRY4 \sspc_q_reg[12]_i_1 (.CI(\sspc_q_reg[8]_i_1_n_0 ), .CO(\NLW_sspc_q_reg[12]_i_1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_sspc_q_reg[12]_i_1_O_UNCONNECTED [3],\sspc_q_reg[12]_i_1_n_5 ,\sspc_q_reg[12]_i_1_n_6 ,\sspc_q_reg[12]_i_1_n_7 }), .S({1'b0,\sspc_q[12]_i_2_n_0 ,\sspc_q[12]_i_3_n_0 ,\sspc_q[12]_i_4_n_0 })); FDCE \sspc_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[12]_i_1_n_6 ), .Q(sspc_q_reg[13])); FDCE \sspc_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[12]_i_1_n_5 ), .Q(sspc_q_reg[14])); FDCE \sspc_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[0]_i_1_n_6 ), .Q(sspc_q_reg[1])); FDCE \sspc_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[0]_i_1_n_5 ), .Q(sspc_q_reg[2])); FDCE \sspc_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[0]_i_1_n_4 ), .Q(sspc_q_reg[3])); FDCE \sspc_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[4]_i_1_n_7 ), .Q(sspc_q_reg[4])); (* ADDER_THRESHOLD = "35" *) CARRY4 \sspc_q_reg[4]_i_1 (.CI(\sspc_q_reg[0]_i_1_n_0 ), .CO({\sspc_q_reg[4]_i_1_n_0 ,\NLW_sspc_q_reg[4]_i_1_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\sspc_q_reg[4]_i_1_n_4 ,\sspc_q_reg[4]_i_1_n_5 ,\sspc_q_reg[4]_i_1_n_6 ,\sspc_q_reg[4]_i_1_n_7 }), .S({\sspc_q[4]_i_2_n_0 ,\sspc_q[4]_i_3_n_0 ,\sspc_q[4]_i_4_n_0 ,\sspc_q[4]_i_5_n_0 })); FDCE \sspc_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[4]_i_1_n_6 ), .Q(sspc_q_reg[5])); FDCE \sspc_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[4]_i_1_n_5 ), .Q(sspc_q_reg[6])); FDCE \sspc_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[4]_i_1_n_4 ), .Q(sspc_q_reg[7])); FDCE \sspc_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[8]_i_1_n_7 ), .Q(sspc_q_reg[8])); (* ADDER_THRESHOLD = "35" *) CARRY4 \sspc_q_reg[8]_i_1 (.CI(\sspc_q_reg[4]_i_1_n_0 ), .CO({\sspc_q_reg[8]_i_1_n_0 ,\NLW_sspc_q_reg[8]_i_1_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\sspc_q_reg[8]_i_1_n_4 ,\sspc_q_reg[8]_i_1_n_5 ,\sspc_q_reg[8]_i_1_n_6 ,\sspc_q_reg[8]_i_1_n_7 }), .S({\sspc_q[8]_i_2_n_0 ,\sspc_q[8]_i_3_n_0 ,\sspc_q[8]_i_4_n_0 ,\sspc_q[8]_i_5_n_0 })); FDCE \sspc_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(sel), .CLR(first_ssp_q_reg_0), .D(\sspc_q_reg[8]_i_1_n_6 ), .Q(sspc_q_reg[9])); endmodule module bm_top (tx_data_prev, rx_data_wbs, sspc_ena_q, btmc_meas_running_q, bit_err, \write_pointer_q_reg[0] , \timestamp[4] , \timestamp[32] , Q, \timestamp[33] , \timestamp[34] , \timestamp[35] , \timestamp[37] , \trv_delay_shadowed_reg[6] , sync_edge, bit_err_d2, prev_sample_q_reg, sync_edge3__0, trv_delay_sum, p_0_out, clk_sys_IBUF_BUFG, reg_q_reg, can_tx_OBUF, can_rx_IBUF, reg_q_reg_0, sspc_ena_q_reg, btmc_meas_running_q_reg, bit_err_d0_out, \write_pointer_q_reg[0]_0 , timestamp_IBUF, adress_IBUF, \r_data_reg[6] , \cc_stat[bst_ctr] , \cc_stat[dst_ctr] , \r_data_reg[6]_0 , \pc_dbg[is_arbitration] , rx_data_sync_prev_reg, rx_data_sync_prev_reg_0, rx_data_sync_prev_reg_1, bit_err_enable, \btmc_q_reg[0] , tx_trigger_ssp, tran_delay_meas, scan_mode_IBUF, rst_n_out_OBUF, \mr_ctrl_out[settings_ena] , prev_sample_q_reg_0, prev_sample_q_reg_1, first_ssp_q0, D, \mr_ctrl_out[ssp_cfg_ssp_offset] ); output tx_data_prev; output rx_data_wbs; output sspc_ena_q; output btmc_meas_running_q; output bit_err; output [0:0]\write_pointer_q_reg[0] ; output \timestamp[4] ; output \timestamp[32] ; output [0:0]Q; output \timestamp[33] ; output \timestamp[34] ; output \timestamp[35] ; output \timestamp[37] ; output \trv_delay_shadowed_reg[6] ; output sync_edge; output bit_err_d2; output prev_sample_q_reg; output sync_edge3__0; output [8:0]trv_delay_sum; input p_0_out; input clk_sys_IBUF_BUFG; input reg_q_reg; input can_tx_OBUF; input can_rx_IBUF; input reg_q_reg_0; input sspc_ena_q_reg; input btmc_meas_running_q_reg; input bit_err_d0_out; input \write_pointer_q_reg[0]_0 ; input [11:0]timestamp_IBUF; input [1:0]adress_IBUF; input \r_data_reg[6] ; input [2:0]\cc_stat[bst_ctr] ; input [2:0]\cc_stat[dst_ctr] ; input \r_data_reg[6]_0 ; input \pc_dbg[is_arbitration] ; input rx_data_sync_prev_reg; input rx_data_sync_prev_reg_0; input rx_data_sync_prev_reg_1; input bit_err_enable; input \btmc_q_reg[0] ; input tx_trigger_ssp; input tran_delay_meas; input scan_mode_IBUF; input rst_n_out_OBUF; input \mr_ctrl_out[settings_ena] ; input prev_sample_q_reg_0; input prev_sample_q_reg_1; input first_ssp_q0; input [8:0]D; input [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [8:0]D; wire [0:0]Q; wire [1:0]adress_IBUF; wire bit_err; wire bit_err_d0_out; wire bit_err_d2; wire bit_err_enable; wire bit_err_ssp_condition; wire btmc_meas_running_q; wire btmc_meas_running_q_reg; wire \btmc_q_reg[0] ; wire can_rx_IBUF; wire can_tx_OBUF; wire [2:0]\cc_stat[bst_ctr] ; wire [2:0]\cc_stat[dst_ctr] ; wire clk_sys_IBUF_BUFG; wire data_tx_delayed; wire first_ssp_q0; wire i_bm_trv_delay_meas_n_17; wire i_bm_trv_delay_meas_n_18; wire i_bm_trv_delay_meas_n_19; wire i_bm_trv_delay_meas_n_20; wire i_bm_trv_delay_meas_n_21; wire i_bm_trv_delay_meas_n_22; wire i_bm_trv_delay_meas_n_23; wire i_bm_trv_delay_meas_n_24; wire i_bm_trv_delay_meas_n_25; wire \mr_ctrl_out[settings_ena] ; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire p_0_out; wire \pc_dbg[is_arbitration] ; wire prev_sample_q; wire prev_sample_q_reg; wire prev_sample_q_reg_0; wire prev_sample_q_reg_1; wire q_i; wire \r_data_reg[6] ; wire \r_data_reg[6]_0 ; wire reg_q_reg; wire reg_q_reg_0; wire rst_n_out_OBUF; wire rx_data_prev; wire rx_data_sync_prev; wire rx_data_sync_prev_reg; wire rx_data_sync_prev_reg_0; wire rx_data_sync_prev_reg_1; wire rx_data_wbs; wire sample_sec; wire scan_mode_IBUF; wire sspc_ena_q; wire sspc_ena_q_reg; wire sspc_expired; wire sync_edge; wire sync_edge3__0; wire \timestamp[32] ; wire \timestamp[33] ; wire \timestamp[34] ; wire \timestamp[35] ; wire \timestamp[37] ; wire \timestamp[4] ; wire [11:0]timestamp_IBUF; wire tran_delay_meas; wire \trv_delay_shadowed_reg[6] ; wire [8:0]trv_delay_sum; wire tx_data_prev; wire tx_trigger_ssp; wire [0:0]\write_pointer_q_reg[0] ; wire \write_pointer_q_reg[0]_0 ; bm_bit_err_detector i_bm_bit_err_detector (.bit_err(bit_err), .bit_err_d0_out(bit_err_d0_out), .bit_err_d2(bit_err_d2), .bit_err_ssp_capt_q_reg_0(reg_q_reg), .bit_err_ssp_capt_q_reg_1(prev_sample_q_reg_0), .bit_err_ssp_condition(bit_err_ssp_condition), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG)); bm_data_edge_detector i_bm_data_edge_detector (.can_tx_OBUF(can_tx_OBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .prev_sample_q(prev_sample_q), .rx_data_prev(rx_data_prev), .rx_data_prev_reg_0(rx_data_wbs), .rx_data_sync_prev(rx_data_sync_prev), .rx_data_sync_prev_reg_0(reg_q_reg), .rx_data_sync_prev_reg_1(rx_data_sync_prev_reg), .rx_data_sync_prev_reg_2(rx_data_sync_prev_reg_0), .rx_data_sync_prev_reg_3(rx_data_sync_prev_reg_1), .sync_edge(sync_edge), .tx_data_prev(tx_data_prev)); bm_sample_mux i_bm_sample_mux (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .prev_sample_q(prev_sample_q), .prev_sample_q_reg_0(prev_sample_q_reg), .prev_sample_q_reg_1(rx_data_wbs), .prev_sample_q_reg_2(prev_sample_q_reg_0), .prev_sample_q_reg_3(prev_sample_q_reg_1), .prev_sample_q_reg_4(reg_q_reg), .rx_data_sync_prev(rx_data_sync_prev), .sample_sec(sample_sec)); bm_ssp_generator i_bm_ssp_generator (.CO(sspc_expired), .Q({i_bm_trv_delay_meas_n_17,i_bm_trv_delay_meas_n_18,i_bm_trv_delay_meas_n_19,i_bm_trv_delay_meas_n_20,i_bm_trv_delay_meas_n_21,i_bm_trv_delay_meas_n_22,i_bm_trv_delay_meas_n_23,i_bm_trv_delay_meas_n_24,i_bm_trv_delay_meas_n_25}), .bit_err_enable(bit_err_enable), .bit_err_ssp_capt_q_reg(rx_data_wbs), .bit_err_ssp_condition(bit_err_ssp_condition), .btmc_meas_running_q(btmc_meas_running_q), .btmc_meas_running_q_reg_0(btmc_meas_running_q_reg), .\btmc_q_reg[0]_0 (\btmc_q_reg[0] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_tx_delayed(data_tx_delayed), .first_ssp_q0(first_ssp_q0), .first_ssp_q_reg_0(reg_q_reg), .sample_sec(sample_sec), .sspc_ena_q_reg_0(sspc_ena_q), .sspc_ena_q_reg_1(sspc_ena_q_reg)); bm_trv_delay_meas i_bm_trv_delay_meas (.D(D), .Q(Q), .adress_IBUF(adress_IBUF), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[bst_ctr] (\cc_stat[bst_ctr] ), .\cc_stat[dst_ctr] (\cc_stat[dst_ctr] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .p_0_out(p_0_out), .\pc_dbg[is_arbitration] (\pc_dbg[is_arbitration] ), .\r_data_reg[6] (\r_data_reg[6] ), .\r_data_reg[6]_0 (\r_data_reg[6]_0 ), .reg_q_reg(reg_q_reg), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_prev(rx_data_prev), .scan_mode_IBUF(scan_mode_IBUF), .\ssp_delay_shadowed_reg[8]_0 ({i_bm_trv_delay_meas_n_17,i_bm_trv_delay_meas_n_18,i_bm_trv_delay_meas_n_19,i_bm_trv_delay_meas_n_20,i_bm_trv_delay_meas_n_21,i_bm_trv_delay_meas_n_22,i_bm_trv_delay_meas_n_23,i_bm_trv_delay_meas_n_24,i_bm_trv_delay_meas_n_25}), .\timestamp[32] (\timestamp[32] ), .\timestamp[33] (\timestamp[33] ), .\timestamp[34] (\timestamp[34] ), .\timestamp[35] (\timestamp[35] ), .\timestamp[37] (\timestamp[37] ), .\timestamp[4] (\timestamp[4] ), .timestamp_IBUF(timestamp_IBUF), .tran_delay_meas(tran_delay_meas), .\trv_delay_shadowed_reg[6]_0 (\trv_delay_shadowed_reg[6] ), .trv_delay_sum(trv_delay_sum), .trv_meas_progress_q_reg_0(rx_data_wbs), .tx_data_prev(tx_data_prev)); bm_tx_data_cache i_bm_tx_data_cache (.CO(sspc_expired), .can_tx_OBUF(can_tx_OBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_tx_delayed(data_tx_delayed), .q_i(q_i), .\read_pointer_q_reg[0]_0 (sspc_ena_q), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF), .tx_trigger_ssp(tx_trigger_ssp), .\write_pointer_q_reg[0]_0 (\write_pointer_q_reg[0] ), .\write_pointer_q_reg[0]_1 (\write_pointer_q_reg[0]_0 )); sig_sync i_can_rx_sig_sync (.can_rx_IBUF(can_rx_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .rff_reg_0(reg_q_reg), .rx_data_sync_prev(rx_data_sync_prev), .sync_edge3__0(sync_edge3__0), .sync_reg_0(rx_data_wbs)); rst_reg_82 i_shift_regs_rst_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .q_i(q_i), .reg_q_reg(reg_q_reg_0), .reg_q_reg_0(reg_q_reg)); endmodule module bm_trv_delay_meas (\timestamp[4] , \timestamp[32] , \timestamp[33] , \timestamp[34] , \timestamp[35] , \timestamp[37] , \trv_delay_shadowed_reg[6]_0 , trv_delay_sum, Q, \ssp_delay_shadowed_reg[8]_0 , p_0_out, clk_sys_IBUF_BUFG, reg_q_reg, timestamp_IBUF, adress_IBUF, \r_data_reg[6] , \cc_stat[bst_ctr] , \cc_stat[dst_ctr] , \r_data_reg[6]_0 , \pc_dbg[is_arbitration] , trv_meas_progress_q_reg_0, rx_data_prev, can_tx_OBUF, tx_data_prev, tran_delay_meas, scan_mode_IBUF, rst_n_out_OBUF, D, \mr_ctrl_out[ssp_cfg_ssp_offset] ); output \timestamp[4] ; output \timestamp[32] ; output \timestamp[33] ; output \timestamp[34] ; output \timestamp[35] ; output \timestamp[37] ; output \trv_delay_shadowed_reg[6]_0 ; output [8:0]trv_delay_sum; output [0:0]Q; output [8:0]\ssp_delay_shadowed_reg[8]_0 ; input p_0_out; input clk_sys_IBUF_BUFG; input reg_q_reg; input [11:0]timestamp_IBUF; input [1:0]adress_IBUF; input \r_data_reg[6] ; input [2:0]\cc_stat[bst_ctr] ; input [2:0]\cc_stat[dst_ctr] ; input \r_data_reg[6]_0 ; input \pc_dbg[is_arbitration] ; input trv_meas_progress_q_reg_0; input rx_data_prev; input can_tx_OBUF; input tx_data_prev; input tran_delay_meas; input scan_mode_IBUF; input rst_n_out_OBUF; input [8:0]D; input [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [8:0]D; wire [0:0]Q; wire [1:0]adress_IBUF; wire can_tx_OBUF; wire [2:0]\cc_stat[bst_ctr] ; wire [2:0]\cc_stat[dst_ctr] ; wire clk_sys_IBUF_BUFG; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire p_0_out; wire \pc_dbg[is_arbitration] ; wire q_i; wire \r_data[0]_i_7_n_0 ; wire \r_data[1]_i_8_n_0 ; wire \r_data[2]_i_9_n_0 ; wire \r_data[3]_i_6_n_0 ; wire \r_data[4]_i_7_n_0 ; wire \r_data[5]_i_8_n_0 ; wire \r_data_reg[6] ; wire \r_data_reg[6]_0 ; wire reg_q_reg; wire rst_n_out_OBUF; wire rx_data_prev; wire scan_mode_IBUF; wire \ssp_delay_shadowed[3]_i_3_n_0 ; wire \ssp_delay_shadowed[3]_i_4_n_0 ; wire \ssp_delay_shadowed[3]_i_5_n_0 ; wire \ssp_delay_shadowed[3]_i_6_n_0 ; wire \ssp_delay_shadowed[7]_i_3_n_0 ; wire \ssp_delay_shadowed[7]_i_4_n_0 ; wire \ssp_delay_shadowed[7]_i_5_n_0 ; wire \ssp_delay_shadowed[7]_i_6_n_0 ; wire \ssp_delay_shadowed_reg[3]_i_2_n_0 ; wire \ssp_delay_shadowed_reg[7]_i_2_n_0 ; wire [8:0]\ssp_delay_shadowed_reg[8]_0 ; wire ssp_shadow_ce; wire \timestamp[32] ; wire \timestamp[33] ; wire \timestamp[34] ; wire \timestamp[35] ; wire \timestamp[37] ; wire \timestamp[4] ; wire [11:0]timestamp_IBUF; wire tran_delay_meas; wire [6:0]trv_delay; wire [7:0]trv_delay_ctr_d; wire [7:0]trv_delay_ctr_q; wire \trv_delay_ctr_q[3]_i_2_n_0 ; wire \trv_delay_ctr_q[7]_i_2_n_0 ; wire \trv_delay_ctr_q[7]_i_3_n_0 ; wire \trv_delay_shadowed_reg[6]_0 ; wire [8:0]trv_delay_sum; wire trv_meas_progress_del; wire trv_meas_progress_q; wire trv_meas_progress_q_i_1_n_0; wire trv_meas_progress_q_reg_0; wire tx_data_prev; wire [2:0]\NLW_ssp_delay_shadowed_reg[3]_i_2_CO_UNCONNECTED ; wire [2:0]\NLW_ssp_delay_shadowed_reg[7]_i_2_CO_UNCONNECTED ; wire [3:1]\NLW_ssp_delay_shadowed_reg[8]_i_2_CO_UNCONNECTED ; wire [3:0]\NLW_ssp_delay_shadowed_reg[8]_i_2_O_UNCONNECTED ; rst_reg_84 i_trv_delay_rst_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .p_0_out(p_0_out), .q_i(q_i), .reg_q_reg(reg_q_reg)); LUT6 #( .INIT(64'hC4F4FFFFC4F40000)) \r_data[0]_i_3__0 (.I0(timestamp_IBUF[6]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[0]), .I4(\r_data_reg[6] ), .I5(\r_data[0]_i_7_n_0 ), .O(\timestamp[32] )); LUT4 #( .INIT(16'h3DFD)) \r_data[0]_i_7 (.I0(trv_delay[0]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\cc_stat[bst_ctr] [0]), .O(\r_data[0]_i_7_n_0 )); LUT6 #( .INIT(64'hC4F4FFFFC4F40000)) \r_data[1]_i_3__0 (.I0(timestamp_IBUF[7]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[1]), .I4(\r_data_reg[6] ), .I5(\r_data[1]_i_8_n_0 ), .O(\timestamp[33] )); LUT4 #( .INIT(16'h3DFD)) \r_data[1]_i_8 (.I0(trv_delay[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\cc_stat[bst_ctr] [1]), .O(\r_data[1]_i_8_n_0 )); LUT6 #( .INIT(64'hC4F4FFFFC4F40000)) \r_data[2]_i_4 (.I0(timestamp_IBUF[8]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[2]), .I4(\r_data_reg[6] ), .I5(\r_data[2]_i_9_n_0 ), .O(\timestamp[34] )); LUT4 #( .INIT(16'h3DFD)) \r_data[2]_i_9 (.I0(trv_delay[2]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\cc_stat[bst_ctr] [2]), .O(\r_data[2]_i_9_n_0 )); LUT6 #( .INIT(64'hC4F4FFFFC4F40000)) \r_data[3]_i_3__0 (.I0(timestamp_IBUF[9]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[3]), .I4(\r_data_reg[6] ), .I5(\r_data[3]_i_6_n_0 ), .O(\timestamp[35] )); LUT4 #( .INIT(16'h3DFD)) \r_data[3]_i_6 (.I0(trv_delay[3]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\cc_stat[dst_ctr] [0]), .O(\r_data[3]_i_6_n_0 )); LUT6 #( .INIT(64'hC7F7FFFFC7F70000)) \r_data[4]_i_3 (.I0(timestamp_IBUF[4]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(timestamp_IBUF[10]), .I4(\r_data_reg[6] ), .I5(\r_data[4]_i_7_n_0 ), .O(\timestamp[4] )); LUT4 #( .INIT(16'h3DFD)) \r_data[4]_i_7 (.I0(trv_delay[4]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\cc_stat[dst_ctr] [1]), .O(\r_data[4]_i_7_n_0 )); LUT6 #( .INIT(64'hC4F4FFFFC4F40000)) \r_data[5]_i_3__0 (.I0(timestamp_IBUF[11]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[5]), .I4(\r_data_reg[6] ), .I5(\r_data[5]_i_8_n_0 ), .O(\timestamp[37] )); LUT4 #( .INIT(16'h3DFD)) \r_data[5]_i_8 (.I0(trv_delay[5]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\cc_stat[dst_ctr] [2]), .O(\r_data[5]_i_8_n_0 )); LUT6 #( .INIT(64'h88BBBB8BBBBBBB8B)) \r_data[6]_i_3__0 (.I0(\r_data_reg[6]_0 ), .I1(\r_data_reg[6] ), .I2(trv_delay[6]), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\pc_dbg[is_arbitration] ), .O(\trv_delay_shadowed_reg[6]_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[3]_i_3 (.I0(trv_delay_ctr_q[3]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [3]), .O(\ssp_delay_shadowed[3]_i_3_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[3]_i_4 (.I0(trv_delay_ctr_q[2]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [2]), .O(\ssp_delay_shadowed[3]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[3]_i_5 (.I0(trv_delay_ctr_q[1]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [1]), .O(\ssp_delay_shadowed[3]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[3]_i_6 (.I0(trv_delay_ctr_q[0]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [0]), .O(\ssp_delay_shadowed[3]_i_6_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[7]_i_3 (.I0(trv_delay_ctr_q[7]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [7]), .O(\ssp_delay_shadowed[7]_i_3_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[7]_i_4 (.I0(trv_delay_ctr_q[6]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [6]), .O(\ssp_delay_shadowed[7]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[7]_i_5 (.I0(trv_delay_ctr_q[5]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [5]), .O(\ssp_delay_shadowed[7]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \ssp_delay_shadowed[7]_i_6 (.I0(trv_delay_ctr_q[4]), .I1(\mr_ctrl_out[ssp_cfg_ssp_offset] [4]), .O(\ssp_delay_shadowed[7]_i_6_n_0 )); FDCE \ssp_delay_shadowed_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[0]), .Q(\ssp_delay_shadowed_reg[8]_0 [0])); FDCE \ssp_delay_shadowed_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[1]), .Q(\ssp_delay_shadowed_reg[8]_0 [1])); FDCE \ssp_delay_shadowed_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[2]), .Q(\ssp_delay_shadowed_reg[8]_0 [2])); FDCE \ssp_delay_shadowed_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[3]), .Q(\ssp_delay_shadowed_reg[8]_0 [3])); CARRY4 \ssp_delay_shadowed_reg[3]_i_2 (.CI(1'b0), .CO({\ssp_delay_shadowed_reg[3]_i_2_n_0 ,\NLW_ssp_delay_shadowed_reg[3]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI(trv_delay_ctr_q[3:0]), .O(trv_delay_sum[3:0]), .S({\ssp_delay_shadowed[3]_i_3_n_0 ,\ssp_delay_shadowed[3]_i_4_n_0 ,\ssp_delay_shadowed[3]_i_5_n_0 ,\ssp_delay_shadowed[3]_i_6_n_0 })); FDCE \ssp_delay_shadowed_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[4]), .Q(\ssp_delay_shadowed_reg[8]_0 [4])); FDCE \ssp_delay_shadowed_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[5]), .Q(\ssp_delay_shadowed_reg[8]_0 [5])); FDCE \ssp_delay_shadowed_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[6]), .Q(\ssp_delay_shadowed_reg[8]_0 [6])); FDCE \ssp_delay_shadowed_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[7]), .Q(\ssp_delay_shadowed_reg[8]_0 [7])); CARRY4 \ssp_delay_shadowed_reg[7]_i_2 (.CI(\ssp_delay_shadowed_reg[3]_i_2_n_0 ), .CO({\ssp_delay_shadowed_reg[7]_i_2_n_0 ,\NLW_ssp_delay_shadowed_reg[7]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI(trv_delay_ctr_q[7:4]), .O(trv_delay_sum[7:4]), .S({\ssp_delay_shadowed[7]_i_3_n_0 ,\ssp_delay_shadowed[7]_i_4_n_0 ,\ssp_delay_shadowed[7]_i_5_n_0 ,\ssp_delay_shadowed[7]_i_6_n_0 })); FDCE \ssp_delay_shadowed_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(D[8]), .Q(\ssp_delay_shadowed_reg[8]_0 [8])); CARRY4 \ssp_delay_shadowed_reg[8]_i_2 (.CI(\ssp_delay_shadowed_reg[7]_i_2_n_0 ), .CO({\NLW_ssp_delay_shadowed_reg[8]_i_2_CO_UNCONNECTED [3:1],trv_delay_sum[8]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_ssp_delay_shadowed_reg[8]_i_2_O_UNCONNECTED [3:0]), .S({1'b0,1'b0,1'b0,1'b1})); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT5 #( .INIT(32'h8000FFFF)) \trv_delay_ctr_q[0]_i_1 (.I0(\trv_delay_ctr_q[3]_i_2_n_0 ), .I1(trv_delay_ctr_q[3]), .I2(trv_delay_ctr_q[2]), .I3(trv_delay_ctr_q[1]), .I4(trv_delay_ctr_q[0]), .O(trv_delay_ctr_d[0])); LUT5 #( .INIT(32'hD555AAAA)) \trv_delay_ctr_q[1]_i_1 (.I0(trv_delay_ctr_q[1]), .I1(\trv_delay_ctr_q[3]_i_2_n_0 ), .I2(trv_delay_ctr_q[3]), .I3(trv_delay_ctr_q[2]), .I4(trv_delay_ctr_q[0]), .O(trv_delay_ctr_d[1])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'hD5AAAAAA)) \trv_delay_ctr_q[2]_i_1 (.I0(trv_delay_ctr_q[2]), .I1(\trv_delay_ctr_q[3]_i_2_n_0 ), .I2(trv_delay_ctr_q[3]), .I3(trv_delay_ctr_q[1]), .I4(trv_delay_ctr_q[0]), .O(trv_delay_ctr_d[2])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'hEAAA6AAA)) \trv_delay_ctr_q[3]_i_1 (.I0(trv_delay_ctr_q[3]), .I1(trv_delay_ctr_q[1]), .I2(trv_delay_ctr_q[0]), .I3(trv_delay_ctr_q[2]), .I4(\trv_delay_ctr_q[3]_i_2_n_0 ), .O(trv_delay_ctr_d[3])); LUT4 #( .INIT(16'h8000)) \trv_delay_ctr_q[3]_i_2 (.I0(trv_delay_ctr_q[7]), .I1(trv_delay_ctr_q[6]), .I2(trv_delay_ctr_q[5]), .I3(trv_delay_ctr_q[4]), .O(\trv_delay_ctr_q[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT5 #( .INIT(32'hB9999999)) \trv_delay_ctr_q[4]_i_1 (.I0(trv_delay_ctr_q[4]), .I1(\trv_delay_ctr_q[7]_i_3_n_0 ), .I2(trv_delay_ctr_q[7]), .I3(trv_delay_ctr_q[6]), .I4(trv_delay_ctr_q[5]), .O(trv_delay_ctr_d[4])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT5 #( .INIT(32'hBA9A9A9A)) \trv_delay_ctr_q[5]_i_1 (.I0(trv_delay_ctr_q[5]), .I1(\trv_delay_ctr_q[7]_i_3_n_0 ), .I2(trv_delay_ctr_q[4]), .I3(trv_delay_ctr_q[6]), .I4(trv_delay_ctr_q[7]), .O(trv_delay_ctr_d[5])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT5 #( .INIT(32'hAAEAAA6A)) \trv_delay_ctr_q[6]_i_1 (.I0(trv_delay_ctr_q[6]), .I1(trv_delay_ctr_q[5]), .I2(trv_delay_ctr_q[4]), .I3(\trv_delay_ctr_q[7]_i_3_n_0 ), .I4(trv_delay_ctr_q[7]), .O(trv_delay_ctr_d[6])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT5 #( .INIT(32'hFFFF0800)) \trv_delay_ctr_q[7]_i_1 (.I0(trv_delay_ctr_q[5]), .I1(trv_delay_ctr_q[4]), .I2(\trv_delay_ctr_q[7]_i_3_n_0 ), .I3(trv_delay_ctr_q[6]), .I4(trv_delay_ctr_q[7]), .O(trv_delay_ctr_d[7])); LUT3 #( .INIT(8'h1D)) \trv_delay_ctr_q[7]_i_2 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(\trv_delay_ctr_q[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT4 #( .INIT(16'h7FFF)) \trv_delay_ctr_q[7]_i_3 (.I0(trv_delay_ctr_q[2]), .I1(trv_delay_ctr_q[0]), .I2(trv_delay_ctr_q[1]), .I3(trv_delay_ctr_q[3]), .O(\trv_delay_ctr_q[7]_i_3_n_0 )); FDPE \trv_delay_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .D(trv_delay_ctr_d[0]), .PRE(\trv_delay_ctr_q[7]_i_2_n_0 ), .Q(trv_delay_ctr_q[0])); FDCE \trv_delay_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[1]), .Q(trv_delay_ctr_q[1])); FDCE \trv_delay_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[2]), .Q(trv_delay_ctr_q[2])); FDCE \trv_delay_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[3]), .Q(trv_delay_ctr_q[3])); FDCE \trv_delay_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[4]), .Q(trv_delay_ctr_q[4])); FDCE \trv_delay_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[5]), .Q(trv_delay_ctr_q[5])); FDCE \trv_delay_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[6]), .Q(trv_delay_ctr_q[6])); FDCE \trv_delay_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(trv_meas_progress_q), .CLR(\trv_delay_ctr_q[7]_i_2_n_0 ), .D(trv_delay_ctr_d[7]), .Q(trv_delay_ctr_q[7])); LUT2 #( .INIT(4'h2)) \trv_delay_shadowed[7]_i_1 (.I0(trv_meas_progress_del), .I1(trv_meas_progress_q), .O(ssp_shadow_ce)); FDCE \trv_delay_shadowed_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[0]), .Q(trv_delay[0])); FDCE \trv_delay_shadowed_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[1]), .Q(trv_delay[1])); FDCE \trv_delay_shadowed_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[2]), .Q(trv_delay[2])); FDCE \trv_delay_shadowed_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[3]), .Q(trv_delay[3])); FDCE \trv_delay_shadowed_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[4]), .Q(trv_delay[4])); FDCE \trv_delay_shadowed_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[5]), .Q(trv_delay[5])); FDCE \trv_delay_shadowed_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[6]), .Q(trv_delay[6])); FDCE \trv_delay_shadowed_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(ssp_shadow_ce), .CLR(reg_q_reg), .D(trv_delay_ctr_q[7]), .Q(Q)); FDCE trv_meas_progress_del_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg), .D(trv_meas_progress_q), .Q(trv_meas_progress_del)); LUT6 #( .INIT(64'hBFBB00000F000000)) trv_meas_progress_q_i_1 (.I0(trv_meas_progress_q_reg_0), .I1(rx_data_prev), .I2(can_tx_OBUF), .I3(tx_data_prev), .I4(tran_delay_meas), .I5(trv_meas_progress_q), .O(trv_meas_progress_q_i_1_n_0)); FDCE trv_meas_progress_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg), .D(trv_meas_progress_q_i_1_n_0), .Q(trv_meas_progress_q)); endmodule module bm_tx_data_cache (\write_pointer_q_reg[0]_0 , data_tx_delayed, clk_sys_IBUF_BUFG, \write_pointer_q_reg[0]_1 , tx_trigger_ssp, can_tx_OBUF, q_i, scan_mode_IBUF, rst_n_out_OBUF, CO, \read_pointer_q_reg[0]_0 ); output \write_pointer_q_reg[0]_0 ; output data_tx_delayed; input clk_sys_IBUF_BUFG; input \write_pointer_q_reg[0]_1 ; input tx_trigger_ssp; input can_tx_OBUF; input q_i; input scan_mode_IBUF; input rst_n_out_OBUF; input [0:0]CO; input \read_pointer_q_reg[0]_0 ; wire [0:0]CO; wire bit_err_ssp_capt_q_i_4_n_0; wire bit_err_ssp_capt_q_i_5_n_0; wire can_tx_OBUF; wire clk_sys_IBUF_BUFG; wire data_tx_delayed; wire q_i; wire \read_pointer_q[0]_i_1_n_0 ; wire \read_pointer_q[1]_i_1_n_0 ; wire \read_pointer_q[2]_i_1_n_0 ; wire [2:0]read_pointer_q_reg; wire \read_pointer_q_reg[0]_0 ; wire rst_n_out_OBUF; wire scan_mode_IBUF; wire [7:0]tx_cache_mem; wire \tx_cache_mem[0]_i_1_n_0 ; wire \tx_cache_mem[1]_i_1_n_0 ; wire \tx_cache_mem[2]_i_1_n_0 ; wire \tx_cache_mem[3]_i_1_n_0 ; wire \tx_cache_mem[4]_i_1_n_0 ; wire \tx_cache_mem[5]_i_1_n_0 ; wire \tx_cache_mem[6]_i_1_n_0 ; wire \tx_cache_mem[7]_i_1_n_0 ; wire \tx_cache_mem[7]_i_2_n_0 ; wire tx_trigger_ssp; wire \write_pointer_q[1]_i_1_n_0 ; wire \write_pointer_q[2]_i_1_n_0 ; wire [2:1]write_pointer_q_reg; wire \write_pointer_q_reg[0]_0 ; wire \write_pointer_q_reg[0]_1 ; LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) bit_err_ssp_capt_q_i_4 (.I0(tx_cache_mem[3]), .I1(tx_cache_mem[2]), .I2(read_pointer_q_reg[1]), .I3(tx_cache_mem[1]), .I4(read_pointer_q_reg[0]), .I5(tx_cache_mem[0]), .O(bit_err_ssp_capt_q_i_4_n_0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) bit_err_ssp_capt_q_i_5 (.I0(tx_cache_mem[7]), .I1(tx_cache_mem[6]), .I2(read_pointer_q_reg[1]), .I3(tx_cache_mem[5]), .I4(read_pointer_q_reg[0]), .I5(tx_cache_mem[4]), .O(bit_err_ssp_capt_q_i_5_n_0)); MUXF7 bit_err_ssp_capt_q_reg_i_3 (.I0(bit_err_ssp_capt_q_i_4_n_0), .I1(bit_err_ssp_capt_q_i_5_n_0), .O(data_tx_delayed), .S(read_pointer_q_reg[2])); LUT3 #( .INIT(8'h78)) \read_pointer_q[0]_i_1 (.I0(\read_pointer_q_reg[0]_0 ), .I1(CO), .I2(read_pointer_q_reg[0]), .O(\read_pointer_q[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT4 #( .INIT(16'h7F80)) \read_pointer_q[1]_i_1 (.I0(read_pointer_q_reg[0]), .I1(CO), .I2(\read_pointer_q_reg[0]_0 ), .I3(read_pointer_q_reg[1]), .O(\read_pointer_q[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT5 #( .INIT(32'h7FFF8000)) \read_pointer_q[2]_i_1 (.I0(read_pointer_q_reg[0]), .I1(read_pointer_q_reg[1]), .I2(CO), .I3(\read_pointer_q_reg[0]_0 ), .I4(read_pointer_q_reg[2]), .O(\read_pointer_q[2]_i_1_n_0 )); FDCE \read_pointer_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\tx_cache_mem[7]_i_2_n_0 ), .D(\read_pointer_q[0]_i_1_n_0 ), .Q(read_pointer_q_reg[0])); FDCE \read_pointer_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\tx_cache_mem[7]_i_2_n_0 ), .D(\read_pointer_q[1]_i_1_n_0 ), .Q(read_pointer_q_reg[1])); FDCE \read_pointer_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\tx_cache_mem[7]_i_2_n_0 ), .D(\read_pointer_q[2]_i_1_n_0 ), .Q(read_pointer_q_reg[2])); LUT6 #( .INIT(64'hFFFFFFFB00000008)) \tx_cache_mem[0]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .I3(\write_pointer_q_reg[0]_0 ), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[0]), .O(\tx_cache_mem[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFBFF00000800)) \tx_cache_mem[1]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .I3(\write_pointer_q_reg[0]_0 ), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[1]), .O(\tx_cache_mem[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFBFF00000800)) \tx_cache_mem[2]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(\write_pointer_q_reg[0]_0 ), .I3(write_pointer_q_reg[1]), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[2]), .O(\tx_cache_mem[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFBFFF00008000)) \tx_cache_mem[3]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .I3(\write_pointer_q_reg[0]_0 ), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[3]), .O(\tx_cache_mem[3]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFBFFFF00080000)) \tx_cache_mem[4]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .I3(\write_pointer_q_reg[0]_0 ), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[4]), .O(\tx_cache_mem[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFBFFFFFF08000000)) \tx_cache_mem[5]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .I3(\write_pointer_q_reg[0]_0 ), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[5]), .O(\tx_cache_mem[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFBFFFFFF08000000)) \tx_cache_mem[6]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(\write_pointer_q_reg[0]_0 ), .I3(write_pointer_q_reg[1]), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[6]), .O(\tx_cache_mem[6]_i_1_n_0 )); LUT6 #( .INIT(64'hBFFFFFFF80000000)) \tx_cache_mem[7]_i_1 (.I0(can_tx_OBUF), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .I3(\write_pointer_q_reg[0]_0 ), .I4(write_pointer_q_reg[2]), .I5(tx_cache_mem[7]), .O(\tx_cache_mem[7]_i_1_n_0 )); LUT3 #( .INIT(8'h1D)) \tx_cache_mem[7]_i_2 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(\tx_cache_mem[7]_i_2_n_0 )); FDPE \tx_cache_mem_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[0]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[0])); FDPE \tx_cache_mem_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[1]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[1])); FDPE \tx_cache_mem_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[2]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[2])); FDPE \tx_cache_mem_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[3]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[3])); FDPE \tx_cache_mem_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[4]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[4])); FDPE \tx_cache_mem_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[5]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[5])); FDPE \tx_cache_mem_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[6]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[6])); FDPE \tx_cache_mem_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\tx_cache_mem[7]_i_1_n_0 ), .PRE(\tx_cache_mem[7]_i_2_n_0 ), .Q(tx_cache_mem[7])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT3 #( .INIT(8'h78)) \write_pointer_q[1]_i_1 (.I0(\write_pointer_q_reg[0]_0 ), .I1(tx_trigger_ssp), .I2(write_pointer_q_reg[1]), .O(\write_pointer_q[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT4 #( .INIT(16'h7F80)) \write_pointer_q[2]_i_1 (.I0(\write_pointer_q_reg[0]_0 ), .I1(write_pointer_q_reg[1]), .I2(tx_trigger_ssp), .I3(write_pointer_q_reg[2]), .O(\write_pointer_q[2]_i_1_n_0 )); FDCE \write_pointer_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\tx_cache_mem[7]_i_2_n_0 ), .D(\write_pointer_q_reg[0]_1 ), .Q(\write_pointer_q_reg[0]_0 )); FDCE \write_pointer_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\tx_cache_mem[7]_i_2_n_0 ), .D(\write_pointer_q[1]_i_1_n_0 ), .Q(write_pointer_q_reg[1])); FDCE \write_pointer_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\tx_cache_mem[7]_i_2_n_0 ), .D(\write_pointer_q[2]_i_1_n_0 ), .Q(write_pointer_q_reg[2])); endmodule module btl_cfg_capture (mr_settings_ena_reg_reg_0, DI, Q, \tseg1_nbt_reg[7]_0 , \tseg1_nbt_reg[7]_1 , E, mr_settings_ena_reg_reg_1, \mr_ctrl_out[settings_ena] , clk_sys_IBUF_BUFG, mr_settings_ena_reg_2_reg_0, \exp_seg_length_q_reg[7]_i_2__0 , \exp_seg_length_q_reg[7]_i_2 , \exp_seg_length_q_reg[0] , \exp_seg_length_q_reg[0]_0 , \exp_seg_length_q_reg[0]_1 , mr_btr_prop, \mr_ctrl_out[btr_ph1] , \tseg1_dbt_reg[0]_0 , \mr_ctrl_out[btr_fd_prop_fd] , \mr_ctrl_out[btr_fd_ph1_fd] , D); output mr_settings_ena_reg_reg_0; output [1:0]DI; output [6:0]Q; output [1:0]\tseg1_nbt_reg[7]_0 ; output [7:0]\tseg1_nbt_reg[7]_1 ; output [0:0]E; output mr_settings_ena_reg_reg_1; input \mr_ctrl_out[settings_ena] ; input clk_sys_IBUF_BUFG; input mr_settings_ena_reg_2_reg_0; input \exp_seg_length_q_reg[7]_i_2__0 ; input \exp_seg_length_q_reg[7]_i_2 ; input \exp_seg_length_q_reg[0] ; input \exp_seg_length_q_reg[0]_0 ; input \exp_seg_length_q_reg[0]_1 ; input [6:0]mr_btr_prop; input [5:0]\mr_ctrl_out[btr_ph1] ; input [0:0]\tseg1_dbt_reg[0]_0 ; input [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; input [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; input [0:0]D; wire [0:0]D; wire [1:0]DI; wire [0:0]E; wire [6:0]Q; wire clk_sys_IBUF_BUFG; wire \exp_seg_length_q_reg[0] ; wire \exp_seg_length_q_reg[0]_0 ; wire \exp_seg_length_q_reg[0]_1 ; wire \exp_seg_length_q_reg[7]_i_2 ; wire \exp_seg_length_q_reg[7]_i_2__0 ; wire [6:0]mr_btr_prop; wire [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; wire [5:0]\mr_ctrl_out[btr_ph1] ; wire \mr_ctrl_out[settings_ena] ; wire mr_settings_ena_reg_2; wire mr_settings_ena_reg_2_reg_0; wire mr_settings_ena_reg_reg_0; wire mr_settings_ena_reg_reg_1; wire \tseg1_dbt[6]_i_2_n_0 ; wire [6:1]tseg1_dbt_d; wire [0:0]\tseg1_dbt_reg[0]_0 ; wire \tseg1_nbt[3]_i_2_n_0 ; wire \tseg1_nbt[3]_i_3_n_0 ; wire \tseg1_nbt[3]_i_4_n_0 ; wire \tseg1_nbt[3]_i_5_n_0 ; wire \tseg1_nbt[7]_i_3_n_0 ; wire \tseg1_nbt[7]_i_4_n_0 ; wire [7:0]tseg1_nbt_d; wire \tseg1_nbt_reg[3]_i_1_n_0 ; wire [1:0]\tseg1_nbt_reg[7]_0 ; wire [7:0]\tseg1_nbt_reg[7]_1 ; wire [2:0]\NLW_tseg1_nbt_reg[3]_i_1_CO_UNCONNECTED ; wire [2:0]\NLW_tseg1_nbt_reg[7]_i_2_CO_UNCONNECTED ; wire [3:3]\NLW_tseg1_nbt_reg[7]_i_2_O_UNCONNECTED ; LUT2 #( .INIT(4'h2)) \exp_seg_length_q[7]_i_4 (.I0(Q[6]), .I1(\exp_seg_length_q_reg[7]_i_2__0 ), .O(DI[1])); LUT2 #( .INIT(4'h2)) \exp_seg_length_q[7]_i_4__0 (.I0(\tseg1_nbt_reg[7]_1 [7]), .I1(\exp_seg_length_q_reg[7]_i_2 ), .O(\tseg1_nbt_reg[7]_0 [1])); LUT2 #( .INIT(4'h2)) \exp_seg_length_q[7]_i_5 (.I0(Q[5]), .I1(\exp_seg_length_q_reg[7]_i_2__0 ), .O(DI[0])); LUT2 #( .INIT(4'h2)) \exp_seg_length_q[7]_i_5__0 (.I0(\tseg1_nbt_reg[7]_1 [6]), .I1(\exp_seg_length_q_reg[7]_i_2 ), .O(\tseg1_nbt_reg[7]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT5 #( .INIT(32'hEEFEFFFF)) \exp_seg_length_q[8]_i_1 (.I0(\exp_seg_length_q_reg[0] ), .I1(\exp_seg_length_q_reg[0]_0 ), .I2(mr_settings_ena_reg_reg_0), .I3(mr_settings_ena_reg_2), .I4(\exp_seg_length_q_reg[0]_1 ), .O(E)); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'h2)) \exp_seg_length_q[8]_i_11 (.I0(mr_settings_ena_reg_reg_0), .I1(mr_settings_ena_reg_2), .O(mr_settings_ena_reg_reg_1)); FDCE mr_settings_ena_reg_2_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(mr_settings_ena_reg_2_reg_0), .D(mr_settings_ena_reg_reg_0), .Q(mr_settings_ena_reg_2)); FDCE mr_settings_ena_reg_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(mr_settings_ena_reg_2_reg_0), .D(\mr_ctrl_out[settings_ena] ), .Q(mr_settings_ena_reg_reg_0)); LUT4 #( .INIT(16'hE11E)) \tseg1_dbt[1]_i_1 (.I0(\mr_ctrl_out[btr_fd_ph1_fd] [0]), .I1(\mr_ctrl_out[btr_fd_prop_fd] [0]), .I2(\mr_ctrl_out[btr_fd_ph1_fd] [1]), .I3(\mr_ctrl_out[btr_fd_prop_fd] [1]), .O(tseg1_dbt_d[1])); LUT6 #( .INIT(64'hFEE0011F011FFEE0)) \tseg1_dbt[2]_i_1 (.I0(\mr_ctrl_out[btr_fd_prop_fd] [0]), .I1(\mr_ctrl_out[btr_fd_ph1_fd] [0]), .I2(\mr_ctrl_out[btr_fd_prop_fd] [1]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [1]), .I4(\mr_ctrl_out[btr_fd_ph1_fd] [2]), .I5(\mr_ctrl_out[btr_fd_prop_fd] [2]), .O(tseg1_dbt_d[2])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT3 #( .INIT(8'h96)) \tseg1_dbt[3]_i_1 (.I0(\tseg1_dbt[6]_i_2_n_0 ), .I1(\mr_ctrl_out[btr_fd_ph1_fd] [3]), .I2(\mr_ctrl_out[btr_fd_prop_fd] [3]), .O(tseg1_dbt_d[3])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT5 #( .INIT(32'hE81717E8)) \tseg1_dbt[4]_i_1 (.I0(\tseg1_dbt[6]_i_2_n_0 ), .I1(\mr_ctrl_out[btr_fd_prop_fd] [3]), .I2(\mr_ctrl_out[btr_fd_ph1_fd] [3]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [4]), .I4(\mr_ctrl_out[btr_fd_prop_fd] [4]), .O(tseg1_dbt_d[4])); LUT6 #( .INIT(64'h001717FFFFE8E800)) \tseg1_dbt[5]_i_1 (.I0(\mr_ctrl_out[btr_fd_ph1_fd] [3]), .I1(\mr_ctrl_out[btr_fd_prop_fd] [3]), .I2(\tseg1_dbt[6]_i_2_n_0 ), .I3(\mr_ctrl_out[btr_fd_prop_fd] [4]), .I4(\mr_ctrl_out[btr_fd_ph1_fd] [4]), .I5(\mr_ctrl_out[btr_fd_prop_fd] [5]), .O(tseg1_dbt_d[5])); LUT6 #( .INIT(64'hAAAAA880A8800000)) \tseg1_dbt[6]_i_1 (.I0(\mr_ctrl_out[btr_fd_prop_fd] [5]), .I1(\mr_ctrl_out[btr_fd_ph1_fd] [3]), .I2(\mr_ctrl_out[btr_fd_prop_fd] [3]), .I3(\tseg1_dbt[6]_i_2_n_0 ), .I4(\mr_ctrl_out[btr_fd_prop_fd] [4]), .I5(\mr_ctrl_out[btr_fd_ph1_fd] [4]), .O(tseg1_dbt_d[6])); LUT6 #( .INIT(64'hEEEEEEE8EEE88888)) \tseg1_dbt[6]_i_2 (.I0(\mr_ctrl_out[btr_fd_ph1_fd] [2]), .I1(\mr_ctrl_out[btr_fd_prop_fd] [2]), .I2(\mr_ctrl_out[btr_fd_prop_fd] [0]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [0]), .I4(\mr_ctrl_out[btr_fd_prop_fd] [1]), .I5(\mr_ctrl_out[btr_fd_ph1_fd] [1]), .O(\tseg1_dbt[6]_i_2_n_0 )); FDPE \tseg1_dbt_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .D(D), .PRE(mr_settings_ena_reg_2_reg_0), .Q(Q[0])); FDPE \tseg1_dbt_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .D(tseg1_dbt_d[1]), .PRE(mr_settings_ena_reg_2_reg_0), .Q(Q[1])); FDPE \tseg1_dbt_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .D(tseg1_dbt_d[2]), .PRE(mr_settings_ena_reg_2_reg_0), .Q(Q[2])); FDCE \tseg1_dbt_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_dbt_d[3]), .Q(Q[3])); FDCE \tseg1_dbt_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_dbt_d[4]), .Q(Q[4])); FDCE \tseg1_dbt_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_dbt_d[5]), .Q(Q[5])); FDCE \tseg1_dbt_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_dbt_d[6]), .Q(Q[6])); LUT2 #( .INIT(4'h6)) \tseg1_nbt[3]_i_2 (.I0(mr_btr_prop[3]), .I1(\mr_ctrl_out[btr_ph1] [3]), .O(\tseg1_nbt[3]_i_2_n_0 )); LUT2 #( .INIT(4'h6)) \tseg1_nbt[3]_i_3 (.I0(mr_btr_prop[2]), .I1(\mr_ctrl_out[btr_ph1] [2]), .O(\tseg1_nbt[3]_i_3_n_0 )); LUT2 #( .INIT(4'h6)) \tseg1_nbt[3]_i_4 (.I0(mr_btr_prop[1]), .I1(\mr_ctrl_out[btr_ph1] [1]), .O(\tseg1_nbt[3]_i_4_n_0 )); LUT2 #( .INIT(4'h6)) \tseg1_nbt[3]_i_5 (.I0(mr_btr_prop[0]), .I1(\mr_ctrl_out[btr_ph1] [0]), .O(\tseg1_nbt[3]_i_5_n_0 )); LUT2 #( .INIT(4'h6)) \tseg1_nbt[7]_i_3 (.I0(mr_btr_prop[5]), .I1(\mr_ctrl_out[btr_ph1] [5]), .O(\tseg1_nbt[7]_i_3_n_0 )); LUT2 #( .INIT(4'h6)) \tseg1_nbt[7]_i_4 (.I0(mr_btr_prop[4]), .I1(\mr_ctrl_out[btr_ph1] [4]), .O(\tseg1_nbt[7]_i_4_n_0 )); FDPE \tseg1_nbt_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .D(tseg1_nbt_d[0]), .PRE(mr_settings_ena_reg_2_reg_0), .Q(\tseg1_nbt_reg[7]_1 [0])); FDCE \tseg1_nbt_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_nbt_d[1]), .Q(\tseg1_nbt_reg[7]_1 [1])); FDCE \tseg1_nbt_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_nbt_d[2]), .Q(\tseg1_nbt_reg[7]_1 [2])); FDPE \tseg1_nbt_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .D(tseg1_nbt_d[3]), .PRE(mr_settings_ena_reg_2_reg_0), .Q(\tseg1_nbt_reg[7]_1 [3])); CARRY4 \tseg1_nbt_reg[3]_i_1 (.CI(1'b0), .CO({\tseg1_nbt_reg[3]_i_1_n_0 ,\NLW_tseg1_nbt_reg[3]_i_1_CO_UNCONNECTED [2:0]}), .CYINIT(1'b1), .DI(mr_btr_prop[3:0]), .O(tseg1_nbt_d[3:0]), .S({\tseg1_nbt[3]_i_2_n_0 ,\tseg1_nbt[3]_i_3_n_0 ,\tseg1_nbt[3]_i_4_n_0 ,\tseg1_nbt[3]_i_5_n_0 })); FDCE \tseg1_nbt_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_nbt_d[4]), .Q(\tseg1_nbt_reg[7]_1 [4])); FDCE \tseg1_nbt_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_nbt_d[5]), .Q(\tseg1_nbt_reg[7]_1 [5])); FDCE \tseg1_nbt_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_nbt_d[6]), .Q(\tseg1_nbt_reg[7]_1 [6])); FDCE \tseg1_nbt_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\tseg1_dbt_reg[0]_0 ), .CLR(mr_settings_ena_reg_2_reg_0), .D(tseg1_nbt_d[7]), .Q(\tseg1_nbt_reg[7]_1 [7])); CARRY4 \tseg1_nbt_reg[7]_i_2 (.CI(\tseg1_nbt_reg[3]_i_1_n_0 ), .CO({tseg1_nbt_d[7],\NLW_tseg1_nbt_reg[7]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,mr_btr_prop[5:4]}), .O({\NLW_tseg1_nbt_reg[7]_i_2_O_UNCONNECTED [3],tseg1_nbt_d[6:4]}), .S({1'b1,mr_btr_prop[6],\tseg1_nbt[7]_i_3_n_0 ,\tseg1_nbt[7]_i_4_n_0 })); endmodule module btl_counters (D, O, Q, \tq_counter_q_reg[7]_0 , DI, S, \segm_counter_q_reg[1]_0 , \segm_counter_q_reg[7]_0 , \g_bit[1].reg_value_r_reg[1] , \segm_counter_q_reg[7]_1 , \g_bit[2].reg_value_r_reg[2] , \g_bit[3].reg_value_r_reg[3] , \g_bit[4].reg_value_r_reg[4] , \segm_counter_q_reg[5]_0 , \FSM_onehot_current_state_reg[2] , \segm_counter_q_reg[0]_0 , \exp_seg_length_q_reg[8] , \tq_counter_q_reg[7]_1 , \tq_counter_q_reg[7]_2 , \tq_counter_q_reg[7]_3 , neg_phase_err, \mr_ctrl_out[btr_sjw] , \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 , exit_segm_regular_tseg11_carry, CO, \exp_seg_length_q_reg[7] , \exp_seg_length_q_reg[7]_0 , \exp_seg_length_q_reg[8]_0 , \exp_seg_length_q[3]_i_10 , \exp_seg_length_q[8]_i_5 , \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 , \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_1 , \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_2 , \exp_seg_length_q[8]_i_5_0 , E, clk_sys_IBUF_BUFG, \segm_counter_q_reg[0]_1 , \segm_counter_q_reg[0]_2 , \tq_counter_q_reg[0]_0 ); output [0:0]D; output [3:0]O; output [7:0]Q; output [7:0]\tq_counter_q_reg[7]_0 ; output [1:0]DI; output [0:0]S; output [0:0]\segm_counter_q_reg[1]_0 ; output [1:0]\segm_counter_q_reg[7]_0 ; output \g_bit[1].reg_value_r_reg[1] ; output \segm_counter_q_reg[7]_1 ; output \g_bit[2].reg_value_r_reg[2] ; output \g_bit[3].reg_value_r_reg[3] ; output \g_bit[4].reg_value_r_reg[4] ; output \segm_counter_q_reg[5]_0 ; output \FSM_onehot_current_state_reg[2] ; output [0:0]\segm_counter_q_reg[0]_0 ; input \exp_seg_length_q_reg[8] ; input \tq_counter_q_reg[7]_1 ; input \tq_counter_q_reg[7]_2 ; input \tq_counter_q_reg[7]_3 ; input [3:0]neg_phase_err; input [4:0]\mr_ctrl_out[btr_sjw] ; input \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ; input [1:0]exit_segm_regular_tseg11_carry; input [0:0]CO; input [3:0]\exp_seg_length_q_reg[7] ; input [3:0]\exp_seg_length_q_reg[7]_0 ; input [0:0]\exp_seg_length_q_reg[8]_0 ; input \exp_seg_length_q[3]_i_10 ; input [0:0]\exp_seg_length_q[8]_i_5 ; input \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ; input \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_1 ; input \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_2 ; input \exp_seg_length_q[8]_i_5_0 ; input [0:0]E; input clk_sys_IBUF_BUFG; input \segm_counter_q_reg[0]_1 ; input [0:0]\segm_counter_q_reg[0]_2 ; input [0:0]\tq_counter_q_reg[0]_0 ; wire [0:0]CO; wire [0:0]D; wire [1:0]DI; wire [0:0]E; wire \FSM_onehot_current_state_reg[2] ; wire [3:0]O; wire [7:0]Q; wire [0:0]S; wire clk_sys_IBUF_BUFG; wire [1:0]exit_segm_regular_tseg11_carry; wire \exp_seg_length_q[3]_i_10 ; wire [0:0]\exp_seg_length_q[8]_i_5 ; wire \exp_seg_length_q[8]_i_5_0 ; wire [3:0]\exp_seg_length_q_reg[7] ; wire [3:0]\exp_seg_length_q_reg[7]_0 ; wire \exp_seg_length_q_reg[7]_i_2_n_0 ; wire \exp_seg_length_q_reg[8] ; wire [0:0]\exp_seg_length_q_reg[8]_0 ; wire \g_bit[1].reg_value_r_reg[1] ; wire \g_bit[2].reg_value_r_reg[2] ; wire \g_bit[3].reg_value_r_reg[3] ; wire \g_bit[4].reg_value_r_reg[4] ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_1 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_2 ; wire [4:0]\mr_ctrl_out[btr_sjw] ; wire [3:0]neg_phase_err; wire \segm_counter_q[1]_i_1_n_0 ; wire \segm_counter_q[2]_i_1_n_0 ; wire \segm_counter_q[3]_i_1_n_0 ; wire \segm_counter_q[4]_i_1_n_0 ; wire \segm_counter_q[4]_i_2__0_n_0 ; wire \segm_counter_q[5]_i_1_n_0 ; wire \segm_counter_q[5]_i_2_n_0 ; wire \segm_counter_q[6]_i_1_n_0 ; wire \segm_counter_q[7]_i_2_n_0 ; wire \segm_counter_q[7]_i_5_n_0 ; wire [0:0]\segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire [0:0]\segm_counter_q_reg[0]_2 ; wire [0:0]\segm_counter_q_reg[1]_0 ; wire \segm_counter_q_reg[5]_0 ; wire [1:0]\segm_counter_q_reg[7]_0 ; wire \segm_counter_q_reg[7]_1 ; wire [8:8]sync_segm_length; wire \test_probe[tx_trigger]_INST_0_i_14_n_0 ; wire [7:0]tq_counter_d; wire \tq_counter_q[3]_i_2_n_0 ; wire \tq_counter_q[4]_i_2_n_0 ; wire \tq_counter_q[5]_i_2_n_0 ; wire \tq_counter_q[7]_i_3__0_n_0 ; wire [0:0]\tq_counter_q_reg[0]_0 ; wire [7:0]\tq_counter_q_reg[7]_0 ; wire \tq_counter_q_reg[7]_1 ; wire \tq_counter_q_reg[7]_2 ; wire \tq_counter_q_reg[7]_3 ; wire [2:0]\NLW_exp_seg_length_q_reg[7]_i_2_CO_UNCONNECTED ; wire [3:0]\NLW_exp_seg_length_q_reg[8]_i_4_CO_UNCONNECTED ; wire [3:1]\NLW_exp_seg_length_q_reg[8]_i_4_O_UNCONNECTED ; LUT4 #( .INIT(16'hB828)) exit_segm_regular_tseg11_carry_i_4 (.I0(Q[1]), .I1(exit_segm_regular_tseg11_carry[1]), .I2(exit_segm_regular_tseg11_carry[0]), .I3(Q[0]), .O(\segm_counter_q_reg[1]_0 )); LUT4 #( .INIT(16'hFFE2)) \exp_seg_length_q[3]_i_11 (.I0(Q[0]), .I1(\exp_seg_length_q[8]_i_5 ), .I2(\mr_ctrl_out[btr_sjw] [0]), .I3(\segm_counter_q_reg[7]_1 ), .O(\segm_counter_q_reg[0]_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[3]_i_12__0 (.I0(\exp_seg_length_q[3]_i_10 ), .I1(\segm_counter_q_reg[7]_1 ), .I2(\mr_ctrl_out[btr_sjw] [3]), .I3(\exp_seg_length_q[8]_i_5 ), .I4(Q[3]), .O(\g_bit[3].reg_value_r_reg[3] )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[3]_i_13__0 (.I0(\exp_seg_length_q[3]_i_10 ), .I1(\segm_counter_q_reg[7]_1 ), .I2(\mr_ctrl_out[btr_sjw] [2]), .I3(\exp_seg_length_q[8]_i_5 ), .I4(Q[2]), .O(\g_bit[2].reg_value_r_reg[2] )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[3]_i_14__0 (.I0(\exp_seg_length_q[3]_i_10 ), .I1(\segm_counter_q_reg[7]_1 ), .I2(\mr_ctrl_out[btr_sjw] [1]), .I3(\exp_seg_length_q[8]_i_5 ), .I4(Q[1]), .O(\g_bit[1].reg_value_r_reg[1] )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'hAA9A)) \exp_seg_length_q[7]_i_12__0 (.I0(\exp_seg_length_q[3]_i_10 ), .I1(\segm_counter_q_reg[7]_1 ), .I2(Q[5]), .I3(\exp_seg_length_q[8]_i_5 ), .O(\segm_counter_q_reg[5]_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[7]_i_13__0 (.I0(\exp_seg_length_q[3]_i_10 ), .I1(\segm_counter_q_reg[7]_1 ), .I2(\mr_ctrl_out[btr_sjw] [4]), .I3(\exp_seg_length_q[8]_i_5 ), .I4(Q[4]), .O(\g_bit[4].reg_value_r_reg[4] )); LUT6 #( .INIT(64'hFF00FFFEFF00FF00)) \exp_seg_length_q[8]_i_12 (.I0(\test_probe[tx_trigger]_INST_0_i_14_n_0 ), .I1(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ), .I2(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_1 ), .I3(\tq_counter_q_reg[7]_2 ), .I4(\exp_seg_length_q[8]_i_5 ), .I5(\exp_seg_length_q[8]_i_5_0 ), .O(\segm_counter_q_reg[7]_1 )); LUT2 #( .INIT(4'h8)) \exp_seg_length_q[8]_i_2 (.I0(sync_segm_length), .I1(\exp_seg_length_q_reg[8] ), .O(D)); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 \exp_seg_length_q_reg[7]_i_2 (.CI(CO), .CO({\exp_seg_length_q_reg[7]_i_2_n_0 ,\NLW_exp_seg_length_q_reg[7]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI(\exp_seg_length_q_reg[7] ), .O(O), .S(\exp_seg_length_q_reg[7]_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 \exp_seg_length_q_reg[8]_i_4 (.CI(\exp_seg_length_q_reg[7]_i_2_n_0 ), .CO(\NLW_exp_seg_length_q_reg[8]_i_4_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_exp_seg_length_q_reg[8]_i_4_O_UNCONNECTED [3:1],sync_segm_length}), .S({1'b0,1'b0,1'b0,\exp_seg_length_q_reg[8]_0 })); LUT1 #( .INIT(2'h1)) i__carry_i_14 (.I0(Q[7]), .O(\segm_counter_q_reg[7]_0 [1])); LUT1 #( .INIT(2'h1)) i__carry_i_15 (.I0(Q[6]), .O(\segm_counter_q_reg[7]_0 [0])); LUT5 #( .INIT(32'hFFFACCFA)) i__carry_i_1__3 (.I0(Q[7]), .I1(neg_phase_err[3]), .I2(Q[6]), .I3(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ), .I4(neg_phase_err[2]), .O(DI[1])); LUT6 #( .INIT(64'hCFCCAFAFCFCCAAAA)) i__carry_i_2__4 (.I0(Q[5]), .I1(neg_phase_err[1]), .I2(\mr_ctrl_out[btr_sjw] [4]), .I3(neg_phase_err[0]), .I4(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ), .I5(Q[4]), .O(DI[0])); LUT5 #( .INIT(32'h00440347)) i__carry_i_5__3 (.I0(neg_phase_err[2]), .I1(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ), .I2(Q[6]), .I3(neg_phase_err[3]), .I4(Q[7]), .O(S)); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0110)) \segm_counter_q[1]_i_1 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(Q[1]), .I3(Q[0]), .O(\segm_counter_q[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT5 #( .INIT(32'h01111000)) \segm_counter_q[2]_i_1 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .O(\segm_counter_q[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0111111110000000)) \segm_counter_q[3]_i_1 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(Q[3]), .O(\segm_counter_q[3]_i_1_n_0 )); LUT4 #( .INIT(16'h0110)) \segm_counter_q[4]_i_1 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[4]_i_2__0_n_0 ), .I3(Q[4]), .O(\segm_counter_q[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT4 #( .INIT(16'h8000)) \segm_counter_q[4]_i_2__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(\segm_counter_q[4]_i_2__0_n_0 )); LUT4 #( .INIT(16'h0110)) \segm_counter_q[5]_i_1 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[5]_i_2_n_0 ), .I3(Q[5]), .O(\segm_counter_q[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'h80000000)) \segm_counter_q[5]_i_2 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .I4(Q[4]), .O(\segm_counter_q[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT4 #( .INIT(16'h0110)) \segm_counter_q[6]_i_1 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[7]_i_5_n_0 ), .I3(Q[6]), .O(\segm_counter_q[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'h01111000)) \segm_counter_q[7]_i_2 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[7]_i_5_n_0 ), .I3(Q[6]), .I4(Q[7]), .O(\segm_counter_q[7]_i_2_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \segm_counter_q[7]_i_5 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .I5(Q[5]), .O(\segm_counter_q[7]_i_5_n_0 )); FDCE \segm_counter_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q_reg[0]_2 ), .Q(Q[0])); FDCE \segm_counter_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[1]_i_1_n_0 ), .Q(Q[1])); FDCE \segm_counter_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[2]_i_1_n_0 ), .Q(Q[2])); FDCE \segm_counter_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[3]_i_1_n_0 ), .Q(Q[3])); FDCE \segm_counter_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[4]_i_1_n_0 ), .Q(Q[4])); FDCE \segm_counter_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[5]_i_1_n_0 ), .Q(Q[5])); FDCE \segm_counter_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[6]_i_1_n_0 ), .Q(Q[6])); FDCE \segm_counter_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\segm_counter_q_reg[0]_1 ), .D(\segm_counter_q[7]_i_2_n_0 ), .Q(Q[7])); LUT5 #( .INIT(32'hFFFACCFA)) \test_probe[tx_trigger]_INST_0_i_14 (.I0(Q[7]), .I1(neg_phase_err[3]), .I2(Q[6]), .I3(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ), .I4(neg_phase_err[2]), .O(\test_probe[tx_trigger]_INST_0_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFE00FFFFFFFF)) \test_probe[tx_trigger]_INST_0_i_7 (.I0(\test_probe[tx_trigger]_INST_0_i_14_n_0 ), .I1(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ), .I2(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_1 ), .I3(\exp_seg_length_q[8]_i_5 ), .I4(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_2 ), .I5(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ), .O(\FSM_onehot_current_state_reg[2] )); LUT4 #( .INIT(16'hFDFF)) \tq_counter_q[0]_i_1__0 (.I0(\tq_counter_q_reg[7]_0 [0]), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q_reg[7]_3 ), .O(tq_counter_d[0])); LUT5 #( .INIT(32'h00101000)) \tq_counter_q[1]_i_1__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q_reg[7]_0 [1]), .I4(\tq_counter_q_reg[7]_0 [0]), .O(tq_counter_d[1])); LUT6 #( .INIT(64'h0010101010000000)) \tq_counter_q[2]_i_1__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q_reg[7]_0 [0]), .I4(\tq_counter_q_reg[7]_0 [1]), .I5(\tq_counter_q_reg[7]_0 [2]), .O(tq_counter_d[2])); LUT5 #( .INIT(32'h00101000)) \tq_counter_q[3]_i_1__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q[3]_i_2_n_0 ), .I4(\tq_counter_q_reg[7]_0 [3]), .O(tq_counter_d[3])); LUT3 #( .INIT(8'h80)) \tq_counter_q[3]_i_2 (.I0(\tq_counter_q_reg[7]_0 [1]), .I1(\tq_counter_q_reg[7]_0 [0]), .I2(\tq_counter_q_reg[7]_0 [2]), .O(\tq_counter_q[3]_i_2_n_0 )); LUT5 #( .INIT(32'h00101000)) \tq_counter_q[4]_i_1__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q[4]_i_2_n_0 ), .I4(\tq_counter_q_reg[7]_0 [4]), .O(tq_counter_d[4])); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h8000)) \tq_counter_q[4]_i_2 (.I0(\tq_counter_q_reg[7]_0 [2]), .I1(\tq_counter_q_reg[7]_0 [0]), .I2(\tq_counter_q_reg[7]_0 [1]), .I3(\tq_counter_q_reg[7]_0 [3]), .O(\tq_counter_q[4]_i_2_n_0 )); LUT5 #( .INIT(32'h00101000)) \tq_counter_q[5]_i_1__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q[5]_i_2_n_0 ), .I4(\tq_counter_q_reg[7]_0 [5]), .O(tq_counter_d[5])); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT5 #( .INIT(32'h80000000)) \tq_counter_q[5]_i_2 (.I0(\tq_counter_q_reg[7]_0 [3]), .I1(\tq_counter_q_reg[7]_0 [1]), .I2(\tq_counter_q_reg[7]_0 [0]), .I3(\tq_counter_q_reg[7]_0 [2]), .I4(\tq_counter_q_reg[7]_0 [4]), .O(\tq_counter_q[5]_i_2_n_0 )); LUT5 #( .INIT(32'h00101000)) \tq_counter_q[6]_i_1__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q[7]_i_3__0_n_0 ), .I4(\tq_counter_q_reg[7]_0 [6]), .O(tq_counter_d[6])); LUT6 #( .INIT(64'h0010101010000000)) \tq_counter_q[7]_i_2__0 (.I0(\tq_counter_q_reg[7]_2 ), .I1(\tq_counter_q_reg[7]_1 ), .I2(\tq_counter_q_reg[7]_3 ), .I3(\tq_counter_q_reg[7]_0 [6]), .I4(\tq_counter_q[7]_i_3__0_n_0 ), .I5(\tq_counter_q_reg[7]_0 [7]), .O(tq_counter_d[7])); LUT6 #( .INIT(64'h8000000000000000)) \tq_counter_q[7]_i_3__0 (.I0(\tq_counter_q_reg[7]_0 [4]), .I1(\tq_counter_q_reg[7]_0 [2]), .I2(\tq_counter_q_reg[7]_0 [0]), .I3(\tq_counter_q_reg[7]_0 [1]), .I4(\tq_counter_q_reg[7]_0 [3]), .I5(\tq_counter_q_reg[7]_0 [5]), .O(\tq_counter_q[7]_i_3__0_n_0 )); FDPE \tq_counter_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .D(tq_counter_d[0]), .PRE(\segm_counter_q_reg[0]_1 ), .Q(\tq_counter_q_reg[7]_0 [0])); FDCE \tq_counter_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[1]), .Q(\tq_counter_q_reg[7]_0 [1])); FDCE \tq_counter_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[2]), .Q(\tq_counter_q_reg[7]_0 [2])); FDCE \tq_counter_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[3]), .Q(\tq_counter_q_reg[7]_0 [3])); FDCE \tq_counter_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[4]), .Q(\tq_counter_q_reg[7]_0 [4])); FDCE \tq_counter_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[5]), .Q(\tq_counter_q_reg[7]_0 [5])); FDCE \tq_counter_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[6]), .Q(\tq_counter_q_reg[7]_0 [6])); FDCE \tq_counter_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(tq_counter_d[7]), .Q(\tq_counter_q_reg[7]_0 [7])); endmodule (* ORIG_REF_NAME = "btl_counters" *) module btl_counters__parameterized0 (Q, \tq_counter_q_reg[7]_0 , S, DI, \segm_counter_q_reg[6]_0 , D, \tq_counter_q_reg[7]_1 , \tq_counter_q_reg[7]_2 , \tq_counter_q_reg[7]_3 , \exp_seg_length_d9_inferred__0/i__carry , O, exit_segm_regular_tseg11_carry, \segm_counter_q_reg[0]_0 , clk_sys_IBUF_BUFG, \segm_counter_q_reg[0]_1 , \tq_counter_q_reg[0]_0 ); output [6:0]Q; output [7:0]\tq_counter_q_reg[7]_0 ; output [0:0]S; output [0:0]DI; output [1:0]\segm_counter_q_reg[6]_0 ; input [0:0]D; input \tq_counter_q_reg[7]_1 ; input \tq_counter_q_reg[7]_2 ; input \tq_counter_q_reg[7]_3 ; input \exp_seg_length_d9_inferred__0/i__carry ; input [0:0]O; input [1:0]exit_segm_regular_tseg11_carry; input [0:0]\segm_counter_q_reg[0]_0 ; input clk_sys_IBUF_BUFG; input \segm_counter_q_reg[0]_1 ; input [0:0]\tq_counter_q_reg[0]_0 ; wire [0:0]D; wire [0:0]DI; wire [0:0]O; wire [6:0]Q; wire [0:0]S; wire clk_sys_IBUF_BUFG; wire [1:0]exit_segm_regular_tseg11_carry; wire \exp_seg_length_d9_inferred__0/i__carry ; wire [6:1]segm_counter_d; wire \segm_counter_q[4]_i_2_n_0 ; wire \segm_counter_q[6]_i_4_n_0 ; wire [0:0]\segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire [1:0]\segm_counter_q_reg[6]_0 ; wire \tq_counter_q[0]_i_1_n_0 ; wire \tq_counter_q[1]_i_1_n_0 ; wire \tq_counter_q[2]_i_1_n_0 ; wire \tq_counter_q[3]_i_1_n_0 ; wire \tq_counter_q[3]_i_2__0_n_0 ; wire \tq_counter_q[4]_i_1_n_0 ; wire \tq_counter_q[4]_i_2__0_n_0 ; wire \tq_counter_q[5]_i_1_n_0 ; wire \tq_counter_q[5]_i_2__0_n_0 ; wire \tq_counter_q[6]_i_1_n_0 ; wire \tq_counter_q[7]_i_2_n_0 ; wire \tq_counter_q[7]_i_5_n_0 ; wire [0:0]\tq_counter_q_reg[0]_0 ; wire [7:0]\tq_counter_q_reg[7]_0 ; wire \tq_counter_q_reg[7]_1 ; wire \tq_counter_q_reg[7]_2 ; wire \tq_counter_q_reg[7]_3 ; LUT4 #( .INIT(16'hB828)) exit_segm_regular_tseg11_carry_i_4__0 (.I0(Q[1]), .I1(exit_segm_regular_tseg11_carry[1]), .I2(exit_segm_regular_tseg11_carry[0]), .I3(Q[0]), .O(DI)); LUT1 #( .INIT(2'h1)) i__carry_i_13__0 (.I0(Q[6]), .O(\segm_counter_q_reg[6]_0 [1])); LUT1 #( .INIT(2'h1)) i__carry_i_14__0 (.I0(Q[5]), .O(\segm_counter_q_reg[6]_0 [0])); LUT3 #( .INIT(8'h1D)) i__carry_i_5__2 (.I0(Q[6]), .I1(\exp_seg_length_d9_inferred__0/i__carry ), .I2(O), .O(S)); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT4 #( .INIT(16'h0110)) \segm_counter_q[1]_i_1__0 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(Q[1]), .I3(Q[0]), .O(segm_counter_d[1])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( .INIT(32'h01111000)) \segm_counter_q[2]_i_1__0 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .O(segm_counter_d[2])); LUT6 #( .INIT(64'h0111111110000000)) \segm_counter_q[3]_i_1__0 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(Q[3]), .O(segm_counter_d[3])); LUT4 #( .INIT(16'h0110)) \segm_counter_q[4]_i_1__0 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[4]_i_2_n_0 ), .I3(Q[4]), .O(segm_counter_d[4])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT4 #( .INIT(16'h8000)) \segm_counter_q[4]_i_2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .O(\segm_counter_q[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT4 #( .INIT(16'h0110)) \segm_counter_q[5]_i_1__0 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[6]_i_4_n_0 ), .I3(Q[5]), .O(segm_counter_d[5])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT5 #( .INIT(32'h01111000)) \segm_counter_q[6]_i_2 (.I0(\tq_counter_q_reg[7]_1 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\segm_counter_q[6]_i_4_n_0 ), .I3(Q[5]), .I4(Q[6]), .O(segm_counter_d[6])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT5 #( .INIT(32'h80000000)) \segm_counter_q[6]_i_4 (.I0(Q[3]), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .I4(Q[4]), .O(\segm_counter_q[6]_i_4_n_0 )); FDCE \segm_counter_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(D), .Q(Q[0])); FDCE \segm_counter_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(segm_counter_d[1]), .Q(Q[1])); FDCE \segm_counter_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(segm_counter_d[2]), .Q(Q[2])); FDCE \segm_counter_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(segm_counter_d[3]), .Q(Q[3])); FDCE \segm_counter_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(segm_counter_d[4]), .Q(Q[4])); FDCE \segm_counter_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(segm_counter_d[5]), .Q(Q[5])); FDCE \segm_counter_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\segm_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(segm_counter_d[6]), .Q(Q[6])); LUT4 #( .INIT(16'hFFFD)) \tq_counter_q[0]_i_1 (.I0(\tq_counter_q_reg[7]_0 [0]), .I1(\tq_counter_q_reg[7]_3 ), .I2(\tq_counter_q_reg[7]_2 ), .I3(\tq_counter_q_reg[7]_1 ), .O(\tq_counter_q[0]_i_1_n_0 )); LUT5 #( .INIT(32'h00010100)) \tq_counter_q[1]_i_1 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q_reg[7]_0 [1]), .I4(\tq_counter_q_reg[7]_0 [0]), .O(\tq_counter_q[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0001010101000000)) \tq_counter_q[2]_i_1 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q_reg[7]_0 [0]), .I4(\tq_counter_q_reg[7]_0 [1]), .I5(\tq_counter_q_reg[7]_0 [2]), .O(\tq_counter_q[2]_i_1_n_0 )); LUT5 #( .INIT(32'h00010100)) \tq_counter_q[3]_i_1 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q[3]_i_2__0_n_0 ), .I4(\tq_counter_q_reg[7]_0 [3]), .O(\tq_counter_q[3]_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \tq_counter_q[3]_i_2__0 (.I0(\tq_counter_q_reg[7]_0 [1]), .I1(\tq_counter_q_reg[7]_0 [0]), .I2(\tq_counter_q_reg[7]_0 [2]), .O(\tq_counter_q[3]_i_2__0_n_0 )); LUT5 #( .INIT(32'h00010100)) \tq_counter_q[4]_i_1 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q[4]_i_2__0_n_0 ), .I4(\tq_counter_q_reg[7]_0 [4]), .O(\tq_counter_q[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h8000)) \tq_counter_q[4]_i_2__0 (.I0(\tq_counter_q_reg[7]_0 [2]), .I1(\tq_counter_q_reg[7]_0 [0]), .I2(\tq_counter_q_reg[7]_0 [1]), .I3(\tq_counter_q_reg[7]_0 [3]), .O(\tq_counter_q[4]_i_2__0_n_0 )); LUT5 #( .INIT(32'h00010100)) \tq_counter_q[5]_i_1 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q[5]_i_2__0_n_0 ), .I4(\tq_counter_q_reg[7]_0 [5]), .O(\tq_counter_q[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT5 #( .INIT(32'h80000000)) \tq_counter_q[5]_i_2__0 (.I0(\tq_counter_q_reg[7]_0 [3]), .I1(\tq_counter_q_reg[7]_0 [1]), .I2(\tq_counter_q_reg[7]_0 [0]), .I3(\tq_counter_q_reg[7]_0 [2]), .I4(\tq_counter_q_reg[7]_0 [4]), .O(\tq_counter_q[5]_i_2__0_n_0 )); LUT5 #( .INIT(32'h00010100)) \tq_counter_q[6]_i_1 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q[7]_i_5_n_0 ), .I4(\tq_counter_q_reg[7]_0 [6]), .O(\tq_counter_q[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0001010101000000)) \tq_counter_q[7]_i_2 (.I0(\tq_counter_q_reg[7]_3 ), .I1(\tq_counter_q_reg[7]_2 ), .I2(\tq_counter_q_reg[7]_1 ), .I3(\tq_counter_q_reg[7]_0 [6]), .I4(\tq_counter_q[7]_i_5_n_0 ), .I5(\tq_counter_q_reg[7]_0 [7]), .O(\tq_counter_q[7]_i_2_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \tq_counter_q[7]_i_5 (.I0(\tq_counter_q_reg[7]_0 [4]), .I1(\tq_counter_q_reg[7]_0 [2]), .I2(\tq_counter_q_reg[7]_0 [0]), .I3(\tq_counter_q_reg[7]_0 [1]), .I4(\tq_counter_q_reg[7]_0 [3]), .I5(\tq_counter_q_reg[7]_0 [5]), .O(\tq_counter_q[7]_i_5_n_0 )); FDPE \tq_counter_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .D(\tq_counter_q[0]_i_1_n_0 ), .PRE(\segm_counter_q_reg[0]_1 ), .Q(\tq_counter_q_reg[7]_0 [0])); FDCE \tq_counter_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[1]_i_1_n_0 ), .Q(\tq_counter_q_reg[7]_0 [1])); FDCE \tq_counter_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[2]_i_1_n_0 ), .Q(\tq_counter_q_reg[7]_0 [2])); FDCE \tq_counter_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[3]_i_1_n_0 ), .Q(\tq_counter_q_reg[7]_0 [3])); FDCE \tq_counter_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[4]_i_1_n_0 ), .Q(\tq_counter_q_reg[7]_0 [4])); FDCE \tq_counter_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[5]_i_1_n_0 ), .Q(\tq_counter_q_reg[7]_0 [5])); FDCE \tq_counter_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[6]_i_1_n_0 ), .Q(\tq_counter_q_reg[7]_0 [6])); FDCE \tq_counter_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\tq_counter_q_reg[0]_0 ), .CLR(\segm_counter_q_reg[0]_1 ), .D(\tq_counter_q[7]_i_2_n_0 ), .Q(\tq_counter_q_reg[7]_0 [7])); endmodule module btl_fsm (rx_trig_req_q_reg, rx_trig_req_q_reg_0, \FSM_onehot_current_state_reg[1]_0 , \FSM_onehot_current_state_reg[1]_1 , \FSM_onehot_current_state_reg[2]_0 , \FSM_onehot_current_state_reg[2]_1 , D, \FSM_onehot_current_state_reg[2]_2 , \tseg1_nbt_reg[7] , \FSM_onehot_current_state_reg[1]_2 , \FSM_onehot_current_state_reg[2]_3 , \g_bit[2].reg_value_r_reg[2] , \segm_counter_q_reg[0] , \FSM_onehot_current_state_reg[1]_3 , \segm_counter_q_reg[0]_0 , \FSM_onehot_current_state_reg[2]_4 , \FSM_onehot_current_state_reg[2]_5 , \FSM_onehot_current_state_reg[1]_4 , \FSM_onehot_current_state_reg[2]_6 , reg_q_reg, \FSM_onehot_current_state_reg[2]_7 , \FSM_onehot_current_state_reg[2]_8 , \FSM_onehot_current_state_reg[2]_9 , \FSM_onehot_current_state_reg[2]_10 , \FSM_onehot_current_state_reg[2]_11 , \FSM_onehot_current_state_reg[2]_12 , S, \FSM_onehot_current_state_reg[2]_13 , DI, \FSM_onehot_current_state_reg[2]_14 , \FSM_onehot_current_state_reg[2]_15 , \FSM_onehot_current_state_reg[2]_16 , \FSM_onehot_current_state_reg[2]_17 , \FSM_onehot_current_state_reg[2]_18 , \g_bit[0].reg_value_r_reg[0] , \FSM_onehot_current_state_reg[2]_19 , \FSM_onehot_current_state_reg[0]_0 , \dst_ctr_q_reg[1] , \segm_counter_q_reg[0]_1 , \mr_ctrl_out[btr_fd_ph2_fd] , Q, \exp_seg_length_q_reg[6] , \exp_seg_length_q_reg[7] , O, \mr_ctrl_out[btr_ph2] , \exp_seg_length_q_reg[7]_0 , \exp_seg_length_q_reg[0] , \test_probe[tx_trigger]_INST_0_i_16 , \test_probe[tx_trigger]_INST_0_i_9 , reg_q_reg_0, \FSM_onehot_current_state_reg[1]_5 , reg_q_reg_1, \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] , \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 , CO, reg_q_reg_2, reg_q_reg_3, \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] , \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 , \exp_seg_length_q[7]_i_11 , sync_edge, \test_probe[tx_trigger]_INST_0_i_3_0 , can_tx_OBUF, sync_flag, crc_data_tx_wbs, \mr_ctrl_out[settings_ena] , \mr_ctrl_out[mode_bmm] , \test_probe[tx_trigger]_INST_0_i_9_0 , i__carry_i_3__3, \mr_ctrl_out[btr_sjw] , neg_phase_err, \exp_seg_length_q_reg[3] , \exp_seg_length_q_reg[3]_0 , \exp_seg_length_q_reg[7]_1 , \exp_seg_length_q_reg[7]_2 , reg_q_reg_4, reg_q_reg_5, tx_trig_req_flag_q, clk_sys_IBUF_BUFG, \FSM_onehot_current_state_reg[0]_1 ); output rx_trig_req_q_reg; output rx_trig_req_q_reg_0; output \FSM_onehot_current_state_reg[1]_0 ; output \FSM_onehot_current_state_reg[1]_1 ; output \FSM_onehot_current_state_reg[2]_0 ; output \FSM_onehot_current_state_reg[2]_1 ; output [7:0]D; output \FSM_onehot_current_state_reg[2]_2 ; output [7:0]\tseg1_nbt_reg[7] ; output \FSM_onehot_current_state_reg[1]_2 ; output \FSM_onehot_current_state_reg[2]_3 ; output [1:0]\g_bit[2].reg_value_r_reg[2] ; output [0:0]\segm_counter_q_reg[0] ; output \FSM_onehot_current_state_reg[1]_3 ; output [0:0]\segm_counter_q_reg[0]_0 ; output \FSM_onehot_current_state_reg[2]_4 ; output \FSM_onehot_current_state_reg[2]_5 ; output \FSM_onehot_current_state_reg[1]_4 ; output \FSM_onehot_current_state_reg[2]_6 ; output reg_q_reg; output \FSM_onehot_current_state_reg[2]_7 ; output \FSM_onehot_current_state_reg[2]_8 ; output \FSM_onehot_current_state_reg[2]_9 ; output \FSM_onehot_current_state_reg[2]_10 ; output \FSM_onehot_current_state_reg[2]_11 ; output \FSM_onehot_current_state_reg[2]_12 ; output [0:0]S; output \FSM_onehot_current_state_reg[2]_13 ; output [0:0]DI; output \FSM_onehot_current_state_reg[2]_14 ; output \FSM_onehot_current_state_reg[2]_15 ; output \FSM_onehot_current_state_reg[2]_16 ; output [0:0]\FSM_onehot_current_state_reg[2]_17 ; output [0:0]\FSM_onehot_current_state_reg[2]_18 ; output [0:0]\g_bit[0].reg_value_r_reg[0] ; output \FSM_onehot_current_state_reg[2]_19 ; output \FSM_onehot_current_state_reg[0]_0 ; input \dst_ctr_q_reg[1] ; input \segm_counter_q_reg[0]_1 ; input [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; input [6:0]Q; input \exp_seg_length_q_reg[6] ; input \exp_seg_length_q_reg[7] ; input [3:0]O; input [5:0]\mr_ctrl_out[btr_ph2] ; input [7:0]\exp_seg_length_q_reg[7]_0 ; input \exp_seg_length_q_reg[0] ; input [4:0]\test_probe[tx_trigger]_INST_0_i_16 ; input [5:0]\test_probe[tx_trigger]_INST_0_i_9 ; input reg_q_reg_0; input \FSM_onehot_current_state_reg[1]_5 ; input reg_q_reg_1; input \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ; input \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ; input [0:0]CO; input reg_q_reg_2; input reg_q_reg_3; input [0:0]\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ; input \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ; input [1:0]\exp_seg_length_q[7]_i_11 ; input sync_edge; input \test_probe[tx_trigger]_INST_0_i_3_0 ; input can_tx_OBUF; input sync_flag; input crc_data_tx_wbs; input \mr_ctrl_out[settings_ena] ; input \mr_ctrl_out[mode_bmm] ; input [1:0]\test_probe[tx_trigger]_INST_0_i_9_0 ; input [2:0]i__carry_i_3__3; input [1:0]\mr_ctrl_out[btr_sjw] ; input [4:0]neg_phase_err; input [3:0]\exp_seg_length_q_reg[3] ; input [3:0]\exp_seg_length_q_reg[3]_0 ; input [1:0]\exp_seg_length_q_reg[7]_1 ; input [2:0]\exp_seg_length_q_reg[7]_2 ; input reg_q_reg_4; input reg_q_reg_5; input tx_trig_req_flag_q; input clk_sys_IBUF_BUFG; input \FSM_onehot_current_state_reg[0]_1 ; wire [0:0]CO; wire [7:0]D; wire [0:0]DI; wire \FSM_onehot_current_state[0]_i_1_n_0 ; wire \FSM_onehot_current_state[1]_i_1_n_0 ; wire \FSM_onehot_current_state[2]_i_1_n_0 ; wire \FSM_onehot_current_state[2]_i_4_n_0 ; wire \FSM_onehot_current_state_reg[0]_0 ; wire \FSM_onehot_current_state_reg[0]_1 ; wire \FSM_onehot_current_state_reg[1]_0 ; wire \FSM_onehot_current_state_reg[1]_1 ; wire \FSM_onehot_current_state_reg[1]_2 ; wire \FSM_onehot_current_state_reg[1]_3 ; wire \FSM_onehot_current_state_reg[1]_4 ; wire \FSM_onehot_current_state_reg[1]_5 ; wire \FSM_onehot_current_state_reg[2]_0 ; wire \FSM_onehot_current_state_reg[2]_1 ; wire \FSM_onehot_current_state_reg[2]_10 ; wire \FSM_onehot_current_state_reg[2]_11 ; wire \FSM_onehot_current_state_reg[2]_12 ; wire \FSM_onehot_current_state_reg[2]_13 ; wire \FSM_onehot_current_state_reg[2]_14 ; wire \FSM_onehot_current_state_reg[2]_15 ; wire \FSM_onehot_current_state_reg[2]_16 ; wire [0:0]\FSM_onehot_current_state_reg[2]_18 ; wire \FSM_onehot_current_state_reg[2]_19 ; wire \FSM_onehot_current_state_reg[2]_2 ; wire \FSM_onehot_current_state_reg[2]_3 ; wire \FSM_onehot_current_state_reg[2]_4 ; wire \FSM_onehot_current_state_reg[2]_5 ; wire \FSM_onehot_current_state_reg[2]_6 ; wire \FSM_onehot_current_state_reg[2]_8 ; wire \FSM_onehot_current_state_reg[2]_9 ; wire [3:0]O; wire [6:0]Q; wire [0:0]S; wire [3:0]basic_segm_length; wire can_tx_OBUF; wire clk_sys_IBUF_BUFG; wire crc_data_tx_wbs; wire \dst_ctr_q_reg[1] ; wire \exp_seg_length_q[3]_i_3_n_0 ; wire \exp_seg_length_q[3]_i_4_n_0 ; wire \exp_seg_length_q[3]_i_5_n_0 ; wire \exp_seg_length_q[3]_i_6_n_0 ; wire \exp_seg_length_q[3]_i_7_n_0 ; wire [1:0]\exp_seg_length_q[7]_i_11 ; wire \exp_seg_length_q[7]_i_3__0_n_0 ; wire \exp_seg_length_q[7]_i_6_n_0 ; wire \exp_seg_length_q_reg[0] ; wire [3:0]\exp_seg_length_q_reg[3] ; wire [3:0]\exp_seg_length_q_reg[3]_0 ; wire \exp_seg_length_q_reg[3]_i_2__0_n_0 ; wire \exp_seg_length_q_reg[3]_i_2__0_n_4 ; wire \exp_seg_length_q_reg[3]_i_2__0_n_5 ; wire \exp_seg_length_q_reg[3]_i_2__0_n_6 ; wire \exp_seg_length_q_reg[3]_i_2__0_n_7 ; wire \exp_seg_length_q_reg[6] ; wire \exp_seg_length_q_reg[7] ; wire [7:0]\exp_seg_length_q_reg[7]_0 ; wire [1:0]\exp_seg_length_q_reg[7]_1 ; wire [2:0]\exp_seg_length_q_reg[7]_2 ; wire \exp_seg_length_q_reg[7]_i_2__0_n_4 ; wire \exp_seg_length_q_reg[7]_i_2__0_n_5 ; wire \exp_seg_length_q_reg[7]_i_2__0_n_6 ; wire \exp_seg_length_q_reg[7]_i_2__0_n_7 ; wire [0:0]\g_bit[0].reg_value_r_reg[0] ; wire [1:0]\g_bit[2].reg_value_r_reg[2] ; wire [0:0]\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ; wire [2:0]i__carry_i_3__3; wire [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [5:0]\mr_ctrl_out[btr_ph2] ; wire [1:0]\mr_ctrl_out[btr_sjw] ; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[settings_ena] ; wire [4:0]neg_phase_err; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire rx_trig_req_q_reg; wire rx_trig_req_q_reg_0; wire [0:0]\segm_counter_q_reg[0] ; wire [0:0]\segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire sync_edge; wire sync_flag; wire [3:0]sync_segm_length; wire \test_probe[tx_trigger]_INST_0_i_10_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_12_n_0 ; wire [4:0]\test_probe[tx_trigger]_INST_0_i_16 ; wire \test_probe[tx_trigger]_INST_0_i_3_0 ; wire \test_probe[tx_trigger]_INST_0_i_3_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_4_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_6_n_0 ; wire [5:0]\test_probe[tx_trigger]_INST_0_i_9 ; wire [1:0]\test_probe[tx_trigger]_INST_0_i_9_0 ; wire [7:0]\tseg1_nbt_reg[7] ; wire tx_trig_req_flag_q; wire [2:0]\NLW_exp_seg_length_q_reg[3]_i_2_CO_UNCONNECTED ; wire [2:0]\NLW_exp_seg_length_q_reg[3]_i_2__0_CO_UNCONNECTED ; wire [3:0]\NLW_exp_seg_length_q_reg[7]_i_2__0_CO_UNCONNECTED ; assign \FSM_onehot_current_state_reg[2]_17 [0] = \exp_seg_length_q[3]_i_7_n_0 ; assign \FSM_onehot_current_state_reg[2]_7 = \exp_seg_length_q[3]_i_7_n_0 ; LUT5 #( .INIT(32'h00E0FFFF)) \FSM_onehot_current_state[0]_i_1 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\FSM_onehot_current_state_reg[1]_1 ), .I2(\FSM_onehot_current_state_reg[0]_0 ), .I3(\FSM_onehot_current_state_reg[1]_3 ), .I4(\mr_ctrl_out[settings_ena] ), .O(\FSM_onehot_current_state[0]_i_1_n_0 )); LUT6 #( .INIT(64'h07A2F7F250005000)) \FSM_onehot_current_state[1]_i_1 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\FSM_onehot_current_state_reg[2]_0 ), .I2(\FSM_onehot_current_state_reg[1]_1 ), .I3(\FSM_onehot_current_state_reg[0]_0 ), .I4(\FSM_onehot_current_state_reg[1]_3 ), .I5(\mr_ctrl_out[settings_ena] ), .O(\FSM_onehot_current_state[1]_i_1_n_0 )); LUT5 #( .INIT(32'hF8880000)) \FSM_onehot_current_state[2]_i_1 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\FSM_onehot_current_state_reg[2]_0 ), .I2(\FSM_onehot_current_state_reg[1]_1 ), .I3(\FSM_onehot_current_state_reg[1]_3 ), .I4(\mr_ctrl_out[settings_ena] ), .O(\FSM_onehot_current_state[2]_i_1_n_0 )); LUT6 #( .INIT(64'h0000001F1F1F1F1F)) \FSM_onehot_current_state[2]_i_2 (.I0(\FSM_onehot_current_state_reg[2]_4 ), .I1(\FSM_onehot_current_state[2]_i_4_n_0 ), .I2(reg_q_reg_0), .I3(\FSM_onehot_current_state_reg[1]_5 ), .I4(\FSM_onehot_current_state_reg[2]_5 ), .I5(reg_q_reg_1), .O(\FSM_onehot_current_state_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h5504)) \FSM_onehot_current_state[2]_i_3 (.I0(\FSM_onehot_current_state_reg[2]_0 ), .I1(\FSM_onehot_current_state_reg[1]_1 ), .I2(\segm_counter_q_reg[0]_1 ), .I3(\FSM_onehot_current_state_reg[2]_1 ), .O(\FSM_onehot_current_state_reg[1]_3 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT3 #( .INIT(8'h4F)) \FSM_onehot_current_state[2]_i_4 (.I0(\FSM_onehot_current_state_reg[1]_1 ), .I1(reg_q_reg_2), .I2(\FSM_onehot_current_state_reg[1]_4 ), .O(\FSM_onehot_current_state[2]_i_4_n_0 )); (* FSM_ENCODED_STATES = "s_bt_reset:001,s_bt_tseg2:100,s_bt_tseg1:010" *) FDPE #( .INIT(1'b0)) \FSM_onehot_current_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\FSM_onehot_current_state[0]_i_1_n_0 ), .PRE(\FSM_onehot_current_state_reg[0]_1 ), .Q(\FSM_onehot_current_state_reg[0]_0 )); (* FSM_ENCODED_STATES = "s_bt_reset:001,s_bt_tseg2:100,s_bt_tseg1:010" *) FDCE #( .INIT(1'b1)) \FSM_onehot_current_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_onehot_current_state_reg[0]_1 ), .D(\FSM_onehot_current_state[1]_i_1_n_0 ), .Q(\FSM_onehot_current_state_reg[1]_1 )); (* FSM_ENCODED_STATES = "s_bt_reset:001,s_bt_tseg2:100,s_bt_tseg1:010" *) FDCE #( .INIT(1'b0)) \FSM_onehot_current_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_onehot_current_state_reg[0]_1 ), .D(\FSM_onehot_current_state[2]_i_1_n_0 ), .Q(\FSM_onehot_current_state_reg[2]_1 )); LUT2 #( .INIT(4'h2)) \bst_ctr_q[2]_i_2 (.I0(rx_trig_req_q_reg_0), .I1(\dst_ctr_q_reg[1] ), .O(rx_trig_req_q_reg)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT5 #( .INIT(32'h00002202)) \dst_ctr_q[2]_i_3 (.I0(\FSM_onehot_current_state_reg[1]_1 ), .I1(\FSM_onehot_current_state_reg[2]_0 ), .I2(\segm_counter_q_reg[0]_1 ), .I3(\FSM_onehot_current_state_reg[2]_1 ), .I4(\dst_ctr_q_reg[1] ), .O(\FSM_onehot_current_state_reg[1]_0 )); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[0]_i_1 (.I0(\exp_seg_length_q_reg[3]_i_2__0_n_7 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(\mr_ctrl_out[btr_fd_ph2_fd] [0]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .I4(Q[0]), .O(D[0])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[0]_i_1__0 (.I0(sync_segm_length[0]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\mr_ctrl_out[btr_ph2] [0]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .I4(\exp_seg_length_q_reg[7]_0 [0]), .O(\tseg1_nbt_reg[7] [0])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[1]_i_1 (.I0(\exp_seg_length_q_reg[3]_i_2__0_n_6 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(\mr_ctrl_out[btr_fd_ph2_fd] [1]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .I4(Q[1]), .O(D[1])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[1]_i_1__0 (.I0(sync_segm_length[1]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\mr_ctrl_out[btr_ph2] [1]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .I4(\exp_seg_length_q_reg[7]_0 [1]), .O(\tseg1_nbt_reg[7] [1])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[2]_i_1 (.I0(\exp_seg_length_q_reg[3]_i_2__0_n_5 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(\mr_ctrl_out[btr_fd_ph2_fd] [2]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .I4(Q[2]), .O(D[2])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[2]_i_1__0 (.I0(sync_segm_length[2]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\mr_ctrl_out[btr_ph2] [2]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .I4(\exp_seg_length_q_reg[7]_0 [2]), .O(\tseg1_nbt_reg[7] [2])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[3]_i_1 (.I0(\exp_seg_length_q_reg[3]_i_2__0_n_4 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(\mr_ctrl_out[btr_fd_ph2_fd] [3]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .I4(Q[3]), .O(D[3])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[3]_i_1__0 (.I0(sync_segm_length[3]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\mr_ctrl_out[btr_ph2] [3]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .I4(\exp_seg_length_q_reg[7]_0 [3]), .O(\tseg1_nbt_reg[7] [3])); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_3 (.I0(\mr_ctrl_out[btr_fd_ph2_fd] [0]), .I1(\FSM_onehot_current_state_reg[2]_2 ), .I2(Q[0]), .O(\exp_seg_length_q[3]_i_3_n_0 )); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_3__0 (.I0(\mr_ctrl_out[btr_ph2] [0]), .I1(\FSM_onehot_current_state_reg[2]_3 ), .I2(\exp_seg_length_q_reg[7]_0 [0]), .O(basic_segm_length[0])); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_4 (.I0(\mr_ctrl_out[btr_fd_ph2_fd] [3]), .I1(\FSM_onehot_current_state_reg[2]_2 ), .I2(Q[3]), .O(\exp_seg_length_q[3]_i_4_n_0 )); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_4__0 (.I0(\mr_ctrl_out[btr_ph2] [3]), .I1(\FSM_onehot_current_state_reg[2]_3 ), .I2(\exp_seg_length_q_reg[7]_0 [3]), .O(basic_segm_length[3])); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_5 (.I0(\mr_ctrl_out[btr_fd_ph2_fd] [2]), .I1(\FSM_onehot_current_state_reg[2]_2 ), .I2(Q[2]), .O(\exp_seg_length_q[3]_i_5_n_0 )); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_5__0 (.I0(\mr_ctrl_out[btr_ph2] [2]), .I1(\FSM_onehot_current_state_reg[2]_3 ), .I2(\exp_seg_length_q_reg[7]_0 [2]), .O(basic_segm_length[2])); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_6 (.I0(\mr_ctrl_out[btr_fd_ph2_fd] [1]), .I1(\FSM_onehot_current_state_reg[2]_2 ), .I2(Q[1]), .O(\exp_seg_length_q[3]_i_6_n_0 )); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[3]_i_6__0 (.I0(\mr_ctrl_out[btr_ph2] [1]), .I1(\FSM_onehot_current_state_reg[2]_3 ), .I2(\exp_seg_length_q_reg[7]_0 [1]), .O(basic_segm_length[1])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[4]_i_1 (.I0(\exp_seg_length_q_reg[7]_i_2__0_n_7 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(\mr_ctrl_out[btr_fd_ph2_fd] [4]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .I4(Q[4]), .O(D[4])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[4]_i_1__0 (.I0(O[0]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\mr_ctrl_out[btr_ph2] [4]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .I4(\exp_seg_length_q_reg[7]_0 [4]), .O(\tseg1_nbt_reg[7] [4])); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'h88B8)) \exp_seg_length_q[5]_i_1 (.I0(\exp_seg_length_q_reg[7]_i_2__0_n_6 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(Q[5]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .O(D[5])); LUT5 #( .INIT(32'hB8BBB888)) \exp_seg_length_q[5]_i_1__0 (.I0(O[1]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\mr_ctrl_out[btr_ph2] [5]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .I4(\exp_seg_length_q_reg[7]_0 [5]), .O(\tseg1_nbt_reg[7] [5])); LUT4 #( .INIT(16'h88B8)) \exp_seg_length_q[6]_i_1 (.I0(\exp_seg_length_q_reg[7]_i_2__0_n_5 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .I2(Q[6]), .I3(\FSM_onehot_current_state_reg[2]_2 ), .O(D[6])); LUT4 #( .INIT(16'h88B8)) \exp_seg_length_q[6]_i_1__0 (.I0(O[2]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\exp_seg_length_q_reg[7]_0 [6]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .O(\tseg1_nbt_reg[7] [6])); LUT6 #( .INIT(64'h0000000000000F15)) \exp_seg_length_q[6]_i_2 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\segm_counter_q_reg[0]_1 ), .I2(\FSM_onehot_current_state_reg[1]_1 ), .I3(\FSM_onehot_current_state_reg[2]_0 ), .I4(\exp_seg_length_q_reg[6] ), .I5(\exp_seg_length_q_reg[7] ), .O(\FSM_onehot_current_state_reg[2]_2 )); LUT4 #( .INIT(16'h88B8)) \exp_seg_length_q[7]_i_1 (.I0(O[3]), .I1(\FSM_onehot_current_state_reg[1]_2 ), .I2(\exp_seg_length_q_reg[7]_0 [7]), .I3(\FSM_onehot_current_state_reg[2]_3 ), .O(\tseg1_nbt_reg[7] [7])); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT2 #( .INIT(4'h8)) \exp_seg_length_q[7]_i_1__0 (.I0(\exp_seg_length_q_reg[7]_i_2__0_n_4 ), .I1(\exp_seg_length_q[7]_i_3__0_n_0 ), .O(D[7])); LUT6 #( .INIT(64'h0000000000000F15)) \exp_seg_length_q[7]_i_3 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\segm_counter_q_reg[0]_1 ), .I2(\FSM_onehot_current_state_reg[1]_1 ), .I3(\FSM_onehot_current_state_reg[2]_0 ), .I4(\exp_seg_length_q_reg[6] ), .I5(\exp_seg_length_q_reg[0] ), .O(\FSM_onehot_current_state_reg[2]_3 )); LUT6 #( .INIT(64'h5454545455555455)) \exp_seg_length_q[7]_i_3__0 (.I0(\exp_seg_length_q_reg[6] ), .I1(\exp_seg_length_q_reg[7] ), .I2(\FSM_onehot_current_state_reg[2]_0 ), .I3(\FSM_onehot_current_state_reg[1]_1 ), .I4(\segm_counter_q_reg[0]_1 ), .I5(\FSM_onehot_current_state_reg[2]_1 ), .O(\exp_seg_length_q[7]_i_3__0_n_0 )); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[7]_i_6 (.I0(\mr_ctrl_out[btr_fd_ph2_fd] [4]), .I1(\FSM_onehot_current_state_reg[2]_2 ), .I2(Q[4]), .O(\exp_seg_length_q[7]_i_6_n_0 )); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[7]_i_6__0 (.I0(\mr_ctrl_out[btr_ph2] [5]), .I1(\FSM_onehot_current_state_reg[2]_3 ), .I2(\exp_seg_length_q_reg[7]_0 [5]), .O(\g_bit[2].reg_value_r_reg[2] [1])); LUT3 #( .INIT(8'hB8)) \exp_seg_length_q[7]_i_7 (.I0(\mr_ctrl_out[btr_ph2] [4]), .I1(\FSM_onehot_current_state_reg[2]_3 ), .I2(\exp_seg_length_q_reg[7]_0 [4]), .O(\g_bit[2].reg_value_r_reg[2] [0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) (* SOFT_HLUTNM = "soft_lutpair116" *) LUT2 #( .INIT(4'hE)) \exp_seg_length_q[8]_i_15 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\segm_counter_q_reg[0]_1 ), .O(\exp_seg_length_q[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT5 #( .INIT(32'h00000080)) \exp_seg_length_q[8]_i_16 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\exp_seg_length_q[7]_i_11 [1]), .I2(sync_edge), .I3(\exp_seg_length_q[7]_i_11 [0]), .I4(reg_q_reg), .O(\FSM_onehot_current_state_reg[2]_6 )); LUT6 #( .INIT(64'h5454545455555455)) \exp_seg_length_q[8]_i_5 (.I0(\exp_seg_length_q_reg[6] ), .I1(\exp_seg_length_q_reg[0] ), .I2(\FSM_onehot_current_state_reg[2]_0 ), .I3(\FSM_onehot_current_state_reg[1]_1 ), .I4(\segm_counter_q_reg[0]_1 ), .I5(\FSM_onehot_current_state_reg[2]_1 ), .O(\FSM_onehot_current_state_reg[1]_2 )); LUT6 #( .INIT(64'hFF00FF04FF00FFFF)) \exp_seg_length_q[8]_i_6 (.I0(crc_data_tx_wbs), .I1(\mr_ctrl_out[settings_ena] ), .I2(\mr_ctrl_out[mode_bmm] ), .I3(sync_flag), .I4(\FSM_onehot_current_state_reg[2]_1 ), .I5(\FSM_onehot_current_state_reg[1]_1 ), .O(reg_q_reg)); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 \exp_seg_length_q_reg[3]_i_2 (.CI(1'b0), .CO({\g_bit[0].reg_value_r_reg[0] ,\NLW_exp_seg_length_q_reg[3]_i_2_CO_UNCONNECTED [2:0]}), .CYINIT(basic_segm_length[0]), .DI({basic_segm_length[3:1],\exp_seg_length_q[3]_i_7_n_0 }), .O(sync_segm_length), .S(\exp_seg_length_q_reg[3] )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) (* OPT_MODIFIED = "RESYNTH_AREA" *) CARRY4 \exp_seg_length_q_reg[3]_i_2__0 (.CI(1'b0), .CO({\exp_seg_length_q_reg[3]_i_2__0_n_0 ,\NLW_exp_seg_length_q_reg[3]_i_2__0_CO_UNCONNECTED [2:0]}), .CYINIT(\exp_seg_length_q[3]_i_3_n_0 ), .DI({\exp_seg_length_q[3]_i_4_n_0 ,\exp_seg_length_q[3]_i_5_n_0 ,\exp_seg_length_q[3]_i_6_n_0 ,\exp_seg_length_q[3]_i_7_n_0 }), .O({\exp_seg_length_q_reg[3]_i_2__0_n_4 ,\exp_seg_length_q_reg[3]_i_2__0_n_5 ,\exp_seg_length_q_reg[3]_i_2__0_n_6 ,\exp_seg_length_q_reg[3]_i_2__0_n_7 }), .S(\exp_seg_length_q_reg[3]_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) (* OPT_MODIFIED = "RESYNTH_AREA" *) CARRY4 \exp_seg_length_q_reg[7]_i_2__0 (.CI(\exp_seg_length_q_reg[3]_i_2__0_n_0 ), .CO(\NLW_exp_seg_length_q_reg[7]_i_2__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,\exp_seg_length_q_reg[7]_1 ,\exp_seg_length_q[7]_i_6_n_0 }), .O({\exp_seg_length_q_reg[7]_i_2__0_n_4 ,\exp_seg_length_q_reg[7]_i_2__0_n_5 ,\exp_seg_length_q_reg[7]_i_2__0_n_6 ,\exp_seg_length_q_reg[7]_i_2__0_n_7 }), .S({\exp_seg_length_q[3]_i_7_n_0 ,\exp_seg_length_q_reg[7]_2 })); LUT6 #( .INIT(64'hE0E0E000FFFFFFFF)) \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\FSM_onehot_current_state_reg[1]_1 ), .I2(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ), .I3(\test_probe[tx_trigger]_INST_0_i_10_n_0 ), .I4(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ), .I5(reg_q_reg_3), .O(\FSM_onehot_current_state_reg[2]_4 )); LUT6 #( .INIT(64'hFDFDFD5555555555)) \g_segm_end_req_capture[2].segm_end_req_capt_q[2]_i_2 (.I0(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ), .I1(\test_probe[tx_trigger]_INST_0_i_10_n_0 ), .I2(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ), .I3(\FSM_onehot_current_state_reg[2]_1 ), .I4(\FSM_onehot_current_state_reg[1]_1 ), .I5(CO), .O(\FSM_onehot_current_state_reg[2]_5 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT3 #( .INIT(8'hB8)) i__carry_i_10 (.I0(i__carry_i_3__3[2]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [3]), .O(\FSM_onehot_current_state_reg[2]_11 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT3 #( .INIT(8'hB8)) i__carry_i_11 (.I0(neg_phase_err[3]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_16 [3]), .O(\FSM_onehot_current_state_reg[2]_15 )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT3 #( .INIT(8'hB8)) i__carry_i_12 (.I0(i__carry_i_3__3[0]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [1]), .O(\FSM_onehot_current_state_reg[2]_9 )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT3 #( .INIT(8'hB8)) i__carry_i_12__0 (.I0(neg_phase_err[1]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_16 [1]), .O(\FSM_onehot_current_state_reg[2]_13 )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT3 #( .INIT(8'hB8)) i__carry_i_13 (.I0(neg_phase_err[2]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_16 [2]), .O(\FSM_onehot_current_state_reg[2]_14 )); LUT3 #( .INIT(8'hB8)) i__carry_i_1__4 (.I0(\test_probe[tx_trigger]_INST_0_i_9_0 [1]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [5]), .O(\FSM_onehot_current_state_reg[2]_18 )); LUT6 #( .INIT(64'h00E2FFFF000000E2)) i__carry_i_4__4 (.I0(\test_probe[tx_trigger]_INST_0_i_16 [0]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(neg_phase_err[0]), .I3(\mr_ctrl_out[btr_sjw] [0]), .I4(\mr_ctrl_out[btr_sjw] [1]), .I5(\FSM_onehot_current_state_reg[2]_13 ), .O(DI)); LUT6 #( .INIT(64'h9099900009000999)) i__carry_i_8__3 (.I0(\FSM_onehot_current_state_reg[2]_13 ), .I1(\mr_ctrl_out[btr_sjw] [1]), .I2(neg_phase_err[0]), .I3(\FSM_onehot_current_state_reg[2]_1 ), .I4(\test_probe[tx_trigger]_INST_0_i_16 [0]), .I5(\mr_ctrl_out[btr_sjw] [0]), .O(S)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT4 #( .INIT(16'h0B00)) rx_trig_req_q_i_1 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\segm_counter_q_reg[0]_1 ), .I2(\FSM_onehot_current_state_reg[2]_0 ), .I3(\FSM_onehot_current_state_reg[1]_1 ), .O(\FSM_onehot_current_state_reg[2]_19 )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT3 #( .INIT(8'h01)) \segm_counter_q[0]_i_1 (.I0(\FSM_onehot_current_state_reg[1]_3 ), .I1(\segm_counter_q_reg[0]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_16 [0]), .O(\segm_counter_q_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT3 #( .INIT(8'h01)) \segm_counter_q[0]_i_1__0 (.I0(\FSM_onehot_current_state_reg[1]_3 ), .I1(\segm_counter_q_reg[0]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [0]), .O(\segm_counter_q_reg[0]_0 )); LUT6 #( .INIT(64'h5555555551511151)) \test_probe[tx_trigger]_INST_0_i_1 (.I0(reg_q_reg_4), .I1(reg_q_reg_5), .I2(\FSM_onehot_current_state_reg[2]_1 ), .I3(\test_probe[tx_trigger]_INST_0_i_3_n_0 ), .I4(\test_probe[tx_trigger]_INST_0_i_4_n_0 ), .I5(tx_trig_req_flag_q), .O(rx_trig_req_q_reg_0)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT5 #( .INIT(32'hFFFFFFBF)) \test_probe[tx_trigger]_INST_0_i_10 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\exp_seg_length_q[7]_i_11 [1]), .I2(sync_edge), .I3(\exp_seg_length_q[7]_i_11 [0]), .I4(reg_q_reg), .O(\test_probe[tx_trigger]_INST_0_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT3 #( .INIT(8'h1F)) \test_probe[tx_trigger]_INST_0_i_12 (.I0(\FSM_onehot_current_state_reg[2]_1 ), .I1(\FSM_onehot_current_state_reg[1]_1 ), .I2(CO), .O(\test_probe[tx_trigger]_INST_0_i_12_n_0 )); LUT3 #( .INIT(8'hB8)) \test_probe[tx_trigger]_INST_0_i_19 (.I0(\test_probe[tx_trigger]_INST_0_i_9_0 [1]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [5]), .O(\FSM_onehot_current_state_reg[2]_8 )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT3 #( .INIT(8'hB8)) \test_probe[tx_trigger]_INST_0_i_21 (.I0(neg_phase_err[4]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_16 [4]), .O(\FSM_onehot_current_state_reg[2]_16 )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT3 #( .INIT(8'hB8)) \test_probe[tx_trigger]_INST_0_i_24 (.I0(i__carry_i_3__3[1]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [2]), .O(\FSM_onehot_current_state_reg[2]_10 )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT3 #( .INIT(8'hB8)) \test_probe[tx_trigger]_INST_0_i_26 (.I0(\test_probe[tx_trigger]_INST_0_i_9_0 [0]), .I1(\FSM_onehot_current_state_reg[2]_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_9 [4]), .O(\FSM_onehot_current_state_reg[2]_12 )); LUT6 #( .INIT(64'h5555DF5555555555)) \test_probe[tx_trigger]_INST_0_i_3 (.I0(reg_q_reg_0), .I1(\FSM_onehot_current_state_reg[1]_1 ), .I2(reg_q_reg_2), .I3(\FSM_onehot_current_state_reg[1]_4 ), .I4(\test_probe[tx_trigger]_INST_0_i_6_n_0 ), .I5(reg_q_reg_3), .O(\test_probe[tx_trigger]_INST_0_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA2222AAA2)) \test_probe[tx_trigger]_INST_0_i_4 (.I0(reg_q_reg_1), .I1(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ), .I2(\test_probe[tx_trigger]_INST_0_i_10_n_0 ), .I3(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ), .I4(\test_probe[tx_trigger]_INST_0_i_12_n_0 ), .I5(\FSM_onehot_current_state_reg[1]_5 ), .O(\test_probe[tx_trigger]_INST_0_i_4_n_0 )); LUT6 #( .INIT(64'hFFF2FFFFFFFFFFFF)) \test_probe[tx_trigger]_INST_0_i_5 (.I0(\FSM_onehot_current_state_reg[1]_1 ), .I1(can_tx_OBUF), .I2(sync_flag), .I3(\exp_seg_length_q[7]_i_11 [1]), .I4(sync_edge), .I5(\exp_seg_length_q[7]_i_11 [0]), .O(\FSM_onehot_current_state_reg[1]_4 )); LUT5 #( .INIT(32'hF0F0E000)) \test_probe[tx_trigger]_INST_0_i_6 (.I0(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ), .I1(\test_probe[tx_trigger]_INST_0_i_3_0 ), .I2(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ), .I3(\FSM_onehot_current_state_reg[1]_1 ), .I4(\FSM_onehot_current_state_reg[2]_1 ), .O(\test_probe[tx_trigger]_INST_0_i_6_n_0 )); endmodule module btl_segment_end_detector (\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 , \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 , is_tseg1, \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_1 , \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_1 , clk_sys_IBUF_BUFG, \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_2 , \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_2 ); output \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ; output \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ; input is_tseg1; input \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_1 ; input \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_1 ; input clk_sys_IBUF_BUFG; input \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_2 ; input \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_2 ; wire clk_sys_IBUF_BUFG; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_1_n_0 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_1 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_2 ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q[2]_i_1_n_0 ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_1 ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_2 ; wire is_tseg1; wire p_0_in; (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'h32)) \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_1 (.I0(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_1 ), .I1(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_1 ), .I2(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 ), .O(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_1_n_0 )); FDCE \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_2 ), .D(\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_1_n_0 ), .Q(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'h32)) \g_segm_end_req_capture[2].segm_end_req_capt_q[2]_i_1 (.I0(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_2 ), .I1(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_1 ), .I2(p_0_in), .O(\g_segm_end_req_capture[2].segm_end_req_capt_q[2]_i_1_n_0 )); FDCE \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_2 ), .D(\g_segm_end_req_capture[2].segm_end_req_capt_q[2]_i_1_n_0 ), .Q(p_0_in)); LUT2 #( .INIT(4'h2)) \test_probe[tx_trigger]_INST_0_i_13 (.I0(p_0_in), .I1(is_tseg1), .O(\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 )); endmodule module btl_segment_meter (\segm_counter_q_reg[7] , \exp_seg_length_q_reg[6]_0 , Q, \tseg1_nbt_reg[3] , \segm_counter_q_reg[7]_0 , DI, S, exit_segm_regular_tseg11_carry__0_0, exit_segm_regular_tseg11_carry_0, E, D, clk_sys_IBUF_BUFG, \exp_seg_length_q_reg[0]_0 , \exp_seg_length_q_reg[3]_i_2 , \exp_seg_length_q_reg[7]_i_2 , \exp_seg_length_q_reg[7]_i_2_0 , \mr_ctrl_out[btr_ph2] , \exp_seg_length_q_reg[3]_i_2_0 , \exp_seg_length_q_reg[3]_i_2_1 , \exp_seg_length_q_reg[7]_i_2_1 , \exp_seg_length_q_reg[7]_i_2_2 , \exp_seg_length_q_reg[7]_i_2_3 , \exp_seg_length_q_reg[7]_i_2_4 ); output [0:0]\segm_counter_q_reg[7] ; output [0:0]\exp_seg_length_q_reg[6]_0 ; output [1:0]Q; output [2:0]\tseg1_nbt_reg[3] ; output [3:0]\segm_counter_q_reg[7]_0 ; input [3:0]DI; input [3:0]S; input [0:0]exit_segm_regular_tseg11_carry__0_0; input [7:0]exit_segm_regular_tseg11_carry_0; input [0:0]E; input [8:0]D; input clk_sys_IBUF_BUFG; input \exp_seg_length_q_reg[0]_0 ; input \exp_seg_length_q_reg[3]_i_2 ; input [6:0]\exp_seg_length_q_reg[7]_i_2 ; input \exp_seg_length_q_reg[7]_i_2_0 ; input [4:0]\mr_ctrl_out[btr_ph2] ; input \exp_seg_length_q_reg[3]_i_2_0 ; input \exp_seg_length_q_reg[3]_i_2_1 ; input \exp_seg_length_q_reg[7]_i_2_1 ; input \exp_seg_length_q_reg[7]_i_2_2 ; input \exp_seg_length_q_reg[7]_i_2_3 ; input \exp_seg_length_q_reg[7]_i_2_4 ; wire [8:0]D; wire [3:0]DI; wire [0:0]E; wire [1:0]Q; wire [3:0]S; wire clk_sys_IBUF_BUFG; wire [7:0]exit_segm_regular_tseg11_carry_0; wire [0:0]exit_segm_regular_tseg11_carry__0_0; wire exit_segm_regular_tseg11_carry__0_i_1_n_0; wire exit_segm_regular_tseg11_carry_i_10_n_0; wire exit_segm_regular_tseg11_carry_i_1_n_0; wire exit_segm_regular_tseg11_carry_i_2_n_0; wire exit_segm_regular_tseg11_carry_i_3_n_0; wire exit_segm_regular_tseg11_carry_i_5_n_0; wire exit_segm_regular_tseg11_carry_i_6_n_0; wire exit_segm_regular_tseg11_carry_i_7_n_0; wire exit_segm_regular_tseg11_carry_i_8_n_0; wire exit_segm_regular_tseg11_carry_i_9_n_0; wire exit_segm_regular_tseg11_carry_n_0; wire [8:2]exp_seg_length_q; wire \exp_seg_length_q_reg[0]_0 ; wire \exp_seg_length_q_reg[3]_i_2 ; wire \exp_seg_length_q_reg[3]_i_2_0 ; wire \exp_seg_length_q_reg[3]_i_2_1 ; wire [0:0]\exp_seg_length_q_reg[6]_0 ; wire [6:0]\exp_seg_length_q_reg[7]_i_2 ; wire \exp_seg_length_q_reg[7]_i_2_0 ; wire \exp_seg_length_q_reg[7]_i_2_1 ; wire \exp_seg_length_q_reg[7]_i_2_2 ; wire \exp_seg_length_q_reg[7]_i_2_3 ; wire \exp_seg_length_q_reg[7]_i_2_4 ; wire [4:0]\mr_ctrl_out[btr_ph2] ; wire [0:0]\segm_counter_q_reg[7] ; wire [3:0]\segm_counter_q_reg[7]_0 ; wire [2:0]\tseg1_nbt_reg[3] ; wire [2:0]NLW_exit_segm_regular_tseg11_carry_CO_UNCONNECTED; wire [3:0]NLW_exit_segm_regular_tseg11_carry_O_UNCONNECTED; wire [3:1]NLW_exit_segm_regular_tseg11_carry__0_CO_UNCONNECTED; wire [3:0]NLW_exit_segm_regular_tseg11_carry__0_O_UNCONNECTED; wire [2:0]\NLW_exp_seg_length_d9_inferred__0/i__carry_CO_UNCONNECTED ; wire [3:0]\NLW_exp_seg_length_d9_inferred__0/i__carry_O_UNCONNECTED ; (* COMPARATOR_THRESHOLD = "11" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 exit_segm_regular_tseg11_carry (.CI(1'b0), .CO({exit_segm_regular_tseg11_carry_n_0,NLW_exit_segm_regular_tseg11_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({exit_segm_regular_tseg11_carry_i_1_n_0,exit_segm_regular_tseg11_carry_i_2_n_0,exit_segm_regular_tseg11_carry_i_3_n_0,exit_segm_regular_tseg11_carry__0_0}), .O(NLW_exit_segm_regular_tseg11_carry_O_UNCONNECTED[3:0]), .S({exit_segm_regular_tseg11_carry_i_5_n_0,exit_segm_regular_tseg11_carry_i_6_n_0,exit_segm_regular_tseg11_carry_i_7_n_0,exit_segm_regular_tseg11_carry_i_8_n_0})); (* COMPARATOR_THRESHOLD = "11" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 exit_segm_regular_tseg11_carry__0 (.CI(exit_segm_regular_tseg11_carry_n_0), .CO({NLW_exit_segm_regular_tseg11_carry__0_CO_UNCONNECTED[3:1],\exp_seg_length_q_reg[6]_0 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_exit_segm_regular_tseg11_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,exit_segm_regular_tseg11_carry__0_i_1_n_0})); LUT4 #( .INIT(16'h02FD)) exit_segm_regular_tseg11_carry__0_i_1 (.I0(exit_segm_regular_tseg11_carry_i_9_n_0), .I1(exp_seg_length_q[6]), .I2(exp_seg_length_q[7]), .I3(exp_seg_length_q[8]), .O(exit_segm_regular_tseg11_carry__0_i_1_n_0)); LUT5 #( .INIT(32'h8AE308A2)) exit_segm_regular_tseg11_carry_i_1 (.I0(exit_segm_regular_tseg11_carry_0[7]), .I1(exit_segm_regular_tseg11_carry_i_9_n_0), .I2(exp_seg_length_q[6]), .I3(exp_seg_length_q[7]), .I4(exit_segm_regular_tseg11_carry_0[6]), .O(exit_segm_regular_tseg11_carry_i_1_n_0)); LUT4 #( .INIT(16'h0001)) exit_segm_regular_tseg11_carry_i_10 (.I0(exp_seg_length_q[2]), .I1(Q[0]), .I2(Q[1]), .I3(exp_seg_length_q[3]), .O(exit_segm_regular_tseg11_carry_i_10_n_0)); LUT5 #( .INIT(32'h8AE308A2)) exit_segm_regular_tseg11_carry_i_2 (.I0(exit_segm_regular_tseg11_carry_0[5]), .I1(exit_segm_regular_tseg11_carry_i_10_n_0), .I2(exp_seg_length_q[4]), .I3(exp_seg_length_q[5]), .I4(exit_segm_regular_tseg11_carry_0[4]), .O(exit_segm_regular_tseg11_carry_i_2_n_0)); LUT6 #( .INIT(64'h02AAABFC0002AAA8)) exit_segm_regular_tseg11_carry_i_3 (.I0(exit_segm_regular_tseg11_carry_0[3]), .I1(Q[1]), .I2(Q[0]), .I3(exp_seg_length_q[2]), .I4(exp_seg_length_q[3]), .I5(exit_segm_regular_tseg11_carry_0[2]), .O(exit_segm_regular_tseg11_carry_i_3_n_0)); LUT5 #( .INIT(32'h06909009)) exit_segm_regular_tseg11_carry_i_5 (.I0(exp_seg_length_q[7]), .I1(exit_segm_regular_tseg11_carry_0[7]), .I2(exp_seg_length_q[6]), .I3(exit_segm_regular_tseg11_carry_i_9_n_0), .I4(exit_segm_regular_tseg11_carry_0[6]), .O(exit_segm_regular_tseg11_carry_i_5_n_0)); LUT5 #( .INIT(32'h06909009)) exit_segm_regular_tseg11_carry_i_6 (.I0(exp_seg_length_q[5]), .I1(exit_segm_regular_tseg11_carry_0[5]), .I2(exp_seg_length_q[4]), .I3(exit_segm_regular_tseg11_carry_i_10_n_0), .I4(exit_segm_regular_tseg11_carry_0[4]), .O(exit_segm_regular_tseg11_carry_i_6_n_0)); LUT6 #( .INIT(64'h9090900609090990)) exit_segm_regular_tseg11_carry_i_7 (.I0(exp_seg_length_q[3]), .I1(exit_segm_regular_tseg11_carry_0[3]), .I2(exp_seg_length_q[2]), .I3(Q[1]), .I4(Q[0]), .I5(exit_segm_regular_tseg11_carry_0[2]), .O(exit_segm_regular_tseg11_carry_i_7_n_0)); LUT4 #( .INIT(16'h0690)) exit_segm_regular_tseg11_carry_i_8 (.I0(Q[1]), .I1(exit_segm_regular_tseg11_carry_0[1]), .I2(Q[0]), .I3(exit_segm_regular_tseg11_carry_0[0]), .O(exit_segm_regular_tseg11_carry_i_8_n_0)); LUT6 #( .INIT(64'h0000000000000001)) exit_segm_regular_tseg11_carry_i_9 (.I0(exp_seg_length_q[4]), .I1(exp_seg_length_q[2]), .I2(Q[0]), .I3(Q[1]), .I4(exp_seg_length_q[3]), .I5(exp_seg_length_q[5]), .O(exit_segm_regular_tseg11_carry_i_9_n_0)); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \exp_seg_length_d9_inferred__0/i__carry (.CI(1'b0), .CO({\segm_counter_q_reg[7] ,\NLW_exp_seg_length_d9_inferred__0/i__carry_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI(DI), .O(\NLW_exp_seg_length_d9_inferred__0/i__carry_O_UNCONNECTED [3:0]), .S(S)); LUT4 #( .INIT(16'h56A6)) \exp_seg_length_q[3]_i_10 (.I0(\exp_seg_length_q_reg[3]_i_2 ), .I1(\exp_seg_length_q_reg[7]_i_2 [0]), .I2(\exp_seg_length_q_reg[7]_i_2_0 ), .I3(\mr_ctrl_out[btr_ph2] [0]), .O(\tseg1_nbt_reg[3] [0])); LUT4 #( .INIT(16'h56A6)) \exp_seg_length_q[3]_i_8 (.I0(\exp_seg_length_q_reg[3]_i_2_1 ), .I1(\exp_seg_length_q_reg[7]_i_2 [2]), .I2(\exp_seg_length_q_reg[7]_i_2_0 ), .I3(\mr_ctrl_out[btr_ph2] [2]), .O(\tseg1_nbt_reg[3] [2])); LUT4 #( .INIT(16'h56A6)) \exp_seg_length_q[3]_i_9 (.I0(\exp_seg_length_q_reg[3]_i_2_0 ), .I1(\exp_seg_length_q_reg[7]_i_2 [1]), .I2(\exp_seg_length_q_reg[7]_i_2_0 ), .I3(\mr_ctrl_out[btr_ph2] [1]), .O(\tseg1_nbt_reg[3] [1])); LUT4 #( .INIT(16'h56A6)) \exp_seg_length_q[7]_i_10 (.I0(\exp_seg_length_q_reg[7]_i_2_2 ), .I1(\exp_seg_length_q_reg[7]_i_2 [4]), .I2(\exp_seg_length_q_reg[7]_i_2_0 ), .I3(\mr_ctrl_out[btr_ph2] [4]), .O(\segm_counter_q_reg[7]_0 [1])); LUT4 #( .INIT(16'h56A6)) \exp_seg_length_q[7]_i_11 (.I0(\exp_seg_length_q_reg[7]_i_2_1 ), .I1(\exp_seg_length_q_reg[7]_i_2 [3]), .I2(\exp_seg_length_q_reg[7]_i_2_0 ), .I3(\mr_ctrl_out[btr_ph2] [3]), .O(\segm_counter_q_reg[7]_0 [0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFB0404FBFB04FB04)) \exp_seg_length_q[7]_i_8 (.I0(\segm_counter_q_reg[7] ), .I1(exit_segm_regular_tseg11_carry_0[7]), .I2(\exp_seg_length_q_reg[7]_i_2_3 ), .I3(\exp_seg_length_q_reg[7]_i_2_4 ), .I4(\exp_seg_length_q_reg[7]_i_2_0 ), .I5(\exp_seg_length_q_reg[7]_i_2 [6]), .O(\segm_counter_q_reg[7]_0 [3])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFB0404FBFB04FB04)) \exp_seg_length_q[7]_i_9 (.I0(\segm_counter_q_reg[7] ), .I1(exit_segm_regular_tseg11_carry_0[6]), .I2(\exp_seg_length_q_reg[7]_i_2_3 ), .I3(\exp_seg_length_q_reg[7]_i_2_4 ), .I4(\exp_seg_length_q_reg[7]_i_2_0 ), .I5(\exp_seg_length_q_reg[7]_i_2 [5]), .O(\segm_counter_q_reg[7]_0 [2])); FDPE \exp_seg_length_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[0]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(Q[0])); FDPE \exp_seg_length_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[1]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(Q[1])); FDPE \exp_seg_length_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[2]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[2])); FDPE \exp_seg_length_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[3]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[3])); FDPE \exp_seg_length_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[4]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[4])); FDPE \exp_seg_length_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[5]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[5])); FDPE \exp_seg_length_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[6]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[6])); FDPE \exp_seg_length_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[7]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[7])); FDPE \exp_seg_length_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[8]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(exp_seg_length_q[8])); endmodule (* ORIG_REF_NAME = "btl_segment_meter" *) module btl_segment_meter__parameterized0 (CO, \exp_seg_length_q_reg[7]_0 , \segm_counter_q_reg[6] , \exp_seg_length_q_reg[1]_0 , DI, S, \test_probe[tx_trigger]_INST_0_i_12 , Q, \exp_seg_length_q_reg[7]_i_2__0 , \exp_seg_length_q_reg[7]_i_2__0_0 , \exp_seg_length_q_reg[7]_i_2__0_1 , \exp_seg_length_q_reg[7]_i_2__0_2 , E, D, clk_sys_IBUF_BUFG, \exp_seg_length_q_reg[0]_0 ); output [0:0]CO; output [0:0]\exp_seg_length_q_reg[7]_0 ; output [1:0]\segm_counter_q_reg[6] ; output [1:0]\exp_seg_length_q_reg[1]_0 ; input [3:0]DI; input [3:0]S; input [0:0]\test_probe[tx_trigger]_INST_0_i_12 ; input [6:0]Q; input \exp_seg_length_q_reg[7]_i_2__0 ; input \exp_seg_length_q_reg[7]_i_2__0_0 ; input \exp_seg_length_q_reg[7]_i_2__0_1 ; input [1:0]\exp_seg_length_q_reg[7]_i_2__0_2 ; input [0:0]E; input [7:0]D; input clk_sys_IBUF_BUFG; input \exp_seg_length_q_reg[0]_0 ; wire [0:0]CO; wire [7:0]D; wire [3:0]DI; wire [0:0]E; wire [6:0]Q; wire [3:0]S; wire clk_sys_IBUF_BUFG; wire exit_segm_regular_tseg11_carry_i_10__0_n_0; wire exit_segm_regular_tseg11_carry_i_1__0_n_0; wire exit_segm_regular_tseg11_carry_i_2__0_n_0; wire exit_segm_regular_tseg11_carry_i_3__0_n_0; wire exit_segm_regular_tseg11_carry_i_5__0_n_0; wire exit_segm_regular_tseg11_carry_i_6__0_n_0; wire exit_segm_regular_tseg11_carry_i_7__0_n_0; wire exit_segm_regular_tseg11_carry_i_8__0_n_0; wire exit_segm_regular_tseg11_carry_i_9__0_n_0; wire \exp_seg_length_q_reg[0]_0 ; wire [1:0]\exp_seg_length_q_reg[1]_0 ; wire [0:0]\exp_seg_length_q_reg[7]_0 ; wire \exp_seg_length_q_reg[7]_i_2__0 ; wire \exp_seg_length_q_reg[7]_i_2__0_0 ; wire \exp_seg_length_q_reg[7]_i_2__0_1 ; wire [1:0]\exp_seg_length_q_reg[7]_i_2__0_2 ; wire \exp_seg_length_q_reg_n_0_[2] ; wire \exp_seg_length_q_reg_n_0_[3] ; wire \exp_seg_length_q_reg_n_0_[4] ; wire \exp_seg_length_q_reg_n_0_[5] ; wire \exp_seg_length_q_reg_n_0_[6] ; wire \exp_seg_length_q_reg_n_0_[7] ; wire [1:0]\segm_counter_q_reg[6] ; wire [0:0]\test_probe[tx_trigger]_INST_0_i_12 ; wire [2:0]NLW_exit_segm_regular_tseg11_carry_CO_UNCONNECTED; wire [3:0]NLW_exit_segm_regular_tseg11_carry_O_UNCONNECTED; wire [2:0]\NLW_exp_seg_length_d9_inferred__0/i__carry_CO_UNCONNECTED ; wire [3:0]\NLW_exp_seg_length_d9_inferred__0/i__carry_O_UNCONNECTED ; (* COMPARATOR_THRESHOLD = "11" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 exit_segm_regular_tseg11_carry (.CI(1'b0), .CO({\exp_seg_length_q_reg[7]_0 ,NLW_exit_segm_regular_tseg11_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({exit_segm_regular_tseg11_carry_i_1__0_n_0,exit_segm_regular_tseg11_carry_i_2__0_n_0,exit_segm_regular_tseg11_carry_i_3__0_n_0,\test_probe[tx_trigger]_INST_0_i_12 }), .O(NLW_exit_segm_regular_tseg11_carry_O_UNCONNECTED[3:0]), .S({exit_segm_regular_tseg11_carry_i_5__0_n_0,exit_segm_regular_tseg11_carry_i_6__0_n_0,exit_segm_regular_tseg11_carry_i_7__0_n_0,exit_segm_regular_tseg11_carry_i_8__0_n_0})); LUT4 #( .INIT(16'h0001)) exit_segm_regular_tseg11_carry_i_10__0 (.I0(\exp_seg_length_q_reg_n_0_[2] ), .I1(\exp_seg_length_q_reg[1]_0 [0]), .I2(\exp_seg_length_q_reg[1]_0 [1]), .I3(\exp_seg_length_q_reg_n_0_[3] ), .O(exit_segm_regular_tseg11_carry_i_10__0_n_0)); LUT4 #( .INIT(16'h4004)) exit_segm_regular_tseg11_carry_i_1__0 (.I0(\exp_seg_length_q_reg_n_0_[7] ), .I1(Q[6]), .I2(\exp_seg_length_q_reg_n_0_[6] ), .I3(exit_segm_regular_tseg11_carry_i_9__0_n_0), .O(exit_segm_regular_tseg11_carry_i_1__0_n_0)); LUT5 #( .INIT(32'h8AE308A2)) exit_segm_regular_tseg11_carry_i_2__0 (.I0(Q[5]), .I1(exit_segm_regular_tseg11_carry_i_10__0_n_0), .I2(\exp_seg_length_q_reg_n_0_[4] ), .I3(\exp_seg_length_q_reg_n_0_[5] ), .I4(Q[4]), .O(exit_segm_regular_tseg11_carry_i_2__0_n_0)); LUT6 #( .INIT(64'h02AAABFC0002AAA8)) exit_segm_regular_tseg11_carry_i_3__0 (.I0(Q[3]), .I1(\exp_seg_length_q_reg[1]_0 [1]), .I2(\exp_seg_length_q_reg[1]_0 [0]), .I3(\exp_seg_length_q_reg_n_0_[2] ), .I4(\exp_seg_length_q_reg_n_0_[3] ), .I5(Q[2]), .O(exit_segm_regular_tseg11_carry_i_3__0_n_0)); LUT4 #( .INIT(16'h2441)) exit_segm_regular_tseg11_carry_i_5__0 (.I0(\exp_seg_length_q_reg_n_0_[7] ), .I1(\exp_seg_length_q_reg_n_0_[6] ), .I2(exit_segm_regular_tseg11_carry_i_9__0_n_0), .I3(Q[6]), .O(exit_segm_regular_tseg11_carry_i_5__0_n_0)); LUT5 #( .INIT(32'h06909009)) exit_segm_regular_tseg11_carry_i_6__0 (.I0(\exp_seg_length_q_reg_n_0_[5] ), .I1(Q[5]), .I2(\exp_seg_length_q_reg_n_0_[4] ), .I3(exit_segm_regular_tseg11_carry_i_10__0_n_0), .I4(Q[4]), .O(exit_segm_regular_tseg11_carry_i_6__0_n_0)); LUT6 #( .INIT(64'h9090900609090990)) exit_segm_regular_tseg11_carry_i_7__0 (.I0(\exp_seg_length_q_reg_n_0_[3] ), .I1(Q[3]), .I2(\exp_seg_length_q_reg_n_0_[2] ), .I3(\exp_seg_length_q_reg[1]_0 [1]), .I4(\exp_seg_length_q_reg[1]_0 [0]), .I5(Q[2]), .O(exit_segm_regular_tseg11_carry_i_7__0_n_0)); LUT4 #( .INIT(16'h0690)) exit_segm_regular_tseg11_carry_i_8__0 (.I0(\exp_seg_length_q_reg[1]_0 [1]), .I1(Q[1]), .I2(\exp_seg_length_q_reg[1]_0 [0]), .I3(Q[0]), .O(exit_segm_regular_tseg11_carry_i_8__0_n_0)); LUT6 #( .INIT(64'h0000000000000001)) exit_segm_regular_tseg11_carry_i_9__0 (.I0(\exp_seg_length_q_reg_n_0_[4] ), .I1(\exp_seg_length_q_reg_n_0_[2] ), .I2(\exp_seg_length_q_reg[1]_0 [0]), .I3(\exp_seg_length_q_reg[1]_0 [1]), .I4(\exp_seg_length_q_reg_n_0_[3] ), .I5(\exp_seg_length_q_reg_n_0_[5] ), .O(exit_segm_regular_tseg11_carry_i_9__0_n_0)); (* COMPARATOR_THRESHOLD = "11" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 \exp_seg_length_d9_inferred__0/i__carry (.CI(1'b0), .CO({CO,\NLW_exp_seg_length_d9_inferred__0/i__carry_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI(DI), .O(\NLW_exp_seg_length_d9_inferred__0/i__carry_O_UNCONNECTED [3:0]), .S(S)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFB0404FBFB04FB04)) \exp_seg_length_q[7]_i_8 (.I0(CO), .I1(Q[6]), .I2(\exp_seg_length_q_reg[7]_i_2__0 ), .I3(\exp_seg_length_q_reg[7]_i_2__0_0 ), .I4(\exp_seg_length_q_reg[7]_i_2__0_1 ), .I5(\exp_seg_length_q_reg[7]_i_2__0_2 [1]), .O(\segm_counter_q_reg[6] [1])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFB0404FBFB04FB04)) \exp_seg_length_q[7]_i_9 (.I0(CO), .I1(Q[5]), .I2(\exp_seg_length_q_reg[7]_i_2__0 ), .I3(\exp_seg_length_q_reg[7]_i_2__0_0 ), .I4(\exp_seg_length_q_reg[7]_i_2__0_1 ), .I5(\exp_seg_length_q_reg[7]_i_2__0_2 [0]), .O(\segm_counter_q_reg[6] [0])); FDPE \exp_seg_length_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[0]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg[1]_0 [0])); FDPE \exp_seg_length_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[1]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg[1]_0 [1])); FDPE \exp_seg_length_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[2]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg_n_0_[2] )); FDPE \exp_seg_length_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[3]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg_n_0_[3] )); FDPE \exp_seg_length_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[4]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg_n_0_[4] )); FDPE \exp_seg_length_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[5]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg_n_0_[5] )); FDPE \exp_seg_length_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[6]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg_n_0_[6] )); FDPE \exp_seg_length_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E), .D(D[7]), .PRE(\exp_seg_length_q_reg[0]_0 ), .Q(\exp_seg_length_q_reg_n_0_[7] )); endmodule module btl_synchronisation_checker (sync_flag, sync_flag_reg_0, clk_sys_IBUF_BUFG, sync_flag_reg_1); output sync_flag; input sync_flag_reg_0; input clk_sys_IBUF_BUFG; input sync_flag_reg_1; wire clk_sys_IBUF_BUFG; wire sync_flag; wire sync_flag_reg_0; wire sync_flag_reg_1; FDCE sync_flag_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(sync_flag_reg_1), .D(sync_flag_reg_0), .Q(sync_flag)); endmodule module btl_top (mr_settings_ena_reg, sync_flag, rx_trig_req_q_reg, \FSM_onehot_current_state_reg[2] , CO, rx_trig_req_q_reg_0, rx_trig_req_q_reg_1, \FSM_onehot_current_state_reg[1] , is_tseg1, \FSM_onehot_current_state_reg[2]_0 , is_tseg2, rx_trig_req_q_reg_2, \FSM_onehot_current_state_reg[2]_1 , Q, \FSM_onehot_current_state_reg[1]_0 , \segm_counter_q_reg[5] , \segm_counter_q_reg[6] , \tq_counter_q_reg[7] , \tq_counter_q_reg[7]_0 , \FSM_onehot_current_state_reg[1]_1 , \FSM_onehot_current_state_reg[2]_2 , reg_q_reg, \FSM_onehot_current_state_reg[2]_3 , \FSM_onehot_current_state_reg[2]_4 , \FSM_onehot_current_state_reg[2]_5 , \FSM_onehot_current_state_reg[2]_6 , \FSM_onehot_current_state_reg[2]_7 , \FSM_onehot_current_state_reg[2]_8 , \FSM_onehot_current_state_reg[2]_9 , \FSM_onehot_current_state_reg[2]_10 , \FSM_onehot_current_state_reg[2]_11 , \FSM_onehot_current_state_reg[2]_12 , \segm_counter_q_reg[7] , \segm_counter_q_reg[6]_0 , current_state_reg, \mr_ctrl_out[settings_ena] , clk_sys_IBUF_BUFG, rx_trig_req_q_reg_3, sync_flag_reg, DI, S, \exp_seg_length_q[3]_i_11__0 , \exp_seg_length_q[3]_i_11__0_0 , \dst_ctr_q_reg[1] , \segm_counter_q_reg[0] , destuffed, \mr_ctrl_out[btr_fd_ph2_fd] , \exp_seg_length_q_reg[7] , \mr_ctrl_out[btr_ph2] , \tq_counter_q_reg[7]_1 , \tq_counter_q_reg[7]_2 , \exp_seg_length_q_reg[0] , reg_q_reg_0, reg_q_reg_1, \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] , \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 , \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] , \exp_seg_length_q[7]_i_11 , sync_edge, can_tx_OBUF, crc_data_tx_wbs, \mr_ctrl_out[mode_bmm] , O, i__carry_i_3__3, \mr_ctrl_out[btr_sjw] , neg_phase_err, \exp_seg_length_q_reg[3] , \exp_seg_length_q_reg[7]_0 , reg_q_reg_2, \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 , \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 , E, mr_btr_prop, \mr_ctrl_out[btr_ph1] , \tseg1_dbt_reg[0] , \tq_counter_q_reg[0] , \segm_counter_q_reg[0]_0 , \mr_ctrl_out[btr_fd_prop_fd] , \mr_ctrl_out[btr_fd_ph1_fd] , D, \tq_counter_q_reg[0]_0 , lopt); output mr_settings_ena_reg; output sync_flag; output rx_trig_req_q_reg; output \FSM_onehot_current_state_reg[2] ; output [0:0]CO; output rx_trig_req_q_reg_0; output rx_trig_req_q_reg_1; output \FSM_onehot_current_state_reg[1] ; output is_tseg1; output \FSM_onehot_current_state_reg[2]_0 ; output is_tseg2; output rx_trig_req_q_reg_2; output \FSM_onehot_current_state_reg[2]_1 ; output [3:0]Q; output \FSM_onehot_current_state_reg[1]_0 ; output [5:0]\segm_counter_q_reg[5] ; output [6:0]\segm_counter_q_reg[6] ; output [7:0]\tq_counter_q_reg[7] ; output [7:0]\tq_counter_q_reg[7]_0 ; output \FSM_onehot_current_state_reg[1]_1 ; output \FSM_onehot_current_state_reg[2]_2 ; output reg_q_reg; output \FSM_onehot_current_state_reg[2]_3 ; output \FSM_onehot_current_state_reg[2]_4 ; output \FSM_onehot_current_state_reg[2]_5 ; output \FSM_onehot_current_state_reg[2]_6 ; output \FSM_onehot_current_state_reg[2]_7 ; output \FSM_onehot_current_state_reg[2]_8 ; output \FSM_onehot_current_state_reg[2]_9 ; output \FSM_onehot_current_state_reg[2]_10 ; output \FSM_onehot_current_state_reg[2]_11 ; output \FSM_onehot_current_state_reg[2]_12 ; output [1:0]\segm_counter_q_reg[7] ; output [1:0]\segm_counter_q_reg[6]_0 ; output [0:0]current_state_reg; input \mr_ctrl_out[settings_ena] ; input clk_sys_IBUF_BUFG; input rx_trig_req_q_reg_3; input sync_flag_reg; input [0:0]DI; input [1:0]S; input [2:0]\exp_seg_length_q[3]_i_11__0 ; input [2:0]\exp_seg_length_q[3]_i_11__0_0 ; input \dst_ctr_q_reg[1] ; input \segm_counter_q_reg[0] ; input destuffed; input [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; input \exp_seg_length_q_reg[7] ; input [5:0]\mr_ctrl_out[btr_ph2] ; input \tq_counter_q_reg[7]_1 ; input \tq_counter_q_reg[7]_2 ; input \exp_seg_length_q_reg[0] ; input reg_q_reg_0; input reg_q_reg_1; input \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ; input \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ; input \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ; input [1:0]\exp_seg_length_q[7]_i_11 ; input sync_edge; input can_tx_OBUF; input crc_data_tx_wbs; input \mr_ctrl_out[mode_bmm] ; input [1:0]O; input [2:0]i__carry_i_3__3; input [4:0]\mr_ctrl_out[btr_sjw] ; input [7:0]neg_phase_err; input [3:0]\exp_seg_length_q_reg[3] ; input [0:0]\exp_seg_length_q_reg[7]_0 ; input reg_q_reg_2; input \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ; input \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ; input [0:0]E; input [6:0]mr_btr_prop; input [5:0]\mr_ctrl_out[btr_ph1] ; input [0:0]\tseg1_dbt_reg[0] ; input [0:0]\tq_counter_q_reg[0] ; input [0:0]\segm_counter_q_reg[0]_0 ; input [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; input [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; input [0:0]D; input [0:0]\tq_counter_q_reg[0]_0 ; output lopt; wire [0:0]CO; wire [0:0]D; wire [0:0]DI; wire [0:0]E; wire \FSM_onehot_current_state_reg[1] ; wire \FSM_onehot_current_state_reg[1]_0 ; wire \FSM_onehot_current_state_reg[1]_1 ; wire \FSM_onehot_current_state_reg[2] ; wire \FSM_onehot_current_state_reg[2]_0 ; wire \FSM_onehot_current_state_reg[2]_1 ; wire \FSM_onehot_current_state_reg[2]_10 ; wire \FSM_onehot_current_state_reg[2]_11 ; wire \FSM_onehot_current_state_reg[2]_12 ; wire \FSM_onehot_current_state_reg[2]_2 ; wire \FSM_onehot_current_state_reg[2]_3 ; wire \FSM_onehot_current_state_reg[2]_4 ; wire \FSM_onehot_current_state_reg[2]_5 ; wire \FSM_onehot_current_state_reg[2]_6 ; wire \FSM_onehot_current_state_reg[2]_7 ; wire \FSM_onehot_current_state_reg[2]_8 ; wire \FSM_onehot_current_state_reg[2]_9 ; wire [1:0]O; wire [3:0]Q; wire [1:0]S; wire [7:4]basic_segm_length; wire can_tx_OBUF; wire clk_sys_IBUF_BUFG; wire crc_data_tx_wbs; wire [0:0]current_state_reg; wire destuffed; wire \dst_ctr_q_reg[1] ; wire exit_segm_regular; wire exit_segm_regular_0; wire exp_seg_length_ce; wire [8:0]exp_seg_length_d; wire [1:0]exp_seg_length_q; wire [2:0]\exp_seg_length_q[3]_i_11__0 ; wire [2:0]\exp_seg_length_q[3]_i_11__0_0 ; wire [1:0]\exp_seg_length_q[7]_i_11 ; wire \exp_seg_length_q_reg[0] ; wire [3:0]\exp_seg_length_q_reg[3] ; wire \exp_seg_length_q_reg[7] ; wire [0:0]\exp_seg_length_q_reg[7]_0 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ; wire \g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ; wire \g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ; wire [2:0]i__carry_i_3__3; wire i_btl_cfg_capture_n_1; wire i_btl_cfg_capture_n_2; wire i_btl_cfg_capture_n_21; wire i_btl_counters_dbt_n_15; wire i_btl_counters_dbt_n_16; wire i_btl_counters_nbt_n_21; wire i_btl_counters_nbt_n_22; wire i_btl_counters_nbt_n_23; wire i_btl_counters_nbt_n_24; wire i_btl_counters_nbt_n_27; wire i_btl_counters_nbt_n_28; wire i_btl_counters_nbt_n_29; wire i_btl_counters_nbt_n_30; wire i_btl_counters_nbt_n_31; wire i_btl_counters_nbt_n_32; wire i_btl_counters_nbt_n_33; wire i_btl_counters_nbt_n_34; wire i_btl_fsm_n_10; wire i_btl_fsm_n_11; wire i_btl_fsm_n_12; wire i_btl_fsm_n_13; wire i_btl_fsm_n_23; wire i_btl_fsm_n_24; wire i_btl_fsm_n_27; wire i_btl_fsm_n_30; wire i_btl_fsm_n_31; wire i_btl_fsm_n_41; wire i_btl_fsm_n_43; wire i_btl_fsm_n_47; wire i_btl_fsm_n_48; wire i_btl_fsm_n_49; wire i_btl_fsm_n_6; wire i_btl_fsm_n_7; wire i_btl_fsm_n_8; wire i_btl_fsm_n_9; wire i_btl_segment_end_detector_n_0; wire i_btl_segment_end_detector_n_1; wire i_btl_segment_meter_dbt_n_2; wire i_btl_segment_meter_dbt_n_3; wire i_btl_segment_meter_dbt_n_4; wire i_btl_segment_meter_dbt_n_5; wire i_btl_segment_meter_nbt_n_10; wire i_btl_segment_meter_nbt_n_4; wire i_btl_segment_meter_nbt_n_5; wire i_btl_segment_meter_nbt_n_6; wire i_btl_segment_meter_nbt_n_7; wire i_btl_segment_meter_nbt_n_8; wire i_btl_segment_meter_nbt_n_9; wire is_tseg1; wire is_tseg2; wire lopt; wire [6:0]mr_btr_prop; wire [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; wire [5:0]\mr_ctrl_out[btr_ph1] ; wire [5:0]\mr_ctrl_out[btr_ph2] ; wire [4:0]\mr_ctrl_out[btr_sjw] ; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[settings_ena] ; wire mr_settings_ena_reg; wire [7:0]neg_phase_err; wire phase_err_mt_sjw; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire rx_trig_req_q_reg; wire rx_trig_req_q_reg_0; wire rx_trig_req_q_reg_1; wire rx_trig_req_q_reg_2; wire rx_trig_req_q_reg_3; wire [0:0]segm_counter_d; wire [7:6]segm_counter_q; wire \segm_counter_q_reg[0] ; wire [0:0]\segm_counter_q_reg[0]_0 ; wire [5:0]\segm_counter_q_reg[5] ; wire [6:0]\segm_counter_q_reg[6] ; wire [1:0]\segm_counter_q_reg[6]_0 ; wire [1:0]\segm_counter_q_reg[7] ; wire sync_edge; wire sync_flag; wire sync_flag_reg; wire [7:4]sync_segm_length; wire [0:0]\tq_counter_q_reg[0] ; wire [0:0]\tq_counter_q_reg[0]_0 ; wire [7:0]\tq_counter_q_reg[7] ; wire [7:0]\tq_counter_q_reg[7]_0 ; wire \tq_counter_q_reg[7]_1 ; wire \tq_counter_q_reg[7]_2 ; wire [6:0]tseg1_dbt; wire [0:0]\tseg1_dbt_reg[0] ; wire [7:0]tseg1_nbt; wire tx_trig_req_flag_q; btl_cfg_capture i_btl_cfg_capture (.D(D), .DI({i_btl_cfg_capture_n_1,i_btl_cfg_capture_n_2}), .E(exp_seg_length_ce), .Q({tseg1_dbt[6:5],Q,tseg1_dbt[0]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\exp_seg_length_q_reg[0] (\FSM_onehot_current_state_reg[1]_0 ), .\exp_seg_length_q_reg[0]_0 (\segm_counter_q_reg[0] ), .\exp_seg_length_q_reg[0]_1 (\exp_seg_length_q_reg[0] ), .\exp_seg_length_q_reg[7]_i_2 (i_btl_fsm_n_24), .\exp_seg_length_q_reg[7]_i_2__0 (\FSM_onehot_current_state_reg[2]_1 ), .mr_btr_prop(mr_btr_prop), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] ), .\mr_ctrl_out[btr_fd_prop_fd] (\mr_ctrl_out[btr_fd_prop_fd] ), .\mr_ctrl_out[btr_ph1] (\mr_ctrl_out[btr_ph1] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .mr_settings_ena_reg_2_reg_0(rx_trig_req_q_reg_3), .mr_settings_ena_reg_reg_0(mr_settings_ena_reg), .mr_settings_ena_reg_reg_1(i_btl_cfg_capture_n_21), .\tseg1_dbt_reg[0]_0 (\tseg1_dbt_reg[0] ), .\tseg1_nbt_reg[7]_0 (basic_segm_length[7:6]), .\tseg1_nbt_reg[7]_1 (tseg1_nbt)); btl_counters__parameterized0 i_btl_counters_dbt (.D(segm_counter_d), .DI(i_btl_counters_dbt_n_16), .O(O[1]), .Q(\segm_counter_q_reg[6] ), .S(i_btl_counters_dbt_n_15), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .exit_segm_regular_tseg11_carry({i_btl_segment_meter_dbt_n_4,i_btl_segment_meter_dbt_n_5}), .\exp_seg_length_d9_inferred__0/i__carry (is_tseg2), .\segm_counter_q_reg[0]_0 (\segm_counter_q_reg[0]_0 ), .\segm_counter_q_reg[0]_1 (rx_trig_req_q_reg_3), .\segm_counter_q_reg[6]_0 (\segm_counter_q_reg[6]_0 ), .\tq_counter_q_reg[0]_0 (\tq_counter_q_reg[0]_0 ), .\tq_counter_q_reg[7]_0 (\tq_counter_q_reg[7] ), .\tq_counter_q_reg[7]_1 (\FSM_onehot_current_state_reg[1]_0 ), .\tq_counter_q_reg[7]_2 (\segm_counter_q_reg[0] ), .\tq_counter_q_reg[7]_3 (\tq_counter_q_reg[7]_1 )); btl_counters i_btl_counters_nbt (.CO(i_btl_fsm_n_49), .D(exp_seg_length_d[8]), .DI({i_btl_counters_nbt_n_21,i_btl_counters_nbt_n_22}), .E(E), .\FSM_onehot_current_state_reg[2] (i_btl_counters_nbt_n_33), .O(sync_segm_length), .Q({segm_counter_q,\segm_counter_q_reg[5] }), .S(i_btl_counters_nbt_n_23), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .exit_segm_regular_tseg11_carry(exp_seg_length_q), .\exp_seg_length_q[3]_i_10 (\FSM_onehot_current_state_reg[2]_3 ), .\exp_seg_length_q[8]_i_5 (phase_err_mt_sjw), .\exp_seg_length_q[8]_i_5_0 (\FSM_onehot_current_state_reg[2]_2 ), .\exp_seg_length_q_reg[7] (basic_segm_length), .\exp_seg_length_q_reg[7]_0 ({i_btl_segment_meter_nbt_n_7,i_btl_segment_meter_nbt_n_8,i_btl_segment_meter_nbt_n_9,i_btl_segment_meter_nbt_n_10}), .\exp_seg_length_q_reg[8] (i_btl_fsm_n_23), .\exp_seg_length_q_reg[8]_0 (i_btl_fsm_n_47), .\g_bit[1].reg_value_r_reg[1] (i_btl_counters_nbt_n_27), .\g_bit[2].reg_value_r_reg[2] (i_btl_counters_nbt_n_29), .\g_bit[3].reg_value_r_reg[3] (i_btl_counters_nbt_n_30), .\g_bit[4].reg_value_r_reg[4] (i_btl_counters_nbt_n_31), .\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 (is_tseg2), .\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 (\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 ), .\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_1 (\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 ), .\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_2 (\exp_seg_length_q_reg[0] ), .\mr_ctrl_out[btr_sjw] (\mr_ctrl_out[btr_sjw] ), .neg_phase_err(neg_phase_err[7:4]), .\segm_counter_q_reg[0]_0 (i_btl_counters_nbt_n_34), .\segm_counter_q_reg[0]_1 (rx_trig_req_q_reg_3), .\segm_counter_q_reg[0]_2 (i_btl_fsm_n_27), .\segm_counter_q_reg[1]_0 (i_btl_counters_nbt_n_24), .\segm_counter_q_reg[5]_0 (i_btl_counters_nbt_n_32), .\segm_counter_q_reg[7]_0 (\segm_counter_q_reg[7] ), .\segm_counter_q_reg[7]_1 (i_btl_counters_nbt_n_28), .\tq_counter_q_reg[0]_0 (\tq_counter_q_reg[0] ), .\tq_counter_q_reg[7]_0 (\tq_counter_q_reg[7]_0 ), .\tq_counter_q_reg[7]_1 (\FSM_onehot_current_state_reg[1]_0 ), .\tq_counter_q_reg[7]_2 (\segm_counter_q_reg[0] ), .\tq_counter_q_reg[7]_3 (\tq_counter_q_reg[7]_2 )); btl_fsm i_btl_fsm (.CO(exit_segm_regular), .D({i_btl_fsm_n_6,i_btl_fsm_n_7,i_btl_fsm_n_8,i_btl_fsm_n_9,i_btl_fsm_n_10,i_btl_fsm_n_11,i_btl_fsm_n_12,i_btl_fsm_n_13}), .DI(i_btl_fsm_n_43), .\FSM_onehot_current_state_reg[0]_0 (current_state_reg), .\FSM_onehot_current_state_reg[0]_1 (rx_trig_req_q_reg_3), .\FSM_onehot_current_state_reg[1]_0 (\FSM_onehot_current_state_reg[1] ), .\FSM_onehot_current_state_reg[1]_1 (is_tseg1), .\FSM_onehot_current_state_reg[1]_2 (i_btl_fsm_n_23), .\FSM_onehot_current_state_reg[1]_3 (\FSM_onehot_current_state_reg[1]_0 ), .\FSM_onehot_current_state_reg[1]_4 (\FSM_onehot_current_state_reg[1]_1 ), .\FSM_onehot_current_state_reg[1]_5 (i_btl_segment_end_detector_n_0), .\FSM_onehot_current_state_reg[2]_0 (\FSM_onehot_current_state_reg[2]_0 ), .\FSM_onehot_current_state_reg[2]_1 (is_tseg2), .\FSM_onehot_current_state_reg[2]_10 (\FSM_onehot_current_state_reg[2]_6 ), .\FSM_onehot_current_state_reg[2]_11 (\FSM_onehot_current_state_reg[2]_7 ), .\FSM_onehot_current_state_reg[2]_12 (\FSM_onehot_current_state_reg[2]_8 ), .\FSM_onehot_current_state_reg[2]_13 (\FSM_onehot_current_state_reg[2]_9 ), .\FSM_onehot_current_state_reg[2]_14 (\FSM_onehot_current_state_reg[2]_10 ), .\FSM_onehot_current_state_reg[2]_15 (\FSM_onehot_current_state_reg[2]_11 ), .\FSM_onehot_current_state_reg[2]_16 (\FSM_onehot_current_state_reg[2]_12 ), .\FSM_onehot_current_state_reg[2]_17 (i_btl_fsm_n_47), .\FSM_onehot_current_state_reg[2]_18 (i_btl_fsm_n_48), .\FSM_onehot_current_state_reg[2]_19 (\FSM_onehot_current_state_reg[2] ), .\FSM_onehot_current_state_reg[2]_2 (\FSM_onehot_current_state_reg[2]_1 ), .\FSM_onehot_current_state_reg[2]_3 (i_btl_fsm_n_24), .\FSM_onehot_current_state_reg[2]_4 (i_btl_fsm_n_30), .\FSM_onehot_current_state_reg[2]_5 (i_btl_fsm_n_31), .\FSM_onehot_current_state_reg[2]_6 (\FSM_onehot_current_state_reg[2]_2 ), .\FSM_onehot_current_state_reg[2]_7 (\FSM_onehot_current_state_reg[2]_3 ), .\FSM_onehot_current_state_reg[2]_8 (\FSM_onehot_current_state_reg[2]_4 ), .\FSM_onehot_current_state_reg[2]_9 (\FSM_onehot_current_state_reg[2]_5 ), .O(sync_segm_length), .Q({tseg1_dbt[6:5],Q,tseg1_dbt[0]}), .S(i_btl_fsm_n_41), .can_tx_OBUF(can_tx_OBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_tx_wbs(crc_data_tx_wbs), .\dst_ctr_q_reg[1] (\dst_ctr_q_reg[1] ), .\exp_seg_length_q[7]_i_11 (\exp_seg_length_q[7]_i_11 ), .\exp_seg_length_q_reg[0] (i_btl_counters_nbt_n_28), .\exp_seg_length_q_reg[3] ({i_btl_segment_meter_nbt_n_4,i_btl_segment_meter_nbt_n_5,i_btl_segment_meter_nbt_n_6,i_btl_counters_nbt_n_34}), .\exp_seg_length_q_reg[3]_0 (\exp_seg_length_q_reg[3] ), .\exp_seg_length_q_reg[6] (i_btl_cfg_capture_n_21), .\exp_seg_length_q_reg[7] (\exp_seg_length_q_reg[7] ), .\exp_seg_length_q_reg[7]_0 (tseg1_nbt), .\exp_seg_length_q_reg[7]_1 ({i_btl_cfg_capture_n_1,i_btl_cfg_capture_n_2}), .\exp_seg_length_q_reg[7]_2 ({i_btl_segment_meter_dbt_n_2,i_btl_segment_meter_dbt_n_3,\exp_seg_length_q_reg[7]_0 }), .\g_bit[0].reg_value_r_reg[0] (i_btl_fsm_n_49), .\g_bit[2].reg_value_r_reg[2] (basic_segm_length[5:4]), .\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] (exit_segm_regular_0), .\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 (\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] ), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] (\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] ), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 (\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 ), .i__carry_i_3__3(i__carry_i_3__3), .\mr_ctrl_out[btr_fd_ph2_fd] (\mr_ctrl_out[btr_fd_ph2_fd] ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] ), .\mr_ctrl_out[btr_sjw] (\mr_ctrl_out[btr_sjw] [1:0]), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .neg_phase_err({neg_phase_err[5],neg_phase_err[3:0]}), .reg_q_reg(reg_q_reg), .reg_q_reg_0(reg_q_reg_0), .reg_q_reg_1(reg_q_reg_1), .reg_q_reg_2(i_btl_segment_end_detector_n_1), .reg_q_reg_3(i_btl_counters_nbt_n_33), .reg_q_reg_4(rx_trig_req_q_reg), .reg_q_reg_5(reg_q_reg_2), .rx_trig_req_q_reg(rx_trig_req_q_reg_0), .rx_trig_req_q_reg_0(rx_trig_req_q_reg_1), .\segm_counter_q_reg[0] (i_btl_fsm_n_27), .\segm_counter_q_reg[0]_0 (segm_counter_d), .\segm_counter_q_reg[0]_1 (\segm_counter_q_reg[0] ), .sync_edge(sync_edge), .sync_flag(sync_flag), .\test_probe[tx_trigger]_INST_0_i_16 ({\segm_counter_q_reg[5] [5],\segm_counter_q_reg[5] [3:0]}), .\test_probe[tx_trigger]_INST_0_i_3_0 (\exp_seg_length_q_reg[0] ), .\test_probe[tx_trigger]_INST_0_i_9 ({\segm_counter_q_reg[6] [6:5],\segm_counter_q_reg[6] [3:0]}), .\test_probe[tx_trigger]_INST_0_i_9_0 (O), .\tseg1_nbt_reg[7] (exp_seg_length_d[7:0]), .tx_trig_req_flag_q(tx_trig_req_flag_q)); btl_segment_end_detector i_btl_segment_end_detector (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_0 (i_btl_segment_end_detector_n_1), .\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_1 (i_btl_fsm_n_30), .\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1]_2 (rx_trig_req_q_reg_3), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 (i_btl_segment_end_detector_n_0), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_1 (\FSM_onehot_current_state_reg[1]_0 ), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_2 (i_btl_fsm_n_31), .is_tseg1(is_tseg1)); btl_segment_meter__parameterized0 i_btl_segment_meter_dbt (.CO(CO), .D({i_btl_fsm_n_6,i_btl_fsm_n_7,i_btl_fsm_n_8,i_btl_fsm_n_9,i_btl_fsm_n_10,i_btl_fsm_n_11,i_btl_fsm_n_12,i_btl_fsm_n_13}), .DI({i_btl_fsm_n_48,\exp_seg_length_q[3]_i_11__0 }), .E(exp_seg_length_ce), .Q(\segm_counter_q_reg[6] ), .S({i_btl_counters_dbt_n_15,\exp_seg_length_q[3]_i_11__0_0 }), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\exp_seg_length_q_reg[0]_0 (rx_trig_req_q_reg_3), .\exp_seg_length_q_reg[1]_0 ({i_btl_segment_meter_dbt_n_4,i_btl_segment_meter_dbt_n_5}), .\exp_seg_length_q_reg[7]_0 (exit_segm_regular), .\exp_seg_length_q_reg[7]_i_2__0 (\exp_seg_length_q_reg[7] ), .\exp_seg_length_q_reg[7]_i_2__0_0 (\FSM_onehot_current_state_reg[2]_3 ), .\exp_seg_length_q_reg[7]_i_2__0_1 (\FSM_onehot_current_state_reg[2]_1 ), .\exp_seg_length_q_reg[7]_i_2__0_2 (tseg1_dbt[6:5]), .\segm_counter_q_reg[6] ({i_btl_segment_meter_dbt_n_2,i_btl_segment_meter_dbt_n_3}), .\test_probe[tx_trigger]_INST_0_i_12 (i_btl_counters_dbt_n_16)); btl_segment_meter i_btl_segment_meter_nbt (.D(exp_seg_length_d), .DI({i_btl_counters_nbt_n_21,i_btl_counters_nbt_n_22,DI,i_btl_fsm_n_43}), .E(exp_seg_length_ce), .Q(exp_seg_length_q), .S({i_btl_counters_nbt_n_23,S,i_btl_fsm_n_41}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .exit_segm_regular_tseg11_carry_0({segm_counter_q,\segm_counter_q_reg[5] }), .exit_segm_regular_tseg11_carry__0_0(i_btl_counters_nbt_n_24), .\exp_seg_length_q_reg[0]_0 (rx_trig_req_q_reg_3), .\exp_seg_length_q_reg[3]_i_2 (i_btl_counters_nbt_n_27), .\exp_seg_length_q_reg[3]_i_2_0 (i_btl_counters_nbt_n_29), .\exp_seg_length_q_reg[3]_i_2_1 (i_btl_counters_nbt_n_30), .\exp_seg_length_q_reg[6]_0 (exit_segm_regular_0), .\exp_seg_length_q_reg[7]_i_2 (tseg1_nbt[7:1]), .\exp_seg_length_q_reg[7]_i_2_0 (i_btl_fsm_n_24), .\exp_seg_length_q_reg[7]_i_2_1 (i_btl_counters_nbt_n_31), .\exp_seg_length_q_reg[7]_i_2_2 (i_btl_counters_nbt_n_32), .\exp_seg_length_q_reg[7]_i_2_3 (i_btl_counters_nbt_n_28), .\exp_seg_length_q_reg[7]_i_2_4 (\FSM_onehot_current_state_reg[2]_3 ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] [5:1]), .\segm_counter_q_reg[7] (phase_err_mt_sjw), .\segm_counter_q_reg[7]_0 ({i_btl_segment_meter_nbt_n_7,i_btl_segment_meter_nbt_n_8,i_btl_segment_meter_nbt_n_9,i_btl_segment_meter_nbt_n_10}), .\tseg1_nbt_reg[3] ({i_btl_segment_meter_nbt_n_4,i_btl_segment_meter_nbt_n_5,i_btl_segment_meter_nbt_n_6})); btl_synchronisation_checker i_btl_synchronisation_checker (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .sync_flag(sync_flag), .sync_flag_reg_0(sync_flag_reg), .sync_flag_reg_1(rx_trig_req_q_reg_3)); btl_trigger_generator i_btl_trigger_generator (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .current_state_reg(current_state_reg), .destuffed(destuffed), .lopt(lopt), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .rx_trig_req_q_reg_0(rx_trig_req_q_reg), .rx_trig_req_q_reg_1(rx_trig_req_q_reg_2), .rx_trig_req_q_reg_2(\FSM_onehot_current_state_reg[2] ), .rx_trig_req_q_reg_3(rx_trig_req_q_reg_3), .tx_trig_req_flag_q(tx_trig_req_flag_q), .tx_trig_req_flag_q_reg_0(\FSM_onehot_current_state_reg[2]_0 ), .tx_trig_req_flag_q_reg_1(is_tseg2)); endmodule module btl_trigger_generator (rx_trig_req_q_reg_0, rx_trig_req_q_reg_1, tx_trig_req_flag_q, rx_trig_req_q_reg_2, clk_sys_IBUF_BUFG, rx_trig_req_q_reg_3, destuffed, tx_trig_req_flag_q_reg_0, tx_trig_req_flag_q_reg_1, \mr_ctrl_out[settings_ena] , current_state_reg, lopt); output rx_trig_req_q_reg_0; output rx_trig_req_q_reg_1; output tx_trig_req_flag_q; input rx_trig_req_q_reg_2; input clk_sys_IBUF_BUFG; input rx_trig_req_q_reg_3; input destuffed; input tx_trig_req_flag_q_reg_0; input tx_trig_req_flag_q_reg_1; input \mr_ctrl_out[settings_ena] ; input [0:0]current_state_reg; output lopt; wire clk_sys_IBUF_BUFG; wire [0:0]current_state_reg; wire destuffed; wire \mr_ctrl_out[settings_ena] ; wire rx_trig_req_q_reg_0; wire rx_trig_req_q_reg_1; wire rx_trig_req_q_reg_2; wire rx_trig_req_q_reg_3; wire rx_trig_req_q_reg_lopt_replica_1; wire tx_trig_req_flag_q; wire tx_trig_req_flag_q_i_1_n_0; wire tx_trig_req_flag_q_reg_0; wire tx_trig_req_flag_q_reg_1; assign lopt = rx_trig_req_q_reg_lopt_replica_1; FDCE rx_trig_req_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(rx_trig_req_q_reg_3), .D(rx_trig_req_q_reg_2), .Q(rx_trig_req_q_reg_0)); (* OPT_INSERTED_REPDRIVER *) (* OPT_MODIFIED = "RESYNTH_AREA" *) FDCE #( .INIT(1'b0)) rx_trig_req_q_reg_lopt_replica (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(rx_trig_req_q_reg_3), .D(rx_trig_req_q_reg_2), .Q(rx_trig_req_q_reg_lopt_replica_1)); LUT2 #( .INIT(4'h2)) \test_probe[rx_trigger_nbs]_INST_0_i_1 (.I0(rx_trig_req_q_reg_0), .I1(destuffed), .O(rx_trig_req_q_reg_1)); LUT6 #( .INIT(64'hFFFF0000F4440000)) tx_trig_req_flag_q_i_1 (.I0(tx_trig_req_flag_q_reg_0), .I1(tx_trig_req_flag_q_reg_1), .I2(\mr_ctrl_out[settings_ena] ), .I3(current_state_reg), .I4(rx_trig_req_q_reg_0), .I5(tx_trig_req_flag_q), .O(tx_trig_req_flag_q_i_1_n_0)); FDCE tx_trig_req_flag_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(rx_trig_req_q_reg_3), .D(tx_trig_req_flag_q_i_1_n_0), .Q(tx_trig_req_flag_q)); endmodule module control_registers_reg_map (\g_bit[0].reg_value_r_reg[0] , \mr_ctrl_out[mode_stm] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \mr_ctrl_out[mode_tttm] , \g_bit[0].reg_value_r_reg[0]_2 , \mr_ctrl_out[mode_acf] , \g_bit[0].reg_value_r_reg[0]_3 , \mr_ctrl_out[mode_rxbam] , \g_bit[0].reg_value_r_reg[0]_4 , \mr_ctrl_out[mode_sam] , \mr_ctrl_out[mode_erfm] , \mr_ctrl_out[settings_rtrle] , \g_bit[3].reg_value_r_reg[3] , \mr_ctrl_out[settings_ilbp] , \g_bit[0].reg_value_r_reg[0]_5 , \mr_ctrl_out[settings_nisofd] , \mr_ctrl_out[settings_pex] , \g_bit[0].reg_value_r_reg[0]_6 , \g_bit[0].reg_value_r_reg[0]_7 , \g_bit[0].reg_value_r_reg[0]_8 , mr_btr_prop, \mr_ctrl_out[btr_ph1] , DI, \mr_ctrl_out[btr_ph2] , \g_bit[0].reg_value_r_reg[0]_9 , \g_bit[1].reg_value_r_reg[1] , \g_bit[2].reg_value_r_reg[2] , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4] , \mr_ctrl_out[btr_fd_prop_fd] , \mr_ctrl_out[btr_fd_ph1_fd] , \g_bit[0].reg_value_r_reg[0]_10 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[0].reg_value_r_reg[0]_11 , \g_bit[1].reg_value_r_reg[1]_1 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_1 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5] , \g_bit[6].reg_value_r_reg[6] , \g_bit[7].reg_value_r_reg[7] , \g_bit[0].reg_value_r_reg[0]_12 , \g_bit[1].reg_value_r_reg[1]_2 , \g_bit[2].reg_value_r_reg[2]_1 , \g_bit[3].reg_value_r_reg[3]_2 , \g_bit[4].reg_value_r_reg[4]_1 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , \mr_ctrl_out[ctr_pres_ctpv] , \g_bit[0].reg_value_r_reg[0]_13 , \g_bit[0].reg_value_r_reg[0]_14 , \g_bit[0].reg_value_r_reg[0]_15 , \g_bit[0].reg_value_r_reg[0]_16 , \g_bit[0].reg_value_r_reg[0]_17 , \g_bit[0].reg_value_r_reg[0]_18 , \g_bit[0].reg_value_r_reg[0]_19 , \g_bit[0].reg_value_r_reg[0]_20 , \g_bit[0].reg_value_r_reg[0]_21 , \g_bit[0].reg_value_r_reg[0]_22 , \g_bit[0].reg_value_r_reg[0]_23 , \mr_ctrl_out[rx_settings_rtsop] , \g_bit[0].reg_value_r_reg[0]_24 , \g_bit[0].reg_value_r_reg[0]_25 , \mr_tx_priority[0] , \mr_tx_priority[1] , \mr_tx_priority[2] , \mr_tx_priority[3] , \mr_ctrl_out[ssp_cfg_ssp_offset] , \g_bit[0].reg_value_r_reg[0]_26 , \g_bit[1].reg_value_r_reg[1]_3 , \adress[2] , \adress[5] , \adress[3] , \timestamp[26] , \timestamp[27] , \timestamp[28] , \timestamp[61] , \timestamp[62] , \timestamp[63] , \adress[5]_0 , \g_bit[0].reg_value_r_reg[0]_27 , soft_res_d_n, \adress[8] , wr_en, wr_en_0, wr_en_1, wr_en_2, wr_en_3, wr_en_4, wr_en_5, \g_bit[6].reg_value_r_reg[6]_1 , \g_bit[0].reg_value_r_reg[0]_28 , \g_bit[1].reg_value_r_reg[1]_4 , \g_bit[4].reg_value_r_reg[4]_2 , \adress[4] , \g_bit[2].reg_value_r_reg[2]_2 , \g_bit[3].reg_value_r_reg[3]_3 , \g_bit[4].reg_value_r_reg[4]_3 , \g_bit[0].reg_value_r_reg[0]_29 , \adress[4]_0 , \g_bit[0].reg_value_r_reg[0]_30 , \g_bit[2].reg_value_r_reg[2]_3 , \g_bit[0].reg_value_r_reg[0]_31 , \adress[2]_0 , \adress[3]_0 , \g_bit[1].reg_value_r_reg[1]_5 , \g_bit[2].reg_value_r_reg[2]_4 , \g_bit[3].reg_value_r_reg[3]_4 , \g_bit[4].reg_value_r_reg[4]_4 , \mr_tst_out[tst_control_twrstb] , \g_bit[0].reg_value_r_reg[0]_32 , wr_en_6, \mr_ctrl_out[ctr_pres_ptx] , \mr_ctrl_out[ctr_pres_prx] , \mr_ctrl_out[ctr_pres_enorm] , \mr_ctrl_out[ctr_pres_efd] , E, \g_bit[0].reg_value_r_reg[0]_33 , \g_bit[0].reg_value_r_reg[0]_34 , \adress[5]_1 , \adress[5]_2 , \nom_err_ctr_q_reg[9] , \nom_err_ctr_q_reg[10] , \g_bit[3].reg_value_r_reg[3]_5 , \adress[4]_1 , \g_bit[0].reg_value_r_reg[0]_35 , \g_bit[1].reg_value_r_reg[1]_6 , \adress[6] , \timestamp[50] , \g_bit[2].reg_value_r_reg[2]_5 , \g_bit[1].reg_value_r_reg[1]_7 , \g_bit[0].reg_value_r_reg[0]_36 , \timestamp[44] , \g_bit[3].reg_value_r_reg[3]_6 , \g_bit[0].reg_value_r_reg[0]_37 , \timestamp[38] , \g_bit[4].reg_value_r_reg[4]_5 , \g_bit[2].reg_value_r_reg[2]_6 , \g_bit[1].reg_value_r_reg[1]_8 , \FSM_sequential_curr_state_reg[0] , \g_bit[0].reg_value_r_reg[0]_38 , abort_applied, \FSM_sequential_curr_state_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_39 , abort_applied_3, \txtb_hw_cmd_q_reg[lock] , \select_buf_index_reg_reg[0] , \FSM_sequential_curr_state_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_40 , \txtb_hw_cmd_q[err] , \g_bit[0].reg_value_r_reg[0]_41 , can_tx_OBUF, \g_bit[0].reg_value_r_reg[0]_42 , \g_bit[0].reg_value_r_reg[0]_43 , \g_bit[0].reg_value_r_reg[0]_44 , S, \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \g_bit[7].reg_value_r_reg[7]_3 , \segm_counter_q_reg[6] , \g_bit[0].reg_value_r_reg[0]_45 , \tq_counter_q_reg[6] , \g_bit[4].reg_value_r_reg[4]_6 , O, \segm_counter_q_reg[4] , \g_bit[4].reg_value_r_reg[4]_7 , \g_bit[0].reg_value_r_reg[0]_46 , \tq_counter_q_reg[7] , \g_bit[1].reg_value_r_reg[1]_9 , \g_bit[4].reg_value_r_reg[4]_8 , \g_bit[4].reg_value_r_reg[4]_9 , neg_phase_err, \g_bit[2].reg_value_r_reg[2]_7 , \g_bit[1].reg_value_r_reg[1]_10 , \g_bit[0].reg_value_r_reg[0]_47 , bit_err_d0_out, \g_bit[1].reg_value_r_reg[1]_11 , tx_command_txcr_valid, tx_command_txce_valid, tx_command_txcr_valid_4, tx_command_txce_valid_5, \adress[4]_2 , \adress[6]_0 , \g_bit[0].reg_value_r_reg[0]_48 , \g_bit[0].reg_value_r_reg[0]_49 , \g_bit[5].reg_value_r_reg[5]_1 , \g_bit[3].reg_value_r_reg[3]_7 , \g_bit[0].reg_value_r_reg[0]_50 , \select_buf_index_reg_reg[0]_0 , \FSM_onehot_current_state_reg[2] , \g_bit[0].reg_value_r_reg[0]_51 , \g_bit[0].reg_value_r_reg[0]_52 , \g_bit[0].reg_value_r_reg[0]_53 , \tseg1_dbt_reg[3] , \tseg1_dbt_reg[4] , Q, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[2].reg_value_r_reg[2]_8 , sbe_IBUF, adress_IBUF, \r_data_reg[25]_0 , \r_data_reg[23]_0 , \r_data_reg[23]_1 , \r_data_reg[22]_0 , \r_data_reg[22]_1 , \r_data_reg[7]_0 , timestamp_IBUF, \r_data_reg[3]_0 , \r_data_reg[5]_0 , \r_data_reg[5]_1 , \r_data_reg[5]_2 , \r_data_reg[5]_3 , \r_data_reg[12]_0 , \r_data_reg[21]_0 , \g_bit[2].reg_value_r_reg[2]_9 , \g_bit[0].reg_value_r_reg[0]_54 , \g_bit[0].reg_value_r_reg[0]_55 , swr_IBUF, \g_bit[0].reg_value_r_reg[0]_56 , \g_bit[7].reg_value_r_reg[7]_4 , \r_data_reg[3]_1 , \r_data_reg[3]_2 , \r_data_reg[12]_1 , \r_data_reg[7]_1 , \r_data_reg[7]_2 , \r_data_reg[31]_0 , \r_data_reg[12]_2 , \r_data_reg[21]_1 , \r_data_reg[21]_2 , \g_bit[0].reg_value_r_reg[0]_57 , \g_bit[0].reg_value_r_reg[0]_58 , srd_IBUF, scs_IBUF, \r_data[17]_i_2 , \FSM_sequential_curr_state_reg[2] , txtb_allow_bb, \FSM_sequential_curr_state[0]_i_2__0 , txtb_hw_cmd_cs, \FSM_sequential_curr_state[0]_i_2__0_0 , \FSM_sequential_curr_state[0]_i_2__2 , \txtb_hw_cmd[lock] , tran_frame_valid_com_reg, fsm_wait_state_q, fsm_wait_state_q_reg, \select_buf_index_reg_reg[1] , txtb_available, \select_buf_index_reg_reg[1]_0 , curr_state, \txtb_hw_cmd_q_reg[err] , crc_data_tx_wbs, \txtb_hw_cmd_q_reg[err]_0 , tran_frame_type, pc_rx_data_nbs, \err_capt_err_type_q[2]_i_13 , next_state2_carry, \next_state2_inferred__0/i__carry , \exp_seg_length_q[6]_i_2 , CO, \exp_seg_length_q[6]_i_2_0 , mr_settings_ena_reg, \segm_counter_q_reg[0] , \exp_seg_length_q[7]_i_11 , is_tseg2, \exp_seg_length_d9_inferred__0/i__carry , \test_probe[tx_trigger]_INST_0_i_9 , \test_probe[tx_trigger]_INST_0_i_9_0 , \exp_seg_length_d9_inferred__0/i__carry_0 , \segm_counter_q_reg[0]_0 , \test_probe[tx_trigger]_INST_0_i_7 , \exp_seg_length_d9_inferred__0/i__carry_1 , \test_probe[tx_trigger]_INST_0_i_7_0 , \exp_seg_length_d9_inferred__0/i__carry_2 , i__carry_i_9, current_state_reg, i__carry_i_2__4, \test_probe[tx_trigger]_INST_0_i_27 , bit_err_enable, bit_err_q_reg, bit_err_q_reg_0, bit_err_d2, rx_data_wbs, trv_delay_sum, mr_tx_command_txcr_q, mr_tx_command_txce_q, mr_tx_command_txca_q, \cc_stat[is_err_active] , \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 , \test_probe[tx_trigger]_INST_0_i_4 , \test_probe[tx_trigger]_INST_0_i_4_0 , \exp_seg_length_q_reg[7]_i_2__0 , \exp_seg_length_q_reg[7]_i_2__0_0 , D); output \g_bit[0].reg_value_r_reg[0] ; output \mr_ctrl_out[mode_stm] ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \mr_ctrl_out[mode_tttm] ; output \g_bit[0].reg_value_r_reg[0]_2 ; output \mr_ctrl_out[mode_acf] ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \mr_ctrl_out[mode_rxbam] ; output \g_bit[0].reg_value_r_reg[0]_4 ; output \mr_ctrl_out[mode_sam] ; output \mr_ctrl_out[mode_erfm] ; output \mr_ctrl_out[settings_rtrle] ; output [1:0]\g_bit[3].reg_value_r_reg[3] ; output \mr_ctrl_out[settings_ilbp] ; output \g_bit[0].reg_value_r_reg[0]_5 ; output \mr_ctrl_out[settings_nisofd] ; output \mr_ctrl_out[settings_pex] ; output \g_bit[0].reg_value_r_reg[0]_6 ; output \g_bit[0].reg_value_r_reg[0]_7 ; output \g_bit[0].reg_value_r_reg[0]_8 ; output [6:0]mr_btr_prop; output [5:0]\mr_ctrl_out[btr_ph1] ; output [3:0]DI; output [1:0]\mr_ctrl_out[btr_ph2] ; output \g_bit[0].reg_value_r_reg[0]_9 ; output \g_bit[1].reg_value_r_reg[1] ; output \g_bit[2].reg_value_r_reg[2] ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4] ; output [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; output [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; output [3:0]\g_bit[0].reg_value_r_reg[0]_10 ; output [0:0]\g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[0].reg_value_r_reg[0]_11 ; output \g_bit[1].reg_value_r_reg[1]_1 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_1 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5] ; output \g_bit[6].reg_value_r_reg[6] ; output \g_bit[7].reg_value_r_reg[7] ; output \g_bit[0].reg_value_r_reg[0]_12 ; output \g_bit[1].reg_value_r_reg[1]_2 ; output \g_bit[2].reg_value_r_reg[2]_1 ; output \g_bit[3].reg_value_r_reg[3]_2 ; output \g_bit[4].reg_value_r_reg[4]_1 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; output \g_bit[0].reg_value_r_reg[0]_13 ; output \g_bit[0].reg_value_r_reg[0]_14 ; output \g_bit[0].reg_value_r_reg[0]_15 ; output \g_bit[0].reg_value_r_reg[0]_16 ; output \g_bit[0].reg_value_r_reg[0]_17 ; output \g_bit[0].reg_value_r_reg[0]_18 ; output \g_bit[0].reg_value_r_reg[0]_19 ; output \g_bit[0].reg_value_r_reg[0]_20 ; output \g_bit[0].reg_value_r_reg[0]_21 ; output \g_bit[0].reg_value_r_reg[0]_22 ; output \g_bit[0].reg_value_r_reg[0]_23 ; output \mr_ctrl_out[rx_settings_rtsop] ; output \g_bit[0].reg_value_r_reg[0]_24 ; output \g_bit[0].reg_value_r_reg[0]_25 ; output [2:0]\mr_tx_priority[0] ; output [2:0]\mr_tx_priority[1] ; output [2:0]\mr_tx_priority[2] ; output [2:0]\mr_tx_priority[3] ; output [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; output \g_bit[0].reg_value_r_reg[0]_26 ; output \g_bit[1].reg_value_r_reg[1]_3 ; output \adress[2] ; output \adress[5] ; output \adress[3] ; output \timestamp[26] ; output \timestamp[27] ; output \timestamp[28] ; output \timestamp[61] ; output \timestamp[62] ; output \timestamp[63] ; output \adress[5]_0 ; output \g_bit[0].reg_value_r_reg[0]_27 ; output soft_res_d_n; output \adress[8] ; output wr_en; output wr_en_0; output wr_en_1; output wr_en_2; output wr_en_3; output wr_en_4; output wr_en_5; output \g_bit[6].reg_value_r_reg[6]_1 ; output \g_bit[0].reg_value_r_reg[0]_28 ; output \g_bit[1].reg_value_r_reg[1]_4 ; output \g_bit[4].reg_value_r_reg[4]_2 ; output \adress[4] ; output \g_bit[2].reg_value_r_reg[2]_2 ; output \g_bit[3].reg_value_r_reg[3]_3 ; output \g_bit[4].reg_value_r_reg[4]_3 ; output \g_bit[0].reg_value_r_reg[0]_29 ; output \adress[4]_0 ; output \g_bit[0].reg_value_r_reg[0]_30 ; output \g_bit[2].reg_value_r_reg[2]_3 ; output \g_bit[0].reg_value_r_reg[0]_31 ; output \adress[2]_0 ; output \adress[3]_0 ; output \g_bit[1].reg_value_r_reg[1]_5 ; output \g_bit[2].reg_value_r_reg[2]_4 ; output \g_bit[3].reg_value_r_reg[3]_4 ; output \g_bit[4].reg_value_r_reg[4]_4 ; output \mr_tst_out[tst_control_twrstb] ; output \g_bit[0].reg_value_r_reg[0]_32 ; output wr_en_6; output \mr_ctrl_out[ctr_pres_ptx] ; output \mr_ctrl_out[ctr_pres_prx] ; output \mr_ctrl_out[ctr_pres_enorm] ; output \mr_ctrl_out[ctr_pres_efd] ; output [0:0]E; output \g_bit[0].reg_value_r_reg[0]_33 ; output \g_bit[0].reg_value_r_reg[0]_34 ; output \adress[5]_1 ; output \adress[5]_2 ; output \nom_err_ctr_q_reg[9] ; output \nom_err_ctr_q_reg[10] ; output \g_bit[3].reg_value_r_reg[3]_5 ; output \adress[4]_1 ; output \g_bit[0].reg_value_r_reg[0]_35 ; output \g_bit[1].reg_value_r_reg[1]_6 ; output \adress[6] ; output \timestamp[50] ; output \g_bit[2].reg_value_r_reg[2]_5 ; output \g_bit[1].reg_value_r_reg[1]_7 ; output \g_bit[0].reg_value_r_reg[0]_36 ; output \timestamp[44] ; output \g_bit[3].reg_value_r_reg[3]_6 ; output \g_bit[0].reg_value_r_reg[0]_37 ; output \timestamp[38] ; output \g_bit[4].reg_value_r_reg[4]_5 ; output \g_bit[2].reg_value_r_reg[2]_6 ; output \g_bit[1].reg_value_r_reg[1]_8 ; output \FSM_sequential_curr_state_reg[0] ; output \g_bit[0].reg_value_r_reg[0]_38 ; output abort_applied; output \FSM_sequential_curr_state_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_39 ; output abort_applied_3; output \txtb_hw_cmd_q_reg[lock] ; output \select_buf_index_reg_reg[0] ; output [1:0]\FSM_sequential_curr_state_reg[0]_1 ; output \g_bit[0].reg_value_r_reg[0]_40 ; output \txtb_hw_cmd_q[err] ; output \g_bit[0].reg_value_r_reg[0]_41 ; output can_tx_OBUF; output \g_bit[0].reg_value_r_reg[0]_42 ; output \g_bit[0].reg_value_r_reg[0]_43 ; output \g_bit[0].reg_value_r_reg[0]_44 ; output [3:0]S; output [3:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [3:0]\g_bit[7].reg_value_r_reg[7]_2 ; output [3:0]\g_bit[7].reg_value_r_reg[7]_3 ; output \segm_counter_q_reg[6] ; output [0:0]\g_bit[0].reg_value_r_reg[0]_45 ; output \tq_counter_q_reg[6] ; output \g_bit[4].reg_value_r_reg[4]_6 ; output [1:0]O; output [2:0]\segm_counter_q_reg[4] ; output [2:0]\g_bit[4].reg_value_r_reg[4]_7 ; output [2:0]\g_bit[0].reg_value_r_reg[0]_46 ; output \tq_counter_q_reg[7] ; output \g_bit[1].reg_value_r_reg[1]_9 ; output \g_bit[4].reg_value_r_reg[4]_8 ; output [1:0]\g_bit[4].reg_value_r_reg[4]_9 ; output [7:0]neg_phase_err; output [0:0]\g_bit[2].reg_value_r_reg[2]_7 ; output \g_bit[1].reg_value_r_reg[1]_10 ; output \g_bit[0].reg_value_r_reg[0]_47 ; output bit_err_d0_out; output [8:0]\g_bit[1].reg_value_r_reg[1]_11 ; output tx_command_txcr_valid; output tx_command_txce_valid; output tx_command_txcr_valid_4; output tx_command_txce_valid_5; output \adress[4]_2 ; output \adress[6]_0 ; output \g_bit[0].reg_value_r_reg[0]_48 ; output \g_bit[0].reg_value_r_reg[0]_49 ; output \g_bit[5].reg_value_r_reg[5]_1 ; output \g_bit[3].reg_value_r_reg[3]_7 ; output \g_bit[0].reg_value_r_reg[0]_50 ; output \select_buf_index_reg_reg[0]_0 ; output \FSM_onehot_current_state_reg[2] ; output \g_bit[0].reg_value_r_reg[0]_51 ; output \g_bit[0].reg_value_r_reg[0]_52 ; output [0:0]\g_bit[0].reg_value_r_reg[0]_53 ; output [3:0]\tseg1_dbt_reg[3] ; output [0:0]\tseg1_dbt_reg[4] ; output [31:0]Q; input [31:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[2].reg_value_r_reg[2]_8 ; input [3:0]sbe_IBUF; input [9:0]adress_IBUF; input \r_data_reg[25]_0 ; input \r_data_reg[23]_0 ; input \r_data_reg[23]_1 ; input \r_data_reg[22]_0 ; input \r_data_reg[22]_1 ; input \r_data_reg[7]_0 ; input [31:0]timestamp_IBUF; input \r_data_reg[3]_0 ; input \r_data_reg[5]_0 ; input \r_data_reg[5]_1 ; input \r_data_reg[5]_2 ; input \r_data_reg[5]_3 ; input \r_data_reg[12]_0 ; input \r_data_reg[21]_0 ; input \g_bit[2].reg_value_r_reg[2]_9 ; input \g_bit[0].reg_value_r_reg[0]_54 ; input \g_bit[0].reg_value_r_reg[0]_55 ; input swr_IBUF; input \g_bit[0].reg_value_r_reg[0]_56 ; input \g_bit[7].reg_value_r_reg[7]_4 ; input \r_data_reg[3]_1 ; input \r_data_reg[3]_2 ; input [2:0]\r_data_reg[12]_1 ; input \r_data_reg[7]_1 ; input \r_data_reg[7]_2 ; input [6:0]\r_data_reg[31]_0 ; input \r_data_reg[12]_2 ; input \r_data_reg[21]_1 ; input [0:0]\r_data_reg[21]_2 ; input \g_bit[0].reg_value_r_reg[0]_57 ; input \g_bit[0].reg_value_r_reg[0]_58 ; input srd_IBUF; input scs_IBUF; input [0:0]\r_data[17]_i_2 ; input [1:0]\FSM_sequential_curr_state_reg[2] ; input [1:0]txtb_allow_bb; input \FSM_sequential_curr_state[0]_i_2__0 ; input [1:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state[0]_i_2__0_0 ; input \FSM_sequential_curr_state[0]_i_2__2 ; input \txtb_hw_cmd[lock] ; input tran_frame_valid_com_reg; input fsm_wait_state_q; input [1:0]fsm_wait_state_q_reg; input \select_buf_index_reg_reg[1] ; input [3:0]txtb_available; input \select_buf_index_reg_reg[1]_0 ; input [1:0]curr_state; input \txtb_hw_cmd_q_reg[err] ; input crc_data_tx_wbs; input [3:0]\txtb_hw_cmd_q_reg[err]_0 ; input tran_frame_type; input pc_rx_data_nbs; input [0:0]\err_capt_err_type_q[2]_i_13 ; input [7:0]next_state2_carry; input [7:0]\next_state2_inferred__0/i__carry ; input \exp_seg_length_q[6]_i_2 ; input [0:0]CO; input \exp_seg_length_q[6]_i_2_0 ; input mr_settings_ena_reg; input [7:0]\segm_counter_q_reg[0] ; input [6:0]\exp_seg_length_q[7]_i_11 ; input is_tseg2; input \exp_seg_length_d9_inferred__0/i__carry ; input \test_probe[tx_trigger]_INST_0_i_9 ; input \test_probe[tx_trigger]_INST_0_i_9_0 ; input \exp_seg_length_d9_inferred__0/i__carry_0 ; input [7:0]\segm_counter_q_reg[0]_0 ; input \test_probe[tx_trigger]_INST_0_i_7 ; input \exp_seg_length_d9_inferred__0/i__carry_1 ; input \test_probe[tx_trigger]_INST_0_i_7_0 ; input \exp_seg_length_d9_inferred__0/i__carry_2 ; input [5:0]i__carry_i_9; input [0:0]current_state_reg; input [1:0]i__carry_i_2__4; input [1:0]\test_probe[tx_trigger]_INST_0_i_27 ; input bit_err_enable; input bit_err_q_reg; input bit_err_q_reg_0; input bit_err_d2; input rx_data_wbs; input [8:0]trv_delay_sum; input mr_tx_command_txcr_q; input mr_tx_command_txce_q; input mr_tx_command_txca_q; input \cc_stat[is_err_active] ; input \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 ; input \test_probe[tx_trigger]_INST_0_i_4 ; input \test_probe[tx_trigger]_INST_0_i_4_0 ; input [3:0]\exp_seg_length_q_reg[7]_i_2__0 ; input \exp_seg_length_q_reg[7]_i_2__0_0 ; input [23:0]D; wire [0:0]CO; wire [23:0]D; wire [3:0]DI; wire [0:0]E; wire \FSM_onehot_current_state_reg[2] ; wire \FSM_sequential_curr_state[0]_i_2__0 ; wire \FSM_sequential_curr_state[0]_i_2__0_0 ; wire \FSM_sequential_curr_state[0]_i_2__2 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire [1:0]\FSM_sequential_curr_state_reg[0]_1 ; wire [1:0]\FSM_sequential_curr_state_reg[2] ; wire [1:0]O; wire [31:0]Q; wire [3:0]S; wire abort_applied; wire abort_applied_3; wire \adress[2] ; wire \adress[2]_0 ; wire \adress[3] ; wire \adress[3]_0 ; wire \adress[4] ; wire \adress[4]_0 ; wire \adress[4]_1 ; wire \adress[4]_2 ; wire \adress[5] ; wire \adress[5]_0 ; wire \adress[5]_1 ; wire \adress[5]_2 ; wire \adress[6] ; wire \adress[6]_0 ; wire \adress[8] ; wire [9:0]adress_IBUF; wire bit_err_d0_out; wire bit_err_d2; wire bit_err_enable; wire bit_err_q_reg; wire bit_err_q_reg_0; wire can_tx_OBUF; wire \cc_stat[is_err_active] ; wire clk_sys_IBUF_BUFG; wire crc_data_tx_wbs; wire [1:0]curr_state; wire [0:0]current_state_reg; wire [31:0]data_in_IBUF; wire [0:0]\err_capt_err_type_q[2]_i_13 ; wire \exp_seg_length_d9_inferred__0/i__carry ; wire \exp_seg_length_d9_inferred__0/i__carry_0 ; wire \exp_seg_length_d9_inferred__0/i__carry_1 ; wire \exp_seg_length_d9_inferred__0/i__carry_2 ; wire \exp_seg_length_q[6]_i_2 ; wire \exp_seg_length_q[6]_i_2_0 ; wire [6:0]\exp_seg_length_q[7]_i_11 ; wire [3:0]\exp_seg_length_q_reg[7]_i_2__0 ; wire \exp_seg_length_q_reg[7]_i_2__0_0 ; wire fsm_wait_state_q; wire [1:0]fsm_wait_state_q_reg; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire [3:0]\g_bit[0].reg_value_r_reg[0]_10 ; wire \g_bit[0].reg_value_r_reg[0]_11 ; wire \g_bit[0].reg_value_r_reg[0]_12 ; wire \g_bit[0].reg_value_r_reg[0]_13 ; wire \g_bit[0].reg_value_r_reg[0]_14 ; wire \g_bit[0].reg_value_r_reg[0]_15 ; wire \g_bit[0].reg_value_r_reg[0]_16 ; wire \g_bit[0].reg_value_r_reg[0]_17 ; wire \g_bit[0].reg_value_r_reg[0]_18 ; wire \g_bit[0].reg_value_r_reg[0]_19 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_20 ; wire \g_bit[0].reg_value_r_reg[0]_21 ; wire \g_bit[0].reg_value_r_reg[0]_22 ; wire \g_bit[0].reg_value_r_reg[0]_23 ; wire \g_bit[0].reg_value_r_reg[0]_24 ; wire \g_bit[0].reg_value_r_reg[0]_25 ; wire \g_bit[0].reg_value_r_reg[0]_26 ; wire \g_bit[0].reg_value_r_reg[0]_27 ; wire \g_bit[0].reg_value_r_reg[0]_28 ; wire \g_bit[0].reg_value_r_reg[0]_29 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_30 ; wire \g_bit[0].reg_value_r_reg[0]_31 ; wire \g_bit[0].reg_value_r_reg[0]_32 ; wire \g_bit[0].reg_value_r_reg[0]_33 ; wire \g_bit[0].reg_value_r_reg[0]_34 ; wire \g_bit[0].reg_value_r_reg[0]_35 ; wire \g_bit[0].reg_value_r_reg[0]_36 ; wire \g_bit[0].reg_value_r_reg[0]_37 ; wire \g_bit[0].reg_value_r_reg[0]_38 ; wire \g_bit[0].reg_value_r_reg[0]_39 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[0].reg_value_r_reg[0]_40 ; wire \g_bit[0].reg_value_r_reg[0]_41 ; wire \g_bit[0].reg_value_r_reg[0]_42 ; wire \g_bit[0].reg_value_r_reg[0]_43 ; wire \g_bit[0].reg_value_r_reg[0]_44 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_45 ; wire [2:0]\g_bit[0].reg_value_r_reg[0]_46 ; wire \g_bit[0].reg_value_r_reg[0]_47 ; wire \g_bit[0].reg_value_r_reg[0]_48 ; wire \g_bit[0].reg_value_r_reg[0]_49 ; wire \g_bit[0].reg_value_r_reg[0]_5 ; wire \g_bit[0].reg_value_r_reg[0]_50 ; wire \g_bit[0].reg_value_r_reg[0]_51 ; wire \g_bit[0].reg_value_r_reg[0]_52 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_53 ; wire \g_bit[0].reg_value_r_reg[0]_54 ; wire \g_bit[0].reg_value_r_reg[0]_55 ; wire \g_bit[0].reg_value_r_reg[0]_56 ; wire \g_bit[0].reg_value_r_reg[0]_57 ; wire \g_bit[0].reg_value_r_reg[0]_58 ; wire \g_bit[0].reg_value_r_reg[0]_6 ; wire \g_bit[0].reg_value_r_reg[0]_7 ; wire \g_bit[0].reg_value_r_reg[0]_8 ; wire \g_bit[0].reg_value_r_reg[0]_9 ; wire \g_bit[1].reg_value_r_reg[1] ; wire [0:0]\g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[1].reg_value_r_reg[1]_1 ; wire \g_bit[1].reg_value_r_reg[1]_10 ; wire [8:0]\g_bit[1].reg_value_r_reg[1]_11 ; wire \g_bit[1].reg_value_r_reg[1]_2 ; wire \g_bit[1].reg_value_r_reg[1]_3 ; wire \g_bit[1].reg_value_r_reg[1]_4 ; wire \g_bit[1].reg_value_r_reg[1]_5 ; wire \g_bit[1].reg_value_r_reg[1]_6 ; wire \g_bit[1].reg_value_r_reg[1]_7 ; wire \g_bit[1].reg_value_r_reg[1]_8 ; wire \g_bit[1].reg_value_r_reg[1]_9 ; wire \g_bit[2].reg_value_r_reg[2] ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire \g_bit[2].reg_value_r_reg[2]_2 ; wire \g_bit[2].reg_value_r_reg[2]_3 ; wire \g_bit[2].reg_value_r_reg[2]_4 ; wire \g_bit[2].reg_value_r_reg[2]_5 ; wire \g_bit[2].reg_value_r_reg[2]_6 ; wire [0:0]\g_bit[2].reg_value_r_reg[2]_7 ; wire \g_bit[2].reg_value_r_reg[2]_8 ; wire \g_bit[2].reg_value_r_reg[2]_9 ; wire [1:0]\g_bit[3].reg_value_r_reg[3] ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[3].reg_value_r_reg[3]_2 ; wire \g_bit[3].reg_value_r_reg[3]_3 ; wire \g_bit[3].reg_value_r_reg[3]_4 ; wire \g_bit[3].reg_value_r_reg[3]_5 ; wire \g_bit[3].reg_value_r_reg[3]_6 ; wire \g_bit[3].reg_value_r_reg[3]_7 ; wire \g_bit[4].reg_value_r_reg[4] ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire \g_bit[4].reg_value_r_reg[4]_2 ; wire \g_bit[4].reg_value_r_reg[4]_3 ; wire \g_bit[4].reg_value_r_reg[4]_4 ; wire \g_bit[4].reg_value_r_reg[4]_5 ; wire \g_bit[4].reg_value_r_reg[4]_6 ; wire [2:0]\g_bit[4].reg_value_r_reg[4]_7 ; wire \g_bit[4].reg_value_r_reg[4]_8 ; wire [1:0]\g_bit[4].reg_value_r_reg[4]_9 ; wire \g_bit[5].reg_value_r_reg[5] ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[5].reg_value_r_reg[5]_1 ; wire \g_bit[6].reg_value_r_reg[6] ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[6].reg_value_r_reg[6]_1 ; wire \g_bit[7].reg_value_r_reg[7] ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire \g_bit[7].reg_value_r_reg[7]_4 ; wire \g_tx_command_txb4_t.i_tx_command_txb4_reg_n_0 ; wire \g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg_n_8 ; wire \g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg_n_9 ; wire [1:0]i__carry_i_2__4; wire [5:0]i__carry_i_9; wire \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 ; wire i_btr_brp_slice_1_reg_n_5; wire i_btr_brp_slice_1_reg_n_6; wire i_btr_brp_slice_1_reg_n_7; wire i_btr_brp_slice_2_reg_n_1; wire i_btr_fd_brp_fd_slice_1_reg_n_5; wire i_btr_fd_brp_fd_slice_1_reg_n_6; wire i_btr_fd_ph2_fd_slice_1_reg_n_3; wire i_btr_fd_ph2_fd_slice_1_reg_n_7; wire i_btr_fd_ph2_fd_slice_2_reg_n_5; wire i_btr_fd_ph2_fd_slice_2_reg_n_7; wire i_btr_fd_sjw_fd_reg_n_6; wire i_btr_fd_sjw_fd_reg_n_7; wire i_btr_ph1_slice_2_reg_n_5; wire i_btr_ph2_slice_1_reg_n_6; wire i_btr_ph2_slice_2_reg_n_10; wire i_btr_ph2_slice_2_reg_n_8; wire i_mode_txbbm_reg_n_5; wire i_mode_txbbm_reg_n_6; wire i_mode_txbbm_reg_n_7; wire i_settings_ena_reg_n_10; wire i_settings_ena_reg_n_2; wire i_settings_ena_reg_n_6; wire i_ssp_cfg_ssp_offset_reg_n_11; wire i_ssp_cfg_ssp_offset_reg_n_13; wire i_ssp_cfg_ssp_src_reg_n_14; wire i_ssp_cfg_ssp_src_reg_n_4; wire i_tx_command_txb2_reg_n_0; wire i_tx_priority_txt1p_reg_n_4; wire i_tx_priority_txt1p_reg_n_5; wire i_tx_priority_txt1p_reg_n_6; wire is_tseg2; wire [6:0]mr_btr_prop; wire [5:0]\mr_ctrl_out[btr_brp] ; wire [7:5]\mr_ctrl_out[btr_fd_brp_fd] ; wire [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; wire [4:0]\mr_ctrl_out[btr_fd_sjw_fd] ; wire [5:0]\mr_ctrl_out[btr_ph1] ; wire [1:0]\mr_ctrl_out[btr_ph2] ; wire [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire \mr_ctrl_out[mode_acf] ; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_rxbam] ; wire \mr_ctrl_out[mode_sam] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[mode_tttm] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_ctrl_out[settings_rtrle] ; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire mr_settings_ena_reg; wire \mr_tst_out[tst_control_twrstb] ; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txcr_q; wire [2:0]\mr_tx_priority[0] ; wire [2:0]\mr_tx_priority[1] ; wire [2:0]\mr_tx_priority[2] ; wire [2:0]\mr_tx_priority[3] ; wire [7:0]neg_phase_err; wire [7:0]next_state2_carry; wire [7:0]\next_state2_inferred__0/i__carry ; wire \nom_err_ctr_q_reg[10] ; wire \nom_err_ctr_q_reg[9] ; wire [25:3]p_0_in; wire pc_rx_data_nbs; wire [0:0]\r_data[17]_i_2 ; wire \r_data[17]_i_9_n_0 ; wire \r_data[27]_i_6_n_0 ; wire \r_data[7]_i_4__0_n_0 ; wire \r_data_reg[12]_0 ; wire [2:0]\r_data_reg[12]_1 ; wire \r_data_reg[12]_2 ; wire \r_data_reg[21]_0 ; wire \r_data_reg[21]_1 ; wire [0:0]\r_data_reg[21]_2 ; wire \r_data_reg[22]_0 ; wire \r_data_reg[22]_1 ; wire \r_data_reg[23]_0 ; wire \r_data_reg[23]_1 ; wire \r_data_reg[25]_0 ; wire [6:0]\r_data_reg[31]_0 ; wire \r_data_reg[3]_0 ; wire \r_data_reg[3]_1 ; wire \r_data_reg[3]_2 ; wire \r_data_reg[5]_0 ; wire \r_data_reg[5]_1 ; wire \r_data_reg[5]_2 ; wire \r_data_reg[5]_3 ; wire \r_data_reg[7]_0 ; wire \r_data_reg[7]_1 ; wire \r_data_reg[7]_2 ; wire rx_data_wbs; wire [3:0]sbe_IBUF; wire scs_IBUF; wire [7:0]\segm_counter_q_reg[0] ; wire [7:0]\segm_counter_q_reg[0]_0 ; wire [2:0]\segm_counter_q_reg[4] ; wire \segm_counter_q_reg[6] ; wire \select_buf_index_reg_reg[0] ; wire \select_buf_index_reg_reg[0]_0 ; wire \select_buf_index_reg_reg[1] ; wire \select_buf_index_reg_reg[1]_0 ; wire soft_res_d_n; wire srd_IBUF; wire swr_IBUF; wire [1:0]\test_probe[tx_trigger]_INST_0_i_27 ; wire \test_probe[tx_trigger]_INST_0_i_4 ; wire \test_probe[tx_trigger]_INST_0_i_4_0 ; wire \test_probe[tx_trigger]_INST_0_i_7 ; wire \test_probe[tx_trigger]_INST_0_i_7_0 ; wire \test_probe[tx_trigger]_INST_0_i_9 ; wire \test_probe[tx_trigger]_INST_0_i_9_0 ; wire \timestamp[26] ; wire \timestamp[27] ; wire \timestamp[28] ; wire \timestamp[38] ; wire \timestamp[44] ; wire \timestamp[50] ; wire \timestamp[61] ; wire \timestamp[62] ; wire \timestamp[63] ; wire [31:0]timestamp_IBUF; wire \tq_counter_q_reg[6] ; wire \tq_counter_q_reg[7] ; wire tran_frame_type; wire tran_frame_valid_com_reg; wire [8:0]trv_delay_sum; wire [3:0]\tseg1_dbt_reg[3] ; wire [0:0]\tseg1_dbt_reg[4] ; wire tx_command_txce_valid; wire tx_command_txce_valid_5; wire tx_command_txcr_valid; wire tx_command_txcr_valid_4; wire [1:0]txtb_allow_bb; wire [3:0]txtb_available; wire \txtb_hw_cmd[lock] ; wire [1:0]txtb_hw_cmd_cs; wire \txtb_hw_cmd_q[err] ; wire \txtb_hw_cmd_q_reg[err] ; wire [3:0]\txtb_hw_cmd_q_reg[err]_0 ; wire \txtb_hw_cmd_q_reg[lock] ; wire wr_en; wire wr_en_0; wire wr_en_1; wire wr_en_10; wire wr_en_11; wire wr_en_12; wire wr_en_13; wire wr_en_14; wire wr_en_15; wire wr_en_16; wire wr_en_17; wire wr_en_18; wire wr_en_19; wire wr_en_2; wire wr_en_20; wire wr_en_21; wire wr_en_22; wire wr_en_23; wire wr_en_24; wire wr_en_25; wire wr_en_26; wire wr_en_3; wire wr_en_4; wire wr_en_5; wire wr_en_6; wire wr_en_7; wire wr_en_8; wire wr_en_9; memory_reg_rw \g_tx_command_txb3_t.i_tx_command_txb3_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[10]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_25 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_7)); memory_reg_rw_4 \g_tx_command_txb4_t.i_tx_command_txb4_reg (.adress_IBUF(adress_IBUF[5:3]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[11]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_tx_command_txb4_t.i_tx_command_txb4_reg_n_0 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[0].reg_value_r_reg[0]_55 ), .\g_bit[0].reg_value_r_reg[0]_3 (\g_bit[0].reg_value_r_reg[0]_58 ), .wr_en(wr_en_7)); memory_reg_rw__parameterized8 \g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg (.\FSM_sequential_curr_state_reg[0] (\FSM_sequential_curr_state_reg[0]_1 ), .adress_IBUF({adress_IBUF[4],adress_IBUF[2]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[10:8]), .fsm_wait_state_q(fsm_wait_state_q), .fsm_wait_state_q_reg(fsm_wait_state_q_reg), .fsm_wait_state_q_reg_0(i_mode_txbbm_reg_n_5), .\g_bit[0].reg_value_r_reg[0]_0 (\g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg_n_8 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg_n_9 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[0].reg_value_r_reg[0]_55 ), .\g_bit[2].reg_value_r_reg[2]_1 (\adress[8] ), .\g_bit[2].reg_value_r_reg[2]_2 (i_btr_fd_sjw_fd_reg_n_7), .\g_bit[2].reg_value_r_reg[2]_3 (i_btr_fd_sjw_fd_reg_n_6), .\mr_tx_priority[2] (\mr_tx_priority[2] ), .\mr_tx_priority[3] (\mr_tx_priority[3] [1:0]), .\select_buf_index_reg_reg[0] (\select_buf_index_reg_reg[0] ), .\select_buf_index_reg_reg[0]_0 (\select_buf_index_reg_reg[0]_0 ), .\select_buf_index_reg_reg[0]_1 (i_tx_priority_txt1p_reg_n_5), .\select_buf_index_reg_reg[0]_2 (i_mode_txbbm_reg_n_6), .\select_buf_index_reg_reg[1] (\select_buf_index_reg_reg[1] ), .\select_buf_index_reg_reg[1]_0 (i_mode_txbbm_reg_n_7), .\select_buf_index_reg_reg[1]_1 (i_tx_priority_txt1p_reg_n_6), .\select_buf_index_reg_reg[1]_2 (i_tx_priority_txt1p_reg_n_4), .\select_buf_index_reg_reg[1]_3 (\mr_tx_priority[3] [2]), .\select_buf_index_reg_reg[1]_4 (\g_bit[0].reg_value_r_reg[0]_4 ), .tran_frame_valid_com_reg(tran_frame_valid_com_reg), .txtb_available(txtb_available), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .\txtb_hw_cmd_q_reg[lock] (\txtb_hw_cmd_q_reg[lock] ), .wr_en(wr_en_8)); memory_reg_rw__parameterized8_5 \g_tx_priority_txt4p_t.i_tx_priority_txt4p_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[14:12]), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_tx_priority[3] (\mr_tx_priority[3] ), .wr_en(wr_en_8)); memory_reg_rw_lock__parameterized9 i_btr_brp_slice_1_reg (.\adress[2] (i_btr_brp_slice_1_reg_n_5), .adress_IBUF(adress_IBUF[1:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[23:19]), .\g_bit[0].reg_value_r_reg[0]_0 (i_btr_brp_slice_1_reg_n_6), .\g_bit[3].reg_value_r_reg[3]_0 (i_btr_brp_slice_1_reg_n_7), .\g_bit[3].reg_value_r_reg[3]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_brp] (\mr_ctrl_out[btr_brp] [4:0]), .\segm_counter_q[7]_i_4 (\segm_counter_q_reg[0] [5:0]), .\segm_counter_q[7]_i_4_0 (\mr_ctrl_out[btr_brp] [5]), .wr_en(wr_en_21)); memory_reg_rw_lock__parameterized7 i_btr_brp_slice_2_reg (.adress_IBUF(adress_IBUF[3:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[26:24]), .\g_bit[0].reg_value_r_reg[0]_0 (\mr_ctrl_out[btr_brp] [5]), .\g_bit[0].reg_value_r_reg[0]_1 (i_btr_brp_slice_2_reg_n_1), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_3 ), .\g_bit[2].reg_value_r_reg[2]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_brp_fd] (\mr_ctrl_out[btr_fd_brp_fd] [7:6]), .\r_data_reg[25] (\g_bit[0].reg_value_r_reg[0]_6 ), .\r_data_reg[26] (\r_data_reg[31]_0 [1:0]), .\segm_counter_q_reg[0] (\segm_counter_q_reg[0] [7:6]), .\segm_counter_q_reg[0]_0 (i_btr_brp_slice_1_reg_n_6), .\segm_counter_q_reg[0]_1 (i_btr_brp_slice_1_reg_n_7), .\tq_counter_q_reg[6] (\tq_counter_q_reg[6] ), .wr_en(wr_en_23)); memory_reg_rw_lock__parameterized21 i_btr_fd_brp_fd_slice_1_reg (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[23:19]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_28 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_btr_fd_brp_fd_slice_1_reg_n_5), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_4 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_2 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_3 ), .\g_bit[3].reg_value_r_reg[3]_1 (i_btr_fd_brp_fd_slice_1_reg_n_6), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_3 ), .\g_bit[4].reg_value_r_reg[4]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_brp] (\mr_ctrl_out[btr_brp] [4:0]), .\segm_counter_q[6]_i_3 (\mr_ctrl_out[btr_fd_brp_fd] [5]), .\segm_counter_q[6]_i_3_0 (\segm_counter_q_reg[0]_0 [5:0]), .wr_en(wr_en_18)); memory_reg_rw_lock__parameterized7_6 i_btr_fd_brp_fd_slice_2_reg (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[26:24]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_29 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_settings_ena_reg_n_10), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_brp_fd] (\mr_ctrl_out[btr_fd_brp_fd] ), .\r_data[24]_i_3__0 (\mr_ctrl_out[btr_brp] [5]), .\segm_counter_q_reg[0] (\segm_counter_q_reg[0]_0 [7:6]), .\segm_counter_q_reg[0]_0 (i_btr_fd_brp_fd_slice_1_reg_n_5), .\segm_counter_q_reg[0]_1 (i_btr_fd_brp_fd_slice_1_reg_n_6), .\tq_counter_q_reg[7] (\tq_counter_q_reg[7] )); memory_reg_rw_lock__parameterized1 i_btr_fd_ph1_fd_slice_1_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7]), .\g_bit[0].reg_value_r_reg[0]_0 (i_settings_ena_reg_n_6), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] [0])); memory_reg_rw_lock__parameterized15 i_btr_fd_ph1_fd_slice_2_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[11:8]), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] [4:1]), .wr_en(wr_en_20)); memory_reg_rw_lock__parameterized17 i_btr_fd_ph2_fd_slice_1_reg (.CO(i_btr_fd_ph2_fd_slice_1_reg_n_3), .DI(\g_bit[0].reg_value_r_reg[0]_10 [2:0]), .O({\g_bit[0].reg_value_r_reg[0]_46 ,i_btr_fd_ph2_fd_slice_1_reg_n_7}), .S(i_btr_fd_ph2_fd_slice_2_reg_n_7), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[15:13]), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .i__carry_i_11__0_0(\exp_seg_length_q[7]_i_11 [2:0]), .i__carry_i_4__3(\g_bit[0].reg_value_r_reg[0]_10 [3]), .wr_en(wr_en_20)); memory_reg_rw_lock__parameterized19 i_btr_fd_ph2_fd_slice_2_reg (.CO(i_btr_fd_ph2_fd_slice_1_reg_n_3), .DI(\g_bit[1].reg_value_r_reg[1]_0 ), .O({O,i_btr_fd_ph2_fd_slice_2_reg_n_5}), .S(i_btr_fd_ph2_fd_slice_2_reg_n_7), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[17:16]), .\exp_seg_length_d9_inferred__0/i__carry (\exp_seg_length_q[7]_i_11 [5:3]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_10 [3]), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[4].reg_value_r_reg[4] (\g_bit[4].reg_value_r_reg[4]_7 [2]), .is_tseg2(is_tseg2), .\mr_ctrl_out[btr_fd_sjw_fd] (\mr_ctrl_out[btr_fd_sjw_fd] [4]), .\segm_counter_q_reg[4] (\segm_counter_q_reg[4] [2]), .\test_probe[tx_trigger]_INST_0_i_27 (\test_probe[tx_trigger]_INST_0_i_27 ), .wr_en(wr_en_18)); memory_reg_rw_lock__parameterized13 i_btr_fd_prop_fd_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[5:0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_53 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_settings_ena_reg_n_6), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] [0]), .\mr_ctrl_out[btr_fd_prop_fd] (\mr_ctrl_out[btr_fd_prop_fd] )); memory_reg_rw_lock__parameterized11 i_btr_fd_sjw_fd_reg (.CO(CO), .\FSM_onehot_current_state_reg[2] (\segm_counter_q_reg[4] [1:0]), .\FSM_onehot_current_state_reg[2]_0 (\FSM_onehot_current_state_reg[2] ), .O({O[1],i_btr_fd_ph2_fd_slice_2_reg_n_5}), .\adress[2] (i_btr_fd_sjw_fd_reg_n_6), .\adress[7] (i_btr_fd_sjw_fd_reg_n_7), .\adress[8] (\adress[8] ), .adress_IBUF({adress_IBUF[9:5],adress_IBUF[3],adress_IBUF[1:0]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[31:27]), .\exp_seg_length_d9_inferred__0/i__carry (\exp_seg_length_d9_inferred__0/i__carry ), .\exp_seg_length_d9_inferred__0/i__carry_0 ({\g_bit[0].reg_value_r_reg[0]_46 [1],i_btr_fd_ph2_fd_slice_1_reg_n_7}), .\exp_seg_length_d9_inferred__0/i__carry_1 (\exp_seg_length_d9_inferred__0/i__carry_0 ), .\exp_seg_length_q[6]_i_2 (\exp_seg_length_q[6]_i_2 ), .\exp_seg_length_q[6]_i_2_0 (\exp_seg_length_q[6]_i_2_0 ), .\exp_seg_length_q[7]_i_11_0 ({\exp_seg_length_q[7]_i_11 [6],\exp_seg_length_q[7]_i_11 [4:0]}), .\exp_seg_length_q_reg[3]_i_2__0 (\g_bit[0].reg_value_r_reg[0]_10 [3:1]), .\exp_seg_length_q_reg[7]_i_2__0 (\exp_seg_length_q_reg[7]_i_2__0 ), .\exp_seg_length_q_reg[7]_i_2__0_0 (\exp_seg_length_q_reg[7]_i_2__0_0 ), .\exp_seg_length_q_reg[7]_i_2__0_1 (\g_bit[1].reg_value_r_reg[1]_0 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[4].reg_value_r_reg[4]_7 [1:0]), .\g_bit[3].reg_value_r_reg[3]_1 (i_settings_ena_reg_n_10), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_6 ), .\g_bit[4].reg_value_r_reg[4]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 (\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 ), .is_tseg2(is_tseg2), .\mr_ctrl_out[btr_fd_sjw_fd] (\mr_ctrl_out[btr_fd_sjw_fd] ), .scs_IBUF(scs_IBUF), .\segm_counter_q_reg[6] (\segm_counter_q_reg[6] ), .\test_probe[tx_trigger]_INST_0_i_4 (\test_probe[tx_trigger]_INST_0_i_4 ), .\test_probe[tx_trigger]_INST_0_i_4_0 (\test_probe[tx_trigger]_INST_0_i_4_0 ), .\test_probe[tx_trigger]_INST_0_i_9_0 (\test_probe[tx_trigger]_INST_0_i_9 ), .\test_probe[tx_trigger]_INST_0_i_9_1 (\test_probe[tx_trigger]_INST_0_i_9_0 ), .\tseg1_dbt_reg[3] (\tseg1_dbt_reg[3] ), .\tseg1_dbt_reg[4] (\tseg1_dbt_reg[4] )); memory_reg_rw_lock__parameterized1_7 i_btr_ph1_slice_1_reg (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_49 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_settings_ena_reg_n_2), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] [0]), .\mr_ctrl_out[btr_ph1] (\mr_ctrl_out[btr_ph1] [0]), .\r_data[7]_i_11 (\g_bit[7].reg_value_r_reg[7] )); memory_reg_rw_lock__parameterized3 i_btr_ph1_slice_2_reg (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[12:8]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_37 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_6 ), .\g_bit[4].reg_value_r_reg[4]_0 (i_btr_ph1_slice_2_reg_n_5), .\g_bit[4].reg_value_r_reg[4]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] [4:1]), .\mr_ctrl_out[btr_ph1] (\mr_ctrl_out[btr_ph1] [5:1]), .\nom_err_ctr_q_reg[10] (\nom_err_ctr_q_reg[10] ), .\nom_err_ctr_q_reg[9] (\nom_err_ctr_q_reg[9] ), .\r_data[10]_i_8_0 (\g_bit[2].reg_value_r_reg[2]_1 ), .\r_data[11]_i_6 (\g_bit[3].reg_value_r_reg[3]_2 ), .\r_data[8]_i_7 (\g_bit[0].reg_value_r_reg[0]_12 ), .\r_data[9]_i_8_0 (\g_bit[1].reg_value_r_reg[1]_2 ), .\r_data_reg[12] (\g_bit[4].reg_value_r_reg[4]_1 ), .\r_data_reg[12]_0 (\r_data_reg[12]_1 ), .wr_en(wr_en_22)); memory_reg_rw_lock__parameterized5 i_btr_ph2_slice_1_reg (.CO(i_btr_ph2_slice_1_reg_n_6), .DI(DI[2:0]), .S(i_btr_ph2_slice_2_reg_n_10), .adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[15:13]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_36 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_7 ), .\g_bit[1].reg_value_r_reg[1]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_5 ), .i__carry_i_10__0_0(i__carry_i_9[2:0]), .i__carry_i_8__3(DI[3]), .neg_phase_err(neg_phase_err[3:0]), .\r_data[14]_i_4__0 (\g_bit[6].reg_value_r_reg[6]_0 ), .\r_data[15]_i_3__0 (\g_bit[0].reg_value_r_reg[0]_10 [2:0]), .\r_data[15]_i_3__0_0 (\g_bit[7].reg_value_r_reg[7]_0 ), .\r_data_reg[13] (\g_bit[5].reg_value_r_reg[5]_0 ), .wr_en(wr_en_22)); memory_reg_rw_lock__parameterized7_8 i_btr_ph2_slice_2_reg (.CO(i_btr_ph2_slice_1_reg_n_6), .\FSM_onehot_current_state_reg[2] (i_btr_ph2_slice_2_reg_n_8), .S(i_btr_ph2_slice_2_reg_n_10), .adress_IBUF(adress_IBUF[2:0]), .\cc_stat[is_err_active] (\cc_stat[is_err_active] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[18:16]), .\g_bit[0].reg_value_r_reg[0]_0 (DI[3]), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_48 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[4].reg_value_r_reg[4] (\g_bit[4].reg_value_r_reg[4]_9 [1]), .i__carry_i_2__4(i__carry_i_2__4), .i__carry_i_9_0(i__carry_i_9[5:3]), .is_tseg2(is_tseg2), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] ), .neg_phase_err(neg_phase_err[7:4]), .\r_data[16]_i_4__0 (\g_bit[0].reg_value_r_reg[0]_10 [3]), .\test_probe[tx_trigger]_INST_0_i_16 (\g_bit[4].reg_value_r_reg[4] ), .wr_en(wr_en_21)); memory_reg_rw_lock i_btr_prop_reg (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[6:0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_50 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_settings_ena_reg_n_2), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_8 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_6 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_7 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_5 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5]_1 ), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .mr_btr_prop(mr_btr_prop), .\mr_ctrl_out[btr_fd_prop_fd] (\mr_ctrl_out[btr_fd_prop_fd] ), .\r_data[0]_i_6 (\g_bit[0].reg_value_r_reg[0]_11 ), .\r_data[1]_i_6 (\g_bit[1].reg_value_r_reg[1]_1 ), .\r_data[2]_i_3__0 (\g_bit[2].reg_value_r_reg[2]_0 ), .\r_data[3]_i_10 (\g_bit[3].reg_value_r_reg[3]_1 ), .\r_data[4]_i_4 (\g_bit[4].reg_value_r_reg[4]_0 ), .\r_data[5]_i_6 (\g_bit[5].reg_value_r_reg[5] )); memory_reg_rw_lock__parameterized11_9 i_btr_sjw_reg (.\FSM_onehot_current_state_reg[2] (\g_bit[4].reg_value_r_reg[4]_9 [0]), .adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[31:27]), .\exp_seg_length_d9_inferred__0/i__carry (\exp_seg_length_d9_inferred__0/i__carry_1 ), .\exp_seg_length_d9_inferred__0/i__carry_0 (\exp_seg_length_d9_inferred__0/i__carry_2 ), .\exp_seg_length_d9_inferred__0/i__carry_1 ({i__carry_i_9[3:2],i__carry_i_9[0]}), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_9 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_31 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1] ), .\g_bit[1].reg_value_r_reg[1]_1 (\g_bit[1].reg_value_r_reg[1]_5 ), .\g_bit[1].reg_value_r_reg[1]_2 (\g_bit[1].reg_value_r_reg[1]_9 ), .\g_bit[1].reg_value_r_reg[1]_3 (\g_bit[1].reg_value_r_reg[1]_10 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2] ), .\g_bit[2].reg_value_r_reg[2]_1 (\g_bit[2].reg_value_r_reg[2]_4 ), .\g_bit[2].reg_value_r_reg[2]_2 (\g_bit[2].reg_value_r_reg[2]_7 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_0 ), .\g_bit[3].reg_value_r_reg[3]_1 (\g_bit[3].reg_value_r_reg[3]_4 ), .\g_bit[3].reg_value_r_reg[3]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4] ), .\g_bit[4].reg_value_r_reg[4]_1 (\g_bit[4].reg_value_r_reg[4]_4 ), .\g_bit[4].reg_value_r_reg[4]_2 (\g_bit[4].reg_value_r_reg[4]_8 ), .is_tseg2(is_tseg2), .\mr_ctrl_out[btr_fd_sjw_fd] (\mr_ctrl_out[btr_fd_sjw_fd] ), .neg_phase_err({neg_phase_err[3:2],neg_phase_err[0]}), .\r_data_reg[31] (\r_data_reg[31]_0 [6:2]), .\test_probe[tx_trigger]_INST_0_i_7 (\test_probe[tx_trigger]_INST_0_i_7 ), .\test_probe[tx_trigger]_INST_0_i_7_0 (\test_probe[tx_trigger]_INST_0_i_7_0 ), .\test_probe[tx_trigger]_INST_0_i_7_1 (i_btr_ph2_slice_2_reg_n_8), .wr_en(wr_en_23)); memory_reg_rw_lock__parameterized27 i_ctr_pres_ctpv_slice_1_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7:0]), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] [7:0]), .wr_en(wr_en_15)); memory_reg_rw_lock__parameterized29 i_ctr_pres_ctpv_slice_2_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[8]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] [8]), .wr_en(wr_en_13)); memory_reg_rw_lock__parameterized25 i_erp_erp_limit_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[15:8]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_12 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_2 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_1 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_2 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_1 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5]_0 ), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[6].reg_value_r_reg[6]_0 ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7]_0 ), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_2 ), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7]_3 ), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[2].reg_value_r_reg[2]_8 ), .next_state2_carry(next_state2_carry), .\next_state2_inferred__0/i__carry (\next_state2_inferred__0/i__carry ), .wr_en(wr_en_12)); memory_reg_rw_lock__parameterized23 i_ewl_ew_limit_reg (.S(S), .adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7:0]), .err_warning_limit_q1_carry(next_state2_carry), .\err_warning_limit_q1_inferred__0/i__carry (\next_state2_inferred__0/i__carry ), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_11 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_1 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_0 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_1 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_0 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5] ), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[6].reg_value_r_reg[6] ), .\g_bit[6].reg_value_r_reg[6]_1 (\g_bit[6].reg_value_r_reg[6]_1 ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7] ), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_1 ), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .mr_btr_prop(mr_btr_prop[6]), .wr_en(wr_en_14)); memory_reg_rw__parameterized2 i_filter_control_fafb_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[2]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_14 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_9)); memory_reg_rw__parameterized2_10 i_filter_control_fafe_reg (.D(p_0_in[3]), .adress_IBUF(adress_IBUF[5:3]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[3]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\r_data_reg[3] (\r_data_reg[3]_0 ), .\r_data_reg[3]_0 (\r_data[7]_i_4__0_n_0 ), .\r_data_reg[3]_1 (\r_data_reg[3]_1 ), .\r_data_reg[3]_2 (\r_data_reg[3]_2 ), .sbe_IBUF(sbe_IBUF[0]), .wr_en(wr_en_9)); memory_reg_rw__parameterized2_11 i_filter_control_fanb_reg (.adress_IBUF(adress_IBUF[5:2]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_13 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[2].reg_value_r_reg[2]_9 ), .\g_bit[0].reg_value_r_reg[0]_3 (\adress[2] ), .wr_en(wr_en_9)); memory_reg_rw__parameterized2_12 i_filter_control_fane_reg (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[1]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_33 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_9)); memory_reg_rw_13 i_filter_control_fbfb_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[6]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_16 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_9)); memory_reg_rw_14 i_filter_control_fbfe_reg (.D(p_0_in[7]), .adress_IBUF(adress_IBUF[5:3]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\r_data_reg[7] (\r_data_reg[7]_0 ), .\r_data_reg[7]_0 (\r_data[7]_i_4__0_n_0 ), .\r_data_reg[7]_1 (\r_data_reg[7]_1 ), .\r_data_reg[7]_2 (\r_data_reg[7]_2 ), .sbe_IBUF(sbe_IBUF[0]), .wr_en(wr_en_9)); memory_reg_rw_15 i_filter_control_fbnb_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[4]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_15 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_9)); memory_reg_rw_16 i_filter_control_fbne_reg (.D(p_0_in[5]), .adress_IBUF(adress_IBUF[5:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[5]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\r_data_reg[5] (\r_data_reg[5]_0 ), .\r_data_reg[5]_0 (\r_data_reg[5]_1 ), .\r_data_reg[5]_1 (\r_data_reg[5]_2 ), .\r_data_reg[5]_2 (\r_data_reg[5]_3 ), .sbe_IBUF(sbe_IBUF[0]), .wr_en(wr_en_9)); memory_reg_rw_17 i_filter_control_fcfb_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[10]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_19 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_10)); memory_reg_rw_18 i_filter_control_fcfe_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[11]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_20 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_10)); memory_reg_rw_19 i_filter_control_fcnb_reg (.\adress[2] (\adress[2] ), .adress_IBUF(adress_IBUF[5:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[8]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_17 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[0].reg_value_r_reg[0]_55 ), .wr_en(wr_en_10)); memory_reg_rw_20 i_filter_control_fcne_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[9]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_18 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_10)); memory_reg_rw_21 i_filter_control_frfb_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[14]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_22 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_10)); memory_reg_rw_22 i_filter_control_frfe_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[15]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_23 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_10)); memory_reg_rw_23 i_filter_control_frnb_reg (.D(p_0_in[12]), .adress_IBUF(adress_IBUF[5]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[12]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\r_data_reg[12] (i_btr_ph1_slice_2_reg_n_5), .\r_data_reg[12]_0 (\adress[5]_0 ), .\r_data_reg[12]_1 (\r_data_reg[12]_0 ), .\r_data_reg[12]_2 (\adress[2]_0 ), .\r_data_reg[12]_3 (\adress[3] ), .\r_data_reg[12]_4 (\r_data_reg[12]_2 ), .sbe_IBUF(sbe_IBUF[1]), .wr_en(wr_en_10)); memory_reg_rw_24 i_filter_control_frne_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[13]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_21 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_10)); memory_reg_rw_25 i_mode_acf_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[mode_acf] (\mr_ctrl_out[mode_acf] ), .wr_en(wr_en_11)); memory_reg_rw_26 i_mode_afm_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[3]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_11)); memory_reg_rw_27 i_mode_bmm_reg (.\FSM_sequential_curr_state_reg[0] (\g_bit[0].reg_value_r_reg[0]_2 ), .\FSM_sequential_curr_state_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_6 ), .\FSM_sequential_curr_state_reg[0]_1 (\FSM_sequential_curr_state_reg[2] ), .can_tx_OBUF(can_tx_OBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_tx_wbs(crc_data_tx_wbs), .data_in_IBUF(data_in_IBUF[1]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_51 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[0].reg_value_r_reg[0]_52 ), .\g_bit[0].reg_value_r_reg[0]_3 (\g_bit[2].reg_value_r_reg[2]_8 ), .tx_data_prev_reg(\g_bit[0].reg_value_r_reg[0]_5 ), .wr_en(wr_en_11)); memory_reg_rw_28 i_mode_erfm_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[12]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .wr_en(wr_en_16)); memory_reg_rw__parameterized2_29 i_mode_fde_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[4]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_1 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_42 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .tran_frame_type(tran_frame_type), .wr_en(wr_en_11)); memory_reg_rw_30 i_mode_rom_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[6]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_2 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_11)); memory_reg_rw__parameterized2_31 i_mode_rxbam_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[9]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .wr_en(wr_en_16)); memory_reg_rw_32 i_mode_sam_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .curr_state(curr_state), .data_in_IBUF(data_in_IBUF[11]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_40 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[mode_acf] (\mr_ctrl_out[mode_acf] ), .\mr_ctrl_out[mode_sam] (\mr_ctrl_out[mode_sam] ), .wr_en(wr_en_16)); memory_reg_rw_33 i_mode_stm_reg (.adress_IBUF(adress_IBUF[5:2]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[2]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_btr_brp_slice_1_reg_n_5), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[2].reg_value_r_reg[2]_9 ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .wr_en(wr_en_11)); memory_reg_rw_34 i_mode_tstm_reg (.adress_IBUF(adress_IBUF[5:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF({data_in_IBUF[12:8],data_in_IBUF[1]}), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_3 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_32 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_3 (\g_bit[0].reg_value_r_reg[0]_55 ), .\g_bit[0].reg_value_r_reg[0]_4 (i_btr_brp_slice_1_reg_n_5), .\g_bit[0].reg_value_r_reg[0]_5 (\g_bit[0].reg_value_r_reg[0]_56 ), .\g_bit[0].reg_value_r_reg[0]_6 (i_ssp_cfg_ssp_src_reg_n_4), .\g_bit[0].reg_value_r_reg[0]_7 (\g_bit[0].reg_value_r_reg[0]_57 ), .\g_bit[0].reg_value_r_reg[0]_8 (\adress[8] ), .\g_bit[0].reg_value_r_reg[0]_9 (\g_bit[2].reg_value_r_reg[2]_9 ), .\g_bit[7].reg_value_r_reg[7] (\g_bit[0].reg_value_r_reg[0]_54 ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7]_4 ), .\mr_ctrl_out[ctr_pres_efd] (\mr_ctrl_out[ctr_pres_efd] ), .\mr_ctrl_out[ctr_pres_enorm] (\mr_ctrl_out[ctr_pres_enorm] ), .\mr_ctrl_out[ctr_pres_prx] (\mr_ctrl_out[ctr_pres_prx] ), .\mr_ctrl_out[ctr_pres_ptx] (\mr_ctrl_out[ctr_pres_ptx] ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .sbe_IBUF(sbe_IBUF), .swr_IBUF(swr_IBUF), .wr_en(wr_en), .wr_en_0(wr_en_0), .wr_en_1(wr_en_1), .wr_en_10(wr_en_13), .wr_en_11(wr_en_12), .wr_en_2(wr_en_2), .wr_en_3(wr_en_3), .wr_en_4(wr_en_4), .wr_en_5(wr_en_5), .wr_en_6(wr_en_6), .wr_en_7(wr_en_16), .wr_en_8(wr_en_15), .wr_en_9(wr_en_14)); memory_reg_rw_35 i_mode_tttm_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[5]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .wr_en(wr_en_11)); memory_reg_rw_36 i_mode_txbbm_reg (.\FSM_sequential_curr_state[0]_i_2__0 (\FSM_sequential_curr_state[0]_i_2__0 ), .\FSM_sequential_curr_state[0]_i_2__0_0 (\FSM_sequential_curr_state[0]_i_2__0_0 ), .\FSM_sequential_curr_state[0]_i_2__2 (\FSM_sequential_curr_state[0]_i_2__2 ), .\FSM_sequential_curr_state[0]_i_4__2 (\g_bit[0].reg_value_r_reg[0]_25 ), .\FSM_sequential_curr_state[0]_i_4__2_0 (\g_tx_command_txb4_t.i_tx_command_txb4_reg_n_0 ), .abort_applied(abort_applied), .abort_applied_3(abort_applied_3), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[10]), .fsm_wait_state_q_i_4(i_tx_priority_txt1p_reg_n_4), .fsm_wait_state_q_i_4_0(\g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg_n_9 ), .fsm_wait_state_q_i_4_1(i_tx_priority_txt1p_reg_n_6), .fsm_wait_state_q_i_4_2(\g_tx_priority_txt3p_t.i_tx_priority_txt3p_reg_n_8 ), .fsm_wait_state_q_i_5(\g_bit[0].reg_value_r_reg[0]_24 ), .fsm_wait_state_q_i_5_0(i_tx_command_txb2_reg_n_0), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_38 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[0].reg_value_r_reg[0]_39 ), .\g_bit[0].reg_value_r_reg[0]_3 (i_mode_txbbm_reg_n_5), .\g_bit[0].reg_value_r_reg[0]_4 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[2].reg_value_r_reg[2] (i_mode_txbbm_reg_n_6), .\g_bit[2].reg_value_r_reg[2]_0 (i_mode_txbbm_reg_n_7), .mr_tx_command_txca_q(mr_tx_command_txca_q), .mr_tx_command_txce_q(mr_tx_command_txce_q), .mr_tx_command_txcr_q(mr_tx_command_txcr_q), .\mr_tx_priority[0] (\mr_tx_priority[0] [2]), .\mr_tx_priority[1] (\mr_tx_priority[1] [2]), .\mr_tx_priority[2] (\mr_tx_priority[2] [2]), .\mr_tx_priority[3] (\mr_tx_priority[3] [2]), .\select_buf_index_reg_reg[1] (\select_buf_index_reg_reg[1]_0 ), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txce_valid_5(tx_command_txce_valid_5), .tx_command_txcr_valid(tx_command_txcr_valid), .tx_command_txcr_valid_4(tx_command_txcr_valid_4), .txtb_allow_bb(txtb_allow_bb), .txtb_available({txtb_available[3:2],txtb_available[0]}), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .wr_en(wr_en_16)); memory_reg_rw_37 i_rx_settings_rtsop_reg (.adress_IBUF(adress_IBUF[5:2]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[16]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_1 (i_ssp_cfg_ssp_offset_reg_n_11), .\g_bit[0].reg_value_r_reg[0]_2 (i_btr_fd_sjw_fd_reg_n_6), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] )); memory_reg_rw_38 i_settings_ena_reg (.adress_IBUF(adress_IBUF[5:0]), .bit_err_d0_out(bit_err_d0_out), .bit_err_d2(bit_err_d2), .bit_err_enable(bit_err_enable), .bit_err_q_reg(bit_err_q_reg), .bit_err_q_reg_0(bit_err_q_reg_0), .bit_err_q_reg_1(\g_bit[0].reg_value_r_reg[0] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_tx_wbs(crc_data_tx_wbs), .current_state_reg(current_state_reg), .data_in_IBUF({data_in_IBUF[22],data_in_IBUF[0]}), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_5 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_27 ), .\g_bit[0].reg_value_r_reg[0]_10 (i_ssp_cfg_ssp_src_reg_n_14), .\g_bit[0].reg_value_r_reg[0]_2 (i_settings_ena_reg_n_2), .\g_bit[0].reg_value_r_reg[0]_3 (i_settings_ena_reg_n_6), .\g_bit[0].reg_value_r_reg[0]_4 (\g_bit[0].reg_value_r_reg[0]_45 ), .\g_bit[0].reg_value_r_reg[0]_5 (\g_bit[0].reg_value_r_reg[0]_47 ), .\g_bit[0].reg_value_r_reg[0]_6 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_7 (\g_bit[0].reg_value_r_reg[0]_55 ), .\g_bit[0].reg_value_r_reg[0]_8 (i_ssp_cfg_ssp_offset_reg_n_11), .\g_bit[0].reg_value_r_reg[0]_9 (i_ssp_cfg_ssp_src_reg_n_4), .\g_bit[2].reg_value_r_reg[2] (i_btr_brp_slice_1_reg_n_5), .\g_bit[3].reg_value_r_reg[3] (\adress[8] ), .\g_bit[3].reg_value_r_reg[3]_0 (i_btr_fd_sjw_fd_reg_n_6), .\g_bit[3].reg_value_r_reg[3]_1 (i_btr_fd_sjw_fd_reg_n_7), .mr_settings_ena_reg(mr_settings_ena_reg), .reg_q_reg(\g_bit[2].reg_value_r_reg[2]_9 ), .reg_q_reg_0(\g_bit[0].reg_value_r_reg[0]_54 ), .rx_data_wbs(rx_data_wbs), .sbe_IBUF(sbe_IBUF[3:2]), .swr(i_settings_ena_reg_n_10), .swr_IBUF(swr_IBUF), .wr_en(wr_en_23), .wr_en_0(wr_en_22), .wr_en_1(wr_en_21), .wr_en_2(wr_en_20), .wr_en_3(wr_en_19), .wr_en_4(wr_en_18), .wr_en_5(wr_en_17), .wr_en_6(wr_en_25)); memory_reg_rw_39 i_settings_fdrf_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[26]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_24)); memory_reg_rw_40 i_settings_ilbp_reg (.D(p_0_in[21]), .adress_IBUF({adress_IBUF[5],adress_IBUF[2]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[21]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\r_data_reg[21] (\r_data_reg[21]_0 ), .\r_data_reg[21]_0 (i_ssp_cfg_ssp_offset_reg_n_13), .\r_data_reg[21]_1 (\adress[5] ), .\r_data_reg[21]_2 (\adress[3] ), .\r_data_reg[21]_3 (\r_data_reg[21]_1 ), .\r_data_reg[21]_4 (\r_data_reg[21]_2 ), .\r_data_reg[21]_5 (\adress[3]_0 ), .sbe_IBUF(sbe_IBUF[2]), .wr_en(wr_en_25)); memory_reg_rw_41 i_settings_nisofd_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[23]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .wr_en(wr_en_25)); memory_reg_rw_42 i_settings_pchke_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[27]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_8 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_24)); memory_reg_rw_43 i_settings_pex_reg (.adress_IBUF(adress_IBUF[1:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[24]), .\err_capt_err_type_q[2]_i_13 (\g_bit[0].reg_value_r_reg[0]_1 ), .\err_capt_err_type_q[2]_i_13_0 (\err_capt_err_type_q[2]_i_13 ), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_43 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_44 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[0].reg_value_r_reg[0]_3 (\adress[8] ), .\g_bit[0].reg_value_r_reg[0]_4 (\g_bit[0].reg_value_r_reg[0]_54 ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .pc_rx_data_nbs(pc_rx_data_nbs), .sbe_IBUF(sbe_IBUF[3]), .swr_IBUF(swr_IBUF), .wr_en(wr_en_24)); memory_reg_rw_44 i_settings_rtrle_reg (.adress_IBUF(adress_IBUF[4:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[16]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_35 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .wr_en(wr_en_25)); memory_reg_rw__parameterized4 i_settings_rtrth_reg (.adress_IBUF(adress_IBUF[5:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[20:17]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_34 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_41 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_6 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3] ), .\g_bit[3].reg_value_r_reg[3]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[3].reg_value_r_reg[3]_2 (i_ssp_cfg_ssp_offset_reg_n_11), .\g_bit[3].reg_value_r_reg[3]_3 (i_btr_brp_slice_1_reg_n_5), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .\r_data[17]_i_2 (\r_data[17]_i_9_n_0 ), .\r_data[17]_i_2_0 (\adress[5]_1 ), .\r_data[17]_i_2_1 (\r_data[17]_i_2 ), .\txtb_hw_cmd_q[err] (\txtb_hw_cmd_q[err] ), .\txtb_hw_cmd_q_reg[err] (\txtb_hw_cmd_q_reg[err] ), .\txtb_hw_cmd_q_reg[err]_0 (\txtb_hw_cmd_q_reg[err]_0 ), .wr_en(wr_en_25)); memory_reg_rw__parameterized2_45 i_settings_tbfbo_reg (.\FSM_sequential_curr_state_reg[0] (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[2] (\FSM_sequential_curr_state_reg[2] ), .\FSM_sequential_curr_state_reg[2]_0 (\g_bit[0].reg_value_r_reg[0]_2 ), .\FSM_sequential_curr_state_reg[2]_1 (\g_bit[0].reg_value_r_reg[0] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[25]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .txtb_allow_bb(txtb_allow_bb), .wr_en(wr_en_24)); memory_reg_rw_lock__parameterized31 i_ssp_cfg_ssp_offset_reg (.D(p_0_in[23:22]), .adress_IBUF({adress_IBUF[5:3],adress_IBUF[1:0]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[23:16]), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_5 ), .\g_bit[3].reg_value_r_reg[3]_1 (\adress[8] ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_2 ), .\g_bit[5].reg_value_r_reg[5]_0 (i_ssp_cfg_ssp_offset_reg_n_13), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .\r_data_reg[20] (\adress[4] ), .\r_data_reg[22] (\r_data_reg[22]_0 ), .\r_data_reg[22]_0 (\g_bit[0].reg_value_r_reg[0]_5 ), .\r_data_reg[22]_1 (\r_data_reg[22]_1 ), .\r_data_reg[23] (\r_data_reg[23]_0 ), .\r_data_reg[23]_0 (\adress[5] ), .\r_data_reg[23]_1 (\adress[3] ), .\r_data_reg[23]_2 (\r_data_reg[23]_1 ), .\sbe[2] (i_ssp_cfg_ssp_offset_reg_n_11), .sbe_IBUF(sbe_IBUF[2]), .swr_IBUF(swr_IBUF), .timestamp_IBUF({timestamp_IBUF[23:19],timestamp_IBUF[7:3]}), .wr_en(wr_en_19)); memory_reg_rw_lock__parameterized19_46 i_ssp_cfg_ssp_src_reg (.D(p_0_in[25]), .\adress[5] (i_ssp_cfg_ssp_src_reg_n_4), .\adress[9] (i_ssp_cfg_ssp_src_reg_n_14), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[25:24]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_26 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_30 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_3 ), .\g_bit[1].reg_value_r_reg[1]_1 (\g_bit[1].reg_value_r_reg[1]_11 ), .\g_bit[1].reg_value_r_reg[1]_2 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .\r_data_reg[24] (\adress[4] ), .\r_data_reg[25] (i_btr_brp_slice_2_reg_n_1), .\r_data_reg[25]_0 (\adress[2] ), .\r_data_reg[25]_1 (\r_data_reg[25]_0 ), .sbe_IBUF(sbe_IBUF[3]), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .timestamp_IBUF({timestamp_IBUF[25:24],timestamp_IBUF[9:8]}), .trv_delay_sum(trv_delay_sum), .wr_en(wr_en_17)); memory_reg_rw_47 i_tx_command_txb1_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[8]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_24 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_7)); memory_reg_rw_48 i_tx_command_txb2_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[9]), .\g_bit[0].reg_value_r_reg[0]_0 (i_tx_command_txb2_reg_n_0), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[2].reg_value_r_reg[2]_8 ), .wr_en(wr_en_7)); memory_reg_rw__parameterized6 i_tx_priority_txt1p_reg (.adress_IBUF({adress_IBUF[4],adress_IBUF[2]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[2:0]), .\g_bit[0].reg_value_r_reg[0]_0 (i_tx_priority_txt1p_reg_n_4), .\g_bit[0].reg_value_r_reg[0]_1 (i_tx_priority_txt1p_reg_n_6), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\g_bit[2].reg_value_r_reg[2]_0 (i_tx_priority_txt1p_reg_n_5), .\g_bit[2].reg_value_r_reg[2]_1 (\g_bit[2].reg_value_r_reg[2]_9 ), .\g_bit[2].reg_value_r_reg[2]_2 (\adress[8] ), .\g_bit[2].reg_value_r_reg[2]_3 (i_btr_fd_sjw_fd_reg_n_7), .\g_bit[2].reg_value_r_reg[2]_4 (i_btr_fd_sjw_fd_reg_n_6), .\mr_tx_priority[0] (\mr_tx_priority[0] ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .\select_buf_index_reg_reg[0] (\g_bit[0].reg_value_r_reg[0]_4 ), .txtb_available(txtb_available[1:0]), .wr_en(wr_en_26)); memory_reg_rw__parameterized8_49 i_tx_priority_txt2p_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[6:4]), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_8 ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .wr_en(wr_en_26)); (* SOFT_HLUTNM = "soft_lutpair312" *) LUT2 #( .INIT(4'h7)) mr_tx_command_txce_q_i_2 (.I0(adress_IBUF[3]), .I1(adress_IBUF[4]), .O(\adress[5]_2 )); LUT4 #( .INIT(16'hC4F4)) \r_data[12]_i_7 (.I0(timestamp_IBUF[17]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[1]), .O(\timestamp[44] )); (* SOFT_HLUTNM = "soft_lutpair310" *) LUT3 #( .INIT(8'h04)) \r_data[13]_i_4 (.I0(adress_IBUF[4]), .I1(adress_IBUF[3]), .I2(adress_IBUF[5]), .O(\adress[6] )); (* SOFT_HLUTNM = "soft_lutpair305" *) LUT5 #( .INIT(32'hDFFFFFFF)) \r_data[15]_i_5 (.I0(adress_IBUF[0]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(adress_IBUF[2]), .I4(adress_IBUF[1]), .O(\adress[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair312" *) LUT3 #( .INIT(8'h01)) \r_data[17]_i_9 (.I0(adress_IBUF[4]), .I1(adress_IBUF[3]), .I2(adress_IBUF[2]), .O(\r_data[17]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair311" *) LUT3 #( .INIT(8'h40)) \r_data[18]_i_4__0 (.I0(adress_IBUF[2]), .I1(adress_IBUF[4]), .I2(adress_IBUF[3]), .O(\adress[4]_2 )); (* SOFT_HLUTNM = "soft_lutpair309" *) LUT4 #( .INIT(16'h30BB)) \r_data[18]_i_6 (.I0(timestamp_IBUF[18]), .I1(adress_IBUF[1]), .I2(timestamp_IBUF[2]), .I3(adress_IBUF[0]), .O(\timestamp[50] )); (* SOFT_HLUTNM = "soft_lutpair306" *) LUT5 #( .INIT(32'h7FFFFFFF)) \r_data[20]_i_6 (.I0(adress_IBUF[3]), .I1(adress_IBUF[4]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(adress_IBUF[2]), .O(\adress[5]_1 )); (* SOFT_HLUTNM = "soft_lutpair310" *) LUT2 #( .INIT(4'hE)) \r_data[24]_i_5 (.I0(adress_IBUF[3]), .I1(adress_IBUF[4]), .O(\adress[5] )); (* SOFT_HLUTNM = "soft_lutpair309" *) LUT2 #( .INIT(4'h2)) \r_data[24]_i_7 (.I0(adress_IBUF[2]), .I1(adress_IBUF[1]), .O(\adress[4]_1 )); (* SOFT_HLUTNM = "soft_lutpair308" *) LUT3 #( .INIT(8'h8A)) \r_data[24]_i_8 (.I0(adress_IBUF[2]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .O(\adress[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair307" *) LUT3 #( .INIT(8'hCE)) \r_data[24]_i_9 (.I0(adress_IBUF[2]), .I1(adress_IBUF[4]), .I2(adress_IBUF[3]), .O(\adress[4] )); LUT5 #( .INIT(32'h0A8A008A)) \r_data[26]_i_2 (.I0(\r_data[27]_i_6_n_0 ), .I1(timestamp_IBUF[10]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(timestamp_IBUF[26]), .O(\timestamp[26] )); LUT5 #( .INIT(32'h0A8A008A)) \r_data[27]_i_2 (.I0(\r_data[27]_i_6_n_0 ), .I1(timestamp_IBUF[11]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(timestamp_IBUF[27]), .O(\timestamp[27] )); LUT2 #( .INIT(4'h2)) \r_data[27]_i_5 (.I0(adress_IBUF[3]), .I1(adress_IBUF[4]), .O(\adress[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair307" *) LUT4 #( .INIT(16'h0008)) \r_data[27]_i_6 (.I0(adress_IBUF[2]), .I1(adress_IBUF[5]), .I2(adress_IBUF[3]), .I3(adress_IBUF[4]), .O(\r_data[27]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair305" *) LUT5 #( .INIT(32'hFFFFFFFB)) \r_data[27]_i_7 (.I0(adress_IBUF[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[2]), .I3(adress_IBUF[3]), .I4(adress_IBUF[4]), .O(\adress[3] )); LUT5 #( .INIT(32'h0A8A008A)) \r_data[28]_i_4 (.I0(\r_data[27]_i_6_n_0 ), .I1(timestamp_IBUF[12]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(timestamp_IBUF[28]), .O(\timestamp[28] )); LUT5 #( .INIT(32'h0A800080)) \r_data[29]_i_4 (.I0(\r_data[27]_i_6_n_0 ), .I1(timestamp_IBUF[29]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(timestamp_IBUF[13]), .O(\timestamp[61] )); (* SOFT_HLUTNM = "soft_lutpair311" *) LUT3 #( .INIT(8'h7F)) \r_data[2]_i_14 (.I0(adress_IBUF[4]), .I1(adress_IBUF[3]), .I2(adress_IBUF[2]), .O(\adress[6]_0 )); LUT5 #( .INIT(32'h08AA080A)) \r_data[30]_i_4 (.I0(\r_data[27]_i_6_n_0 ), .I1(timestamp_IBUF[30]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(timestamp_IBUF[14]), .O(\timestamp[62] )); LUT6 #( .INIT(64'h0000000000000020)) \r_data[31]_i_1__0 (.I0(srd_IBUF), .I1(adress_IBUF[7]), .I2(scs_IBUF), .I3(adress_IBUF[8]), .I4(adress_IBUF[9]), .I5(adress_IBUF[6]), .O(E)); (* SOFT_HLUTNM = "soft_lutpair306" *) LUT4 #( .INIT(16'h7FFF)) \r_data[31]_i_5 (.I0(adress_IBUF[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[4]), .I3(adress_IBUF[3]), .O(\adress[3]_0 )); LUT5 #( .INIT(32'h08AA080A)) \r_data[31]_i_6 (.I0(\r_data[27]_i_6_n_0 ), .I1(timestamp_IBUF[31]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(timestamp_IBUF[15]), .O(\timestamp[63] )); LUT4 #( .INIT(16'hC4F4)) \r_data[6]_i_8 (.I0(timestamp_IBUF[16]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[0]), .O(\timestamp[38] )); (* SOFT_HLUTNM = "soft_lutpair308" *) LUT4 #( .INIT(16'hDFFF)) \r_data[7]_i_4__0 (.I0(adress_IBUF[0]), .I1(adress_IBUF[3]), .I2(adress_IBUF[1]), .I3(adress_IBUF[2]), .O(\r_data[7]_i_4__0_n_0 )); FDCE \r_data_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[0]), .Q(Q[0])); FDCE \r_data_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[7]), .Q(Q[10])); FDCE \r_data_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[8]), .Q(Q[11])); FDCE \r_data_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[12]), .Q(Q[12])); FDCE \r_data_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[9]), .Q(Q[13])); FDCE \r_data_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[10]), .Q(Q[14])); FDCE \r_data_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[11]), .Q(Q[15])); FDCE \r_data_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[12]), .Q(Q[16])); FDCE \r_data_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[13]), .Q(Q[17])); FDCE \r_data_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[14]), .Q(Q[18])); FDCE \r_data_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[15]), .Q(Q[19])); FDCE \r_data_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[1]), .Q(Q[1])); FDCE \r_data_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[16]), .Q(Q[20])); FDCE \r_data_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[21]), .Q(Q[21])); FDCE \r_data_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[22]), .Q(Q[22])); FDCE \r_data_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[23]), .Q(Q[23])); FDCE \r_data_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[17]), .Q(Q[24])); FDCE \r_data_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[25]), .Q(Q[25])); FDCE \r_data_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[18]), .Q(Q[26])); FDCE \r_data_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[19]), .Q(Q[27])); FDCE \r_data_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[20]), .Q(Q[28])); FDCE \r_data_reg[29] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[21]), .Q(Q[29])); FDCE \r_data_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[2]), .Q(Q[2])); FDCE \r_data_reg[30] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[22]), .Q(Q[30])); FDCE \r_data_reg[31] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[23]), .Q(Q[31])); FDCE \r_data_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[3]), .Q(Q[3])); FDCE \r_data_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[3]), .Q(Q[4])); FDCE \r_data_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[5]), .Q(Q[5])); FDCE \r_data_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[4]), .Q(Q[6])); FDCE \r_data_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(p_0_in[7]), .Q(Q[7])); FDCE \r_data_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[5]), .Q(Q[8])); FDCE \r_data_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\g_bit[2].reg_value_r_reg[2]_8 ), .D(D[6]), .Q(Q[9])); LUT6 #( .INIT(64'hFFFFFEFFFFFFFFFF)) reg_q_i_1__0 (.I0(\adress[5] ), .I1(adress_IBUF[2]), .I2(adress_IBUF[5]), .I3(i_btr_brp_slice_1_reg_n_5), .I4(\g_bit[2].reg_value_r_reg[2]_9 ), .I5(data_in_IBUF[0]), .O(soft_res_d_n)); endmodule (* G_ACTIVE_TS_BITS = "63" *) (* G_FILT_A_EN = "FALSE" *) (* G_FILT_B_EN = "FALSE" *) (* G_FILT_C_EN = "FALSE" *) (* G_FILT_RANGE_EN = "FALSE" *) (* G_PARITY_EN = "FALSE" *) (* G_RESET_BUF_RAMS = "FALSE" *) (* G_RX_BUF_SIZE = "32" *) (* G_TECHNOLOGY = "1" *) (* G_TEST_REGS_EN = "TRUE" *) (* G_TRAFFIC_CTRS_EN = "FALSE" *) (* G_TXT_BUF_COUNT = "4" *) (* NotValidForBitStream *) module ctu_can_fd_top (clk_sys, rst_n, rst_n_out, scan_mode, data_in, data_out, adress, scs, srd, swr, sbe, int, can_tx, can_rx, \test_probe[rx_trigger_nbs] , \test_probe[rx_trigger_wbs] , \test_probe[tx_trigger] , timestamp); input clk_sys; input rst_n; output rst_n_out; input scan_mode; input [31:0]data_in; output [31:0]data_out; input [15:0]adress; input scs; input srd; input swr; input [3:0]sbe; output int; output can_tx; input can_rx; output \test_probe[rx_trigger_nbs] ; output \test_probe[rx_trigger_wbs] ; output \test_probe[tx_trigger] ; input [63:0]timestamp; wire abort_applied; wire abort_applied_14; wire abort_or_skipped; wire abort_or_skipped_0; wire [15:0]adress; wire [11:2]adress_IBUF; wire arbitration_lost; wire bit_err; wire bit_err_d2; wire bit_err_enable; wire br_shifted; wire btmc_meas_running_q; wire can_rx; wire can_rx_IBUF; wire can_tx; wire can_tx_OBUF; wire [4:0]\cc_stat[alc_bit] ; wire [2:0]\cc_stat[alc_id_field] ; wire [2:0]\cc_stat[bst_ctr] ; wire [15:9]\cc_stat[data_err_ctr] ; wire [2:0]\cc_stat[dst_ctr] ; wire \cc_stat[err_erp] ; wire [3:0]\cc_stat[err_pos] ; wire [2:0]\cc_stat[err_type] ; wire \cc_stat[is_err_active] ; wire \cc_stat[is_transmitter] ; wire [12:9]\cc_stat[norm_err_ctr] ; wire [3:0]\cc_stat[retr_ctr] ; wire [7:0]\cc_stat[rx_err_ctr] ; wire \cc_stat[status_pexs] ; wire [7:0]\cc_stat[tx_err_ctr] ; wire clk_sys; wire clk_sys_IBUF; wire clk_sys_IBUF_BUFG; wire commit_overrun_abort; wire [1:0]crc_21; wire crc_data_tx_wbs; wire [1:0]curr_txtb_index; wire [31:0]data_in; wire [31:0]data_in_IBUF; wire [31:0]data_out; wire [31:0]data_out_OBUF; wire dbt_ctrs_en; wire destuffed; wire err_detected; wire err_warning_limit_q; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_40 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_41 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_42 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_43 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_44 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_45 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_52 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_53 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_54 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_55 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_56 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_57 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_58 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_59 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_60 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_61 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_62 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_63 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_64 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_65 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_66 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_67 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_68 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_69 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_70 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_71 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_72 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_73 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_74 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_75 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_76 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_77 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_78 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_79 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_80 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_81 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_82 ; wire \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_83 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_32 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_37 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_38 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_41 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_42 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_43 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_44 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_45 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_46 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_47 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_48 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_49 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_50 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_51 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_52 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_53 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_54 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_55 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_56 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_57 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_58 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_59 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_60 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_61 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_62 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_63 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_64 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_65 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_66 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_67 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_68 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_69 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_70 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_71 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_72 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_73 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_74 ; wire \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_75 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_32 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_36 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_37 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_38 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_39 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_40 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_41 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_44 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_45 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_46 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_47 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_48 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_49 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_50 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_51 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_52 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_53 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_54 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_55 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_56 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_57 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_58 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_59 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_60 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_61 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_62 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_63 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_64 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_65 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_66 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_67 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_68 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_69 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_70 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_71 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_72 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_73 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_74 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_75 ; wire \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_76 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_32 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_36 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_37 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_38 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_39 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_40 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_43 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_44 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_45 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_46 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_47 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_48 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_49 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_50 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_51 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_52 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_53 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_54 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_55 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_56 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_57 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_58 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_59 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_60 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_61 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_62 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_63 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_64 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_65 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_66 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_67 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_68 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_69 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_70 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_71 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_72 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_73 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_74 ; wire \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_75 ; wire \i_bm_bit_err_detector/bit_err_d0_out ; wire \i_bm_data_edge_detector/sync_edge3__0 ; wire \i_bm_data_edge_detector/tx_data_prev ; wire \i_bm_ssp_generator/first_ssp_q0 ; wire \i_bm_ssp_generator/sspc_ena_q ; wire i_bm_top_n_10; wire i_bm_top_n_11; wire i_bm_top_n_12; wire i_bm_top_n_13; wire i_bm_top_n_16; wire i_bm_top_n_6; wire i_bm_top_n_7; wire i_bm_top_n_9; wire [0:0]\i_bm_tx_data_cache/write_pointer_q_reg ; wire \i_btl_cfg_capture/capture ; wire \i_btl_cfg_capture/mr_settings_ena_reg ; wire \i_btl_counters_dbt/segm_counter_ce ; wire \i_btl_counters_nbt/segm_counter_ce ; wire [1:1]\i_btl_fsm/current_state_reg ; wire \i_btl_segment_meter_dbt/phase_err_mt_sjw ; wire i_btl_top_n_11; wire i_btl_top_n_12; wire i_btl_top_n_17; wire i_btl_top_n_2; wire i_btl_top_n_24; wire i_btl_top_n_25; wire i_btl_top_n_26; wire i_btl_top_n_27; wire i_btl_top_n_28; wire i_btl_top_n_29; wire i_btl_top_n_3; wire i_btl_top_n_30; wire i_btl_top_n_31; wire i_btl_top_n_32; wire i_btl_top_n_33; wire i_btl_top_n_34; wire i_btl_top_n_35; wire i_btl_top_n_36; wire i_btl_top_n_37; wire i_btl_top_n_38; wire i_btl_top_n_47; wire i_btl_top_n_48; wire i_btl_top_n_49; wire i_btl_top_n_5; wire i_btl_top_n_50; wire i_btl_top_n_51; wire i_btl_top_n_52; wire i_btl_top_n_53; wire i_btl_top_n_54; wire i_btl_top_n_55; wire i_btl_top_n_56; wire i_btl_top_n_57; wire i_btl_top_n_58; wire i_btl_top_n_59; wire i_btl_top_n_6; wire i_btl_top_n_60; wire i_btl_top_n_61; wire i_btl_top_n_62; wire i_btl_top_n_63; wire i_btl_top_n_7; wire i_btl_top_n_9; wire [31:0]\i_control_registers_reg_map/p_0_in ; wire \i_control_registers_reg_map/r_data0 ; wire i_ff_top_n_1; wire i_ff_top_n_2; wire \i_global_rst_rst_reg/q_i ; wire i_im_top_n_10; wire i_im_top_n_11; wire i_im_top_n_12; wire i_im_top_n_15; wire i_im_top_n_16; wire i_im_top_n_17; wire i_im_top_n_18; wire i_im_top_n_19; wire i_im_top_n_3; wire i_im_top_n_7; wire i_im_top_n_8; wire i_im_top_n_9; wire [1:0]\i_mac_fc_top/i_mac_fc_fsm/curr_state ; wire [1:0]\i_mac_operation_control/curr_state ; wire \i_mac_pc_top/err_frm_req ; wire \i_mac_pc_top/i_mac_pc_fsm/txtb_hw_cmd_q[err] ; wire \i_mac_pc_top/i_mac_pc_rx_shift_reg/rec_is_rtr_i ; wire [0:0]\i_mac_pc_top/i_mac_pc_tx_shift_reg/p_1_in ; wire i_mac_top_n_100; wire i_mac_top_n_101; wire i_mac_top_n_102; wire i_mac_top_n_103; wire i_mac_top_n_104; wire i_mac_top_n_105; wire i_mac_top_n_106; wire i_mac_top_n_107; wire i_mac_top_n_108; wire i_mac_top_n_109; wire i_mac_top_n_110; wire i_mac_top_n_112; wire i_mac_top_n_113; wire i_mac_top_n_117; wire i_mac_top_n_118; wire i_mac_top_n_119; wire i_mac_top_n_120; wire i_mac_top_n_121; wire i_mac_top_n_128; wire i_mac_top_n_134; wire i_mac_top_n_136; wire i_mac_top_n_138; wire i_mac_top_n_139; wire i_mac_top_n_143; wire i_mac_top_n_144; wire i_mac_top_n_145; wire i_mac_top_n_146; wire i_mac_top_n_147; wire i_mac_top_n_148; wire i_mac_top_n_149; wire i_mac_top_n_150; wire i_mac_top_n_152; wire i_mac_top_n_187; wire i_mac_top_n_188; wire i_mac_top_n_189; wire i_mac_top_n_190; wire i_mac_top_n_198; wire i_mac_top_n_199; wire i_mac_top_n_202; wire i_mac_top_n_203; wire i_mac_top_n_206; wire i_mac_top_n_209; wire i_mac_top_n_211; wire i_mac_top_n_212; wire i_mac_top_n_213; wire i_mac_top_n_214; wire i_mac_top_n_215; wire i_mac_top_n_216; wire i_mac_top_n_217; wire i_mac_top_n_218; wire i_mac_top_n_219; wire i_mac_top_n_220; wire i_mac_top_n_221; wire i_mac_top_n_222; wire i_mac_top_n_223; wire i_mac_top_n_224; wire i_mac_top_n_225; wire i_mac_top_n_39; wire i_mac_top_n_40; wire i_mac_top_n_50; wire i_mac_top_n_51; wire i_mac_top_n_52; wire i_mac_top_n_53; wire i_mac_top_n_54; wire i_mac_top_n_55; wire i_mac_top_n_56; wire i_mac_top_n_57; wire i_mac_top_n_58; wire i_mac_top_n_59; wire i_mac_top_n_60; wire i_mac_top_n_61; wire i_mac_top_n_62; wire i_mac_top_n_66; wire i_mac_top_n_67; wire i_mac_top_n_70; wire i_mac_top_n_74; wire i_mac_top_n_75; wire i_mac_top_n_80; wire i_mac_top_n_81; wire i_mac_top_n_82; wire i_mac_top_n_83; wire i_mac_top_n_84; wire i_mac_top_n_85; wire i_mac_top_n_90; wire i_mac_top_n_91; wire i_mac_top_n_93; wire i_mac_top_n_95; wire i_mac_top_n_96; wire i_mac_top_n_98; wire i_mac_top_n_99; wire i_mr_top_n_1; wire i_mr_top_n_162; wire i_mr_top_n_163; wire i_mr_top_n_164; wire i_mr_top_n_165; wire i_mr_top_n_166; wire i_mr_top_n_167; wire i_mr_top_n_168; wire i_mr_top_n_169; wire i_mr_top_n_170; wire i_mr_top_n_171; wire i_mr_top_n_172; wire i_mr_top_n_173; wire i_mr_top_n_174; wire i_mr_top_n_175; wire i_mr_top_n_176; wire i_mr_top_n_177; wire i_mr_top_n_178; wire i_mr_top_n_179; wire i_mr_top_n_180; wire i_mr_top_n_181; wire i_mr_top_n_182; wire i_mr_top_n_183; wire i_mr_top_n_184; wire i_mr_top_n_185; wire i_mr_top_n_186; wire i_mr_top_n_187; wire i_mr_top_n_188; wire i_mr_top_n_189; wire i_mr_top_n_190; wire i_mr_top_n_191; wire i_mr_top_n_198; wire i_mr_top_n_200; wire i_mr_top_n_203; wire i_mr_top_n_204; wire i_mr_top_n_205; wire i_mr_top_n_206; wire i_mr_top_n_207; wire i_mr_top_n_208; wire i_mr_top_n_209; wire i_mr_top_n_21; wire i_mr_top_n_210; wire i_mr_top_n_211; wire i_mr_top_n_212; wire i_mr_top_n_213; wire i_mr_top_n_214; wire i_mr_top_n_215; wire i_mr_top_n_216; wire i_mr_top_n_217; wire i_mr_top_n_218; wire i_mr_top_n_219; wire i_mr_top_n_22; wire i_mr_top_n_220; wire i_mr_top_n_221; wire i_mr_top_n_222; wire i_mr_top_n_223; wire i_mr_top_n_225; wire i_mr_top_n_228; wire i_mr_top_n_229; wire i_mr_top_n_230; wire i_mr_top_n_231; wire i_mr_top_n_232; wire i_mr_top_n_233; wire i_mr_top_n_234; wire i_mr_top_n_235; wire i_mr_top_n_236; wire i_mr_top_n_245; wire i_mr_top_n_246; wire i_mr_top_n_247; wire i_mr_top_n_248; wire i_mr_top_n_249; wire i_mr_top_n_250; wire i_mr_top_n_251; wire i_mr_top_n_252; wire i_mr_top_n_253; wire i_mr_top_n_254; wire i_mr_top_n_255; wire i_mr_top_n_256; wire i_mr_top_n_257; wire i_mr_top_n_258; wire i_mr_top_n_259; wire i_mr_top_n_260; wire i_mr_top_n_270; wire i_mr_top_n_271; wire i_mr_top_n_272; wire i_mr_top_n_273; wire i_mr_top_n_274; wire i_mr_top_n_275; wire i_mr_top_n_276; wire i_mr_top_n_277; wire i_mr_top_n_278; wire i_mr_top_n_287; wire i_mr_top_n_288; wire i_mr_top_n_289; wire i_mr_top_n_290; wire i_mr_top_n_291; wire i_mr_top_n_292; wire i_mr_top_n_293; wire i_mr_top_n_294; wire i_mr_top_n_295; wire i_mr_top_n_296; wire i_mr_top_n_297; wire i_mr_top_n_298; wire i_mr_top_n_299; wire i_mr_top_n_3; wire i_mr_top_n_300; wire i_mr_top_n_301; wire i_mr_top_n_302; wire i_mr_top_n_312; wire i_mr_top_n_314; wire i_mr_top_n_315; wire i_mr_top_n_316; wire i_mr_top_n_317; wire i_mr_top_n_318; wire i_mr_top_n_319; wire i_mr_top_n_320; wire i_mr_top_n_321; wire i_mr_top_n_330; wire i_mr_top_n_331; wire i_mr_top_n_332; wire i_mr_top_n_333; wire i_mr_top_n_334; wire i_mr_top_n_335; wire i_mr_top_n_336; wire i_mr_top_n_337; wire i_mr_top_n_338; wire i_mr_top_n_339; wire i_mr_top_n_340; wire i_mr_top_n_341; wire i_mr_top_n_342; wire i_mr_top_n_343; wire i_mr_top_n_344; wire i_mr_top_n_345; wire i_mr_top_n_355; wire i_mr_top_n_356; wire i_mr_top_n_357; wire i_mr_top_n_358; wire i_mr_top_n_359; wire i_mr_top_n_360; wire i_mr_top_n_361; wire i_mr_top_n_362; wire i_mr_top_n_363; wire i_mr_top_n_372; wire i_mr_top_n_373; wire i_mr_top_n_374; wire i_mr_top_n_375; wire i_mr_top_n_376; wire i_mr_top_n_377; wire i_mr_top_n_378; wire i_mr_top_n_379; wire i_mr_top_n_380; wire i_mr_top_n_381; wire i_mr_top_n_382; wire i_mr_top_n_383; wire i_mr_top_n_384; wire i_mr_top_n_385; wire i_mr_top_n_386; wire i_mr_top_n_387; wire i_mr_top_n_397; wire i_mr_top_n_399; wire i_mr_top_n_400; wire i_mr_top_n_401; wire i_mr_top_n_403; wire i_mr_top_n_404; wire i_mr_top_n_406; wire i_mr_top_n_408; wire i_mr_top_n_409; wire i_mr_top_n_410; wire i_mr_top_n_411; wire i_mr_top_n_412; wire i_mr_top_n_413; wire i_mr_top_n_414; wire i_mr_top_n_415; wire i_mr_top_n_416; wire i_mr_top_n_417; wire i_mr_top_n_418; wire i_mr_top_n_419; wire i_mr_top_n_420; wire i_mr_top_n_421; wire i_mr_top_n_422; wire i_mr_top_n_423; wire i_mr_top_n_424; wire i_mr_top_n_425; wire i_mr_top_n_426; wire i_mr_top_n_427; wire i_mr_top_n_429; wire i_mr_top_n_430; wire i_mr_top_n_431; wire i_mr_top_n_432; wire i_mr_top_n_433; wire i_mr_top_n_434; wire i_mr_top_n_435; wire i_mr_top_n_436; wire i_mr_top_n_437; wire i_mr_top_n_438; wire i_mr_top_n_439; wire i_mr_top_n_440; wire i_mr_top_n_441; wire i_mr_top_n_442; wire i_mr_top_n_443; wire i_mr_top_n_444; wire i_mr_top_n_445; wire i_mr_top_n_446; wire i_mr_top_n_455; wire i_mr_top_n_456; wire i_mr_top_n_457; wire i_mr_top_n_472; wire i_mr_top_n_473; wire i_mr_top_n_474; wire i_mr_top_n_475; wire i_mr_top_n_476; wire i_mr_top_n_477; wire i_mr_top_n_478; wire i_mr_top_n_479; wire i_mr_top_n_480; wire i_mr_top_n_481; wire i_mr_top_n_482; wire i_mr_top_n_483; wire i_mr_top_n_484; wire i_mr_top_n_485; wire i_mr_top_n_486; wire i_mr_top_n_487; wire i_mr_top_n_488; wire i_mr_top_n_88; wire i_mr_top_n_89; wire i_mr_top_n_90; wire i_mr_top_n_91; wire i_mr_top_n_92; wire i_mr_top_n_93; wire i_mr_top_n_94; wire i_mr_top_n_95; wire i_mr_top_n_96; wire i_mr_top_n_97; wire i_mr_top_n_98; wire i_rst_sync_n_1; wire [14:14]\i_rxb_ram/rxb_port_a_data_in_i ; wire [0:0]\i_rxb_ram/rxb_port_b_address_i ; wire i_rxb_top_n_43; wire i_rxb_top_n_44; wire i_rxb_top_n_46; wire i_rxb_top_n_47; wire i_rxb_top_n_48; wire i_rxb_top_n_49; wire i_rxb_top_n_50; wire i_rxb_top_n_51; wire i_rxb_top_n_52; wire i_rxb_top_n_53; wire i_rxb_top_n_54; wire i_rxb_top_n_55; wire i_rxb_top_n_56; wire i_rxb_top_n_57; wire i_rxb_top_n_58; wire i_rxb_top_n_59; wire i_rxb_top_n_60; wire i_rxb_top_n_61; wire i_rxb_top_n_62; wire i_rxb_top_n_64; wire i_rxb_top_n_65; wire i_rxb_top_n_66; wire i_rxb_top_n_67; wire i_rxb_top_n_69; wire i_rxb_top_n_72; wire i_rxb_top_n_73; wire i_rxb_top_n_74; wire i_rxb_top_n_76; wire i_rxb_top_n_77; wire i_rxb_top_n_78; wire i_rxb_top_n_79; wire i_rxb_top_n_80; wire [0:0]\i_txarb_fsm/curr_state ; wire \i_txarb_fsm/fsm_wait_state_q ; wire i_txarb_top_n_100; wire i_txarb_top_n_101; wire i_txarb_top_n_102; wire i_txarb_top_n_103; wire i_txarb_top_n_104; wire i_txarb_top_n_105; wire i_txarb_top_n_106; wire i_txarb_top_n_107; wire i_txarb_top_n_108; wire i_txarb_top_n_109; wire i_txarb_top_n_110; wire i_txarb_top_n_111; wire i_txarb_top_n_112; wire i_txarb_top_n_113; wire i_txarb_top_n_114; wire i_txarb_top_n_115; wire i_txarb_top_n_116; wire i_txarb_top_n_117; wire i_txarb_top_n_118; wire i_txarb_top_n_119; wire i_txarb_top_n_120; wire i_txarb_top_n_121; wire i_txarb_top_n_124; wire i_txarb_top_n_125; wire i_txarb_top_n_126; wire i_txarb_top_n_30; wire i_txarb_top_n_34; wire i_txarb_top_n_35; wire i_txarb_top_n_37; wire i_txarb_top_n_39; wire i_txarb_top_n_40; wire i_txarb_top_n_41; wire i_txarb_top_n_42; wire i_txarb_top_n_43; wire i_txarb_top_n_44; wire i_txarb_top_n_45; wire i_txarb_top_n_46; wire i_txarb_top_n_47; wire i_txarb_top_n_48; wire i_txarb_top_n_49; wire i_txarb_top_n_50; wire i_txarb_top_n_51; wire i_txarb_top_n_53; wire i_txarb_top_n_59; wire i_txarb_top_n_74; wire i_txarb_top_n_75; wire i_txarb_top_n_76; wire i_txarb_top_n_77; wire i_txarb_top_n_81; wire i_txarb_top_n_82; wire i_txarb_top_n_83; wire i_txarb_top_n_84; wire i_txarb_top_n_85; wire i_txarb_top_n_86; wire i_txarb_top_n_87; wire i_txarb_top_n_88; wire i_txarb_top_n_89; wire i_txarb_top_n_90; wire i_txarb_top_n_91; wire i_txarb_top_n_92; wire i_txarb_top_n_93; wire i_txarb_top_n_94; wire i_txarb_top_n_95; wire i_txarb_top_n_96; wire i_txarb_top_n_97; wire i_txarb_top_n_98; wire i_txarb_top_n_99; wire [1:0]\i_txtb_fsm/curr_state ; wire [1:0]\i_txtb_fsm/curr_state_1 ; wire [1:0]\i_txtb_fsm/curr_state_3 ; wire [1:0]\i_txtb_fsm/curr_state_5 ; wire [7:0]\i_txtb_ram/p_0_in ; wire [7:0]\i_txtb_ram/p_0_in_13 ; wire [7:0]\i_txtb_ram/p_0_in_17 ; wire [7:0]\i_txtb_ram/p_0_in_20 ; wire \i_txtb_ram/tst_ena ; wire \i_txtb_ram/tst_ena_21 ; wire \i_txtb_ram/tst_ena_22 ; wire \i_txtb_ram/tst_ena_23 ; wire [4:0]\i_txtb_ram/txtb_port_a_address_i ; wire [4:0]\i_txtb_ram/txtb_port_a_address_i_11 ; wire [4:0]\i_txtb_ram/txtb_port_a_address_i_15 ; wire [4:0]\i_txtb_ram/txtb_port_a_address_i_18 ; wire [4:0]\i_txtb_ram/txtb_port_b_address_i ; wire [4:0]\i_txtb_ram/txtb_port_b_address_i_12 ; wire [4:0]\i_txtb_ram/txtb_port_b_address_i_16 ; wire [4:0]\i_txtb_ram/txtb_port_b_address_i_19 ; wire ident_valid_q; wire inc_ts_wr_ptr; wire int; wire int_OBUF; wire is_tseg1; wire is_tseg2; wire lopt; wire lopt_1; wire [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; wire [5:0]\mr_ctrl_out[btr_ph1] ; wire [5:0]\mr_ctrl_out[btr_ph2] ; wire [6:0]\mr_ctrl_out[btr_prop] ; wire [4:0]\mr_ctrl_out[btr_sjw] ; wire [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire [7:0]\mr_ctrl_out[erp_erp_limit] ; wire [7:0]\mr_ctrl_out[ewl_ew_limit] ; wire \mr_ctrl_out[mode_acf] ; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[mode_rxbam] ; wire \mr_ctrl_out[mode_sam] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[mode_tstm] ; wire \mr_ctrl_out[mode_tttm] ; wire \mr_ctrl_out[mode_txbbm] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_ctrl_out[settings_rtrle] ; wire [3:2]\mr_ctrl_out[settings_rtrth] ; wire \mr_ctrl_out[settings_tbfbo] ; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; wire [11:4]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_fcsi_o; wire mr_int_stat_txbhci_o; wire \mr_tst_out[tst_control_twrstb] ; wire [4:0]\mr_tst_out[tst_dest_tst_addr] ; wire [31:0]\mr_tst_out[tst_wdata_tst_wdata] ; wire [2:0]mr_tx_command_txbi; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txcr_q; wire [2:0]\mr_tx_priority[0] ; wire [2:0]\mr_tx_priority[1] ; wire [2:0]\mr_tx_priority[2] ; wire [2:0]\mr_tx_priority[3] ; wire nbt_ctrs_en; wire [7:0]neg_phase_err; wire p_0_out; wire \pc_dbg[is_arbitration] ; wire pc_rx_data_nbs; wire rec_abort; wire rec_abort_f; wire rec_brs; wire [3:0]rec_dlc; wire rec_erf; wire rec_esi; wire rec_frame_type; wire [28:0]rec_ident; wire rec_ident_type; wire rec_is_rtr; wire rec_ivld; wire rec_lbpf; wire rec_valid; wire reset_overrun_flag; wire rst_n; wire rst_n_IBUF; wire rst_n_out; wire rst_n_out_OBUF; wire rx_data_overrun; wire rx_data_wbs; wire rx_full; wire [0:0]rx_read_pointer; wire [31:0]rxb_port_b_data_out_i; wire [3:0]sbe; wire [3:0]sbe_IBUF; wire scan_mode; wire scan_mode_IBUF; wire scs; wire scs_IBUF; wire [5:0]segm_counter_q; wire [0:0]select_buf_index; wire [1:0]select_buf_index_reg; wire soft_res_d_n; wire srd; wire srd_IBUF; wire [8:0]ssp_delay; wire [31:0]store_data_word; wire store_metadata; wire swr; wire swr_IBUF; wire [1:0]sync_control; wire sync_edge; wire sync_flag; wire \test_probe[rx_trigger_nbs] ; wire \test_probe[rx_trigger_wbs] ; wire \test_probe[tx_trigger] ; wire [63:0]timestamp; wire [63:0]timestamp_IBUF; wire timestamp_capture_ce; wire [7:0]tq_counter_q; wire tran_brs; wire tran_delay_meas; wire [3:0]tran_dlc; wire \tran_frame_test[fcrc] ; wire \tran_frame_test[fstc] ; wire tran_frame_type; wire tran_frame_valid; wire tran_ident_type; wire [24:7]tran_identifier; wire tran_is_rtr; wire [31:0]tran_word; wire [7:7]trv_delay; wire [8:0]trv_delay_sum; wire [4:1]tseg1_dbt; wire tx_command_txce_valid; wire tx_command_txce_valid_7; wire tx_command_txce_valid_9; wire tx_command_txcr_valid; wire tx_command_txcr_valid_10; wire tx_command_txcr_valid_8; wire tx_trigger_ssp; wire [3:0]txtb_allow_bb; wire [3:0]txtb_available; wire \txtb_hw_cmd[failed] ; wire \txtb_hw_cmd[lock] ; wire \txtb_hw_cmd[valid] ; wire [3:0]txtb_hw_cmd_cs; wire [31:0]txtb_port_b_data_out_i; wire [31:0]txtb_port_b_data_out_i_2; wire [31:0]txtb_port_b_data_out_i_4; wire [31:0]txtb_port_b_data_out_i_6; wire [4:0]txtb_ptr; wire [1:0]\txtb_state[0] ; wire [1:0]\txtb_state[1] ; wire [1:1]\txtb_state[2] ; wire [1:1]\txtb_state[3] ; IBUF \adress_IBUF[10]_inst (.I(adress[10]), .O(adress_IBUF[10])); IBUF \adress_IBUF[11]_inst (.I(adress[11]), .O(adress_IBUF[11])); IBUF \adress_IBUF[2]_inst (.I(adress[2]), .O(adress_IBUF[2])); IBUF \adress_IBUF[3]_inst (.I(adress[3]), .O(adress_IBUF[3])); IBUF \adress_IBUF[4]_inst (.I(adress[4]), .O(adress_IBUF[4])); IBUF \adress_IBUF[5]_inst (.I(adress[5]), .O(adress_IBUF[5])); IBUF \adress_IBUF[6]_inst (.I(adress[6]), .O(adress_IBUF[6])); IBUF \adress_IBUF[7]_inst (.I(adress[7]), .O(adress_IBUF[7])); IBUF \adress_IBUF[8]_inst (.I(adress[8]), .O(adress_IBUF[8])); IBUF \adress_IBUF[9]_inst (.I(adress[9]), .O(adress_IBUF[9])); IBUF can_rx_IBUF_inst (.I(can_rx), .O(can_rx_IBUF)); OBUF can_tx_OBUF_inst (.I(can_tx_OBUF), .O(can_tx)); BUFG clk_sys_IBUF_BUFG_inst (.I(clk_sys_IBUF), .O(clk_sys_IBUF_BUFG)); IBUF clk_sys_IBUF_inst (.I(clk_sys), .O(clk_sys_IBUF)); IBUF \data_in_IBUF[0]_inst (.I(data_in[0]), .O(data_in_IBUF[0])); IBUF \data_in_IBUF[10]_inst (.I(data_in[10]), .O(data_in_IBUF[10])); IBUF \data_in_IBUF[11]_inst (.I(data_in[11]), .O(data_in_IBUF[11])); IBUF \data_in_IBUF[12]_inst (.I(data_in[12]), .O(data_in_IBUF[12])); IBUF \data_in_IBUF[13]_inst (.I(data_in[13]), .O(data_in_IBUF[13])); IBUF \data_in_IBUF[14]_inst (.I(data_in[14]), .O(data_in_IBUF[14])); IBUF \data_in_IBUF[15]_inst (.I(data_in[15]), .O(data_in_IBUF[15])); IBUF \data_in_IBUF[16]_inst (.I(data_in[16]), .O(data_in_IBUF[16])); IBUF \data_in_IBUF[17]_inst (.I(data_in[17]), .O(data_in_IBUF[17])); IBUF \data_in_IBUF[18]_inst (.I(data_in[18]), .O(data_in_IBUF[18])); IBUF \data_in_IBUF[19]_inst (.I(data_in[19]), .O(data_in_IBUF[19])); IBUF \data_in_IBUF[1]_inst (.I(data_in[1]), .O(data_in_IBUF[1])); IBUF \data_in_IBUF[20]_inst (.I(data_in[20]), .O(data_in_IBUF[20])); IBUF \data_in_IBUF[21]_inst (.I(data_in[21]), .O(data_in_IBUF[21])); IBUF \data_in_IBUF[22]_inst (.I(data_in[22]), .O(data_in_IBUF[22])); IBUF \data_in_IBUF[23]_inst (.I(data_in[23]), .O(data_in_IBUF[23])); IBUF \data_in_IBUF[24]_inst (.I(data_in[24]), .O(data_in_IBUF[24])); IBUF \data_in_IBUF[25]_inst (.I(data_in[25]), .O(data_in_IBUF[25])); IBUF \data_in_IBUF[26]_inst (.I(data_in[26]), .O(data_in_IBUF[26])); IBUF \data_in_IBUF[27]_inst (.I(data_in[27]), .O(data_in_IBUF[27])); IBUF \data_in_IBUF[28]_inst (.I(data_in[28]), .O(data_in_IBUF[28])); IBUF \data_in_IBUF[29]_inst (.I(data_in[29]), .O(data_in_IBUF[29])); IBUF \data_in_IBUF[2]_inst (.I(data_in[2]), .O(data_in_IBUF[2])); IBUF \data_in_IBUF[30]_inst (.I(data_in[30]), .O(data_in_IBUF[30])); IBUF \data_in_IBUF[31]_inst (.I(data_in[31]), .O(data_in_IBUF[31])); IBUF \data_in_IBUF[3]_inst (.I(data_in[3]), .O(data_in_IBUF[3])); IBUF \data_in_IBUF[4]_inst (.I(data_in[4]), .O(data_in_IBUF[4])); IBUF \data_in_IBUF[5]_inst (.I(data_in[5]), .O(data_in_IBUF[5])); IBUF \data_in_IBUF[6]_inst (.I(data_in[6]), .O(data_in_IBUF[6])); IBUF \data_in_IBUF[7]_inst (.I(data_in[7]), .O(data_in_IBUF[7])); IBUF \data_in_IBUF[8]_inst (.I(data_in[8]), .O(data_in_IBUF[8])); IBUF \data_in_IBUF[9]_inst (.I(data_in[9]), .O(data_in_IBUF[9])); OBUF \data_out_OBUF[0]_inst (.I(data_out_OBUF[0]), .O(data_out[0])); OBUF \data_out_OBUF[10]_inst (.I(data_out_OBUF[10]), .O(data_out[10])); OBUF \data_out_OBUF[11]_inst (.I(data_out_OBUF[11]), .O(data_out[11])); OBUF \data_out_OBUF[12]_inst (.I(data_out_OBUF[12]), .O(data_out[12])); OBUF \data_out_OBUF[13]_inst (.I(data_out_OBUF[13]), .O(data_out[13])); OBUF \data_out_OBUF[14]_inst (.I(data_out_OBUF[14]), .O(data_out[14])); OBUF \data_out_OBUF[15]_inst (.I(data_out_OBUF[15]), .O(data_out[15])); OBUF \data_out_OBUF[16]_inst (.I(data_out_OBUF[16]), .O(data_out[16])); OBUF \data_out_OBUF[17]_inst (.I(data_out_OBUF[17]), .O(data_out[17])); OBUF \data_out_OBUF[18]_inst (.I(data_out_OBUF[18]), .O(data_out[18])); OBUF \data_out_OBUF[19]_inst (.I(data_out_OBUF[19]), .O(data_out[19])); OBUF \data_out_OBUF[1]_inst (.I(data_out_OBUF[1]), .O(data_out[1])); OBUF \data_out_OBUF[20]_inst (.I(data_out_OBUF[20]), .O(data_out[20])); OBUF \data_out_OBUF[21]_inst (.I(data_out_OBUF[21]), .O(data_out[21])); OBUF \data_out_OBUF[22]_inst (.I(data_out_OBUF[22]), .O(data_out[22])); OBUF \data_out_OBUF[23]_inst (.I(data_out_OBUF[23]), .O(data_out[23])); OBUF \data_out_OBUF[24]_inst (.I(data_out_OBUF[24]), .O(data_out[24])); OBUF \data_out_OBUF[25]_inst (.I(data_out_OBUF[25]), .O(data_out[25])); OBUF \data_out_OBUF[26]_inst (.I(data_out_OBUF[26]), .O(data_out[26])); OBUF \data_out_OBUF[27]_inst (.I(data_out_OBUF[27]), .O(data_out[27])); OBUF \data_out_OBUF[28]_inst (.I(data_out_OBUF[28]), .O(data_out[28])); OBUF \data_out_OBUF[29]_inst (.I(data_out_OBUF[29]), .O(data_out[29])); OBUF \data_out_OBUF[2]_inst (.I(data_out_OBUF[2]), .O(data_out[2])); OBUF \data_out_OBUF[30]_inst (.I(data_out_OBUF[30]), .O(data_out[30])); OBUF \data_out_OBUF[31]_inst (.I(data_out_OBUF[31]), .O(data_out[31])); OBUF \data_out_OBUF[3]_inst (.I(data_out_OBUF[3]), .O(data_out[3])); OBUF \data_out_OBUF[4]_inst (.I(data_out_OBUF[4]), .O(data_out[4])); OBUF \data_out_OBUF[5]_inst (.I(data_out_OBUF[5]), .O(data_out[5])); OBUF \data_out_OBUF[6]_inst (.I(data_out_OBUF[6]), .O(data_out[6])); OBUF \data_out_OBUF[7]_inst (.I(data_out_OBUF[7]), .O(data_out[7])); OBUF \data_out_OBUF[8]_inst (.I(data_out_OBUF[8]), .O(data_out[8])); OBUF \data_out_OBUF[9]_inst (.I(data_out_OBUF[9]), .O(data_out[9])); txtb_even_top \g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top (.ADDRARDADDR(\i_txtb_ram/txtb_port_b_address_i_19 ), .ADDRBWRADDR(\i_txtb_ram/txtb_port_a_address_i_18 ), .D(\i_control_registers_reg_map/p_0_in [2]), .DIADI({i_mr_top_n_229,i_mr_top_n_230,i_mr_top_n_231,i_mr_top_n_232,i_mr_top_n_233,i_mr_top_n_234,i_mr_top_n_235,i_mr_top_n_236,\i_txtb_ram/p_0_in_20 }), .DIBDI({i_mr_top_n_245,i_mr_top_n_246,i_mr_top_n_247,i_mr_top_n_248,i_mr_top_n_249,i_mr_top_n_250,i_mr_top_n_251,i_mr_top_n_252,i_mr_top_n_253,i_mr_top_n_254,i_mr_top_n_255,i_mr_top_n_256,i_mr_top_n_257,i_mr_top_n_258,i_mr_top_n_259,i_mr_top_n_260}), .\FSM_sequential_curr_state_reg[0] (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_44 ), .\FSM_sequential_curr_state_reg[0]_0 (i_mac_top_n_99), .\FSM_sequential_curr_state_reg[0]_1 (i_mr_top_n_481), .\FSM_sequential_curr_state_reg[0]_2 (i_txarb_top_n_30), .\FSM_sequential_curr_state_reg[1] (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_45 ), .\FSM_sequential_curr_state_reg[1]_0 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_52 ), .\FSM_sequential_curr_state_reg[1]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_53 ), .\FSM_sequential_curr_state_reg[1]_10 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_62 ), .\FSM_sequential_curr_state_reg[1]_11 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_63 ), .\FSM_sequential_curr_state_reg[1]_12 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_64 ), .\FSM_sequential_curr_state_reg[1]_13 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_65 ), .\FSM_sequential_curr_state_reg[1]_14 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_66 ), .\FSM_sequential_curr_state_reg[1]_15 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_67 ), .\FSM_sequential_curr_state_reg[1]_16 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_68 ), .\FSM_sequential_curr_state_reg[1]_17 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_69 ), .\FSM_sequential_curr_state_reg[1]_18 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_70 ), .\FSM_sequential_curr_state_reg[1]_19 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_71 ), .\FSM_sequential_curr_state_reg[1]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_54 ), .\FSM_sequential_curr_state_reg[1]_20 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_72 ), .\FSM_sequential_curr_state_reg[1]_21 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_73 ), .\FSM_sequential_curr_state_reg[1]_22 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_74 ), .\FSM_sequential_curr_state_reg[1]_23 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_75 ), .\FSM_sequential_curr_state_reg[1]_24 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_76 ), .\FSM_sequential_curr_state_reg[1]_25 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_77 ), .\FSM_sequential_curr_state_reg[1]_26 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_78 ), .\FSM_sequential_curr_state_reg[1]_27 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_79 ), .\FSM_sequential_curr_state_reg[1]_28 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_80 ), .\FSM_sequential_curr_state_reg[1]_29 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_81 ), .\FSM_sequential_curr_state_reg[1]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_55 ), .\FSM_sequential_curr_state_reg[1]_30 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_82 ), .\FSM_sequential_curr_state_reg[1]_31 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_83 ), .\FSM_sequential_curr_state_reg[1]_32 (i_mac_top_n_101), .\FSM_sequential_curr_state_reg[1]_4 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_56 ), .\FSM_sequential_curr_state_reg[1]_5 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_57 ), .\FSM_sequential_curr_state_reg[1]_6 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_58 ), .\FSM_sequential_curr_state_reg[1]_7 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_59 ), .\FSM_sequential_curr_state_reg[1]_8 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_60 ), .\FSM_sequential_curr_state_reg[1]_9 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_61 ), .\FSM_sequential_curr_state_reg[2] (\txtb_state[0] ), .\FSM_sequential_curr_state_reg[2]_0 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_43 ), .\FSM_sequential_curr_state_reg[2]_1 (i_mr_top_n_228), .\FSM_sequential_curr_state_reg[2]_2 (curr_txtb_index), .\FSM_sequential_curr_state_reg[2]_3 (i_mr_top_n_270), .\FSM_sequential_curr_state_reg[2]_4 (i_mac_top_n_100), .Q(\cc_stat[err_pos] [3:1]), .abort_or_skipped(abort_or_skipped_0), .abort_or_skipped_0(abort_or_skipped), .\adress[3] (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_40 ), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .curr_state(\i_txtb_fsm/curr_state ), .\data_in[2] (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_41 ), .data_in_IBUF(data_in_IBUF[2:0]), .\err_capt_err_pos_q_reg[3] (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_42 ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .mr_tx_command_txbi({mr_tx_command_txbi[2],mr_tx_command_txbi[0]}), .mr_tx_command_txca_q(mr_tx_command_txca_q), .mr_tx_command_txce_q(mr_tx_command_txce_q), .mr_tx_command_txce_q_reg_0(i_im_top_n_11), .mr_tx_command_txce_q_reg_1(i_mr_top_n_205), .mr_tx_command_txce_q_reg_2(i_mr_top_n_172), .mr_tx_command_txcr_q(mr_tx_command_txcr_q), .\mr_tx_priority[0] (\mr_tx_priority[0] [2:1]), .\r_data[2]_i_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_39 ), .\r_data[2]_i_2_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_39 ), .\r_data[2]_i_2_1 (i_im_top_n_3), .\r_data[2]_i_2_2 (i_mr_top_n_473), .\r_data_reg[2] (i_mac_top_n_214), .\r_data_reg[2]_0 (i_bm_top_n_10), .\r_data_reg[2]_1 (i_mr_top_n_163), .\r_data_reg[2]_2 (i_mr_top_n_186), .\r_data_reg[2]_3 (i_mr_top_n_89), .\r_data_reg[2]_4 (i_rxb_top_n_67), .\r_data_reg[2]_5 (i_mr_top_n_472), .sbe_IBUF(sbe_IBUF), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .tst_ena(\i_txtb_ram/tst_ena_22 ), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txcr_valid(tx_command_txcr_valid), .txtb_allow_bb(txtb_allow_bb[0]), .txtb_available(txtb_available[0]), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .txtb_hw_cmd_cs(txtb_hw_cmd_cs[0]), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); txtb_odd_top \g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top (.ADDRARDADDR(\i_txtb_ram/txtb_port_b_address_i_16 ), .ADDRBWRADDR(\i_txtb_ram/txtb_port_a_address_i_15 ), .DIADI({i_mr_top_n_271,i_mr_top_n_272,i_mr_top_n_273,i_mr_top_n_274,i_mr_top_n_275,i_mr_top_n_276,i_mr_top_n_277,i_mr_top_n_278,\i_txtb_ram/p_0_in_17 }), .DIBDI({i_mr_top_n_287,i_mr_top_n_288,i_mr_top_n_289,i_mr_top_n_290,i_mr_top_n_291,i_mr_top_n_292,i_mr_top_n_293,i_mr_top_n_294,i_mr_top_n_295,i_mr_top_n_296,i_mr_top_n_297,i_mr_top_n_298,i_mr_top_n_299,i_mr_top_n_300,i_mr_top_n_301,i_mr_top_n_302}), .\FSM_sequential_curr_state[0]_i_11 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_44 ), .\FSM_sequential_curr_state[2]_i_5__0 (i_mac_top_n_98), .\FSM_sequential_curr_state[2]_i_5__0_0 (i_mac_top_n_99), .\FSM_sequential_curr_state_reg[0] (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_32 ), .\FSM_sequential_curr_state_reg[0]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_41 ), .\FSM_sequential_curr_state_reg[0]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_43 ), .\FSM_sequential_curr_state_reg[0]_2 (i_txarb_top_n_35), .\FSM_sequential_curr_state_reg[0]_3 (i_mr_top_n_481), .\FSM_sequential_curr_state_reg[1] (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_38 ), .\FSM_sequential_curr_state_reg[1]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_44 ), .\FSM_sequential_curr_state_reg[1]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_45 ), .\FSM_sequential_curr_state_reg[1]_10 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_54 ), .\FSM_sequential_curr_state_reg[1]_11 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_55 ), .\FSM_sequential_curr_state_reg[1]_12 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_56 ), .\FSM_sequential_curr_state_reg[1]_13 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_57 ), .\FSM_sequential_curr_state_reg[1]_14 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_58 ), .\FSM_sequential_curr_state_reg[1]_15 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_59 ), .\FSM_sequential_curr_state_reg[1]_16 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_60 ), .\FSM_sequential_curr_state_reg[1]_17 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_61 ), .\FSM_sequential_curr_state_reg[1]_18 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_62 ), .\FSM_sequential_curr_state_reg[1]_19 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_63 ), .\FSM_sequential_curr_state_reg[1]_2 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_46 ), .\FSM_sequential_curr_state_reg[1]_20 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_64 ), .\FSM_sequential_curr_state_reg[1]_21 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_65 ), .\FSM_sequential_curr_state_reg[1]_22 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_66 ), .\FSM_sequential_curr_state_reg[1]_23 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_67 ), .\FSM_sequential_curr_state_reg[1]_24 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_68 ), .\FSM_sequential_curr_state_reg[1]_25 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_69 ), .\FSM_sequential_curr_state_reg[1]_26 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_70 ), .\FSM_sequential_curr_state_reg[1]_27 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_71 ), .\FSM_sequential_curr_state_reg[1]_28 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_72 ), .\FSM_sequential_curr_state_reg[1]_29 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_73 ), .\FSM_sequential_curr_state_reg[1]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_47 ), .\FSM_sequential_curr_state_reg[1]_30 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_74 ), .\FSM_sequential_curr_state_reg[1]_31 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_75 ), .\FSM_sequential_curr_state_reg[1]_32 (i_mac_top_n_103), .\FSM_sequential_curr_state_reg[1]_4 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_48 ), .\FSM_sequential_curr_state_reg[1]_5 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_49 ), .\FSM_sequential_curr_state_reg[1]_6 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_50 ), .\FSM_sequential_curr_state_reg[1]_7 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_51 ), .\FSM_sequential_curr_state_reg[1]_8 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_52 ), .\FSM_sequential_curr_state_reg[1]_9 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_53 ), .\FSM_sequential_curr_state_reg[2] (\txtb_state[1] ), .\FSM_sequential_curr_state_reg[2]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_42 ), .\FSM_sequential_curr_state_reg[2]_1 (i_mr_top_n_312), .\FSM_sequential_curr_state_reg[2]_2 (i_mac_top_n_102), .\FSM_sequential_curr_state_reg[2]_3 (i_txarb_top_n_34), .\FSM_sequential_curr_state_reg[2]_4 (i_mr_top_n_228), .Q(\cc_stat[err_type] [2:1]), .abort_applied(abort_applied_14), .adress_IBUF({adress_IBUF[11:8],adress_IBUF[3:2]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .curr_state(\i_txtb_fsm/curr_state_1 ), .\err_capt_err_type_q_reg[1] (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_37 ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .\mr_tx_priority[1] (\mr_tx_priority[1] [2]), .sbe_IBUF(sbe_IBUF), .scs_IBUF(scs_IBUF), .\select_buf_index_reg_reg[1] (txtb_available[0]), .swr_IBUF(swr_IBUF), .tst_ena(\i_txtb_ram/tst_ena_21 ), .tx_command_txce_valid(tx_command_txce_valid_7), .tx_command_txcr_valid(tx_command_txcr_valid_8), .txtb_allow_bb(txtb_allow_bb[1]), .txtb_available(txtb_available[1]), .txtb_hw_cmd_cs(txtb_hw_cmd_cs[1]), .txtb_port_b_data_out_i(txtb_port_b_data_out_i_2)); txtb_even_top__parameterized0 \g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top (.ADDRARDADDR(\i_txtb_ram/txtb_port_b_address_i_12 ), .ADDRBWRADDR(\i_txtb_ram/txtb_port_a_address_i_11 ), .DIADI({i_mr_top_n_314,i_mr_top_n_315,i_mr_top_n_316,i_mr_top_n_317,i_mr_top_n_318,i_mr_top_n_319,i_mr_top_n_320,i_mr_top_n_321,\i_txtb_ram/p_0_in_13 }), .DIBDI({i_mr_top_n_330,i_mr_top_n_331,i_mr_top_n_332,i_mr_top_n_333,i_mr_top_n_334,i_mr_top_n_335,i_mr_top_n_336,i_mr_top_n_337,i_mr_top_n_338,i_mr_top_n_339,i_mr_top_n_340,i_mr_top_n_341,i_mr_top_n_342,i_mr_top_n_343,i_mr_top_n_344,i_mr_top_n_345}), .\FSM_sequential_curr_state_reg[0] (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_32 ), .\FSM_sequential_curr_state_reg[0]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_40 ), .\FSM_sequential_curr_state_reg[0]_1 (i_mac_top_n_99), .\FSM_sequential_curr_state_reg[0]_2 (i_mr_top_n_481), .\FSM_sequential_curr_state_reg[0]_3 (i_txarb_top_n_37), .\FSM_sequential_curr_state_reg[1] (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_39 ), .\FSM_sequential_curr_state_reg[1]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_41 ), .\FSM_sequential_curr_state_reg[1]_1 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_45 ), .\FSM_sequential_curr_state_reg[1]_10 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_54 ), .\FSM_sequential_curr_state_reg[1]_11 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_55 ), .\FSM_sequential_curr_state_reg[1]_12 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_56 ), .\FSM_sequential_curr_state_reg[1]_13 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_57 ), .\FSM_sequential_curr_state_reg[1]_14 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_58 ), .\FSM_sequential_curr_state_reg[1]_15 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_59 ), .\FSM_sequential_curr_state_reg[1]_16 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_60 ), .\FSM_sequential_curr_state_reg[1]_17 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_61 ), .\FSM_sequential_curr_state_reg[1]_18 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_62 ), .\FSM_sequential_curr_state_reg[1]_19 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_63 ), .\FSM_sequential_curr_state_reg[1]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_46 ), .\FSM_sequential_curr_state_reg[1]_20 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_64 ), .\FSM_sequential_curr_state_reg[1]_21 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_65 ), .\FSM_sequential_curr_state_reg[1]_22 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_66 ), .\FSM_sequential_curr_state_reg[1]_23 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_67 ), .\FSM_sequential_curr_state_reg[1]_24 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_68 ), .\FSM_sequential_curr_state_reg[1]_25 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_69 ), .\FSM_sequential_curr_state_reg[1]_26 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_70 ), .\FSM_sequential_curr_state_reg[1]_27 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_71 ), .\FSM_sequential_curr_state_reg[1]_28 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_72 ), .\FSM_sequential_curr_state_reg[1]_29 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_73 ), .\FSM_sequential_curr_state_reg[1]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_47 ), .\FSM_sequential_curr_state_reg[1]_30 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_74 ), .\FSM_sequential_curr_state_reg[1]_31 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_75 ), .\FSM_sequential_curr_state_reg[1]_32 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_76 ), .\FSM_sequential_curr_state_reg[1]_33 (i_mac_top_n_105), .\FSM_sequential_curr_state_reg[1]_4 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_48 ), .\FSM_sequential_curr_state_reg[1]_5 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_49 ), .\FSM_sequential_curr_state_reg[1]_6 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_50 ), .\FSM_sequential_curr_state_reg[1]_7 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_51 ), .\FSM_sequential_curr_state_reg[1]_8 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_52 ), .\FSM_sequential_curr_state_reg[1]_9 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_53 ), .\FSM_sequential_curr_state_reg[2] (\txtb_state[2] ), .\FSM_sequential_curr_state_reg[2]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_37 ), .\FSM_sequential_curr_state_reg[2]_1 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_44 ), .\FSM_sequential_curr_state_reg[2]_2 (curr_txtb_index), .\FSM_sequential_curr_state_reg[2]_3 (i_mr_top_n_355), .\FSM_sequential_curr_state_reg[2]_4 (i_mac_top_n_104), .\FSM_sequential_curr_state_reg[2]_5 (i_mr_top_n_228), .Q(\cc_stat[retr_ctr] ), .abort_or_skipped(abort_or_skipped), .adress_IBUF({adress_IBUF[11:8],adress_IBUF[3:2]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .curr_state(\i_txtb_fsm/curr_state_3 ), .curr_state_0(\i_txtb_fsm/curr_state_1 ), .fsm_wait_state_q_i_5(txtb_available[3]), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .mr_tx_command_txbi(mr_tx_command_txbi[2]), .mr_tx_command_txca_q(mr_tx_command_txca_q), .mr_tx_command_txce_q(mr_tx_command_txce_q), .mr_tx_command_txcr_q(mr_tx_command_txcr_q), .\mr_tx_priority[2] (\mr_tx_priority[2] ), .\r_data[2]_i_5 (\txtb_state[1] [1]), .\retr_ctr_q_reg[0] (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_36 ), .\retr_ctr_q_reg[2] (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_38 ), .sbe_IBUF(sbe_IBUF), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .tst_ena(\i_txtb_ram/tst_ena_23 ), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txcr_valid(tx_command_txcr_valid), .txtb_allow_bb(txtb_allow_bb[2]), .txtb_available(txtb_available[2]), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .txtb_hw_cmd_cs(txtb_hw_cmd_cs[2]), .txtb_port_b_data_out_i(txtb_port_b_data_out_i_4)); txtb_odd_top__parameterized0 \g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top (.ADDRARDADDR(\i_txtb_ram/txtb_port_b_address_i ), .ADDRBWRADDR(\i_txtb_ram/txtb_port_a_address_i ), .DIADI({i_mr_top_n_356,i_mr_top_n_357,i_mr_top_n_358,i_mr_top_n_359,i_mr_top_n_360,i_mr_top_n_361,i_mr_top_n_362,i_mr_top_n_363,\i_txtb_ram/p_0_in }), .DIBDI({i_mr_top_n_372,i_mr_top_n_373,i_mr_top_n_374,i_mr_top_n_375,i_mr_top_n_376,i_mr_top_n_377,i_mr_top_n_378,i_mr_top_n_379,i_mr_top_n_380,i_mr_top_n_381,i_mr_top_n_382,i_mr_top_n_383,i_mr_top_n_384,i_mr_top_n_385,i_mr_top_n_386,i_mr_top_n_387}), .\FSM_sequential_curr_state[2]_i_5__2 (i_mac_top_n_98), .\FSM_sequential_curr_state[2]_i_5__2_0 (i_mac_top_n_99), .\FSM_sequential_curr_state_reg[0] (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_36 ), .\FSM_sequential_curr_state_reg[0]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_38 ), .\FSM_sequential_curr_state_reg[0]_1 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_43 ), .\FSM_sequential_curr_state_reg[0]_2 (i_txarb_top_n_40), .\FSM_sequential_curr_state_reg[0]_3 (i_mr_top_n_481), .\FSM_sequential_curr_state_reg[1] (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_39 ), .\FSM_sequential_curr_state_reg[1]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_40 ), .\FSM_sequential_curr_state_reg[1]_1 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_44 ), .\FSM_sequential_curr_state_reg[1]_10 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_53 ), .\FSM_sequential_curr_state_reg[1]_11 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_54 ), .\FSM_sequential_curr_state_reg[1]_12 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_55 ), .\FSM_sequential_curr_state_reg[1]_13 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_56 ), .\FSM_sequential_curr_state_reg[1]_14 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_57 ), .\FSM_sequential_curr_state_reg[1]_15 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_58 ), .\FSM_sequential_curr_state_reg[1]_16 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_59 ), .\FSM_sequential_curr_state_reg[1]_17 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_60 ), .\FSM_sequential_curr_state_reg[1]_18 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_61 ), .\FSM_sequential_curr_state_reg[1]_19 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_62 ), .\FSM_sequential_curr_state_reg[1]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_45 ), .\FSM_sequential_curr_state_reg[1]_20 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_63 ), .\FSM_sequential_curr_state_reg[1]_21 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_64 ), .\FSM_sequential_curr_state_reg[1]_22 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_65 ), .\FSM_sequential_curr_state_reg[1]_23 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_66 ), .\FSM_sequential_curr_state_reg[1]_24 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_67 ), .\FSM_sequential_curr_state_reg[1]_25 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_68 ), .\FSM_sequential_curr_state_reg[1]_26 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_69 ), .\FSM_sequential_curr_state_reg[1]_27 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_70 ), .\FSM_sequential_curr_state_reg[1]_28 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_71 ), .\FSM_sequential_curr_state_reg[1]_29 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_72 ), .\FSM_sequential_curr_state_reg[1]_3 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_46 ), .\FSM_sequential_curr_state_reg[1]_30 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_73 ), .\FSM_sequential_curr_state_reg[1]_31 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_74 ), .\FSM_sequential_curr_state_reg[1]_32 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_75 ), .\FSM_sequential_curr_state_reg[1]_33 (i_mac_top_n_107), .\FSM_sequential_curr_state_reg[1]_4 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_47 ), .\FSM_sequential_curr_state_reg[1]_5 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_48 ), .\FSM_sequential_curr_state_reg[1]_6 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_49 ), .\FSM_sequential_curr_state_reg[1]_7 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_50 ), .\FSM_sequential_curr_state_reg[1]_8 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_51 ), .\FSM_sequential_curr_state_reg[1]_9 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_52 ), .\FSM_sequential_curr_state_reg[2] (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_32 ), .\FSM_sequential_curr_state_reg[2]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_37 ), .\FSM_sequential_curr_state_reg[2]_1 (txtb_available[3]), .\FSM_sequential_curr_state_reg[2]_2 (i_mr_top_n_397), .\FSM_sequential_curr_state_reg[2]_3 (i_mac_top_n_106), .\FSM_sequential_curr_state_reg[2]_4 (i_txarb_top_n_39), .\FSM_sequential_curr_state_reg[2]_5 (i_mr_top_n_228), .abort_applied(abort_applied), .adress_IBUF({adress_IBUF[11:8],adress_IBUF[4:2]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .curr_state(\i_txtb_fsm/curr_state_5 ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .\mr_tx_priority[3] (\mr_tx_priority[3] ), .\r_data[15]_i_2 (i_rxb_top_n_57), .sbe_IBUF(sbe_IBUF), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .tst_ena(\i_txtb_ram/tst_ena ), .tx_command_txce_valid(tx_command_txce_valid_9), .tx_command_txcr_valid(tx_command_txcr_valid_10), .txtb_allow_bb(txtb_allow_bb[3]), .txtb_hw_cmd_cs(txtb_hw_cmd_cs[3]), .txtb_port_b_data_out_i(txtb_port_b_data_out_i_6), .\txtb_state[3] (\txtb_state[3] )); bm_top i_bm_top (.D(ssp_delay), .Q(trv_delay), .adress_IBUF(adress_IBUF[3:2]), .bit_err(bit_err), .bit_err_d0_out(\i_bm_bit_err_detector/bit_err_d0_out ), .bit_err_d2(bit_err_d2), .bit_err_enable(bit_err_enable), .btmc_meas_running_q(btmc_meas_running_q), .btmc_meas_running_q_reg(i_mac_top_n_224), .\btmc_q_reg[0] (i_mac_top_n_218), .can_rx_IBUF(can_rx_IBUF), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[bst_ctr] (\cc_stat[bst_ctr] ), .\cc_stat[dst_ctr] (\cc_stat[dst_ctr] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .first_ssp_q0(\i_bm_ssp_generator/first_ssp_q0 ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .p_0_out(p_0_out), .\pc_dbg[is_arbitration] (\pc_dbg[is_arbitration] ), .prev_sample_q_reg(i_bm_top_n_16), .prev_sample_q_reg_0(i_btl_top_n_3), .prev_sample_q_reg_1(i_mac_top_n_209), .\r_data_reg[6] (i_mr_top_n_177), .\r_data_reg[6]_0 (i_mr_top_n_220), .reg_q_reg(i_mr_top_n_228), .reg_q_reg_0(i_mac_top_n_217), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_sync_prev_reg(i_mac_top_n_206), .rx_data_sync_prev_reg_0(i_mac_top_n_121), .rx_data_sync_prev_reg_1(i_mr_top_n_442), .rx_data_wbs(rx_data_wbs), .scan_mode_IBUF(scan_mode_IBUF), .sspc_ena_q(\i_bm_ssp_generator/sspc_ena_q ), .sspc_ena_q_reg(i_mac_top_n_223), .sync_edge(sync_edge), .sync_edge3__0(\i_bm_data_edge_detector/sync_edge3__0 ), .\timestamp[32] (i_bm_top_n_7), .\timestamp[33] (i_bm_top_n_9), .\timestamp[34] (i_bm_top_n_10), .\timestamp[35] (i_bm_top_n_11), .\timestamp[37] (i_bm_top_n_12), .\timestamp[4] (i_bm_top_n_6), .timestamp_IBUF({timestamp_IBUF[37:32],timestamp_IBUF[5:0]}), .tran_delay_meas(tran_delay_meas), .\trv_delay_shadowed_reg[6] (i_bm_top_n_13), .trv_delay_sum(trv_delay_sum), .tx_data_prev(\i_bm_data_edge_detector/tx_data_prev ), .tx_trigger_ssp(tx_trigger_ssp), .\write_pointer_q_reg[0] (\i_bm_tx_data_cache/write_pointer_q_reg ), .\write_pointer_q_reg[0]_0 (i_mac_top_n_225)); btl_top i_btl_top (.CO(\i_btl_segment_meter_dbt/phase_err_mt_sjw ), .D(i_mr_top_n_483), .DI(i_mr_top_n_455), .E(\i_btl_counters_nbt/segm_counter_ce ), .\FSM_onehot_current_state_reg[1] (i_btl_top_n_7), .\FSM_onehot_current_state_reg[1]_0 (i_btl_top_n_17), .\FSM_onehot_current_state_reg[1]_1 (i_btl_top_n_47), .\FSM_onehot_current_state_reg[2] (i_btl_top_n_3), .\FSM_onehot_current_state_reg[2]_0 (i_btl_top_n_9), .\FSM_onehot_current_state_reg[2]_1 (i_btl_top_n_12), .\FSM_onehot_current_state_reg[2]_10 (i_btl_top_n_57), .\FSM_onehot_current_state_reg[2]_11 (i_btl_top_n_58), .\FSM_onehot_current_state_reg[2]_12 (i_btl_top_n_59), .\FSM_onehot_current_state_reg[2]_2 (i_btl_top_n_48), .\FSM_onehot_current_state_reg[2]_3 (i_btl_top_n_50), .\FSM_onehot_current_state_reg[2]_4 (i_btl_top_n_51), .\FSM_onehot_current_state_reg[2]_5 (i_btl_top_n_52), .\FSM_onehot_current_state_reg[2]_6 (i_btl_top_n_53), .\FSM_onehot_current_state_reg[2]_7 (i_btl_top_n_54), .\FSM_onehot_current_state_reg[2]_8 (i_btl_top_n_55), .\FSM_onehot_current_state_reg[2]_9 (i_btl_top_n_56), .O({i_mr_top_n_431,i_mr_top_n_432}), .Q(tseg1_dbt), .S({i_mr_top_n_445,i_mr_top_n_446}), .can_tx_OBUF(can_tx_OBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_tx_wbs(crc_data_tx_wbs), .current_state_reg(\i_btl_fsm/current_state_reg ), .destuffed(destuffed), .\dst_ctr_q_reg[1] (i_mac_top_n_134), .\exp_seg_length_q[3]_i_11__0 ({i_mr_top_n_436,i_mr_top_n_437,i_mr_top_n_438}), .\exp_seg_length_q[3]_i_11__0_0 ({i_mr_top_n_433,i_mr_top_n_434,i_mr_top_n_435}), .\exp_seg_length_q[7]_i_11 (sync_control), .\exp_seg_length_q_reg[0] (i_mac_top_n_203), .\exp_seg_length_q_reg[3] ({i_mr_top_n_484,i_mr_top_n_485,i_mr_top_n_486,i_mr_top_n_487}), .\exp_seg_length_q_reg[7] (i_mr_top_n_427), .\exp_seg_length_q_reg[7]_0 (i_mr_top_n_488), .\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2 (i_mr_top_n_443), .\g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_2_0 (i_mr_top_n_444), .\g_segm_end_req_capture[1].segm_end_req_capt_q_reg[1] (i_mr_top_n_456), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2] (i_mr_top_n_480), .\g_segm_end_req_capture[2].segm_end_req_capt_q_reg[2]_0 (i_mr_top_n_430), .i__carry_i_3__3({i_mr_top_n_439,i_mr_top_n_440,i_mr_top_n_441}), .is_tseg1(is_tseg1), .is_tseg2(is_tseg2), .lopt(lopt_1), .mr_btr_prop(\mr_ctrl_out[btr_prop] ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] ), .\mr_ctrl_out[btr_fd_ph2_fd] (\mr_ctrl_out[btr_fd_ph2_fd] ), .\mr_ctrl_out[btr_fd_prop_fd] (\mr_ctrl_out[btr_fd_prop_fd] ), .\mr_ctrl_out[btr_ph1] (\mr_ctrl_out[btr_ph1] ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] ), .\mr_ctrl_out[btr_sjw] (\mr_ctrl_out[btr_sjw] ), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .mr_settings_ena_reg(\i_btl_cfg_capture/mr_settings_ena_reg ), .neg_phase_err(neg_phase_err), .reg_q_reg(i_btl_top_n_49), .reg_q_reg_0(i_mac_top_n_206), .reg_q_reg_1(i_mac_top_n_202), .reg_q_reg_2(i_mr_top_n_457), .rx_trig_req_q_reg(i_btl_top_n_2), .rx_trig_req_q_reg_0(i_btl_top_n_5), .rx_trig_req_q_reg_1(i_btl_top_n_6), .rx_trig_req_q_reg_2(i_btl_top_n_11), .rx_trig_req_q_reg_3(i_mr_top_n_228), .\segm_counter_q_reg[0] (i_mac_top_n_136), .\segm_counter_q_reg[0]_0 (\i_btl_counters_dbt/segm_counter_ce ), .\segm_counter_q_reg[5] (segm_counter_q), .\segm_counter_q_reg[6] ({i_btl_top_n_24,i_btl_top_n_25,i_btl_top_n_26,i_btl_top_n_27,i_btl_top_n_28,i_btl_top_n_29,i_btl_top_n_30}), .\segm_counter_q_reg[6]_0 ({i_btl_top_n_62,i_btl_top_n_63}), .\segm_counter_q_reg[7] ({i_btl_top_n_60,i_btl_top_n_61}), .sync_edge(sync_edge), .sync_flag(sync_flag), .sync_flag_reg(i_mac_top_n_220), .\tq_counter_q_reg[0] (nbt_ctrs_en), .\tq_counter_q_reg[0]_0 (dbt_ctrs_en), .\tq_counter_q_reg[7] ({i_btl_top_n_31,i_btl_top_n_32,i_btl_top_n_33,i_btl_top_n_34,i_btl_top_n_35,i_btl_top_n_36,i_btl_top_n_37,i_btl_top_n_38}), .\tq_counter_q_reg[7]_0 (tq_counter_q), .\tq_counter_q_reg[7]_1 (i_mr_top_n_442), .\tq_counter_q_reg[7]_2 (i_mr_top_n_429), .\tseg1_dbt_reg[0] (\i_btl_cfg_capture/capture )); ff_top i_ff_top (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .commit_overrun_abort(commit_overrun_abort), .ident_valid_q(ident_valid_q), .ident_valid_q_reg_0(i_ff_top_n_1), .ident_valid_q_reg_1(i_ff_top_n_2), .ident_valid_q_reg_2(i_mr_top_n_228), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .rec_abort(rec_abort)); im_top i_im_top (.D(\i_control_registers_reg_map/p_0_in [10:8]), .\adress[4] (i_im_top_n_7), .\adress[5] (i_im_top_n_9), .\adress[5]_0 (i_im_top_n_10), .adress_IBUF(adress_IBUF[7:2]), .arbitration_lost(arbitration_lost), .br_shifted(br_shifted), .\cc_stat[is_transmitter] (\cc_stat[is_transmitter] ), .\cc_stat[status_pexs] (\cc_stat[status_pexs] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[11:0]), .data_overrun_flg_reg(i_im_top_n_8), .err_detected(err_detected), .err_frm_req(\i_mac_pc_top/err_frm_req ), .err_warning_limit_q(err_warning_limit_q), .\g_bit[0].reg_value_r_reg[0] (i_im_top_n_3), .\g_bit[0].reg_value_r_reg[0]_0 (i_im_top_n_15), .\g_bit[0].reg_value_r_reg[0]_1 (i_im_top_n_17), .int_OBUF(int_OBUF), .int_mask_i_reg({mr_int_mask_set_int_mask_set_o[11],mr_int_mask_set_int_mask_set_o[4]}), .int_mask_i_reg_0(i_im_top_n_18), .int_mask_i_reg_1(i_mr_top_n_172), .int_status_reg(i_im_top_n_16), .int_status_reg_0(i_im_top_n_19), .int_status_reg_1(i_mac_top_n_222), .int_status_reg_2(i_mac_top_n_221), .int_status_reg_3(i_mr_top_n_163), .int_status_reg_4(i_mac_top_n_199), .int_status_reg_5(\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_41 ), .int_status_reg_6(i_mac_top_n_198), .int_status_reg_7(i_rxb_top_n_43), .\mr_ctrl_out[mode_acf] (\mr_ctrl_out[mode_acf] ), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .\mr_ctrl_out[mode_sam] (\mr_ctrl_out[mode_sam] ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .\mr_ctrl_out[mode_tstm] (\mr_ctrl_out[mode_tstm] ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .\mr_ctrl_out[mode_txbbm] (\mr_ctrl_out[mode_txbbm] ), .mr_int_stat_fcsi_o(mr_int_stat_fcsi_o), .mr_int_stat_txbhci_o(mr_int_stat_txbhci_o), .\r_data[10]_i_2__0 (i_mr_top_n_207), .\r_data[3]_i_2 (i_mac_top_n_54), .\r_data[7]_i_2__0 (i_mac_top_n_56), .\r_data[8]_i_2 (i_mac_top_n_57), .\r_data[9]_i_2__0 (i_mr_top_n_206), .\r_data_reg[10] (i_mac_top_n_61), .\r_data_reg[10]_0 (i_mr_top_n_94), .\r_data_reg[10]_1 (i_rxb_top_n_51), .\r_data_reg[3]_i_5 (i_mr_top_n_3), .\r_data_reg[3]_i_5_0 (i_mac_top_n_219), .\r_data_reg[7]_i_6 (i_mac_top_n_67), .\r_data_reg[8] (i_mac_top_n_40), .\r_data_reg[8]_0 (i_rxb_top_n_49), .\r_data_reg[8]_1 (i_mr_top_n_92), .\r_data_reg[9] (i_mac_top_n_60), .\r_data_reg[9]_0 (i_mr_top_n_186), .\r_data_reg[9]_1 (i_mr_top_n_93), .\r_data_reg[9]_2 (i_rxb_top_n_50), .rec_valid(rec_valid), .reg_q_reg(i_mr_top_n_1), .rx_data_overrun(rx_data_overrun), .rx_full(rx_full), .\sbe[1] (i_im_top_n_12), .sbe_IBUF(sbe_IBUF[1:0]), .swr(i_im_top_n_11), .swr_IBUF(swr_IBUF), .\txtb_hw_cmd[valid] (\txtb_hw_cmd[valid] )); mac_top i_mac_top (.D({\i_control_registers_reg_map/p_0_in [19:13],\i_control_registers_reg_map/p_0_in [6],\i_control_registers_reg_map/p_0_in [4]}), .DI({i_mr_top_n_415,i_mr_top_n_416,i_mr_top_n_417,i_mr_top_n_418}), .E(timestamp_capture_ce), .\FSM_onehot_curr_state_reg[1] (i_ff_top_n_2), .\FSM_onehot_curr_state_reg[5] (i_mac_top_n_84), .\FSM_onehot_curr_state_reg[5]_0 (i_mac_top_n_90), .\FSM_sequential_curr_state[0]_i_7 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_42 ), .\FSM_sequential_curr_state[0]_i_7_0 (i_txarb_top_n_53), .\FSM_sequential_curr_state[1]_i_2__0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_41 ), .\FSM_sequential_curr_state[1]_i_2__2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_43 ), .\FSM_sequential_curr_state[2]_i_3__3 (i_txarb_top_n_51), .\FSM_sequential_curr_state[2]_i_3__3_0 (i_mr_top_n_400), .\FSM_sequential_curr_state_reg[0] (i_mac_top_n_108), .\FSM_sequential_curr_state_reg[1] (\i_mac_fc_top/i_mac_fc_fsm/curr_state ), .\FSM_sequential_curr_state_reg[1]_0 (i_mac_top_n_67), .\FSM_sequential_curr_state_reg[1]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_44 ), .\FSM_sequential_curr_state_reg[1]_2 (i_mr_top_n_481), .\FSM_sequential_curr_state_reg[1]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_40 ), .\FSM_sequential_curr_state_reg[2] (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_45 ), .\FSM_sequential_curr_state_reg[2]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_38 ), .\FSM_sequential_curr_state_reg[2]_1 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_41 ), .\FSM_sequential_curr_state_reg[2]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_40 ), .Q(\cc_stat[rx_err_ctr] ), .S({i_mr_top_n_411,i_mr_top_n_412,i_mr_top_n_413,i_mr_top_n_414}), .abort_applied(abort_applied_14), .abort_applied_5(abort_applied), .abort_or_skipped(abort_or_skipped_0), .abort_or_skipped_3(abort_or_skipped), .adress_IBUF(adress_IBUF[7:2]), .\alc_alc_bit_reg[4] ({\cc_stat[alc_bit] [4],\cc_stat[alc_bit] [1:0]}), .\alc_alc_id_field_reg[2] (\cc_stat[alc_id_field] ), .arbitration_lost(arbitration_lost), .bit_err(bit_err), .bit_err_enable(bit_err_enable), .bit_err_q_i_2(i_mr_top_n_404), .br_shifted(br_shifted), .\bst_ctr_q_reg[0] (i_btl_top_n_5), .btmc_meas_running_q(btmc_meas_running_q), .btmc_meas_running_q_reg(i_mac_top_n_224), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[bst_ctr] (\cc_stat[bst_ctr] ), .\cc_stat[dst_ctr] (\cc_stat[dst_ctr] ), .\cc_stat[err_erp] (\cc_stat[err_erp] ), .\cc_stat[is_err_active] (\cc_stat[is_err_active] ), .\cc_stat[is_transmitter] (\cc_stat[is_transmitter] ), .\cc_stat[status_pexs] (\cc_stat[status_pexs] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\compl_ctr_q_reg[7] (i_mac_top_n_187), .crc_data_tx_wbs(crc_data_tx_wbs), .\crc_q_reg[0] (i_mac_top_n_149), .\crc_q_reg[10] (i_mac_top_n_143), .\crc_q_reg[1] (crc_21), .\crc_q_reg[1]_0 (i_mac_top_n_148), .\crc_q_reg[2] (i_mac_top_n_147), .\crc_q_reg[7] (i_mac_top_n_146), .\crc_q_reg[8] (i_mac_top_n_145), .\crc_q_reg[9] (i_mac_top_n_144), .\ctrl_ctr_q_reg[1] (i_txarb_top_n_103), .\ctrl_ctr_q_reg[5] (i_txarb_top_n_107), .\ctrl_ctr_q_reg[5]_0 ({tran_dlc[3],tran_dlc[1:0]}), .\ctrl_ctr_q_reg[6] (i_txarb_top_n_106), .\ctrl_ctr_q_reg[8] (i_txarb_top_n_102), .\ctrl_ctr_q_reg[8]_0 (i_txarb_top_n_108), .curr_state(\i_mac_operation_control/curr_state ), .\curr_state[0]_i_3 (i_txarb_top_n_119), .curr_state_0(\i_txtb_fsm/curr_state [0]), .curr_state_1(\i_txtb_fsm/curr_state_1 [0]), .curr_state_2(\i_txtb_fsm/curr_state_3 [0]), .curr_state_4(\i_txtb_fsm/curr_state_5 [0]), .curr_state_6(\i_txarb_fsm/curr_state ), .\curr_state_reg[0] (i_mac_top_n_113), .\curr_state_reg[0]_0 (i_mac_top_n_120), .\curr_state_reg[0]_1 (i_mac_top_n_217), .\curr_state_reg[1] (i_mac_top_n_117), .\curr_state_reg[1]_0 (i_mac_top_n_134), .\curr_state_reg[2] (i_mac_top_n_39), .\curr_state_reg[2]_0 (i_mac_top_n_112), .\curr_state_reg[2]_1 (i_mac_top_n_118), .\curr_state_reg[2]_2 (i_mac_top_n_138), .\curr_state_reg[3] (i_mac_top_n_59), .\curr_state_reg[3]_0 ({i_mac_top_n_188,i_mac_top_n_189,i_mac_top_n_190}), .\curr_state_reg[3]_1 (i_mac_top_n_218), .\curr_state_reg[5] (nbt_ctrs_en), .\curr_state_reg[5]_0 (i_mac_top_n_198), .\curr_state_reg[5]_1 (\i_btl_counters_nbt/segm_counter_ce ), .\data_err_ctr_q_reg[15] (\cc_stat[data_err_ctr] ), .\data_err_ctr_q_reg[4] (i_mac_top_n_211), .\data_err_ctr_q_reg[5] (i_mac_top_n_212), .\data_err_ctr_q_reg[8] (i_mac_top_n_213), .data_in_IBUF({data_in_IBUF[11],data_in_IBUF[7],data_in_IBUF[4]}), .destuff_enable_reg(i_mr_top_n_409), .destuffed(destuffed), .\dst_ctr_q_reg[1] (i_btl_top_n_7), .err_capt_err_erp_reg(i_mac_top_n_74), .\err_capt_err_pos_q_reg[0] (i_mac_top_n_75), .\err_capt_err_pos_q_reg[3] (\cc_stat[err_pos] ), .\err_capt_err_type_q[2]_i_8 (i_mr_top_n_410), .\err_capt_err_type_q_reg[0] (i_mac_top_n_70), .\err_capt_err_type_q_reg[2] (\cc_stat[err_type] ), .err_detected(err_detected), .err_frm_req(\i_mac_pc_top/err_frm_req ), .err_frm_req_reg(dbt_ctrs_en), .err_frm_req_reg_0(\i_btl_counters_dbt/segm_counter_ce ), .err_frm_req_reg_1(i_mac_top_n_216), .err_frm_req_reg_2(i_mac_top_n_219), .err_warning_limit_q(err_warning_limit_q), .\exp_seg_length_q_reg[0] (i_btl_top_n_49), .\exp_seg_length_q_reg[0]_0 (i_bm_top_n_16), .first_ssp_q0(\i_bm_ssp_generator/first_ssp_q0 ), .\g_bit[0].reg_value_r_reg[0] (i_mac_top_n_91), .\g_bit[0].reg_value_r_reg[0]_0 (i_mac_top_n_139), .\g_bit[1].reg_value_r_reg[1] (i_mac_top_n_209), .\g_byte_shift_reg[0].shift_reg_q_reg[0][1] (i_mac_top_n_152), .\g_ram_rst_false.ram_memory_reg (i_rxb_top_n_77), .\g_ram_rst_false.ram_memory_reg_0 (i_rxb_top_n_79), .\g_ram_rst_false.ram_memory_reg_1 (i_rxb_top_n_78), .\g_ram_rst_false.ram_memory_reg_2 (i_rxb_top_n_80), .\g_ram_rst_false.ram_memory_reg_i_55 ({rec_erf,inc_ts_wr_ptr,i_rxb_top_n_72,i_rxb_top_n_73,i_rxb_top_n_74,reset_overrun_flag}), .ident_valid_q(ident_valid_q), .int_status_i_2__1(i_mr_top_n_482), .int_status_i_4(curr_txtb_index), .int_status_reg(i_mac_top_n_221), .int_status_reg_0(i_mac_top_n_222), .int_status_reg_1({mr_int_mask_set_int_mask_set_o[11],mr_int_mask_set_int_mask_set_o[4]}), .int_status_reg_2(i_im_top_n_7), .int_status_reg_3(i_im_top_n_12), .is_tseg1(is_tseg1), .is_tseg2(is_tseg2), .\mr_ctrl_out[btr_fd_ph2_fd] (\mr_ctrl_out[btr_fd_ph2_fd] [4]), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] [5:4]), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] ), .\mr_ctrl_out[ctr_pres_efd] (\mr_ctrl_out[ctr_pres_efd] ), .\mr_ctrl_out[ctr_pres_enorm] (\mr_ctrl_out[ctr_pres_enorm] ), .\mr_ctrl_out[ctr_pres_prx] (\mr_ctrl_out[ctr_pres_prx] ), .\mr_ctrl_out[ctr_pres_ptx] (\mr_ctrl_out[ctr_pres_ptx] ), .\mr_ctrl_out[erp_erp_limit] (\mr_ctrl_out[erp_erp_limit] ), .\mr_ctrl_out[ewl_ew_limit] (\mr_ctrl_out[ewl_ew_limit] ), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .\mr_ctrl_out[settings_rtrth] (\mr_ctrl_out[settings_rtrth] [2]), .\mr_ctrl_out[settings_tbfbo] (\mr_ctrl_out[settings_tbfbo] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] [2:0]), .\mr_ctrl_out[ssp_cfg_ssp_src] (\mr_ctrl_out[ssp_cfg_ssp_src] ), .mr_int_stat_fcsi_o(mr_int_stat_fcsi_o), .mr_int_stat_txbhci_o(mr_int_stat_txbhci_o), .mr_status_pexs_reg(i_im_top_n_11), .mr_status_pexs_reg_0(i_rxb_top_n_44), .\mr_tx_priority[0] (\mr_tx_priority[0] [0]), .\mr_tx_priority[1] (\mr_tx_priority[1] [1:0]), .next_state2_carry__0({i_mr_top_n_419,i_mr_top_n_420,i_mr_top_n_421,i_mr_top_n_422}), .\next_state2_inferred__0/i__carry__0 ({i_mr_top_n_423,i_mr_top_n_424,i_mr_top_n_425,i_mr_top_n_426}), .\nom_err_ctr_q_reg[0] (i_mac_top_n_52), .\nom_err_ctr_q_reg[11] (i_mac_top_n_66), .\nom_err_ctr_q_reg[12] ({\cc_stat[norm_err_ctr] [12],\cc_stat[norm_err_ctr] [10:9]}), .\nom_err_ctr_q_reg[2] (i_mac_top_n_214), .p_0_out(p_0_out), .\pc_dbg[is_arbitration] (\pc_dbg[is_arbitration] ), .pc_rx_data_nbs(pc_rx_data_nbs), .q_i(\i_global_rst_rst_reg/q_i ), .\r_data[0]_i_2 (i_mr_top_n_478), .\r_data[0]_i_5 (\txtb_state[0] [0]), .\r_data[11]_i_2__0 (i_mr_top_n_218), .\r_data[19]_i_2 (i_mr_top_n_174), .\r_data[19]_i_2_0 (i_rxb_top_n_64), .\r_data[1]_i_2__0 (i_mr_top_n_223), .\r_data[4]_i_2 (i_mr_top_n_221), .\r_data[4]_i_2_0 (i_im_top_n_18), .\r_data[5]_i_2 (i_mr_top_n_476), .\r_data[6]_i_2 (i_mr_top_n_173), .\r_data[7]_i_3__0 (trv_delay), .\r_data_reg[12] (i_mr_top_n_162), .\r_data_reg[12]_0 (i_mr_top_n_217), .\r_data_reg[13] (i_mr_top_n_216), .\r_data_reg[13]_0 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_40 ), .\r_data_reg[13]_1 (i_mr_top_n_212), .\r_data_reg[13]_2 (i_mr_top_n_96), .\r_data_reg[13]_3 (i_rxb_top_n_53), .\r_data_reg[14] (i_rxb_top_n_54), .\r_data_reg[14]_i_2 (i_mr_top_n_215), .\r_data_reg[15] (i_mr_top_n_186), .\r_data_reg[15]_0 (i_mr_top_n_98), .\r_data_reg[15]_1 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_32 ), .\r_data_reg[15]_2 (i_mr_top_n_214), .\r_data_reg[16] (i_mr_top_n_163), .\r_data_reg[16]_0 (i_rxb_top_n_56), .\r_data_reg[16]_1 (i_mr_top_n_474), .\r_data_reg[17] (i_mr_top_n_203), .\r_data_reg[17]_0 (i_rxb_top_n_66), .\r_data_reg[18] (i_mr_top_n_472), .\r_data_reg[18]_0 (i_rxb_top_n_65), .\r_data_reg[18]_1 (i_mr_top_n_213), .\r_data_reg[18]_2 (i_mr_top_n_177), .\r_data_reg[18]_3 (i_mr_top_n_205), .\r_data_reg[18]_4 (i_mr_top_n_211), .\r_data_reg[19] (i_mr_top_n_208), .\r_data_reg[19]_0 (i_mr_top_n_164), .\r_data_reg[20] (i_mr_top_n_209), .\r_data_reg[20]_0 (i_mr_top_n_182), .\r_data_reg[20]_1 (i_mr_top_n_171), .\r_data_reg[20]_2 (i_mr_top_n_175), .\r_data_reg[21] (i_mr_top_n_178), .\r_data_reg[22] (i_mr_top_n_179), .\r_data_reg[23] (i_mr_top_n_180), .\r_data_reg[24] (i_mr_top_n_181), .\r_data_reg[2] (i_mr_top_n_222), .\r_data_reg[3]_i_5 (i_mr_top_n_477), .\r_data_reg[4] (i_bm_top_n_6), .\r_data_reg[4]_0 (i_rxb_top_n_60), .\r_data_reg[5]_i_5 (\txtb_state[1] ), .\r_data_reg[6] (i_bm_top_n_13), .\r_data_reg[6]_0 (i_rxb_top_n_47), .\r_data_reg[6]_1 (i_im_top_n_16), .\r_data_reg[7]_i_6 (i_mr_top_n_475), .\r_data_reg[8]_i_4 (i_mr_top_n_219), .rec_abort(rec_abort), .rec_abort_f(rec_abort_f), .rec_abort_reg(i_mac_top_n_80), .rec_brs(rec_brs), .\rec_dlc_reg[1] (i_mac_top_n_95), .\rec_dlc_reg[1]_0 (i_mac_top_n_150), .\rec_dlc_reg[2] (i_mac_top_n_85), .\rec_dlc_reg[2]_0 (i_mac_top_n_93), .\rec_dlc_reg[3] (rec_dlc), .\rec_dlc_reg[3]_0 (i_mac_top_n_96), .rec_esi(rec_esi), .rec_frame_type(rec_frame_type), .\rec_ident_reg[28] (rec_ident), .rec_ident_type(rec_ident_type), .rec_is_rtr(rec_is_rtr), .rec_is_rtr_i(\i_mac_pc_top/i_mac_pc_rx_shift_reg/rec_is_rtr_i ), .rec_ivld(rec_ivld), .rec_lbpf(rec_lbpf), .rec_valid(rec_valid), .rec_valid_reg({i_mac_top_n_81,i_mac_top_n_82,i_mac_top_n_83}), .reg_q_reg(i_mac_top_n_119), .reg_q_reg_0(i_mac_top_n_128), .reg_q_reg_1(i_mr_top_n_228), .reg_q_reg_2(i_mr_top_n_403), .reg_q_reg_3(i_btl_top_n_6), .reg_q_reg_4(i_btl_top_n_3), .reg_q_reg_5(i_mr_top_n_408), .\retr_ctr_q_reg[3] (\cc_stat[retr_ctr] ), .\retr_ctr_q_reg[3]_0 (i_txarb_top_n_77), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_wbs(rx_data_wbs), .\rx_err_ctr_q_reg[1] (i_mac_top_n_53), .\rx_err_ctr_q_reg[3] (i_mac_top_n_54), .\rx_err_ctr_q_reg[5] (i_mac_top_n_55), .\rx_err_ctr_q_reg[7] (i_mac_top_n_56), .\rx_err_ctr_q_reg[8] (i_mac_top_n_57), .\rx_err_ctr_q_reg[8]_0 (i_mac_top_n_199), .\same_bits_q_reg[2] (i_btl_top_n_9), .sbe_IBUF(sbe_IBUF[2:0]), .scan_mode_IBUF(scan_mode_IBUF), .\segm_counter_q_reg[0] (i_mr_top_n_442), .\segm_counter_q_reg[0]_0 (i_btl_top_n_17), .\segm_counter_q_reg[0]_1 (i_mr_top_n_429), .\segm_counter_q_reg[0]_2 (i_btl_top_n_47), .\shift_regs_reg[0] (\i_mac_pc_top/i_mac_pc_tx_shift_reg/p_1_in ), .\shift_regs_reg[11] (i_txarb_top_n_89), .\shift_regs_reg[11]_0 (i_txarb_top_n_48), .\shift_regs_reg[12] (i_txarb_top_n_91), .\shift_regs_reg[12]_0 (i_txarb_top_n_47), .\shift_regs_reg[13] (i_txarb_top_n_90), .\shift_regs_reg[13]_0 (i_txarb_top_n_113), .\shift_regs_reg[14] (i_txarb_top_n_88), .\shift_regs_reg[14]_0 (i_txarb_top_n_114), .\shift_regs_reg[15] (i_txarb_top_n_87), .\shift_regs_reg[15]_0 (i_txarb_top_n_110), .\shift_regs_reg[16] (i_txarb_top_n_43), .\shift_regs_reg[16]_0 (i_txarb_top_n_86), .\shift_regs_reg[16]_1 (i_txarb_top_n_115), .\shift_regs_reg[17] (i_txarb_top_n_93), .\shift_regs_reg[17]_0 (i_txarb_top_n_85), .\shift_regs_reg[18] (i_txarb_top_n_94), .\shift_regs_reg[18]_0 (i_txarb_top_n_84), .\shift_regs_reg[19] (i_txarb_top_n_95), .\shift_regs_reg[19]_0 (i_txarb_top_n_83), .\shift_regs_reg[1] (i_txarb_top_n_50), .\shift_regs_reg[20] (i_txarb_top_n_82), .\shift_regs_reg[20]_0 (i_txarb_top_n_96), .\shift_regs_reg[21] (i_txarb_top_n_46), .\shift_regs_reg[21]_0 (i_txarb_top_n_116), .\shift_regs_reg[22] (i_txarb_top_n_45), .\shift_regs_reg[22]_0 (i_txarb_top_n_117), .\shift_regs_reg[23] (i_txarb_top_n_120), .\shift_regs_reg[24] (i_txarb_top_n_97), .\shift_regs_reg[25] (i_txarb_top_n_98), .\shift_regs_reg[25]_0 (i_txarb_top_n_42), .\shift_regs_reg[26] (i_txarb_top_n_99), .\shift_regs_reg[26]_0 (i_txarb_top_n_41), .\shift_regs_reg[27] (i_txarb_top_n_100), .\shift_regs_reg[27]_0 ({tran_identifier[24:18],tran_identifier[13:7]}), .\shift_regs_reg[28] (i_txarb_top_n_81), .\shift_regs_reg[28]_0 (i_txarb_top_n_59), .\shift_regs_reg[28]_1 (i_txarb_top_n_101), .\shift_regs_reg[28]_2 (i_txarb_top_n_92), .\shift_regs_reg[29] (i_txarb_top_n_74), .\shift_regs_reg[29]_0 (i_txarb_top_n_111), .\shift_regs_reg[2] (i_txarb_top_n_49), .\shift_regs_reg[30] (i_txarb_top_n_75), .\shift_regs_reg[30]_0 (i_txarb_top_n_112), .\shift_regs_reg[31] (i_txarb_top_n_121), .\shift_regs_reg[31]_0 (i_txarb_top_n_44), .\shift_regs_reg[31]_1 (i_txarb_top_n_76), .\sp_control_q_i_reg[0] (i_mac_top_n_136), .\sp_control_q_i_reg[0]_0 (i_mac_top_n_206), .\sp_control_q_i_reg[1] (i_mac_top_n_121), .sspc_ena_q(\i_bm_ssp_generator/sspc_ena_q ), .sspc_ena_q_reg(i_mac_top_n_223), .store_data_word(store_data_word), .store_metadata(store_metadata), .\sync_control_q_reg[0] (i_mac_top_n_203), .\sync_control_q_reg[0]_0 (i_mac_top_n_220), .\sync_control_q_reg[1] (sync_control), .sync_edge(sync_edge), .sync_edge3__0(\i_bm_data_edge_detector/sync_edge3__0 ), .sync_flag(sync_flag), .\timestamp[41] (i_mac_top_n_60), .\timestamp[42] (i_mac_top_n_61), .\timestamp[43] (i_mac_top_n_62), .\timestamp[7] (i_mac_top_n_58), .\timestamp[8] (i_mac_top_n_40), .timestamp_IBUF({timestamp_IBUF[49:45],timestamp_IBUF[43:39],timestamp_IBUF[17:13],timestamp_IBUF[11:7]}), .\tq_counter_q_reg[7] (i_mac_top_n_202), .tran_brs(tran_brs), .tran_delay_meas(tran_delay_meas), .\tran_frame_test[fcrc] (\tran_frame_test[fcrc] ), .\tran_frame_test[fstc] (\tran_frame_test[fstc] ), .tran_frame_type(tran_frame_type), .tran_frame_valid(tran_frame_valid), .tran_ident_type(tran_ident_type), .tran_is_rtr(tran_is_rtr), .tran_word({tran_word[31:27],tran_word[23:21],tran_word[18:15],tran_word[12:9],tran_word[6:3],tran_word[0]}), .tx_data_prev(\i_bm_data_edge_detector/tx_data_prev ), .\tx_err_ctr_q_reg[6] (i_mac_top_n_50), .\tx_err_ctr_q_reg[7] (\cc_stat[tx_err_ctr] ), .\tx_err_ctr_q_reg[7]_0 (i_mac_top_n_51), .tx_frame_no_sof_q_reg(i_btl_top_n_2), .tx_trigger_ssp(tx_trigger_ssp), .txtb_allow_bb(txtb_allow_bb), .\txtb_hw_cmd[failed] (\txtb_hw_cmd[failed] ), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .\txtb_hw_cmd[valid] (\txtb_hw_cmd[valid] ), .txtb_hw_cmd_cs({txtb_hw_cmd_cs[3],txtb_hw_cmd_cs[1]}), .\txtb_hw_cmd_q[err] (\i_mac_pc_top/i_mac_pc_fsm/txtb_hw_cmd_q[err] ), .\txtb_hw_cmd_q_reg[arbl] (i_mr_top_n_406), .\txtb_hw_cmd_q_reg[err] (i_mac_top_n_99), .\txtb_hw_cmd_q_reg[failed] (i_mac_top_n_98), .\txtb_hw_cmd_q_reg[failed]_0 (i_mac_top_n_100), .\txtb_hw_cmd_q_reg[failed]_1 (i_mac_top_n_101), .\txtb_hw_cmd_q_reg[failed]_2 (i_mac_top_n_102), .\txtb_hw_cmd_q_reg[failed]_3 (i_mac_top_n_104), .\txtb_hw_cmd_q_reg[failed]_4 (i_mac_top_n_105), .\txtb_hw_cmd_q_reg[failed]_5 (i_mac_top_n_106), .\txtb_hw_cmd_q_reg[lock] (i_mac_top_n_103), .\txtb_hw_cmd_q_reg[lock]_0 (i_mac_top_n_107), .\txtb_hw_cmd_q_reg[lock]_1 (i_mac_top_n_215), .\txtb_hw_cmd_q_reg[valid] (i_mac_top_n_109), .\txtb_hw_cmd_q_reg[valid]_0 (i_mac_top_n_110), .\txtb_ptr_q_reg[4] (txtb_ptr), .\txtb_ptr_q_reg[4]_0 (i_txarb_top_n_104), .\txtb_ptr_q_reg[4]_1 (i_txarb_top_n_109), .\txtb_ptr_q_reg[4]_2 (i_txarb_top_n_105), .\write_pointer_q_reg[0] (i_mac_top_n_225), .\write_pointer_q_reg[0]_0 (\i_bm_tx_data_cache/write_pointer_q_reg )); mr_top i_mr_top (.ADDRARDADDR(\i_rxb_ram/rxb_port_b_address_i ), .ADDRBWRADDR(\i_txtb_ram/txtb_port_a_address_i_18 ), .CO(\i_btl_segment_meter_dbt/phase_err_mt_sjw ), .D({\i_control_registers_reg_map/p_0_in [31:26],\i_control_registers_reg_map/p_0_in [24],\i_control_registers_reg_map/p_0_in [20:13],\i_control_registers_reg_map/p_0_in [11:8],\i_control_registers_reg_map/p_0_in [6],\i_control_registers_reg_map/p_0_in [4],\i_control_registers_reg_map/p_0_in [2:0]}), .DI({i_mr_top_n_415,i_mr_top_n_416,i_mr_top_n_417,i_mr_top_n_418}), .DIADI(\i_rxb_ram/rxb_port_a_data_in_i ), .DIBDI({i_mr_top_n_245,i_mr_top_n_246,i_mr_top_n_247,i_mr_top_n_248,i_mr_top_n_249,i_mr_top_n_250,i_mr_top_n_251,i_mr_top_n_252,i_mr_top_n_253,i_mr_top_n_254,i_mr_top_n_255,i_mr_top_n_256,i_mr_top_n_257,i_mr_top_n_258,i_mr_top_n_259,i_mr_top_n_260}), .E(\i_control_registers_reg_map/r_data0 ), .\FSM_onehot_current_state_reg[2] (i_mr_top_n_480), .\FSM_sequential_curr_state[0]_i_2__0 (i_mac_top_n_98), .\FSM_sequential_curr_state[0]_i_2__0_0 (i_txarb_top_n_35), .\FSM_sequential_curr_state[0]_i_2__2 (i_txarb_top_n_40), .\FSM_sequential_curr_state_reg[0] (i_mr_top_n_270), .\FSM_sequential_curr_state_reg[0]_0 (i_mr_top_n_355), .\FSM_sequential_curr_state_reg[0]_1 ({i_mr_top_n_401,select_buf_index}), .\FSM_sequential_curr_state_reg[2] (\i_mac_fc_top/i_mac_fc_fsm/curr_state ), .O({i_mr_top_n_431,i_mr_top_n_432}), .Q(rx_read_pointer), .S({i_mr_top_n_411,i_mr_top_n_412,i_mr_top_n_413,i_mr_top_n_414}), .abort_applied(abort_applied_14), .abort_applied_3(abort_applied), .\adress[2] (i_mr_top_n_162), .\adress[2]_0 (i_mr_top_n_186), .\adress[3] (i_mr_top_n_164), .\adress[3]_0 (i_mr_top_n_187), .\adress[4] (i_mr_top_n_177), .\adress[4]_0 (i_mr_top_n_182), .\adress[4]_1 (i_mr_top_n_209), .\adress[4]_2 (i_mr_top_n_472), .\adress[5] (i_mr_top_n_163), .\adress[5]_0 (i_mr_top_n_171), .\adress[5]_1 (i_mr_top_n_204), .\adress[5]_2 (i_mr_top_n_205), .\adress[6] (i_mr_top_n_212), .\adress[6]_0 (i_mr_top_n_473), .\adress[8] (i_mr_top_n_172), .adress_IBUF(adress_IBUF), .bit_err_d0_out(\i_bm_bit_err_detector/bit_err_d0_out ), .bit_err_d2(bit_err_d2), .bit_err_enable(bit_err_enable), .bit_err_q_reg(i_mac_top_n_209), .bit_err_q_reg_0(i_btl_top_n_3), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[is_err_active] (\cc_stat[is_err_active] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_tx_wbs(crc_data_tx_wbs), .curr_state(\i_mac_operation_control/curr_state ), .current_state_reg(\i_btl_fsm/current_state_reg ), .data_in_IBUF(data_in_IBUF), .data_out_OBUF(data_out_OBUF), .\err_capt_err_type_q[2]_i_13 (i_mac_top_n_59), .\exp_seg_length_d9_inferred__0/i__carry (i_btl_top_n_52), .\exp_seg_length_d9_inferred__0/i__carry_0 (i_btl_top_n_54), .\exp_seg_length_d9_inferred__0/i__carry_1 (i_btl_top_n_57), .\exp_seg_length_d9_inferred__0/i__carry_2 (i_btl_top_n_58), .\exp_seg_length_q[6]_i_2 (i_mac_top_n_136), .\exp_seg_length_q[6]_i_2_0 (i_btl_top_n_48), .\exp_seg_length_q[7]_i_11 ({i_btl_top_n_24,i_btl_top_n_25,i_btl_top_n_26,i_btl_top_n_27,i_btl_top_n_28,i_btl_top_n_29,i_btl_top_n_30}), .\exp_seg_length_q_reg[7]_i_2__0 (tseg1_dbt), .\exp_seg_length_q_reg[7]_i_2__0_0 (i_btl_top_n_12), .fsm_wait_state_q(\i_txarb_fsm/fsm_wait_state_q ), .fsm_wait_state_q_reg(select_buf_index_reg), .\g_bit[0].reg_value_r_reg[0] (i_mr_top_n_3), .\g_bit[0].reg_value_r_reg[0]_0 (i_mr_top_n_21), .\g_bit[0].reg_value_r_reg[0]_1 (i_mr_top_n_22), .\g_bit[0].reg_value_r_reg[0]_10 (i_mr_top_n_96), .\g_bit[0].reg_value_r_reg[0]_11 (i_mr_top_n_97), .\g_bit[0].reg_value_r_reg[0]_12 (i_mr_top_n_98), .\g_bit[0].reg_value_r_reg[0]_13 (i_mr_top_n_174), .\g_bit[0].reg_value_r_reg[0]_14 (i_mr_top_n_181), .\g_bit[0].reg_value_r_reg[0]_15 (i_mr_top_n_183), .\g_bit[0].reg_value_r_reg[0]_16 (i_mr_top_n_185), .\g_bit[0].reg_value_r_reg[0]_17 (i_mr_top_n_198), .\g_bit[0].reg_value_r_reg[0]_18 (i_mr_top_n_200), .\g_bit[0].reg_value_r_reg[0]_19 (i_mr_top_n_203), .\g_bit[0].reg_value_r_reg[0]_2 (i_mr_top_n_88), .\g_bit[0].reg_value_r_reg[0]_20 (i_mr_top_n_210), .\g_bit[0].reg_value_r_reg[0]_21 (i_mr_top_n_216), .\g_bit[0].reg_value_r_reg[0]_22 (i_mr_top_n_219), .\g_bit[0].reg_value_r_reg[0]_23 (i_mr_top_n_312), .\g_bit[0].reg_value_r_reg[0]_24 (i_mr_top_n_397), .\g_bit[0].reg_value_r_reg[0]_25 (i_mr_top_n_404), .\g_bit[0].reg_value_r_reg[0]_26 (i_mr_top_n_406), .\g_bit[0].reg_value_r_reg[0]_27 (i_mr_top_n_408), .\g_bit[0].reg_value_r_reg[0]_28 (i_mr_top_n_409), .\g_bit[0].reg_value_r_reg[0]_29 (i_mr_top_n_410), .\g_bit[0].reg_value_r_reg[0]_3 (i_mr_top_n_89), .\g_bit[0].reg_value_r_reg[0]_30 (\i_btl_cfg_capture/capture ), .\g_bit[0].reg_value_r_reg[0]_31 ({i_mr_top_n_439,i_mr_top_n_440,i_mr_top_n_441}), .\g_bit[0].reg_value_r_reg[0]_32 (i_mr_top_n_457), .\g_bit[0].reg_value_r_reg[0]_33 (i_mr_top_n_474), .\g_bit[0].reg_value_r_reg[0]_34 (i_mr_top_n_475), .\g_bit[0].reg_value_r_reg[0]_35 (i_mr_top_n_478), .\g_bit[0].reg_value_r_reg[0]_36 (i_mr_top_n_481), .\g_bit[0].reg_value_r_reg[0]_37 (i_mr_top_n_482), .\g_bit[0].reg_value_r_reg[0]_38 (i_mr_top_n_483), .\g_bit[0].reg_value_r_reg[0]_39 (i_im_top_n_12), .\g_bit[0].reg_value_r_reg[0]_4 (i_mr_top_n_90), .\g_bit[0].reg_value_r_reg[0]_40 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_40 ), .\g_bit[0].reg_value_r_reg[0]_5 (i_mr_top_n_91), .\g_bit[0].reg_value_r_reg[0]_6 (i_mr_top_n_92), .\g_bit[0].reg_value_r_reg[0]_7 (i_mr_top_n_93), .\g_bit[0].reg_value_r_reg[0]_8 (i_mr_top_n_94), .\g_bit[0].reg_value_r_reg[0]_9 (i_mr_top_n_95), .\g_bit[1].reg_value_r_reg[1] (i_mr_top_n_175), .\g_bit[1].reg_value_r_reg[1]_0 (i_mr_top_n_188), .\g_bit[1].reg_value_r_reg[1]_1 (i_mr_top_n_211), .\g_bit[1].reg_value_r_reg[1]_2 (i_mr_top_n_215), .\g_bit[1].reg_value_r_reg[1]_3 (i_mr_top_n_223), .\g_bit[1].reg_value_r_reg[1]_4 (i_mr_top_n_443), .\g_bit[1].reg_value_r_reg[1]_5 (i_mr_top_n_456), .\g_bit[1].reg_value_r_reg[1]_6 (ssp_delay), .\g_bit[2].reg_value_r_reg[2] (i_mr_top_n_178), .\g_bit[2].reg_value_r_reg[2]_0 (i_mr_top_n_184), .\g_bit[2].reg_value_r_reg[2]_1 (i_mr_top_n_189), .\g_bit[2].reg_value_r_reg[2]_2 (i_mr_top_n_214), .\g_bit[2].reg_value_r_reg[2]_3 (i_mr_top_n_222), .\g_bit[2].reg_value_r_reg[2]_4 (i_mr_top_n_455), .\g_bit[3].reg_value_r_reg[3] (\mr_ctrl_out[settings_rtrth] ), .\g_bit[3].reg_value_r_reg[3]_0 (i_mr_top_n_179), .\g_bit[3].reg_value_r_reg[3]_1 (i_mr_top_n_190), .\g_bit[3].reg_value_r_reg[3]_2 (i_mr_top_n_208), .\g_bit[3].reg_value_r_reg[3]_3 (i_mr_top_n_218), .\g_bit[3].reg_value_r_reg[3]_4 (i_mr_top_n_477), .\g_bit[4].reg_value_r_reg[4] (i_mr_top_n_176), .\g_bit[4].reg_value_r_reg[4]_0 (i_mr_top_n_180), .\g_bit[4].reg_value_r_reg[4]_1 (i_mr_top_n_191), .\g_bit[4].reg_value_r_reg[4]_10 (i_mr_top_n_430), .\g_bit[4].reg_value_r_reg[4]_11 ({i_mr_top_n_436,i_mr_top_n_437,i_mr_top_n_438}), .\g_bit[4].reg_value_r_reg[4]_12 (i_mr_top_n_444), .\g_bit[4].reg_value_r_reg[4]_13 ({i_mr_top_n_445,i_mr_top_n_446}), .\g_bit[4].reg_value_r_reg[4]_2 (i_mr_top_n_221), .\g_bit[4].reg_value_r_reg[4]_3 ({\i_txtb_ram/txtb_port_b_address_i_19 [4],\i_txtb_ram/txtb_port_b_address_i_19 [2:0]}), .\g_bit[4].reg_value_r_reg[4]_4 ({\i_txtb_ram/txtb_port_b_address_i_16 [4],\i_txtb_ram/txtb_port_b_address_i_16 [2:0]}), .\g_bit[4].reg_value_r_reg[4]_5 (\i_txtb_ram/txtb_port_a_address_i_15 ), .\g_bit[4].reg_value_r_reg[4]_6 ({\i_txtb_ram/txtb_port_b_address_i_12 [4],\i_txtb_ram/txtb_port_b_address_i_12 [2:0]}), .\g_bit[4].reg_value_r_reg[4]_7 (\i_txtb_ram/txtb_port_a_address_i_11 ), .\g_bit[4].reg_value_r_reg[4]_8 ({\i_txtb_ram/txtb_port_b_address_i [4],\i_txtb_ram/txtb_port_b_address_i [2:0]}), .\g_bit[4].reg_value_r_reg[4]_9 (\i_txtb_ram/txtb_port_a_address_i ), .\g_bit[5].reg_value_r_reg[5] (i_mr_top_n_476), .\g_bit[6].reg_value_r_reg[6] (i_mr_top_n_173), .\g_bit[7].reg_value_r_reg[7] ({\mr_tst_out[tst_wdata_tst_wdata] [31:15],\mr_tst_out[tst_wdata_tst_wdata] [13:0]}), .\g_bit[7].reg_value_r_reg[7]_0 ({i_mr_top_n_229,i_mr_top_n_230,i_mr_top_n_231,i_mr_top_n_232,i_mr_top_n_233,i_mr_top_n_234,i_mr_top_n_235,i_mr_top_n_236,\i_txtb_ram/p_0_in_20 }), .\g_bit[7].reg_value_r_reg[7]_1 ({i_mr_top_n_271,i_mr_top_n_272,i_mr_top_n_273,i_mr_top_n_274,i_mr_top_n_275,i_mr_top_n_276,i_mr_top_n_277,i_mr_top_n_278,\i_txtb_ram/p_0_in_17 }), .\g_bit[7].reg_value_r_reg[7]_2 ({i_mr_top_n_287,i_mr_top_n_288,i_mr_top_n_289,i_mr_top_n_290,i_mr_top_n_291,i_mr_top_n_292,i_mr_top_n_293,i_mr_top_n_294,i_mr_top_n_295,i_mr_top_n_296,i_mr_top_n_297,i_mr_top_n_298,i_mr_top_n_299,i_mr_top_n_300,i_mr_top_n_301,i_mr_top_n_302}), .\g_bit[7].reg_value_r_reg[7]_3 ({i_mr_top_n_314,i_mr_top_n_315,i_mr_top_n_316,i_mr_top_n_317,i_mr_top_n_318,i_mr_top_n_319,i_mr_top_n_320,i_mr_top_n_321,\i_txtb_ram/p_0_in_13 }), .\g_bit[7].reg_value_r_reg[7]_4 ({i_mr_top_n_330,i_mr_top_n_331,i_mr_top_n_332,i_mr_top_n_333,i_mr_top_n_334,i_mr_top_n_335,i_mr_top_n_336,i_mr_top_n_337,i_mr_top_n_338,i_mr_top_n_339,i_mr_top_n_340,i_mr_top_n_341,i_mr_top_n_342,i_mr_top_n_343,i_mr_top_n_344,i_mr_top_n_345}), .\g_bit[7].reg_value_r_reg[7]_5 ({i_mr_top_n_356,i_mr_top_n_357,i_mr_top_n_358,i_mr_top_n_359,i_mr_top_n_360,i_mr_top_n_361,i_mr_top_n_362,i_mr_top_n_363,\i_txtb_ram/p_0_in }), .\g_bit[7].reg_value_r_reg[7]_6 ({i_mr_top_n_372,i_mr_top_n_373,i_mr_top_n_374,i_mr_top_n_375,i_mr_top_n_376,i_mr_top_n_377,i_mr_top_n_378,i_mr_top_n_379,i_mr_top_n_380,i_mr_top_n_381,i_mr_top_n_382,i_mr_top_n_383,i_mr_top_n_384,i_mr_top_n_385,i_mr_top_n_386,i_mr_top_n_387}), .\g_bit[7].reg_value_r_reg[7]_7 ({i_mr_top_n_419,i_mr_top_n_420,i_mr_top_n_421,i_mr_top_n_422}), .\g_bit[7].reg_value_r_reg[7]_8 ({i_mr_top_n_423,i_mr_top_n_424,i_mr_top_n_425,i_mr_top_n_426}), .\g_ram_rst_false.ram_memory_reg (i_rxb_top_n_69), .\g_ram_rst_false.ram_memory_reg_0 (i_mac_top_n_85), .\g_ram_rst_false.ram_memory_reg_1 (i_rxb_top_n_76), .\g_ram_rst_false.ram_memory_reg_2 ({txtb_ptr[4],txtb_ptr[2:0]}), .\g_ram_rst_false.ram_memory_reg_3 (i_txarb_top_n_118), .\g_ram_rst_false.ram_memory_reg_4 (i_txarb_top_n_126), .\g_ram_rst_false.ram_memory_reg_5 (i_txarb_top_n_124), .\g_ram_rst_false.ram_memory_reg_6 (i_txarb_top_n_125), .i__carry_i_2__4({i_btl_top_n_60,i_btl_top_n_61}), .i__carry_i_9(segm_counter_q), .\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 (i_btl_top_n_50), .is_tseg2(is_tseg2), .mr_btr_prop(\mr_ctrl_out[btr_prop] ), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] ), .\mr_ctrl_out[btr_fd_ph2_fd] (\mr_ctrl_out[btr_fd_ph2_fd] ), .\mr_ctrl_out[btr_fd_prop_fd] (\mr_ctrl_out[btr_fd_prop_fd] ), .\mr_ctrl_out[btr_ph1] (\mr_ctrl_out[btr_ph1] ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] ), .\mr_ctrl_out[btr_sjw] (\mr_ctrl_out[btr_sjw] ), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] ), .\mr_ctrl_out[ctr_pres_efd] (\mr_ctrl_out[ctr_pres_efd] ), .\mr_ctrl_out[ctr_pres_enorm] (\mr_ctrl_out[ctr_pres_enorm] ), .\mr_ctrl_out[ctr_pres_prx] (\mr_ctrl_out[ctr_pres_prx] ), .\mr_ctrl_out[ctr_pres_ptx] (\mr_ctrl_out[ctr_pres_ptx] ), .\mr_ctrl_out[erp_erp_limit] (\mr_ctrl_out[erp_erp_limit] ), .\mr_ctrl_out[ewl_ew_limit] (\mr_ctrl_out[ewl_ew_limit] ), .\mr_ctrl_out[mode_acf] (\mr_ctrl_out[mode_acf] ), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .\mr_ctrl_out[mode_sam] (\mr_ctrl_out[mode_sam] ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .\mr_ctrl_out[mode_tstm] (\mr_ctrl_out[mode_tstm] ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .\mr_ctrl_out[mode_txbbm] (\mr_ctrl_out[mode_txbbm] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .\mr_ctrl_out[settings_tbfbo] (\mr_ctrl_out[settings_tbfbo] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .\mr_ctrl_out[ssp_cfg_ssp_src] (\mr_ctrl_out[ssp_cfg_ssp_src] ), .mr_settings_ena_reg(\i_btl_cfg_capture/mr_settings_ena_reg ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .\mr_tst_out[tst_dest_tst_addr] (\mr_tst_out[tst_dest_tst_addr] ), .mr_tx_command_txbi({mr_tx_command_txbi[2],mr_tx_command_txbi[0]}), .mr_tx_command_txca_q(mr_tx_command_txca_q), .mr_tx_command_txce_q(mr_tx_command_txce_q), .mr_tx_command_txcr_q(mr_tx_command_txcr_q), .\mr_tx_priority[0] (\mr_tx_priority[0] ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .\mr_tx_priority[2] (\mr_tx_priority[2] ), .\mr_tx_priority[3] (\mr_tx_priority[3] ), .neg_phase_err(neg_phase_err), .next_state2_carry(\cc_stat[rx_err_ctr] ), .\next_state2_inferred__0/i__carry (\cc_stat[tx_err_ctr] ), .\nom_err_ctr_q_reg[10] (i_mr_top_n_207), .\nom_err_ctr_q_reg[9] (i_mr_top_n_206), .pc_rx_data_nbs(pc_rx_data_nbs), .q_i(\i_global_rst_rst_reg/q_i ), .\r_data[17]_i_2 (\cc_stat[alc_bit] [1]), .\r_data_reg[12] (i_mac_top_n_39), .\r_data_reg[12]_0 ({\cc_stat[norm_err_ctr] [12],\cc_stat[norm_err_ctr] [10:9]}), .\r_data_reg[12]_1 (i_rxb_top_n_52), .\r_data_reg[21] (i_mac_top_n_212), .\r_data_reg[21]_0 (i_rxb_top_n_55), .\r_data_reg[21]_1 (\cc_stat[alc_id_field] [0]), .\r_data_reg[22] (i_mac_top_n_50), .\r_data_reg[22]_0 (i_rxb_top_n_58), .\r_data_reg[23] (i_mac_top_n_51), .\r_data_reg[23]_0 (i_rxb_top_n_59), .\r_data_reg[25] (i_rxb_top_n_62), .\r_data_reg[31] (\cc_stat[data_err_ctr] ), .\r_data_reg[3] (i_bm_top_n_11), .\r_data_reg[3]_0 (i_rxb_top_n_46), .\r_data_reg[3]_1 (i_im_top_n_9), .\r_data_reg[5] (i_bm_top_n_12), .\r_data_reg[5]_0 (i_rxb_top_n_61), .\r_data_reg[5]_1 (i_mac_top_n_55), .\r_data_reg[5]_2 (i_im_top_n_17), .\r_data_reg[7] (i_mac_top_n_58), .\r_data_reg[7]_0 (i_rxb_top_n_48), .\r_data_reg[7]_1 (i_im_top_n_10), .reg_q_reg(i_mr_top_n_1), .reg_q_reg_0(i_mr_top_n_225), .reg_q_reg_1(i_mr_top_n_228), .reg_q_reg_2(i_mr_top_n_403), .reg_q_reg_3(i_rst_sync_n_1), .reg_q_reg_4(i_im_top_n_11), .reg_q_reg_5(i_rxb_top_n_44), .reg_q_reg_6(i_mac_top_n_216), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_wbs(rx_data_wbs), .rxb_port_b_data_out_i(rxb_port_b_data_out_i), .sbe_IBUF(sbe_IBUF), .scan_mode_IBUF(scan_mode_IBUF), .scs_IBUF(scs_IBUF), .\segm_counter_q_reg[0] (tq_counter_q), .\segm_counter_q_reg[0]_0 ({i_btl_top_n_31,i_btl_top_n_32,i_btl_top_n_33,i_btl_top_n_34,i_btl_top_n_35,i_btl_top_n_36,i_btl_top_n_37,i_btl_top_n_38}), .\segm_counter_q_reg[4] ({i_mr_top_n_433,i_mr_top_n_434,i_mr_top_n_435}), .\segm_counter_q_reg[6] (i_mr_top_n_427), .\select_buf_index_reg_reg[0] (i_mr_top_n_400), .\select_buf_index_reg_reg[0]_0 (i_mr_top_n_479), .\select_buf_index_reg_reg[1] (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_43 ), .\select_buf_index_reg_reg[1]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_41 ), .soft_res_d_n(soft_res_d_n), .srd_IBUF(srd_IBUF), .swr_IBUF(swr_IBUF), .\test_probe[tx_trigger]_INST_0_i_27 ({i_btl_top_n_62,i_btl_top_n_63}), .\test_probe[tx_trigger]_INST_0_i_4 (i_btl_top_n_51), .\test_probe[tx_trigger]_INST_0_i_4_0 (i_mac_top_n_203), .\test_probe[tx_trigger]_INST_0_i_7 (i_btl_top_n_56), .\test_probe[tx_trigger]_INST_0_i_7_0 (i_btl_top_n_59), .\test_probe[tx_trigger]_INST_0_i_9 (i_btl_top_n_53), .\test_probe[tx_trigger]_INST_0_i_9_0 (i_btl_top_n_55), .\timestamp[26] (i_mr_top_n_165), .\timestamp[27] (i_mr_top_n_166), .\timestamp[28] (i_mr_top_n_167), .\timestamp[38] (i_mr_top_n_220), .\timestamp[44] (i_mr_top_n_217), .\timestamp[50] (i_mr_top_n_213), .\timestamp[61] (i_mr_top_n_168), .\timestamp[62] (i_mr_top_n_169), .\timestamp[63] (i_mr_top_n_170), .timestamp_IBUF({timestamp_IBUF[63:50],timestamp_IBUF[44],timestamp_IBUF[38],timestamp_IBUF[31:18],timestamp_IBUF[12],timestamp_IBUF[6]}), .\tq_counter_q_reg[6] (i_mr_top_n_429), .\tq_counter_q_reg[7] (i_mr_top_n_442), .tran_frame_type(tran_frame_type), .tran_frame_valid_com_reg(\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_42 ), .trv_delay_sum(trv_delay_sum), .\tseg1_dbt_reg[3] ({i_mr_top_n_484,i_mr_top_n_485,i_mr_top_n_486,i_mr_top_n_487}), .\tseg1_dbt_reg[4] (i_mr_top_n_488), .tst_ena(\i_txtb_ram/tst_ena_23 ), .tst_ena_0(\i_txtb_ram/tst_ena_22 ), .tst_ena_1(\i_txtb_ram/tst_ena_21 ), .tst_ena_2(\i_txtb_ram/tst_ena ), .tx_command_txce_valid(tx_command_txce_valid_9), .tx_command_txce_valid_5(tx_command_txce_valid_7), .tx_command_txcr_valid(tx_command_txcr_valid_10), .tx_command_txcr_valid_4(tx_command_txcr_valid_8), .txtb_allow_bb({txtb_allow_bb[2],txtb_allow_bb[0]}), .txtb_available(txtb_available), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .txtb_hw_cmd_cs({txtb_hw_cmd_cs[2],txtb_hw_cmd_cs[0]}), .\txtb_hw_cmd_q[err] (\i_mac_pc_top/i_mac_pc_fsm/txtb_hw_cmd_q[err] ), .\txtb_hw_cmd_q_reg[err] (i_mac_top_n_138), .\txtb_hw_cmd_q_reg[err]_0 (\cc_stat[retr_ctr] ), .\txtb_hw_cmd_q_reg[lock] (i_mr_top_n_399), .txtb_port_b_data_out_i(txtb_port_b_data_out_i_4), .txtb_port_b_data_out_i_6(txtb_port_b_data_out_i), .txtb_port_b_data_out_i_7(txtb_port_b_data_out_i_2), .txtb_port_b_data_out_i_8(txtb_port_b_data_out_i_6)); rst_sync i_rst_sync (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .lopt(lopt), .rst_n_IBUF(rst_n_IBUF), .rst_n_out_OBUF(rst_n_out_OBUF), .rst_reg_0(i_rst_sync_n_1)); rxb_top i_rxb_top (.ADDRARDADDR(\i_rxb_ram/rxb_port_b_address_i ), .D({\i_control_registers_reg_map/p_0_in [31:26],\i_control_registers_reg_map/p_0_in [24],\i_control_registers_reg_map/p_0_in [20],\i_control_registers_reg_map/p_0_in [11],\i_control_registers_reg_map/p_0_in [1:0]}), .DIADI(\i_rxb_ram/rxb_port_a_data_in_i ), .E(\i_control_registers_reg_map/r_data0 ), .\FSM_onehot_curr_state_reg[0] (i_ff_top_n_2), .\FSM_onehot_curr_state_reg[0]_0 (i_mac_top_n_91), .\FSM_onehot_curr_state_reg[11] (i_mr_top_n_228), .\FSM_onehot_curr_state_reg[11]_0 (i_mac_top_n_84), .\FSM_onehot_curr_state_reg[1] (i_rxb_top_n_76), .\FSM_onehot_curr_state_reg[1]_0 (i_rxb_top_n_80), .\FSM_onehot_curr_state_reg[6] ({i_mac_top_n_81,i_mac_top_n_82,i_mac_top_n_83}), .\FSM_onehot_curr_state_reg[7] (i_rxb_top_n_79), .\FSM_onehot_curr_state_reg[8] ({rec_erf,inc_ts_wr_ptr,i_rxb_top_n_72,i_rxb_top_n_73,i_rxb_top_n_74,reset_overrun_flag}), .\FSM_onehot_curr_state_reg[8]_0 (i_rxb_top_n_77), .\FSM_onehot_curr_state_reg[8]_1 (i_mac_top_n_90), .Q(rx_read_pointer), .\adress[4] (i_rxb_top_n_46), .\adress[4]_0 (i_rxb_top_n_48), .\adress[4]_1 (i_rxb_top_n_61), .\adress[7] (i_rxb_top_n_44), .adress_IBUF(adress_IBUF[7:2]), .\alc_alc_bit_reg[0] (i_rxb_top_n_56), .\cc_stat[err_erp] (\cc_stat[err_erp] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .commit_overrun_abort(commit_overrun_abort), .data_in_IBUF(data_in_IBUF[3:1]), .data_overrun_i_reg_0(i_mr_top_n_172), .data_overrun_i_reg_1(i_im_top_n_11), .\frame_count_reg[3]_0 (i_rxb_top_n_43), .\frame_count_reg[3]_1 (i_rxb_top_n_62), .\g_bit[0].reg_value_r_reg[0] (i_rxb_top_n_47), .\g_bit[0].reg_value_r_reg[0]_0 (i_rxb_top_n_54), .\g_bit[0].reg_value_r_reg[0]_1 (i_rxb_top_n_60), .\g_bit[0].reg_value_r_reg[0]_2 (i_rxb_top_n_69), .\g_byte_shift_reg[1].shift_reg_q_reg[1][6] (i_rxb_top_n_78), .\g_ram_rst_false.ram_memory_reg (i_rxb_top_n_49), .\g_ram_rst_false.ram_memory_reg_0 (i_rxb_top_n_50), .\g_ram_rst_false.ram_memory_reg_1 (i_rxb_top_n_51), .\g_ram_rst_false.ram_memory_reg_10 (i_rxb_top_n_66), .\g_ram_rst_false.ram_memory_reg_11 (i_rxb_top_n_67), .\g_ram_rst_false.ram_memory_reg_12 (i_mr_top_n_200), .\g_ram_rst_false.ram_memory_reg_13 ({\mr_tst_out[tst_wdata_tst_wdata] [31:15],\mr_tst_out[tst_wdata_tst_wdata] [13:0]}), .\g_ram_rst_false.ram_memory_reg_14 (i_mac_top_n_95), .\g_ram_rst_false.ram_memory_reg_15 (i_mac_top_n_96), .\g_ram_rst_false.ram_memory_reg_16 (i_mac_top_n_93), .\g_ram_rst_false.ram_memory_reg_17 (rec_dlc), .\g_ram_rst_false.ram_memory_reg_18 (rec_ident), .\g_ram_rst_false.ram_memory_reg_19 (curr_txtb_index), .\g_ram_rst_false.ram_memory_reg_2 (i_rxb_top_n_52), .\g_ram_rst_false.ram_memory_reg_20 (\cc_stat[err_type] ), .\g_ram_rst_false.ram_memory_reg_21 (\cc_stat[err_pos] ), .\g_ram_rst_false.ram_memory_reg_3 (i_rxb_top_n_53), .\g_ram_rst_false.ram_memory_reg_4 (i_rxb_top_n_55), .\g_ram_rst_false.ram_memory_reg_5 (i_rxb_top_n_57), .\g_ram_rst_false.ram_memory_reg_6 (i_rxb_top_n_58), .\g_ram_rst_false.ram_memory_reg_7 (i_rxb_top_n_59), .\g_ram_rst_false.ram_memory_reg_8 (i_rxb_top_n_64), .\g_ram_rst_false.ram_memory_reg_9 (i_rxb_top_n_65), .\g_ram_rst_false.ram_memory_reg_i_111 (i_mac_top_n_80), .ident_valid_q(ident_valid_q), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .\mr_tst_out[tst_dest_tst_addr] (\mr_tst_out[tst_dest_tst_addr] ), .\r_data[0]_i_2 (i_im_top_n_19), .\r_data[0]_i_2_0 (i_mac_top_n_75), .\r_data[0]_i_2_1 (i_mr_top_n_88), .\r_data[10]_i_2__0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_38 ), .\r_data[11]_i_2__0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_32 ), .\r_data[12]_i_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_36 ), .\r_data[13]_i_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_37 ), .\r_data[14]_i_5 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_38 ), .\r_data[1]_i_2__0 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_43 ), .\r_data[23]_i_2 (\cc_stat[alc_id_field] [2:1]), .\r_data[3]_i_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_42 ), .\r_data[4]_i_2 (i_mac_top_n_74), .\r_data[4]_i_2_0 (i_mr_top_n_90), .\r_data[5]_i_2 (i_mac_top_n_70), .\r_data[6]_i_2 (i_mr_top_n_91), .\r_data[6]_i_4 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_37 ), .\r_data[7]_i_2__0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_32 ), .\r_data[8]_i_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_36 ), .\r_data[9]_i_2__0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_37 ), .\r_data_reg[0] (i_bm_top_n_7), .\r_data_reg[0]_0 (i_mac_top_n_52), .\r_data_reg[11] (i_mr_top_n_163), .\r_data_reg[11]_0 (i_im_top_n_15), .\r_data_reg[11]_1 (i_mac_top_n_62), .\r_data_reg[11]_2 (i_mr_top_n_95), .\r_data_reg[11]_3 (i_mr_top_n_186), .\r_data_reg[11]_4 (i_mac_top_n_66), .\r_data_reg[14]_i_2 (i_mr_top_n_97), .\r_data_reg[16] (i_mr_top_n_162), .\r_data_reg[16]_0 (i_mr_top_n_205), .\r_data_reg[16]_1 (i_mr_top_n_210), .\r_data_reg[1] (i_bm_top_n_9), .\r_data_reg[1]_0 (i_mr_top_n_198), .\r_data_reg[1]_1 (i_mac_top_n_53), .\r_data_reg[1]_2 (i_im_top_n_8), .\r_data_reg[20] (i_mac_top_n_211), .\r_data_reg[20]_0 (i_mr_top_n_176), .\r_data_reg[20]_1 (i_mr_top_n_472), .\r_data_reg[20]_2 ({\cc_stat[alc_bit] [4],\cc_stat[alc_bit] [0]}), .\r_data_reg[20]_3 (i_mr_top_n_204), .\r_data_reg[20]_4 (\mr_ctrl_out[settings_rtrth] [3]), .\r_data_reg[24] (i_mac_top_n_213), .\r_data_reg[24]_0 (i_mr_top_n_183), .\r_data_reg[24]_1 (i_mr_top_n_164), .\r_data_reg[26] (i_mr_top_n_165), .\r_data_reg[26]_0 (i_mr_top_n_184), .\r_data_reg[26]_1 (i_mr_top_n_171), .\r_data_reg[26]_2 (i_mr_top_n_21), .\r_data_reg[27] (i_mr_top_n_166), .\r_data_reg[27]_0 (i_mr_top_n_185), .\r_data_reg[27]_1 (i_mr_top_n_22), .\r_data_reg[28] (i_mr_top_n_188), .\r_data_reg[28]_0 (i_mr_top_n_167), .\r_data_reg[28]_1 (i_mr_top_n_187), .\r_data_reg[29] (i_mr_top_n_189), .\r_data_reg[29]_0 (i_mr_top_n_168), .\r_data_reg[30] (i_mr_top_n_190), .\r_data_reg[30]_0 (i_mr_top_n_169), .\r_data_reg[31] (i_mr_top_n_191), .\r_data_reg[31]_0 (i_mr_top_n_170), .rec_abort(rec_abort), .rec_abort_f(rec_abort_f), .rec_brs(rec_brs), .rec_esi(rec_esi), .rec_frame_type(rec_frame_type), .rec_ident_type(rec_ident_type), .rec_is_rtr(rec_is_rtr), .rec_is_rtr_i(\i_mac_pc_top/i_mac_pc_rx_shift_reg/rec_is_rtr_i ), .rec_ivld(rec_ivld), .rec_lbpf(rec_lbpf), .rec_valid(rec_valid), .reg_q_reg(i_mr_top_n_225), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_overrun(rx_data_overrun), .rx_full(rx_full), .\rx_mem_free_raw_reg[1] (i_ff_top_n_1), .rxb_port_b_data_out_i(rxb_port_b_data_out_i), .sbe_IBUF(sbe_IBUF), .scan_mode_IBUF(scan_mode_IBUF), .soft_res_d_n(soft_res_d_n), .store_data_word(store_data_word), .store_metadata(store_metadata), .timestamp_IBUF(timestamp_IBUF), .\timestamp_capture_reg[63]_0 (timestamp_capture_ce)); txarb_top i_txarb_top (.ADDRARDADDR(\i_txtb_ram/txtb_port_b_address_i_19 [3]), .D({i_mr_top_n_401,select_buf_index}), .\FSM_sequential_curr_state[0]_i_2 (\txtb_state[0] [1]), .\FSM_sequential_curr_state[0]_i_2__1 (\txtb_state[2] ), .\FSM_sequential_curr_state[0]_i_2__3 (i_mac_top_n_110), .\FSM_sequential_curr_state_reg[0] (\i_txarb_fsm/curr_state ), .\FSM_sequential_curr_state_reg[0]_0 (i_txarb_top_n_118), .\FSM_sequential_curr_state_reg[0]_1 (i_mr_top_n_228), .\FSM_sequential_curr_state_reg[1] ({tran_word[31:27],tran_word[23:21],tran_word[18:15],tran_word[12:9],tran_word[6:3],tran_word[0]}), .\FSM_sequential_curr_state_reg[1]_0 (i_txarb_top_n_41), .\FSM_sequential_curr_state_reg[1]_1 (i_txarb_top_n_42), .\FSM_sequential_curr_state_reg[1]_2 (i_txarb_top_n_43), .\FSM_sequential_curr_state_reg[1]_3 (i_txarb_top_n_44), .\FSM_sequential_curr_state_reg[1]_4 (i_txarb_top_n_45), .\FSM_sequential_curr_state_reg[1]_5 (i_txarb_top_n_46), .\FSM_sequential_curr_state_reg[1]_6 (i_txarb_top_n_47), .\FSM_sequential_curr_state_reg[1]_7 (i_txarb_top_n_48), .\FSM_sequential_curr_state_reg[1]_8 (i_txarb_top_n_49), .\FSM_sequential_curr_state_reg[1]_9 (i_txarb_top_n_50), .\FSM_sequential_curr_state_reg[2] (i_txarb_top_n_51), .\FSM_sequential_curr_state_reg[2]_0 (i_txarb_top_n_53), .\FSM_sequential_curr_state_reg[2]_1 (\txtb_state[1] [1]), .\FSM_sequential_curr_state_reg[2]_2 (i_mr_top_n_479), .\FSM_sequential_curr_state_reg[2]_3 (i_mac_top_n_108), .Q(curr_txtb_index), .\bst_ctr_q_reg[2] (i_txarb_top_n_121), .\cc_stat[bst_ctr] ({\cc_stat[bst_ctr] [2],\cc_stat[bst_ctr] [0]}), .\cc_stat[is_transmitter] (\cc_stat[is_transmitter] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\compl_ctr_q_reg[7] (i_txarb_top_n_104), .\crc_q_reg[0] (i_txarb_top_n_89), .\crc_q_reg[1] (i_txarb_top_n_91), .\ctrl_ctr_q[4]_i_6 (i_mac_top_n_152), .curr_state(\i_txtb_fsm/curr_state [1]), .\curr_state[0]_i_8 (i_mac_top_n_139), .curr_state_1(\i_txtb_fsm/curr_state_1 [1]), .curr_state_3(\i_txtb_fsm/curr_state_3 [1]), .curr_state_5(\i_txtb_fsm/curr_state_5 [1]), .\curr_state_reg[2] (\i_mac_pc_top/i_mac_pc_tx_shift_reg/p_1_in ), .\curr_txtb_index_i_reg[0]_0 (i_txarb_top_n_30), .\curr_txtb_index_i_reg[0]_1 (i_txarb_top_n_34), .\curr_txtb_index_i_reg[0]_2 (i_txarb_top_n_39), .\curr_txtb_index_i_reg[1]_0 (i_txarb_top_n_35), .\curr_txtb_index_i_reg[1]_1 (i_txarb_top_n_37), .\curr_txtb_index_i_reg[1]_2 (i_txarb_top_n_40), .fsm_wait_state_q(\i_txarb_fsm/fsm_wait_state_q ), .fsm_wait_state_q_reg(i_mr_top_n_400), .\g_bit[0].reg_value_r_reg[0] (i_txarb_top_n_110), .\g_bit[0].reg_value_r_reg[0]_0 (i_txarb_top_n_113), .\g_bit[0].reg_value_r_reg[0]_1 (i_txarb_top_n_114), .\g_bit[0].reg_value_r_reg[0]_2 (i_txarb_top_n_116), .\g_bit[0].reg_value_r_reg[0]_3 (i_txarb_top_n_117), .\g_bit[0].reg_value_r_reg[0]_4 (i_txarb_top_n_119), .\g_bit[3].reg_value_r_reg[3] (\i_txtb_ram/txtb_port_b_address_i_16 [3]), .\g_bit[3].reg_value_r_reg[3]_0 (\i_txtb_ram/txtb_port_b_address_i_12 [3]), .\g_bit[3].reg_value_r_reg[3]_1 (\i_txtb_ram/txtb_port_b_address_i [3]), .\g_ram_rst_false.ram_memory_reg (txtb_ptr[3]), .\last_txtb_index_reg[1]_0 (i_txarb_top_n_77), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_tstm] (\mr_ctrl_out[mode_tstm] ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_tst_out[tst_dest_tst_addr] (\mr_tst_out[tst_dest_tst_addr] [3]), .\retr_ctr_q_reg[3] (i_mac_top_n_128), .\select_buf_index_reg_reg[1]_0 (select_buf_index_reg), .\shift_regs[17]_i_4 (i_mac_top_n_150), .\shift_regs[31]_i_21_0 (i_mac_top_n_119), .\shift_regs_reg[0] (i_mac_top_n_112), .\shift_regs_reg[11] (i_mac_top_n_120), .\shift_regs_reg[12] (crc_21), .\shift_regs_reg[17] (i_mac_top_n_149), .\shift_regs_reg[18] (i_mac_top_n_148), .\shift_regs_reg[19] (i_mac_top_n_147), .\shift_regs_reg[24] (i_mac_top_n_146), .\shift_regs_reg[25] (i_mac_top_n_145), .\shift_regs_reg[26] (i_mac_top_n_144), .\shift_regs_reg[27] (i_mac_top_n_143), .\shift_regs_reg[28] (i_mac_top_n_118), .\shift_regs_reg[28]_0 (i_mac_top_n_117), .\shift_regs_reg[28]_1 (i_mac_top_n_113), .timestamp_IBUF(timestamp_IBUF), .tran_brs(tran_brs), .\tran_dlc_com_reg[0]_0 (i_txarb_top_n_106), .\tran_dlc_com_reg[0]_1 (i_txarb_top_n_107), .\tran_dlc_com_reg[1]_0 (i_txarb_top_n_109), .\tran_dlc_com_reg[3]_0 ({tran_dlc[3],tran_dlc[1:0]}), .\tran_dlc_com_reg[3]_1 (i_txarb_top_n_102), .\tran_dlc_com_reg[3]_2 (i_txarb_top_n_103), .\tran_dlc_com_reg[3]_3 (i_txarb_top_n_105), .\tran_dlc_com_reg[3]_4 (i_txarb_top_n_108), .\tran_frame_test[fcrc] (\tran_frame_test[fcrc] ), .\tran_frame_test[fstc] (\tran_frame_test[fstc] ), .\tran_frame_test_dbl_buf_reg[fstc]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_75 ), .\tran_frame_test_dbl_buf_reg[fstc]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_83 ), .\tran_frame_test_dbl_buf_reg[fstc]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_76 ), .\tran_frame_test_dbl_buf_reg[fstc]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_75 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_66 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_66 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_67 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_74 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_65 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_73 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_65 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_66 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_64 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_72 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_64 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_65 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_0 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_71 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_63 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_63 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_64 ), .\tran_frame_test_reg[fcrc]_0 (i_txarb_top_n_92), .\tran_frame_test_reg[fstc]_0 (i_txarb_top_n_81), .\tran_frame_test_reg[tprm][0]_0 (i_txarb_top_n_94), .\tran_frame_test_reg[tprm][0]_1 (i_txarb_top_n_99), .\tran_frame_test_reg[tprm][0]_2 (i_txarb_top_n_120), .\tran_frame_test_reg[tprm][1]_0 (i_txarb_top_n_93), .\tran_frame_test_reg[tprm][1]_1 (i_txarb_top_n_95), .\tran_frame_test_reg[tprm][1]_2 (i_txarb_top_n_97), .\tran_frame_test_reg[tprm][1]_3 (i_txarb_top_n_98), .\tran_frame_test_reg[tprm][1]_4 (i_txarb_top_n_100), .\tran_frame_test_reg[tprm][2]_0 (i_txarb_top_n_101), .\tran_frame_test_reg[tprm][2]_1 (i_txarb_top_n_115), .\tran_frame_test_reg[tprm][3]_0 (i_txarb_top_n_111), .\tran_frame_test_reg[tprm][3]_1 (i_txarb_top_n_112), .\tran_frame_test_reg[tprm][4]_0 (i_txarb_top_n_96), .tran_frame_type(tran_frame_type), .tran_frame_type_com_reg_0(i_txarb_top_n_90), .tran_frame_valid(tran_frame_valid), .tran_frame_valid_com_reg_0(\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_42 ), .tran_frame_valid_com_reg_1(i_mr_top_n_399), .tran_frame_valid_com_reg_2(i_mac_top_n_109), .tran_ident_type(tran_ident_type), .\tran_identifier_com_reg[0]_0 (i_txarb_top_n_88), .\tran_identifier_com_reg[15]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_60 ), .\tran_identifier_com_reg[15]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_68 ), .\tran_identifier_com_reg[15]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_61 ), .\tran_identifier_com_reg[15]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_60 ), .\tran_identifier_com_reg[16]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_59 ), .\tran_identifier_com_reg[16]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_67 ), .\tran_identifier_com_reg[16]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_59 ), .\tran_identifier_com_reg[16]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_60 ), .\tran_identifier_com_reg[17]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_58 ), .\tran_identifier_com_reg[17]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_58 ), .\tran_identifier_com_reg[17]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_59 ), .\tran_identifier_com_reg[17]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_66 ), .\tran_identifier_com_reg[18]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_57 ), .\tran_identifier_com_reg[18]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_57 ), .\tran_identifier_com_reg[18]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_58 ), .\tran_identifier_com_reg[18]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_65 ), .\tran_identifier_com_reg[1]_0 (i_txarb_top_n_87), .\tran_identifier_com_reg[21]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_54 ), .\tran_identifier_com_reg[21]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_62 ), .\tran_identifier_com_reg[21]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_54 ), .\tran_identifier_com_reg[21]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_55 ), .\tran_identifier_com_reg[22]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_53 ), .\tran_identifier_com_reg[22]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_61 ), .\tran_identifier_com_reg[22]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_53 ), .\tran_identifier_com_reg[22]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_54 ), .\tran_identifier_com_reg[23]_0 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_60 ), .\tran_identifier_com_reg[23]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_52 ), .\tran_identifier_com_reg[23]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_52 ), .\tran_identifier_com_reg[23]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_53 ), .\tran_identifier_com_reg[24]_0 ({tran_identifier[24:18],tran_identifier[13:7]}), .\tran_identifier_com_reg[25]_0 (i_txarb_top_n_59), .\tran_identifier_com_reg[26]_0 (i_txarb_top_n_74), .\tran_identifier_com_reg[27]_0 (i_txarb_top_n_75), .\tran_identifier_com_reg[27]_1 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_48 ), .\tran_identifier_com_reg[27]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_56 ), .\tran_identifier_com_reg[27]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_49 ), .\tran_identifier_com_reg[27]_4 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_48 ), .\tran_identifier_com_reg[28]_0 (i_txarb_top_n_76), .\tran_identifier_com_reg[28]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_55 ), .\tran_identifier_com_reg[28]_2 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_47 ), .\tran_identifier_com_reg[28]_3 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_47 ), .\tran_identifier_com_reg[28]_4 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_48 ), .\tran_identifier_com_reg[2]_0 (i_txarb_top_n_86), .\tran_identifier_com_reg[3]_0 (i_txarb_top_n_85), .\tran_identifier_com_reg[3]_1 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_72 ), .\tran_identifier_com_reg[3]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_80 ), .\tran_identifier_com_reg[3]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_73 ), .\tran_identifier_com_reg[3]_4 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_72 ), .\tran_identifier_com_reg[4]_0 (i_txarb_top_n_84), .\tran_identifier_com_reg[4]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_79 ), .\tran_identifier_com_reg[4]_2 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_71 ), .\tran_identifier_com_reg[4]_3 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_71 ), .\tran_identifier_com_reg[4]_4 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_72 ), .\tran_identifier_com_reg[5]_0 (i_txarb_top_n_83), .\tran_identifier_com_reg[5]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_70 ), .\tran_identifier_com_reg[5]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_78 ), .\tran_identifier_com_reg[5]_3 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_70 ), .\tran_identifier_com_reg[5]_4 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_71 ), .\tran_identifier_com_reg[6]_0 (i_txarb_top_n_82), .\tran_identifier_com_reg[6]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_69 ), .\tran_identifier_com_reg[6]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_77 ), .\tran_identifier_com_reg[6]_3 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_69 ), .\tran_identifier_com_reg[6]_4 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_70 ), .tran_is_rtr(tran_is_rtr), .\ts_low_internal_reg[13]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_63 ), .\ts_low_internal_reg[13]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_62 ), .\ts_low_internal_reg[13]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_62 ), .\ts_low_internal_reg[13]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_70 ), .\ts_low_internal_reg[14]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_62 ), .\ts_low_internal_reg[14]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_69 ), .\ts_low_internal_reg[14]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_61 ), .\ts_low_internal_reg[14]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_61 ), .\ts_low_internal_reg[19]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_57 ), .\ts_low_internal_reg[19]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_56 ), .\ts_low_internal_reg[19]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_56 ), .\ts_low_internal_reg[19]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_64 ), .\ts_low_internal_reg[1]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_75 ), .\ts_low_internal_reg[1]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_74 ), .\ts_low_internal_reg[1]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_74 ), .\ts_low_internal_reg[1]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_82 ), .\ts_low_internal_reg[20]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_56 ), .\ts_low_internal_reg[20]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_63 ), .\ts_low_internal_reg[20]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_55 ), .\ts_low_internal_reg[20]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_55 ), .\ts_low_internal_reg[24]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_51 ), .\ts_low_internal_reg[24]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_51 ), .\ts_low_internal_reg[24]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_52 ), .\ts_low_internal_reg[24]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_59 ), .\ts_low_internal_reg[25]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_51 ), .\ts_low_internal_reg[25]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_50 ), .\ts_low_internal_reg[25]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_50 ), .\ts_low_internal_reg[25]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_58 ), .\ts_low_internal_reg[26]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_49 ), .\ts_low_internal_reg[26]_1 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_50 ), .\ts_low_internal_reg[26]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_57 ), .\ts_low_internal_reg[26]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_49 ), .\ts_low_internal_reg[29]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_46 ), .\ts_low_internal_reg[29]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_54 ), .\ts_low_internal_reg[29]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_46 ), .\ts_low_internal_reg[29]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_47 ), .\ts_low_internal_reg[2]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_73 ), .\ts_low_internal_reg[2]_1 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_74 ), .\ts_low_internal_reg[2]_2 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_81 ), .\ts_low_internal_reg[2]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_73 ), .\ts_low_internal_reg[30]_0 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_45 ), .\ts_low_internal_reg[30]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_53 ), .\ts_low_internal_reg[30]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_45 ), .\ts_low_internal_reg[30]_3 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_46 ), .\ts_low_internal_reg[31]_0 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_44 ), .\ts_low_internal_reg[31]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_52 ), .\ts_low_internal_reg[31]_2 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_45 ), .\ts_low_internal_reg[31]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_44 ), .\ts_low_internal_reg[7]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_69 ), .\ts_low_internal_reg[7]_1 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_68 ), .\ts_low_internal_reg[7]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_68 ), .\ts_low_internal_reg[7]_3 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_76 ), .\ts_low_internal_reg[8]_0 (\g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top_n_68 ), .\ts_low_internal_reg[8]_1 (\g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top_n_75 ), .\ts_low_internal_reg[8]_2 (\g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top_n_67 ), .\ts_low_internal_reg[8]_3 (\g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top_n_67 ), .tst_ena(\i_txtb_ram/tst_ena_22 ), .tst_ena_0(\i_txtb_ram/tst_ena_21 ), .tst_ena_2(\i_txtb_ram/tst_ena_23 ), .tst_ena_4(\i_txtb_ram/tst_ena ), .tx_command_txce_valid(tx_command_txce_valid_7), .tx_command_txce_valid_6(tx_command_txce_valid_9), .tx_command_txcr_valid(tx_command_txcr_valid_8), .tx_command_txcr_valid_7(tx_command_txcr_valid_10), .txtb_available(txtb_available), .\txtb_hw_cmd[failed] (\txtb_hw_cmd[failed] ), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .\txtb_hw_cmd[valid] (\txtb_hw_cmd[valid] ), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .\txtb_pointer_meta_q_reg[0]_0 (i_txarb_top_n_126), .\txtb_pointer_meta_q_reg[0]_1 (i_mac_top_n_215), .\txtb_pointer_meta_q_reg[1]_0 (i_txarb_top_n_124), .\txtb_pointer_meta_q_reg[4]_0 (i_txarb_top_n_125), .\txtb_ptr_q_reg[4] (i_mac_top_n_187), .\txtb_ptr_q_reg[4]_0 ({i_mac_top_n_188,i_mac_top_n_189,i_mac_top_n_190}), .\txtb_state[3] (\txtb_state[3] )); OBUF int_OBUF_inst (.I(int_OBUF), .O(int)); IBUF rst_n_IBUF_inst (.I(rst_n), .O(rst_n_IBUF)); (* OPT_MODIFIED = "RESYNTH_AREA" *) OBUF rst_n_out_OBUF_inst (.I(lopt), .O(rst_n_out)); IBUF \sbe_IBUF[0]_inst (.I(sbe[0]), .O(sbe_IBUF[0])); IBUF \sbe_IBUF[1]_inst (.I(sbe[1]), .O(sbe_IBUF[1])); IBUF \sbe_IBUF[2]_inst (.I(sbe[2]), .O(sbe_IBUF[2])); IBUF \sbe_IBUF[3]_inst (.I(sbe[3]), .O(sbe_IBUF[3])); IBUF scan_mode_IBUF_inst (.I(scan_mode), .O(scan_mode_IBUF)); IBUF scs_IBUF_inst (.I(scs), .O(scs_IBUF)); IBUF srd_IBUF_inst (.I(srd), .O(srd_IBUF)); IBUF swr_IBUF_inst (.I(swr), .O(swr_IBUF)); OBUF \test_probe[rx_trigger_nbs]_INST_0 (.I(i_btl_top_n_11), .O(\test_probe[rx_trigger_nbs] )); (* OPT_MODIFIED = "RESYNTH_AREA" *) OBUF \test_probe[rx_trigger_wbs]_INST_0 (.I(lopt_1), .O(\test_probe[rx_trigger_wbs] )); OBUF \test_probe[tx_trigger]_INST_0 (.I(i_btl_top_n_6), .O(\test_probe[tx_trigger] )); IBUF \timestamp_IBUF[0]_inst (.I(timestamp[0]), .O(timestamp_IBUF[0])); IBUF \timestamp_IBUF[10]_inst (.I(timestamp[10]), .O(timestamp_IBUF[10])); IBUF \timestamp_IBUF[11]_inst (.I(timestamp[11]), .O(timestamp_IBUF[11])); IBUF \timestamp_IBUF[12]_inst (.I(timestamp[12]), .O(timestamp_IBUF[12])); IBUF \timestamp_IBUF[13]_inst (.I(timestamp[13]), .O(timestamp_IBUF[13])); IBUF \timestamp_IBUF[14]_inst (.I(timestamp[14]), .O(timestamp_IBUF[14])); IBUF \timestamp_IBUF[15]_inst (.I(timestamp[15]), .O(timestamp_IBUF[15])); IBUF \timestamp_IBUF[16]_inst (.I(timestamp[16]), .O(timestamp_IBUF[16])); IBUF \timestamp_IBUF[17]_inst (.I(timestamp[17]), .O(timestamp_IBUF[17])); IBUF \timestamp_IBUF[18]_inst (.I(timestamp[18]), .O(timestamp_IBUF[18])); IBUF \timestamp_IBUF[19]_inst (.I(timestamp[19]), .O(timestamp_IBUF[19])); IBUF \timestamp_IBUF[1]_inst (.I(timestamp[1]), .O(timestamp_IBUF[1])); IBUF \timestamp_IBUF[20]_inst (.I(timestamp[20]), .O(timestamp_IBUF[20])); IBUF \timestamp_IBUF[21]_inst (.I(timestamp[21]), .O(timestamp_IBUF[21])); IBUF \timestamp_IBUF[22]_inst (.I(timestamp[22]), .O(timestamp_IBUF[22])); IBUF \timestamp_IBUF[23]_inst (.I(timestamp[23]), .O(timestamp_IBUF[23])); IBUF \timestamp_IBUF[24]_inst (.I(timestamp[24]), .O(timestamp_IBUF[24])); IBUF \timestamp_IBUF[25]_inst (.I(timestamp[25]), .O(timestamp_IBUF[25])); IBUF \timestamp_IBUF[26]_inst (.I(timestamp[26]), .O(timestamp_IBUF[26])); IBUF \timestamp_IBUF[27]_inst (.I(timestamp[27]), .O(timestamp_IBUF[27])); IBUF \timestamp_IBUF[28]_inst (.I(timestamp[28]), .O(timestamp_IBUF[28])); IBUF \timestamp_IBUF[29]_inst (.I(timestamp[29]), .O(timestamp_IBUF[29])); IBUF \timestamp_IBUF[2]_inst (.I(timestamp[2]), .O(timestamp_IBUF[2])); IBUF \timestamp_IBUF[30]_inst (.I(timestamp[30]), .O(timestamp_IBUF[30])); IBUF \timestamp_IBUF[31]_inst (.I(timestamp[31]), .O(timestamp_IBUF[31])); IBUF \timestamp_IBUF[32]_inst (.I(timestamp[32]), .O(timestamp_IBUF[32])); IBUF \timestamp_IBUF[33]_inst (.I(timestamp[33]), .O(timestamp_IBUF[33])); IBUF \timestamp_IBUF[34]_inst (.I(timestamp[34]), .O(timestamp_IBUF[34])); IBUF \timestamp_IBUF[35]_inst (.I(timestamp[35]), .O(timestamp_IBUF[35])); IBUF \timestamp_IBUF[36]_inst (.I(timestamp[36]), .O(timestamp_IBUF[36])); IBUF \timestamp_IBUF[37]_inst (.I(timestamp[37]), .O(timestamp_IBUF[37])); IBUF \timestamp_IBUF[38]_inst (.I(timestamp[38]), .O(timestamp_IBUF[38])); IBUF \timestamp_IBUF[39]_inst (.I(timestamp[39]), .O(timestamp_IBUF[39])); IBUF \timestamp_IBUF[3]_inst (.I(timestamp[3]), .O(timestamp_IBUF[3])); IBUF \timestamp_IBUF[40]_inst (.I(timestamp[40]), .O(timestamp_IBUF[40])); IBUF \timestamp_IBUF[41]_inst (.I(timestamp[41]), .O(timestamp_IBUF[41])); IBUF \timestamp_IBUF[42]_inst (.I(timestamp[42]), .O(timestamp_IBUF[42])); IBUF \timestamp_IBUF[43]_inst (.I(timestamp[43]), .O(timestamp_IBUF[43])); IBUF \timestamp_IBUF[44]_inst (.I(timestamp[44]), .O(timestamp_IBUF[44])); IBUF \timestamp_IBUF[45]_inst (.I(timestamp[45]), .O(timestamp_IBUF[45])); IBUF \timestamp_IBUF[46]_inst (.I(timestamp[46]), .O(timestamp_IBUF[46])); IBUF \timestamp_IBUF[47]_inst (.I(timestamp[47]), .O(timestamp_IBUF[47])); IBUF \timestamp_IBUF[48]_inst (.I(timestamp[48]), .O(timestamp_IBUF[48])); IBUF \timestamp_IBUF[49]_inst (.I(timestamp[49]), .O(timestamp_IBUF[49])); IBUF \timestamp_IBUF[4]_inst (.I(timestamp[4]), .O(timestamp_IBUF[4])); IBUF \timestamp_IBUF[50]_inst (.I(timestamp[50]), .O(timestamp_IBUF[50])); IBUF \timestamp_IBUF[51]_inst (.I(timestamp[51]), .O(timestamp_IBUF[51])); IBUF \timestamp_IBUF[52]_inst (.I(timestamp[52]), .O(timestamp_IBUF[52])); IBUF \timestamp_IBUF[53]_inst (.I(timestamp[53]), .O(timestamp_IBUF[53])); IBUF \timestamp_IBUF[54]_inst (.I(timestamp[54]), .O(timestamp_IBUF[54])); IBUF \timestamp_IBUF[55]_inst (.I(timestamp[55]), .O(timestamp_IBUF[55])); IBUF \timestamp_IBUF[56]_inst (.I(timestamp[56]), .O(timestamp_IBUF[56])); IBUF \timestamp_IBUF[57]_inst (.I(timestamp[57]), .O(timestamp_IBUF[57])); IBUF \timestamp_IBUF[58]_inst (.I(timestamp[58]), .O(timestamp_IBUF[58])); IBUF \timestamp_IBUF[59]_inst (.I(timestamp[59]), .O(timestamp_IBUF[59])); IBUF \timestamp_IBUF[5]_inst (.I(timestamp[5]), .O(timestamp_IBUF[5])); IBUF \timestamp_IBUF[60]_inst (.I(timestamp[60]), .O(timestamp_IBUF[60])); IBUF \timestamp_IBUF[61]_inst (.I(timestamp[61]), .O(timestamp_IBUF[61])); IBUF \timestamp_IBUF[62]_inst (.I(timestamp[62]), .O(timestamp_IBUF[62])); IBUF \timestamp_IBUF[63]_inst (.I(timestamp[63]), .O(timestamp_IBUF[63])); IBUF \timestamp_IBUF[6]_inst (.I(timestamp[6]), .O(timestamp_IBUF[6])); IBUF \timestamp_IBUF[7]_inst (.I(timestamp[7]), .O(timestamp_IBUF[7])); IBUF \timestamp_IBUF[8]_inst (.I(timestamp[8]), .O(timestamp_IBUF[8])); IBUF \timestamp_IBUF[9]_inst (.I(timestamp[9]), .O(timestamp_IBUF[9])); endmodule module dff_arst (reg_q_reg_0, reg_q_reg_1, clk_sys_IBUF_BUFG, reg_q_reg_2, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg_0; input reg_q_reg_1; input clk_sys_IBUF_BUFG; input reg_q_reg_2; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire q_i; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire rst_n_out_OBUF; wire scan_mode_IBUF; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_2), .D(reg_q_reg_1), .Q(q_i)); LUT3 #( .INIT(8'h1D)) \write_pointer_raw_i[4]_i_3 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_2 (reg_q_reg_0, soft_res_d_n, clk_sys_IBUF_BUFG, reg_q_reg_1, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg_0; input soft_res_d_n; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire q_i; wire reg_q_reg_0; wire reg_q_reg_1; wire rst_n_out_OBUF; wire scan_mode_IBUF; wire soft_res_d_n; LUT3 #( .INIT(8'h1D)) \g_bit[0].reg_value_r[0]_i_2__11 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(reg_q_reg_0)); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_1), .D(soft_res_d_n), .Q(q_i)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_3 (reg_q_reg_0, reg_q_reg_1, reg_q_reg_2, reg_q_reg_3, reg_q_reg_4, clk_sys_IBUF_BUFG, reg_q_reg_5, scan_mode_IBUF, rst_n_out_OBUF, data_in_IBUF, reg_q_reg_6, reg_q_reg_7, reg_q_reg_8); output reg_q_reg_0; output reg_q_reg_1; output reg_q_reg_2; output reg_q_reg_3; input reg_q_reg_4; input clk_sys_IBUF_BUFG; input reg_q_reg_5; input scan_mode_IBUF; input rst_n_out_OBUF; input [0:0]data_in_IBUF; input reg_q_reg_6; input reg_q_reg_7; input reg_q_reg_8; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire reg_q_reg_7; wire reg_q_reg_8; wire rst_n_out_OBUF; wire scan_mode_IBUF; (* SOFT_HLUTNM = "soft_lutpair313" *) LUT3 #( .INIT(8'h1D)) \FSM_onehot_curr_state[11]_i_3 (.I0(reg_q_reg_0), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(reg_q_reg_2)); LUT6 #( .INIT(64'hE2E200E2E2E2E2E2)) reg_q_i_1__1 (.I0(reg_q_reg_0), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .I3(data_in_IBUF), .I4(reg_q_reg_6), .I5(reg_q_reg_7), .O(reg_q_reg_1)); (* SOFT_HLUTNM = "soft_lutpair313" *) LUT4 #( .INIT(16'h00E2)) reg_q_i_1__4 (.I0(reg_q_reg_0), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .I3(reg_q_reg_8), .O(reg_q_reg_3)); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_5), .D(reg_q_reg_4), .Q(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_57 (tx_trigger_q, tx_trigger_ssp, \write_pointer_q_reg[0] , reg_q_reg_0, clk_sys_IBUF_BUFG, reg_q_reg_1, \write_pointer_q_reg[0]_0 , \write_pointer_q_reg[0]_1 ); output tx_trigger_q; output tx_trigger_ssp; output \write_pointer_q_reg[0] ; input reg_q_reg_0; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input \write_pointer_q_reg[0]_0 ; input [0:0]\write_pointer_q_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire reg_q_reg_0; wire reg_q_reg_1; wire tx_trigger_q; wire tx_trigger_ssp; wire \write_pointer_q_reg[0] ; wire \write_pointer_q_reg[0]_0 ; wire [0:0]\write_pointer_q_reg[0]_1 ; LUT2 #( .INIT(4'h6)) \i_bm_tx_data_cache/write_pointer_q[0]_i_1 (.I0(tx_trigger_ssp), .I1(\write_pointer_q_reg[0]_1 ), .O(\write_pointer_q_reg[0] )); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_1), .D(reg_q_reg_0), .Q(tx_trigger_q)); LUT2 #( .INIT(4'h8)) \tx_cache_mem[7]_i_3 (.I0(tx_trigger_q), .I1(\write_pointer_q_reg[0]_0 ), .O(tx_trigger_ssp)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_59 (reg_q_reg_0, reg_q_reg_1, clk_sys_IBUF_BUFG, reg_q_reg_2, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg_0; input reg_q_reg_1; input clk_sys_IBUF_BUFG; input reg_q_reg_2; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire q_i; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire rst_n_out_OBUF; wire scan_mode_IBUF; LUT3 #( .INIT(8'h1D)) \g_byte_shift_reg[1].shift_reg_q[1][7]_i_2 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(reg_q_reg_0)); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_2), .D(reg_q_reg_1), .Q(q_i)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_61 (reg_q_reg_0, reg_q_reg_1, clk_sys_IBUF_BUFG, reg_q_reg_2, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg_0; input reg_q_reg_1; input clk_sys_IBUF_BUFG; input reg_q_reg_2; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire q_i; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire rst_n_out_OBUF; wire scan_mode_IBUF; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_2), .D(reg_q_reg_1), .Q(q_i)); LUT3 #( .INIT(8'h1D)) \rx_err_ctr_q[8]_i_3 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .O(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_62 (reg_q_reg_0, stuff_enable_reg, \same_bits_q_reg[2] , stuff_enable, clk_sys_IBUF_BUFG, reg_q_reg_1, \crc_q_reg[0] , \crc_q_reg[0]_0 , \bst_ctr_q_reg[2] , \bst_ctr_q_reg[2]_0 , \bst_ctr_q_reg[2]_1 ); output reg_q_reg_0; output stuff_enable_reg; output \same_bits_q_reg[2] ; input stuff_enable; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input \crc_q_reg[0] ; input \crc_q_reg[0]_0 ; input \bst_ctr_q_reg[2] ; input \bst_ctr_q_reg[2]_0 ; input \bst_ctr_q_reg[2]_1 ; wire \bst_ctr_q_reg[2] ; wire \bst_ctr_q_reg[2]_0 ; wire \bst_ctr_q_reg[2]_1 ; wire clk_sys_IBUF_BUFG; wire \crc_q_reg[0] ; wire \crc_q_reg[0]_0 ; wire reg_q_reg_0; wire reg_q_reg_1; wire \same_bits_q_reg[2] ; wire stuff_enable; wire stuff_enable_reg; LUT5 #( .INIT(32'hF700FFFF)) \bst_ctr_q[2]_i_3 (.I0(\bst_ctr_q_reg[2] ), .I1(\bst_ctr_q_reg[2]_0 ), .I2(\bst_ctr_q_reg[2]_1 ), .I3(reg_q_reg_0), .I4(stuff_enable), .O(\same_bits_q_reg[2] )); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_1), .D(stuff_enable), .Q(reg_q_reg_0)); LUT4 #( .INIT(16'hF700)) \shift_regs[31]_i_4 (.I0(stuff_enable), .I1(reg_q_reg_0), .I2(\crc_q_reg[0] ), .I3(\crc_q_reg[0]_0 ), .O(stuff_enable_reg)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_64 (data_halt_q, data_halt_d1_out, clk_sys_IBUF_BUFG, reg_q_reg_0); output data_halt_q; input data_halt_d1_out; input clk_sys_IBUF_BUFG; input reg_q_reg_0; wire clk_sys_IBUF_BUFG; wire data_halt_d1_out; wire data_halt_q; wire reg_q_reg_0; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(data_halt_d1_out), .Q(data_halt_q)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_66 (reg_q_reg_0, reg_q_reg_1, rx_trig_req_q_reg, reg_q_reg_2, \same_bits_q_reg[2] , destuffed_d0_out, clk_sys_IBUF_BUFG, reg_q_reg_3, q_i, scan_mode_IBUF, rst_n_out_OBUF, reg_q_reg_4, reg_q_reg_5, \crc_q[16]_i_3 , reg_q_reg_6, reg_q_reg_7, reg_q_reg_8); output reg_q_reg_0; output reg_q_reg_1; output rx_trig_req_q_reg; output reg_q_reg_2; output \same_bits_q_reg[2] ; input destuffed_d0_out; input clk_sys_IBUF_BUFG; input reg_q_reg_3; input q_i; input scan_mode_IBUF; input rst_n_out_OBUF; input reg_q_reg_4; input reg_q_reg_5; input \crc_q[16]_i_3 ; input reg_q_reg_6; input reg_q_reg_7; input reg_q_reg_8; wire clk_sys_IBUF_BUFG; wire \crc_q[16]_i_3 ; wire destuffed_d0_out; wire q_i; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire reg_q_reg_7; wire reg_q_reg_8; wire rst_n_out_OBUF; wire rx_trig_req_q_reg; wire \same_bits_q_reg[2] ; wire scan_mode_IBUF; (* SOFT_HLUTNM = "soft_lutpair130" *) LUT3 #( .INIT(8'h0D)) \crc_q[16]_i_5 (.I0(reg_q_reg_4), .I1(reg_q_reg_0), .I2(\crc_q[16]_i_3 ), .O(rx_trig_req_q_reg)); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT2 #( .INIT(4'hB)) mr_command_ercrst_q_i_2 (.I0(reg_q_reg_0), .I1(reg_q_reg_4), .O(reg_q_reg_2)); LUT6 #( .INIT(64'hE200E2E2E2E2E2E2)) reg_q_i_1__3 (.I0(q_i), .I1(scan_mode_IBUF), .I2(rst_n_out_OBUF), .I3(reg_q_reg_0), .I4(reg_q_reg_4), .I5(reg_q_reg_5), .O(reg_q_reg_1)); LUT3 #( .INIT(8'h08)) reg_q_i_2__7 (.I0(reg_q_reg_6), .I1(reg_q_reg_7), .I2(reg_q_reg_8), .O(\same_bits_q_reg[2] )); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_3), .D(destuffed_d0_out), .Q(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_67 (enable_prev, reg_q_reg_0, dst_ctr_d, destuff_enable, clk_sys_IBUF_BUFG, reg_q_reg_1, \dst_ctr_q_reg[2] , \dst_ctr_q_reg[2]_0 , \dst_ctr_q_reg[2]_1 ); output enable_prev; output reg_q_reg_0; output [0:0]dst_ctr_d; input destuff_enable; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input \dst_ctr_q_reg[2] ; input \dst_ctr_q_reg[2]_0 ; input \dst_ctr_q_reg[2]_1 ; wire clk_sys_IBUF_BUFG; wire destuff_enable; wire [0:0]dst_ctr_d; wire \dst_ctr_q_reg[2] ; wire \dst_ctr_q_reg[2]_0 ; wire \dst_ctr_q_reg[2]_1 ; wire enable_prev; wire reg_q_reg_0; wire reg_q_reg_1; (* SOFT_HLUTNM = "soft_lutpair131" *) LUT4 #( .INIT(16'h2A80)) \dst_ctr_q[2]_i_2 (.I0(enable_prev), .I1(\dst_ctr_q_reg[2] ), .I2(\dst_ctr_q_reg[2]_0 ), .I3(\dst_ctr_q_reg[2]_1 ), .O(dst_ctr_d)); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_1), .D(destuff_enable), .Q(enable_prev)); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT2 #( .INIT(4'h7)) \same_bits_q[2]_i_4__0 (.I0(enable_prev), .I1(destuff_enable), .O(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_68 (stuff_err, stuff_err_d, clk_sys_IBUF_BUFG, reg_q_reg_0); output stuff_err; input stuff_err_d; input clk_sys_IBUF_BUFG; input reg_q_reg_0; wire clk_sys_IBUF_BUFG; wire reg_q_reg_0; wire stuff_err; wire stuff_err_d; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(stuff_err_d), .Q(stuff_err)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_81 (int_OBUF, int_i, clk_sys_IBUF_BUFG, reg_q_reg_0); output int_OBUF; input int_i; input clk_sys_IBUF_BUFG; input reg_q_reg_0; wire clk_sys_IBUF_BUFG; wire int_OBUF; wire int_i; wire reg_q_reg_0; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(int_i), .Q(int_OBUF)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_83 (q_i, reg_q_reg_0, clk_sys_IBUF_BUFG, reg_q_reg_1); output q_i; input reg_q_reg_0; input clk_sys_IBUF_BUFG; input reg_q_reg_1; wire clk_sys_IBUF_BUFG; wire q_i; wire reg_q_reg_0; wire reg_q_reg_1; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_1), .D(reg_q_reg_0), .Q(q_i)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst_85 (q_i, p_0_out, clk_sys_IBUF_BUFG, reg_q_reg_0); output q_i; input p_0_out; input clk_sys_IBUF_BUFG; input reg_q_reg_0; wire clk_sys_IBUF_BUFG; wire p_0_out; wire q_i; wire reg_q_reg_0; FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(p_0_out), .Q(q_i)); endmodule (* ORIG_REF_NAME = "dff_arst" *) module dff_arst__parameterized0 (reg_q, prev_val_d, clk_sys_IBUF_BUFG, reg_q_reg_0); output reg_q; input prev_val_d; input clk_sys_IBUF_BUFG; input reg_q_reg_0; wire clk_sys_IBUF_BUFG; wire prev_val_d; wire reg_q; wire reg_q_reg_0; FDPE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(prev_val_d), .PRE(reg_q_reg_0), .Q(reg_q)); endmodule module dff_arst_ce (crc_data_rx_wbs, bds_data_in, reg_q_reg_0, clk_sys_IBUF_BUFG, reg_q_reg_1); output crc_data_rx_wbs; input bds_data_in; input reg_q_reg_0; input clk_sys_IBUF_BUFG; input reg_q_reg_1; wire bds_data_in; wire clk_sys_IBUF_BUFG; wire crc_data_rx_wbs; wire reg_q_i_1_n_0; wire reg_q_reg_0; wire reg_q_reg_1; LUT3 #( .INIT(8'hB8)) reg_q_i_1 (.I0(bds_data_in), .I1(reg_q_reg_0), .I2(crc_data_rx_wbs), .O(reg_q_i_1_n_0)); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_1), .D(reg_q_i_1_n_0), .Q(crc_data_rx_wbs)); endmodule (* ORIG_REF_NAME = "dff_arst_ce" *) module dff_arst_ce_63 (data_halt_d1_out, \same_bits_q_reg[1] , reg_q_reg_0, reg_q_reg_1, data_halt_q, reg_q_reg_2, stuff_enable, reg_q_reg_3, reg_q_reg_4, reg_q_reg_5, reg_q_reg_6, clk_sys_IBUF_BUFG, reg_q_reg_7); output data_halt_d1_out; output \same_bits_q_reg[1] ; output reg_q_reg_0; input reg_q_reg_1; input data_halt_q; input reg_q_reg_2; input stuff_enable; input reg_q_reg_3; input reg_q_reg_4; input reg_q_reg_5; input reg_q_reg_6; input clk_sys_IBUF_BUFG; input reg_q_reg_7; wire clk_sys_IBUF_BUFG; wire data_halt_d1_out; wire data_halt_q; wire fixed_reg_q; wire reg_q_i_1_n_0; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire reg_q_reg_7; wire \same_bits_q_reg[1] ; wire stuff_enable; LUT5 #( .INIT(32'hA2FF8000)) reg_q_i_1 (.I0(reg_q_reg_2), .I1(reg_q_reg_1), .I2(reg_q_reg_3), .I3(stuff_enable), .I4(fixed_reg_q), .O(reg_q_i_1_n_0)); LUT5 #( .INIT(32'h72000000)) reg_q_i_1__5 (.I0(reg_q_reg_1), .I1(\same_bits_q_reg[1] ), .I2(data_halt_q), .I3(reg_q_reg_2), .I4(stuff_enable), .O(data_halt_d1_out)); LUT6 #( .INIT(64'h08080808AA080808)) reg_q_i_2__2 (.I0(reg_q_reg_1), .I1(reg_q_reg_3), .I2(fixed_reg_q), .I3(reg_q_reg_4), .I4(reg_q_reg_5), .I5(reg_q_reg_6), .O(reg_q_reg_0)); LUT5 #( .INIT(32'hBF00BFBF)) reg_q_i_2__3 (.I0(reg_q_reg_6), .I1(reg_q_reg_5), .I2(reg_q_reg_4), .I3(fixed_reg_q), .I4(reg_q_reg_3), .O(\same_bits_q_reg[1] )); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_7), .D(reg_q_i_1_n_0), .Q(fixed_reg_q)); endmodule (* ORIG_REF_NAME = "dff_arst_ce" *) module dff_arst_ce_69 (destuffed_d0_out, reg_q_reg_0, \same_bits_q_reg[1] , destuff_enable, reg_q_reg_1, reg_q_reg_2, reg_q_reg_3, reg_q_reg_4, \same_bits_q_reg[0] , \same_bits_q_reg[0]_0 , \same_bits_q_reg[0]_1 , enable_prev, clk_sys_IBUF_BUFG, reg_q_reg_5); output destuffed_d0_out; output reg_q_reg_0; output \same_bits_q_reg[1] ; input destuff_enable; input reg_q_reg_1; input reg_q_reg_2; input reg_q_reg_3; input reg_q_reg_4; input \same_bits_q_reg[0] ; input \same_bits_q_reg[0]_0 ; input \same_bits_q_reg[0]_1 ; input enable_prev; input clk_sys_IBUF_BUFG; input reg_q_reg_5; wire clk_sys_IBUF_BUFG; wire destuff_enable; wire destuffed_d0_out; wire enable_prev; wire reg_q_i_1_n_0; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire \same_bits_q_reg[0] ; wire \same_bits_q_reg[0]_0 ; wire \same_bits_q_reg[0]_1 ; wire \same_bits_q_reg[1] ; LUT5 #( .INIT(32'hD0FF8000)) reg_q_i_1 (.I0(reg_q_reg_1), .I1(reg_q_reg_2), .I2(enable_prev), .I3(destuff_enable), .I4(reg_q_reg_0), .O(reg_q_i_1_n_0)); LUT6 #( .INIT(64'hAAAA22A288880080)) reg_q_i_1__7 (.I0(destuff_enable), .I1(reg_q_reg_1), .I2(reg_q_reg_2), .I3(reg_q_reg_0), .I4(reg_q_reg_3), .I5(reg_q_reg_4), .O(destuffed_d0_out)); FDCE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_5), .D(reg_q_i_1_n_0), .Q(reg_q_reg_0)); LUT5 #( .INIT(32'hBF00BFBF)) \same_bits_q[2]_i_2__0 (.I0(\same_bits_q_reg[0] ), .I1(\same_bits_q_reg[0]_0 ), .I2(\same_bits_q_reg[0]_1 ), .I3(reg_q_reg_0), .I4(reg_q_reg_2), .O(\same_bits_q_reg[1] )); endmodule (* ORIG_REF_NAME = "dff_arst_ce" *) module dff_arst_ce__parameterized0 (reg_q_reg_0, reg_q_reg_1, reg_q_reg_2, \same_bits_q_reg[0] , \same_bits_q_reg[0]_0 , reg_q_reg_3, \same_bits_q_reg[0]_1 , reg_q_reg_4, stuff_enable, clk_sys_IBUF_BUFG, reg_q_reg_5); output reg_q_reg_0; output reg_q_reg_1; input reg_q_reg_2; input \same_bits_q_reg[0] ; input \same_bits_q_reg[0]_0 ; input reg_q_reg_3; input \same_bits_q_reg[0]_1 ; input reg_q_reg_4; input stuff_enable; input clk_sys_IBUF_BUFG; input reg_q_reg_5; wire clk_sys_IBUF_BUFG; wire reg_q_i_1_n_0; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire \same_bits_q_reg[0] ; wire \same_bits_q_reg[0]_0 ; wire \same_bits_q_reg[0]_1 ; wire stuff_enable; LUT5 #( .INIT(32'h4C5FECA0)) reg_q_i_1 (.I0(reg_q_reg_4), .I1(reg_q_reg_2), .I2(stuff_enable), .I3(reg_q_reg_3), .I4(reg_q_reg_1), .O(reg_q_i_1_n_0)); FDPE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(reg_q_i_1_n_0), .PRE(reg_q_reg_5), .Q(reg_q_reg_1)); LUT6 #( .INIT(64'hF900FF000000FF00)) \same_bits_q[2]_i_2 (.I0(reg_q_reg_1), .I1(reg_q_reg_2), .I2(\same_bits_q_reg[0] ), .I3(\same_bits_q_reg[0]_0 ), .I4(reg_q_reg_3), .I5(\same_bits_q_reg[0]_1 ), .O(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "dff_arst_ce" *) module dff_arst_ce__parameterized0_65 (reg_q_reg_0, reg_q_reg_1, reg_q_reg_2, reg_q_reg_3, reg_q_reg_4, reg_q_reg_5, reg_q_reg_6, reg_q_reg_7, reg_q_reg_8, reg_q_reg_9, tran_frame_valid, \mr_ctrl_out[settings_pex] , \err_capt_err_type_q[2]_i_3 , Q, sync_edge, rx_data_nbs_prev_reg, rx_data_nbs_prev_reg_0, rx_data_nbs_prev, rec_brs_reg, rec_brs, bds_data_in, reg_q_reg_10, clk_sys_IBUF_BUFG, reg_q_reg_11); output reg_q_reg_0; output reg_q_reg_1; output reg_q_reg_2; output reg_q_reg_3; output reg_q_reg_4; output reg_q_reg_5; output reg_q_reg_6; output reg_q_reg_7; output reg_q_reg_8; output reg_q_reg_9; input tran_frame_valid; input \mr_ctrl_out[settings_pex] ; input \err_capt_err_type_q[2]_i_3 ; input [2:0]Q; input sync_edge; input rx_data_nbs_prev_reg; input rx_data_nbs_prev_reg_0; input rx_data_nbs_prev; input rec_brs_reg; input rec_brs; input bds_data_in; input reg_q_reg_10; input clk_sys_IBUF_BUFG; input reg_q_reg_11; wire [2:0]Q; wire bds_data_in; wire clk_sys_IBUF_BUFG; wire \err_capt_err_type_q[2]_i_3 ; wire \mr_ctrl_out[settings_pex] ; wire rec_brs; wire rec_brs_reg; wire reg_q_i_1_n_0; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_10; wire reg_q_reg_11; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire reg_q_reg_7; wire reg_q_reg_8; wire reg_q_reg_9; wire rx_data_nbs_prev; wire rx_data_nbs_prev_reg; wire rx_data_nbs_prev_reg_0; wire sync_edge; wire tran_frame_valid; (* SOFT_HLUTNM = "soft_lutpair128" *) LUT3 #( .INIT(8'h0D)) \ctrl_ctr_q[3]_i_14 (.I0(reg_q_reg_1), .I1(sync_edge), .I2(Q[1]), .O(reg_q_reg_7)); (* SOFT_HLUTNM = "soft_lutpair128" *) LUT2 #( .INIT(4'h2)) \ctrl_ctr_q[8]_i_34 (.I0(reg_q_reg_1), .I1(Q[0]), .O(reg_q_reg_5)); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h2)) \curr_state[4]_i_10 (.I0(reg_q_reg_1), .I1(\err_capt_err_type_q[2]_i_3 ), .O(reg_q_reg_3)); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h8)) destuff_enable_i_6 (.I0(reg_q_reg_1), .I1(\mr_ctrl_out[settings_pex] ), .O(reg_q_reg_2)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT2 #( .INIT(4'h2)) destuff_enable_i_7 (.I0(reg_q_reg_1), .I1(tran_frame_valid), .O(reg_q_reg_0)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT2 #( .INIT(4'hB)) \err_capt_err_type_q[2]_i_7 (.I0(reg_q_reg_1), .I1(\err_capt_err_type_q[2]_i_3 ), .O(reg_q_reg_6)); LUT5 #( .INIT(32'hFFBF0080)) \i_mac_pc_rx_shift_reg/rec_brs_i_1 (.I0(reg_q_reg_1), .I1(rec_brs_reg), .I2(rx_data_nbs_prev_reg), .I3(rx_data_nbs_prev_reg_0), .I4(rec_brs), .O(reg_q_reg_9)); (* SOFT_HLUTNM = "soft_lutpair127" *) LUT3 #( .INIT(8'hB8)) reg_q_i_1 (.I0(bds_data_in), .I1(reg_q_reg_10), .I2(reg_q_reg_1), .O(reg_q_i_1_n_0)); FDPE reg_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(reg_q_i_1_n_0), .PRE(reg_q_reg_11), .Q(reg_q_reg_1)); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT4 #( .INIT(16'hFB08)) rx_data_nbs_prev_i_1 (.I0(reg_q_reg_1), .I1(rx_data_nbs_prev_reg), .I2(rx_data_nbs_prev_reg_0), .I3(rx_data_nbs_prev), .O(reg_q_reg_8)); LUT2 #( .INIT(4'hE)) tx_frame_no_sof_q_i_3 (.I0(reg_q_reg_1), .I1(Q[2]), .O(reg_q_reg_4)); endmodule module dp_inf_ram (rxb_port_b_data_out_i, D, \g_bit[0].reg_value_r_reg[0] , \adress[4] , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_ram_rst_false.ram_memory_reg_4 , \g_bit[0].reg_value_r_reg[0]_0 , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , \g_ram_rst_false.ram_memory_reg_7 , \g_ram_rst_false.ram_memory_reg_8 , \g_bit[0].reg_value_r_reg[0]_1 , \adress[4]_0 , \frame_count_reg[3] , \g_ram_rst_false.ram_memory_reg_9 , rxb_port_b_data_out, \g_ram_rst_false.ram_memory_reg_10 , clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, rxb_port_a_data_in_i, DIADI, WEBWE, sbe_IBUF, \r_data_reg[11] , \r_data_reg[11]_0 , adress_IBUF, \r_data_reg[11]_1 , \r_data_reg[26] , \r_data_reg[26]_0 , \r_data_reg[26]_1 , \r_data_reg[27] , \r_data_reg[27]_0 , \r_data_reg[28] , \r_data_reg[28]_0 , \r_data_reg[28]_1 , \r_data_reg[28]_2 , \r_data_reg[29] , \r_data_reg[29]_0 , \r_data_reg[30] , \r_data_reg[30]_0 , \r_data_reg[31] , \r_data_reg[31]_0 , \r_data_reg[0] , \r_data_reg[0]_0 , soft_res_d_n, \r_data_reg[0]_1 , \r_data_reg[24] , \r_data_reg[24]_0 , \r_data_reg[24]_1 , \mr_ctrl_out[settings_pex] , \r_data_reg[26]_2 , \r_data_reg[27]_1 , \r_data[6]_i_2 , \r_data[7]_i_2__0 , \r_data[8]_i_2 , \r_data[9]_i_2__0 , \r_data[10]_i_2__0 , \r_data_reg[11]_2 , \r_data_reg[11]_3 , \r_data_reg[11]_4 , \r_data[11]_i_2__0_0 , \r_data[15]_i_6 , \r_data[0]_i_2_0 , \r_data[12]_i_2 , \r_data[13]_i_2 , \r_data_reg[14]_i_2 , \r_data[14]_i_5_0 , \r_data[21]_i_2 , \r_data[21]_i_2_0 , \r_data[23]_i_2 , \r_data[4]_i_2 , \r_data[4]_i_2_0 , \r_data[0]_i_2_1 , \r_data[0]_i_2_2 , \r_data[5]_i_2 , Q, \r_data[6]_i_4_0 , \r_data[4]_i_5_0 , rx_mof, \read_counter_q_reg[0] ); output [31:0]rxb_port_b_data_out_i; output [8:0]D; output \g_bit[0].reg_value_r_reg[0] ; output \adress[4] ; output \g_ram_rst_false.ram_memory_reg_0 ; output \g_ram_rst_false.ram_memory_reg_1 ; output \g_ram_rst_false.ram_memory_reg_2 ; output \g_ram_rst_false.ram_memory_reg_3 ; output \g_ram_rst_false.ram_memory_reg_4 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_ram_rst_false.ram_memory_reg_5 ; output \g_ram_rst_false.ram_memory_reg_6 ; output \g_ram_rst_false.ram_memory_reg_7 ; output \g_ram_rst_false.ram_memory_reg_8 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \adress[4]_0 ; output \frame_count_reg[3] ; output \g_ram_rst_false.ram_memory_reg_9 ; output [0:0]rxb_port_b_data_out; output [4:0]\g_ram_rst_false.ram_memory_reg_10 ; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [30:0]rxb_port_a_data_in_i; input [0:0]DIADI; input [0:0]WEBWE; input [2:0]sbe_IBUF; input \r_data_reg[11] ; input \r_data_reg[11]_0 ; input [5:0]adress_IBUF; input \r_data_reg[11]_1 ; input \r_data_reg[26] ; input \r_data_reg[26]_0 ; input \r_data_reg[26]_1 ; input \r_data_reg[27] ; input \r_data_reg[27]_0 ; input \r_data_reg[28] ; input \r_data_reg[28]_0 ; input \r_data_reg[28]_1 ; input \r_data_reg[28]_2 ; input \r_data_reg[29] ; input \r_data_reg[29]_0 ; input \r_data_reg[30] ; input \r_data_reg[30]_0 ; input \r_data_reg[31] ; input \r_data_reg[31]_0 ; input \r_data_reg[0] ; input \r_data_reg[0]_0 ; input soft_res_d_n; input \r_data_reg[0]_1 ; input \r_data_reg[24] ; input \r_data_reg[24]_0 ; input \r_data_reg[24]_1 ; input \mr_ctrl_out[settings_pex] ; input \r_data_reg[26]_2 ; input \r_data_reg[27]_1 ; input \r_data[6]_i_2 ; input \r_data[7]_i_2__0 ; input \r_data[8]_i_2 ; input \r_data[9]_i_2__0 ; input \r_data[10]_i_2__0 ; input \r_data_reg[11]_2 ; input \r_data_reg[11]_3 ; input \r_data_reg[11]_4 ; input \r_data[11]_i_2__0_0 ; input \r_data[15]_i_6 ; input \r_data[0]_i_2_0 ; input \r_data[12]_i_2 ; input \r_data[13]_i_2 ; input \r_data_reg[14]_i_2 ; input \r_data[14]_i_5_0 ; input \r_data[21]_i_2 ; input [0:0]\r_data[21]_i_2_0 ; input [1:0]\r_data[23]_i_2 ; input \r_data[4]_i_2 ; input \r_data[4]_i_2_0 ; input \r_data[0]_i_2_1 ; input \r_data[0]_i_2_2 ; input \r_data[5]_i_2 ; input [3:0]Q; input \r_data[6]_i_4_0 ; input [2:0]\r_data[4]_i_5_0 ; input rx_mof; input [4:0]\read_counter_q_reg[0] ; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [8:0]D; wire [0:0]DIADI; wire [3:0]Q; wire [0:0]WEBWE; wire \adress[4] ; wire \adress[4]_0 ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire \frame_count_reg[3] ; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire [4:0]\g_ram_rst_false.ram_memory_reg_10 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire \g_ram_rst_false.ram_memory_reg_7 ; wire \g_ram_rst_false.ram_memory_reg_8 ; wire \g_ram_rst_false.ram_memory_reg_9 ; wire \mr_ctrl_out[settings_pex] ; wire \r_data[0]_i_2_0 ; wire \r_data[0]_i_2_1 ; wire \r_data[0]_i_2_2 ; wire \r_data[0]_i_2_n_0 ; wire \r_data[0]_i_5_n_0 ; wire \r_data[0]_i_9_n_0 ; wire \r_data[10]_i_2__0 ; wire \r_data[11]_i_2__0_0 ; wire \r_data[11]_i_2__0_n_0 ; wire \r_data[11]_i_5_n_0 ; wire \r_data[12]_i_2 ; wire \r_data[13]_i_2 ; wire \r_data[14]_i_5_0 ; wire \r_data[14]_i_8_n_0 ; wire \r_data[15]_i_6 ; wire \r_data[21]_i_2 ; wire [0:0]\r_data[21]_i_2_0 ; wire [1:0]\r_data[23]_i_2 ; wire \r_data[24]_i_2_n_0 ; wire \r_data[26]_i_3_n_0 ; wire \r_data[27]_i_3_n_0 ; wire \r_data[28]_i_2_n_0 ; wire \r_data[29]_i_2_n_0 ; wire \r_data[30]_i_2_n_0 ; wire \r_data[31]_i_3_n_0 ; wire \r_data[4]_i_2 ; wire \r_data[4]_i_2_0 ; wire [2:0]\r_data[4]_i_5_0 ; wire \r_data[4]_i_9_n_0 ; wire \r_data[5]_i_2 ; wire \r_data[5]_i_9_n_0 ; wire \r_data[6]_i_12_n_0 ; wire \r_data[6]_i_2 ; wire \r_data[6]_i_4_0 ; wire \r_data[7]_i_2__0 ; wire \r_data[7]_i_8_n_0 ; wire \r_data[8]_i_2 ; wire \r_data[9]_i_2__0 ; wire \r_data_reg[0] ; wire \r_data_reg[0]_0 ; wire \r_data_reg[0]_1 ; wire \r_data_reg[11] ; wire \r_data_reg[11]_0 ; wire \r_data_reg[11]_1 ; wire \r_data_reg[11]_2 ; wire \r_data_reg[11]_3 ; wire \r_data_reg[11]_4 ; wire \r_data_reg[14]_i_2 ; wire \r_data_reg[24] ; wire \r_data_reg[24]_0 ; wire \r_data_reg[24]_1 ; wire \r_data_reg[26] ; wire \r_data_reg[26]_0 ; wire \r_data_reg[26]_1 ; wire \r_data_reg[26]_2 ; wire \r_data_reg[27] ; wire \r_data_reg[27]_0 ; wire \r_data_reg[27]_1 ; wire \r_data_reg[28] ; wire \r_data_reg[28]_0 ; wire \r_data_reg[28]_1 ; wire \r_data_reg[28]_2 ; wire \r_data_reg[29] ; wire \r_data_reg[29]_0 ; wire \r_data_reg[30] ; wire \r_data_reg[30]_0 ; wire \r_data_reg[31] ; wire \r_data_reg[31]_0 ; wire \r_data_reg[6]_i_10_n_0 ; wire [4:0]\read_counter_q_reg[0] ; wire rx_mof; wire [30:0]rxb_port_a_data_in_i; wire [0:0]rxb_port_b_data_out; wire [31:0]rxb_port_b_data_out_i; wire [2:0]sbe_IBUF; wire soft_res_d_n; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED ; (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d32" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d32" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "1024" *) (* RTL_RAM_NAME = "i_rxb_top/i_rxb_ram/i_dp_inf_ram/g_ram_rst_false.ram_memory_reg" *) (* RTL_RAM_STYLE = "auto" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "480" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "31" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \g_ram_rst_false.ram_memory_reg (.ADDRARDADDR({1'b1,1'b1,1'b1,1'b1,ADDRARDADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk_sys_IBUF_BUFG), .CLKBWRCLK(clk_sys_IBUF_BUFG), .DIADI({rxb_port_a_data_in_i[14],DIADI,rxb_port_a_data_in_i[13:0]}), .DIBDI(rxb_port_a_data_in_i[30:15]), .DIPADIP({1'b1,1'b1}), .DIPBDIP({1'b1,1'b1}), .DOADO(rxb_port_b_data_out_i[15:0]), .DOBDO(rxb_port_b_data_out_i[31:16]), .DOPADOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(1'b1), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE({WEBWE,WEBWE,WEBWE,WEBWE})); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[0]_i_1 (.I0(sbe_IBUF[0]), .I1(\r_data[0]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[0] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[0])); LUT6 #( .INIT(64'h000000000000AAEA)) \r_data[0]_i_2 (.I0(\r_data_reg[0]_0 ), .I1(soft_res_d_n), .I2(adress_IBUF[0]), .I3(adress_IBUF[2]), .I4(\r_data[0]_i_5_n_0 ), .I5(\r_data_reg[0]_1 ), .O(\r_data[0]_i_2_n_0 )); LUT6 #( .INIT(64'h00CA00CAFFFF00CA)) \r_data[0]_i_5 (.I0(\r_data[0]_i_9_n_0 ), .I1(\r_data[0]_i_2_1 ), .I2(adress_IBUF[2]), .I3(\r_data[0]_i_2_0 ), .I4(\r_data[0]_i_2_2 ), .I5(\r_data_reg[11]_3 ), .O(\r_data[0]_i_5_n_0 )); LUT5 #( .INIT(32'h2FC020C0)) \r_data[0]_i_9 (.I0(rxb_port_b_data_out_i[0]), .I1(\r_data_reg[28]_2 ), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data[4]_i_5_0 [0]), .O(\r_data[0]_i_9_n_0 )); LUT6 #( .INIT(64'hBBBB8BBBBBBBBBBB)) \r_data[10]_i_5 (.I0(\r_data[10]_i_2__0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data_reg[28]_2 ), .I5(rxb_port_b_data_out_i[10]), .O(\g_ram_rst_false.ram_memory_reg_2 )); LUT6 #( .INIT(64'h00008A880A0A8A88)) \r_data[11]_i_1 (.I0(sbe_IBUF[1]), .I1(\r_data[11]_i_2__0_n_0 ), .I2(\r_data_reg[11] ), .I3(\r_data_reg[11]_0 ), .I4(adress_IBUF[5]), .I5(\r_data_reg[11]_1 ), .O(D[1])); LUT6 #( .INIT(64'h5D5D0C0C0CFF0C0C)) \r_data[11]_i_2__0 (.I0(\r_data[11]_i_5_n_0 ), .I1(\r_data_reg[11]_2 ), .I2(\r_data_reg[11]_3 ), .I3(\r_data_reg[11]_4 ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(\r_data[11]_i_2__0_n_0 )); LUT6 #( .INIT(64'hBBBB8BBBBBBBBBBB)) \r_data[11]_i_5 (.I0(\r_data[11]_i_2__0_0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data_reg[28]_2 ), .I5(rxb_port_b_data_out_i[11]), .O(\r_data[11]_i_5_n_0 )); LUT6 #( .INIT(64'h00FF001000000010)) \r_data[12]_i_5 (.I0(\r_data[15]_i_6 ), .I1(\r_data_reg[28]_2 ), .I2(rxb_port_b_data_out_i[12]), .I3(\r_data[0]_i_2_0 ), .I4(adress_IBUF[2]), .I5(\r_data[12]_i_2 ), .O(\g_ram_rst_false.ram_memory_reg_3 )); LUT6 #( .INIT(64'h00FF001000000010)) \r_data[13]_i_6 (.I0(\r_data[15]_i_6 ), .I1(\r_data_reg[28]_2 ), .I2(rxb_port_b_data_out_i[13]), .I3(\r_data[0]_i_2_0 ), .I4(adress_IBUF[2]), .I5(\r_data[13]_i_2 ), .O(\g_ram_rst_false.ram_memory_reg_4 )); LUT6 #( .INIT(64'hA3AFAFAFAFAFAFAF)) \r_data[14]_i_5 (.I0(\r_data[14]_i_8_n_0 ), .I1(adress_IBUF[0]), .I2(adress_IBUF[3]), .I3(adress_IBUF[1]), .I4(adress_IBUF[2]), .I5(\r_data_reg[14]_i_2 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'hBBBB8BBBBBBBBBBB)) \r_data[14]_i_8 (.I0(\r_data[14]_i_5_0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data_reg[28]_2 ), .I5(rxb_port_b_data_out_i[14]), .O(\r_data[14]_i_8_n_0 )); LUT6 #( .INIT(64'h5FFF5FFF4FFF5FFF)) \r_data[15]_i_9 (.I0(adress_IBUF[2]), .I1(\r_data[15]_i_6 ), .I2(adress_IBUF[4]), .I3(adress_IBUF[3]), .I4(rxb_port_b_data_out_i[15]), .I5(\r_data_reg[28]_2 ), .O(\g_ram_rst_false.ram_memory_reg_6 )); LUT5 #( .INIT(32'hAAAAAAA8)) \r_data[16]_i_9 (.I0(rxb_port_b_data_out_i[16]), .I1(Q[0]), .I2(Q[2]), .I3(Q[1]), .I4(Q[3]), .O(rxb_port_b_data_out)); LUT6 #( .INIT(64'h200000AA20000000)) \r_data[21]_i_5 (.I0(\r_data[21]_i_2 ), .I1(\r_data_reg[28]_2 ), .I2(rxb_port_b_data_out_i[21]), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\r_data[21]_i_2_0 ), .O(\g_ram_rst_false.ram_memory_reg_5 )); LUT5 #( .INIT(32'hAAEFFFEF)) \r_data[22]_i_5 (.I0(\r_data_reg[28]_1 ), .I1(\r_data_reg[28]_2 ), .I2(rxb_port_b_data_out_i[22]), .I3(adress_IBUF[2]), .I4(\r_data[23]_i_2 [0]), .O(\g_ram_rst_false.ram_memory_reg_7 )); LUT5 #( .INIT(32'hAAEFFFEF)) \r_data[23]_i_5 (.I0(\r_data_reg[28]_1 ), .I1(\r_data_reg[28]_2 ), .I2(rxb_port_b_data_out_i[23]), .I3(adress_IBUF[2]), .I4(\r_data[23]_i_2 [1]), .O(\g_ram_rst_false.ram_memory_reg_8 )); LUT6 #( .INIT(64'h008A008A008AAA8A)) \r_data[24]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data[24]_i_2_n_0 ), .I2(\r_data_reg[24] ), .I3(adress_IBUF[5]), .I4(\r_data_reg[24]_0 ), .I5(\r_data_reg[11] ), .O(D[2])); LUT6 #( .INIT(64'h4F444F4F4F444F44)) \r_data[24]_i_2 (.I0(\r_data_reg[24]_1 ), .I1(\mr_ctrl_out[settings_pex] ), .I2(\r_data_reg[28]_1 ), .I3(adress_IBUF[2]), .I4(\r_data_reg[28]_2 ), .I5(rxb_port_b_data_out_i[24]), .O(\r_data[24]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000155555555)) \r_data[25]_i_5 (.I0(adress_IBUF[2]), .I1(Q[3]), .I2(Q[1]), .I3(Q[2]), .I4(Q[0]), .I5(rxb_port_b_data_out_i[25]), .O(\frame_count_reg[3] )); LUT6 #( .INIT(64'h8A888A8A8A888A88)) \r_data[26]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data_reg[26] ), .I2(adress_IBUF[5]), .I3(\r_data[26]_i_3_n_0 ), .I4(\r_data_reg[26]_0 ), .I5(\r_data_reg[26]_1 ), .O(D[3])); LUT6 #( .INIT(64'h4544FFFF45444544)) \r_data[26]_i_3 (.I0(\r_data_reg[28]_1 ), .I1(adress_IBUF[2]), .I2(\r_data_reg[28]_2 ), .I3(rxb_port_b_data_out_i[26]), .I4(\r_data_reg[24]_1 ), .I5(\r_data_reg[26]_2 ), .O(\r_data[26]_i_3_n_0 )); LUT6 #( .INIT(64'h8A888A8A8A888A88)) \r_data[27]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data_reg[27] ), .I2(adress_IBUF[5]), .I3(\r_data[27]_i_3_n_0 ), .I4(\r_data_reg[27]_0 ), .I5(\r_data_reg[26]_1 ), .O(D[4])); LUT6 #( .INIT(64'h4544FFFF45444544)) \r_data[27]_i_3 (.I0(\r_data_reg[28]_1 ), .I1(adress_IBUF[2]), .I2(\r_data_reg[28]_2 ), .I3(rxb_port_b_data_out_i[27]), .I4(\r_data_reg[24]_1 ), .I5(\r_data_reg[27]_1 ), .O(\r_data[27]_i_3_n_0 )); LUT6 #( .INIT(64'h88888888888A8888)) \r_data[28]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data[28]_i_2_n_0 ), .I2(\r_data_reg[28] ), .I3(adress_IBUF[5]), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[5])); LUT6 #( .INIT(64'hABABABABAAAAABAA)) \r_data[28]_i_2 (.I0(\r_data_reg[28]_0 ), .I1(\r_data_reg[28]_1 ), .I2(adress_IBUF[5]), .I3(rxb_port_b_data_out_i[28]), .I4(\r_data_reg[28]_2 ), .I5(adress_IBUF[2]), .O(\r_data[28]_i_2_n_0 )); LUT6 #( .INIT(64'h88888888888A8888)) \r_data[29]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data[29]_i_2_n_0 ), .I2(\r_data_reg[29] ), .I3(adress_IBUF[5]), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[6])); LUT6 #( .INIT(64'hABABABABAAAAABAA)) \r_data[29]_i_2 (.I0(\r_data_reg[29]_0 ), .I1(\r_data_reg[28]_1 ), .I2(adress_IBUF[5]), .I3(rxb_port_b_data_out_i[29]), .I4(\r_data_reg[28]_2 ), .I5(adress_IBUF[2]), .O(\r_data[29]_i_2_n_0 )); LUT6 #( .INIT(64'h22FFF0002200F000)) \r_data[2]_i_7 (.I0(rxb_port_b_data_out_i[2]), .I1(\r_data_reg[28]_2 ), .I2(rx_mof), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\r_data[4]_i_5_0 [1]), .O(\g_ram_rst_false.ram_memory_reg_9 )); LUT6 #( .INIT(64'h88888888888A8888)) \r_data[30]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data[30]_i_2_n_0 ), .I2(\r_data_reg[30] ), .I3(adress_IBUF[5]), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[7])); LUT6 #( .INIT(64'hFFFFFFFF00000100)) \r_data[30]_i_2 (.I0(adress_IBUF[5]), .I1(adress_IBUF[2]), .I2(\r_data_reg[28]_1 ), .I3(rxb_port_b_data_out_i[30]), .I4(\r_data_reg[28]_2 ), .I5(\r_data_reg[30]_0 ), .O(\r_data[30]_i_2_n_0 )); LUT6 #( .INIT(64'h88888888888A8888)) \r_data[31]_i_2 (.I0(sbe_IBUF[2]), .I1(\r_data[31]_i_3_n_0 ), .I2(\r_data_reg[31] ), .I3(adress_IBUF[5]), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[8])); LUT6 #( .INIT(64'hFFFFFFFF00000100)) \r_data[31]_i_3 (.I0(adress_IBUF[5]), .I1(adress_IBUF[2]), .I2(\r_data_reg[28]_1 ), .I3(rxb_port_b_data_out_i[31]), .I4(\r_data_reg[28]_2 ), .I5(\r_data_reg[31]_0 ), .O(\r_data[31]_i_3_n_0 )); LUT6 #( .INIT(64'h00CA00CAFFFF00CA)) \r_data[4]_i_5 (.I0(\r_data[4]_i_9_n_0 ), .I1(\r_data[4]_i_2 ), .I2(adress_IBUF[2]), .I3(\r_data[0]_i_2_0 ), .I4(\r_data[4]_i_2_0 ), .I5(\r_data_reg[11]_3 ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'h22FFF0002200F000)) \r_data[4]_i_9 (.I0(rxb_port_b_data_out_i[4]), .I1(\r_data_reg[28]_2 ), .I2(Q[0]), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\r_data[4]_i_5_0 [2]), .O(\r_data[4]_i_9_n_0 )); LUT5 #( .INIT(32'h0C00BBBB)) \r_data[5]_i_9 (.I0(Q[1]), .I1(adress_IBUF[1]), .I2(\r_data_reg[28]_2 ), .I3(rxb_port_b_data_out_i[5]), .I4(adress_IBUF[0]), .O(\r_data[5]_i_9_n_0 )); LUT5 #( .INIT(32'hF757F7F7)) \r_data[6]_i_12 (.I0(adress_IBUF[1]), .I1(Q[2]), .I2(adress_IBUF[0]), .I3(\r_data_reg[28]_2 ), .I4(rxb_port_b_data_out_i[6]), .O(\r_data[6]_i_12_n_0 )); LUT6 #( .INIT(64'h8BBBBBBBBBBBBBBB)) \r_data[6]_i_4 (.I0(\r_data_reg[6]_i_10_n_0 ), .I1(adress_IBUF[3]), .I2(\r_data[6]_i_2 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(adress_IBUF[2]), .O(\g_bit[0].reg_value_r_reg[0] )); LUT5 #( .INIT(32'hF757F7F7)) \r_data[7]_i_8 (.I0(adress_IBUF[1]), .I1(Q[3]), .I2(adress_IBUF[0]), .I3(\r_data_reg[28]_2 ), .I4(rxb_port_b_data_out_i[7]), .O(\r_data[7]_i_8_n_0 )); LUT6 #( .INIT(64'hBBBB8BBBBBBBBBBB)) \r_data[8]_i_5 (.I0(\r_data[8]_i_2 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data_reg[28]_2 ), .I5(rxb_port_b_data_out_i[8]), .O(\g_ram_rst_false.ram_memory_reg_0 )); LUT6 #( .INIT(64'hBBBB8BBBBBBBBBBB)) \r_data[9]_i_5 (.I0(\r_data[9]_i_2__0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data_reg[28]_2 ), .I5(rxb_port_b_data_out_i[9]), .O(\g_ram_rst_false.ram_memory_reg_1 )); MUXF7 \r_data_reg[5]_i_5 (.I0(\r_data[5]_i_9_n_0 ), .I1(\r_data[5]_i_2 ), .O(\adress[4]_0 ), .S(adress_IBUF[2])); MUXF7 \r_data_reg[6]_i_10 (.I0(\r_data[6]_i_12_n_0 ), .I1(\r_data[6]_i_4_0 ), .O(\r_data_reg[6]_i_10_n_0 ), .S(adress_IBUF[2])); MUXF7 \r_data_reg[7]_i_5 (.I0(\r_data[7]_i_8_n_0 ), .I1(\r_data[7]_i_2__0 ), .O(\adress[4] ), .S(adress_IBUF[2])); LUT6 #( .INIT(64'h00FF00FF00FF00FE)) \read_counter_q[0]_i_1 (.I0(\read_counter_q_reg[0] [4]), .I1(\read_counter_q_reg[0] [2]), .I2(\read_counter_q_reg[0] [1]), .I3(\read_counter_q_reg[0] [0]), .I4(\read_counter_q_reg[0] [3]), .I5(rxb_port_b_data_out_i[11]), .O(\g_ram_rst_false.ram_memory_reg_10 [0])); LUT6 #( .INIT(64'hF00FF00FF00FF00E)) \read_counter_q[1]_i_1 (.I0(\read_counter_q_reg[0] [4]), .I1(\read_counter_q_reg[0] [2]), .I2(\read_counter_q_reg[0] [1]), .I3(\read_counter_q_reg[0] [0]), .I4(\read_counter_q_reg[0] [3]), .I5(rxb_port_b_data_out_i[12]), .O(\g_ram_rst_false.ram_memory_reg_10 [1])); LUT6 #( .INIT(64'hA9A9A9A9A9A9A9A8)) \read_counter_q[2]_i_1 (.I0(\read_counter_q_reg[0] [2]), .I1(\read_counter_q_reg[0] [1]), .I2(\read_counter_q_reg[0] [0]), .I3(rxb_port_b_data_out_i[13]), .I4(\read_counter_q_reg[0] [4]), .I5(\read_counter_q_reg[0] [3]), .O(\g_ram_rst_false.ram_memory_reg_10 [2])); LUT6 #( .INIT(64'hAAA9AAA9AAA9AAA8)) \read_counter_q[3]_i_1 (.I0(\read_counter_q_reg[0] [3]), .I1(\read_counter_q_reg[0] [0]), .I2(\read_counter_q_reg[0] [1]), .I3(\read_counter_q_reg[0] [2]), .I4(\read_counter_q_reg[0] [4]), .I5(rxb_port_b_data_out_i[14]), .O(\g_ram_rst_false.ram_memory_reg_10 [3])); LUT6 #( .INIT(64'hFFFFFFFC00000002)) \read_counter_q[4]_i_1 (.I0(rxb_port_b_data_out_i[15]), .I1(\read_counter_q_reg[0] [3]), .I2(\read_counter_q_reg[0] [0]), .I3(\read_counter_q_reg[0] [1]), .I4(\read_counter_q_reg[0] [2]), .I5(\read_counter_q_reg[0] [4]), .O(\g_ram_rst_false.ram_memory_reg_10 [4])); endmodule module dp_inf_ram_be (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, swr_IBUF, scs_IBUF, adress_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input swr_IBUF; input scs_IBUF; input [3:0]adress_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED ; (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "672" *) (* RTL_RAM_NAME = "g_txt_buf_comp[3].g_txt_buf_odd.i_txtb_odd_top/i_txtb_ram/i_dp_inf_ram_be/g_ram_rst_false.ram_memory_reg" *) (* RTL_RAM_STYLE = "auto" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "20" *) (* ram_offset = "480" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "31" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \g_ram_rst_false.ram_memory_reg (.ADDRARDADDR({1'b1,1'b1,1'b1,1'b1,ADDRARDADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk_sys_IBUF_BUFG), .CLKBWRCLK(clk_sys_IBUF_BUFG), .DIADI(DIADI), .DIBDI(DIBDI), .DIPADIP({1'b1,1'b1}), .DIPBDIP({1'b1,1'b1}), .DOADO(txtb_port_b_data_out_i[15:0]), .DOBDO(txtb_port_b_data_out_i[31:16]), .DOPADOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(1'b1), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE(WEBWE)); LUT6 #( .INIT(64'h0000000000000800)) \g_ram_rst_false.ram_memory_reg_i_49__0 (.I0(swr_IBUF), .I1(scs_IBUF), .I2(adress_IBUF[1]), .I3(adress_IBUF[2]), .I4(adress_IBUF[3]), .I5(adress_IBUF[0]), .O(txtb_port_a_cs)); endmodule (* ORIG_REF_NAME = "dp_inf_ram_be" *) module dp_inf_ram_be_87 (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, adress_IBUF, swr_IBUF, scs_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input [3:0]adress_IBUF; input swr_IBUF; input scs_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED ; (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "672" *) (* RTL_RAM_NAME = "g_txt_buf_comp[2].g_txt_buf_even.i_txtb_even_top/i_txtb_ram/i_dp_inf_ram_be/g_ram_rst_false.ram_memory_reg" *) (* RTL_RAM_STYLE = "auto" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "20" *) (* ram_offset = "480" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "31" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \g_ram_rst_false.ram_memory_reg (.ADDRARDADDR({1'b1,1'b1,1'b1,1'b1,ADDRARDADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk_sys_IBUF_BUFG), .CLKBWRCLK(clk_sys_IBUF_BUFG), .DIADI(DIADI), .DIBDI(DIBDI), .DIPADIP({1'b1,1'b1}), .DIPBDIP({1'b1,1'b1}), .DOADO(txtb_port_b_data_out_i[15:0]), .DOBDO(txtb_port_b_data_out_i[31:16]), .DOPADOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(1'b1), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE(WEBWE)); LUT6 #( .INIT(64'h1000000000000000)) \g_ram_rst_false.ram_memory_reg_i_49__1 (.I0(adress_IBUF[3]), .I1(adress_IBUF[2]), .I2(adress_IBUF[0]), .I3(swr_IBUF), .I4(scs_IBUF), .I5(adress_IBUF[1]), .O(txtb_port_a_cs)); endmodule (* ORIG_REF_NAME = "dp_inf_ram_be" *) module dp_inf_ram_be_89 (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, swr_IBUF, scs_IBUF, adress_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input swr_IBUF; input scs_IBUF; input [3:0]adress_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED ; (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "672" *) (* RTL_RAM_NAME = "g_txt_buf_comp[1].g_txt_buf_odd.i_txtb_odd_top/i_txtb_ram/i_dp_inf_ram_be/g_ram_rst_false.ram_memory_reg" *) (* RTL_RAM_STYLE = "auto" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "20" *) (* ram_offset = "480" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "31" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \g_ram_rst_false.ram_memory_reg (.ADDRARDADDR({1'b1,1'b1,1'b1,1'b1,ADDRARDADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk_sys_IBUF_BUFG), .CLKBWRCLK(clk_sys_IBUF_BUFG), .DIADI(DIADI), .DIBDI(DIBDI), .DIPADIP({1'b1,1'b1}), .DIPBDIP({1'b1,1'b1}), .DOADO(txtb_port_b_data_out_i[15:0]), .DOBDO(txtb_port_b_data_out_i[31:16]), .DOPADOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(1'b1), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE(WEBWE)); LUT6 #( .INIT(64'h0000000000000080)) \g_ram_rst_false.ram_memory_reg_i_49 (.I0(swr_IBUF), .I1(scs_IBUF), .I2(adress_IBUF[1]), .I3(adress_IBUF[3]), .I4(adress_IBUF[0]), .I5(adress_IBUF[2]), .O(txtb_port_a_cs)); endmodule (* ORIG_REF_NAME = "dp_inf_ram_be" *) module dp_inf_ram_be_91 (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, swr_IBUF, scs_IBUF, adress_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input swr_IBUF; input scs_IBUF; input [3:0]adress_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED ; wire [1:0]\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED ; (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "672" *) (* RTL_RAM_NAME = "g_txt_buf_comp[0].g_txt_buf_even.i_txtb_even_top/i_txtb_ram/i_dp_inf_ram_be/g_ram_rst_false.ram_memory_reg" *) (* RTL_RAM_STYLE = "auto" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "20" *) (* ram_offset = "480" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "31" *) RAMB18E1 #( .DOA_REG(0), .DOB_REG(0), .INIT_A(18'h00000), .INIT_B(18'h00000), .RAM_MODE("SDP"), .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), .READ_WIDTH_A(36), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SIM_DEVICE("7SERIES"), .SRVAL_A(18'h00000), .SRVAL_B(18'h00000), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(36)) \g_ram_rst_false.ram_memory_reg (.ADDRARDADDR({1'b1,1'b1,1'b1,1'b1,ADDRARDADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1,1'b1,1'b1}), .CLKARDCLK(clk_sys_IBUF_BUFG), .CLKBWRCLK(clk_sys_IBUF_BUFG), .DIADI(DIADI), .DIBDI(DIBDI), .DIPADIP({1'b1,1'b1}), .DIPBDIP({1'b1,1'b1}), .DOADO(txtb_port_b_data_out_i[15:0]), .DOBDO(txtb_port_b_data_out_i[31:16]), .DOPADOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPADOP_UNCONNECTED [1:0]), .DOPBDOP(\NLW_g_ram_rst_false.ram_memory_reg_DOPBDOP_UNCONNECTED [1:0]), .ENARDEN(1'b1), .ENBWREN(1'b1), .REGCEAREGCE(1'b0), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(1'b0), .RSTREGB(1'b0), .WEA({1'b0,1'b0}), .WEBWE(WEBWE)); LUT6 #( .INIT(64'h0000000800000000)) \g_ram_rst_false.ram_memory_reg_i_50 (.I0(swr_IBUF), .I1(scs_IBUF), .I2(adress_IBUF[1]), .I3(adress_IBUF[3]), .I4(adress_IBUF[2]), .I5(adress_IBUF[0]), .O(txtb_port_a_cs)); endmodule module ff_top (ident_valid_q, ident_valid_q_reg_0, ident_valid_q_reg_1, clk_sys_IBUF_BUFG, ident_valid_q_reg_2, rec_abort, commit_overrun_abort, \mr_ctrl_out[mode_erfm] ); output ident_valid_q; output ident_valid_q_reg_0; output ident_valid_q_reg_1; input clk_sys_IBUF_BUFG; input ident_valid_q_reg_2; input rec_abort; input commit_overrun_abort; input \mr_ctrl_out[mode_erfm] ; wire clk_sys_IBUF_BUFG; wire commit_overrun_abort; wire ident_valid_q; wire ident_valid_q_reg_0; wire ident_valid_q_reg_1; wire ident_valid_q_reg_2; wire \mr_ctrl_out[mode_erfm] ; wire rec_abort; (* SOFT_HLUTNM = "soft_lutpair124" *) LUT3 #( .INIT(8'h7F)) \FSM_onehot_curr_state[1]_i_3 (.I0(ident_valid_q), .I1(rec_abort), .I2(\mr_ctrl_out[mode_erfm] ), .O(ident_valid_q_reg_1)); FDCE ident_valid_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(ident_valid_q_reg_2), .D(1'b1), .Q(ident_valid_q)); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT3 #( .INIT(8'h07)) \rx_mem_free_raw[5]_i_5 (.I0(ident_valid_q), .I1(rec_abort), .I2(commit_overrun_abort), .O(ident_valid_q_reg_0)); endmodule module im_channel (int_status_reg_0, mr_int_stat_rxi_o, mr_int_ena_set_int_ena_set_o, adress_IBUF, int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_mask_i_reg_3, rec_valid, int_status_reg_1, int_ena_i_reg_0, int_ena_i_reg_1); output int_status_reg_0; output mr_int_stat_rxi_o; output [0:0]mr_int_ena_set_int_ena_set_o; input [2:0]adress_IBUF; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_mask_i_reg_3; input rec_valid; input int_status_reg_1; input int_ena_i_reg_0; input int_ena_i_reg_1; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_mask_i_reg_3; wire int_status_i_1_n_0; wire int_status_reg_0; wire int_status_reg_1; wire [0:0]mr_int_ena_set_int_ena_set_o; wire [0:0]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_rxi_o; wire rec_valid; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_0), .I1(int_ena_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'hFFFF4FFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(rec_valid), .I2(int_status_reg_1), .I3(data_in_IBUF), .I4(int_mask_i_reg_2), .I5(mr_int_stat_rxi_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_status_i_1_n_0), .Q(mr_int_stat_rxi_o)); LUT6 #( .INIT(64'h5F5F57F7FFFF57F7)) \r_data[0]_i_8 (.I0(adress_IBUF[2]), .I1(mr_int_stat_rxi_o), .I2(adress_IBUF[0]), .I3(mr_int_ena_set_int_ena_set_o), .I4(adress_IBUF[1]), .I5(mr_int_mask_set_int_mask_set_o), .O(int_status_reg_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_70 (D, mr_int_ena_set_int_ena_set_o, mr_int_stat_rbnei_o, sbe_IBUF, adress_IBUF, \r_data_reg[10] , \r_data_reg[10]_0 , \r_data_reg[10]_1 , \r_data_reg[10]_2 , \r_data[10]_i_2__0_0 , \mr_ctrl_out[mode_txbbm] , int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_mask_i_reg_3, int_status_reg_0, int_status_reg_1, int_ena_i_reg_0, int_ena_i_reg_1); output [0:0]D; output [0:0]mr_int_ena_set_int_ena_set_o; output mr_int_stat_rbnei_o; input [0:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[10] ; input \r_data_reg[10]_0 ; input \r_data_reg[10]_1 ; input \r_data_reg[10]_2 ; input \r_data[10]_i_2__0_0 ; input \mr_ctrl_out[mode_txbbm] ; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_mask_i_reg_3; input int_status_reg_0; input int_status_reg_1; input int_ena_i_reg_0; input int_ena_i_reg_1; wire [0:0]D; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_mask_i_reg_3; wire int_status_i_1_n_0; wire int_status_reg_0; wire int_status_reg_1; wire \mr_ctrl_out[mode_txbbm] ; wire [0:0]mr_int_ena_set_int_ena_set_o; wire [10:10]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_rbnei_o; wire \r_data[10]_i_10_n_0 ; wire \r_data[10]_i_2__0_0 ; wire \r_data[10]_i_2__0_n_0 ; wire \r_data[10]_i_7_n_0 ; wire \r_data_reg[10] ; wire \r_data_reg[10]_0 ; wire \r_data_reg[10]_1 ; wire \r_data_reg[10]_2 ; wire \r_data_reg[10]_i_4_n_0 ; wire [0:0]sbe_IBUF; LUT5 #( .INIT(32'hDFFF5000)) int_ena_i_i_1 (.I0(int_ena_i_reg_0), .I1(int_ena_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hDFFF5000)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'h1FFFFFFF11111111)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(int_status_reg_0), .I2(int_status_reg_1), .I3(data_in_IBUF), .I4(int_mask_i_reg_2), .I5(mr_int_stat_rbnei_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_status_i_1_n_0), .Q(mr_int_stat_rbnei_o)); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[10]_i_1 (.I0(sbe_IBUF), .I1(\r_data[10]_i_2__0_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[10] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D)); LUT5 #( .INIT(32'hB833B800)) \r_data[10]_i_10 (.I0(mr_int_mask_set_int_mask_set_o), .I1(adress_IBUF[1]), .I2(mr_int_ena_set_int_ena_set_o), .I3(adress_IBUF[0]), .I4(mr_int_stat_rbnei_o), .O(\r_data[10]_i_10_n_0 )); LUT6 #( .INIT(64'hF351F3510051F351)) \r_data[10]_i_2__0 (.I0(\r_data_reg[10]_i_4_n_0 ), .I1(\r_data_reg[10]_0 ), .I2(\r_data_reg[10]_1 ), .I3(adress_IBUF[4]), .I4(adress_IBUF[3]), .I5(\r_data_reg[10]_2 ), .O(\r_data[10]_i_2__0_n_0 )); LUT5 #( .INIT(32'h8B888888)) \r_data[10]_i_7 (.I0(\r_data[10]_i_10_n_0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[mode_txbbm] ), .I4(adress_IBUF[0]), .O(\r_data[10]_i_7_n_0 )); MUXF7 \r_data_reg[10]_i_4 (.I0(\r_data[10]_i_7_n_0 ), .I1(\r_data[10]_i_2__0_0 ), .O(\r_data_reg[10]_i_4_n_0 ), .S(adress_IBUF[3])); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_71 (mr_int_stat_txbhci_o, \adress[6] , \adress[4] , \adress[2] , \g_bit[0].reg_value_r_reg[0] , int_mask_i_reg_0, int_status_reg_0, int_status_reg_1, clk_sys_IBUF_BUFG, int_ena_i_reg_0, adress_IBUF, int_status_reg_2, int_status_reg_3, \mr_ctrl_out[mode_sam] , reg_q_reg, mr_int_stat_rbnei_o, mr_int_stat_bsi_o, int_mask_i_reg_1, int_mask_i_reg_2, data_in_IBUF, int_mask_i_reg_3); output mr_int_stat_txbhci_o; output \adress[6] ; output \adress[4] ; output \adress[2] ; output \g_bit[0].reg_value_r_reg[0] ; output [0:0]int_mask_i_reg_0; output int_status_reg_0; input int_status_reg_1; input clk_sys_IBUF_BUFG; input int_ena_i_reg_0; input [5:0]adress_IBUF; input int_status_reg_2; input int_status_reg_3; input \mr_ctrl_out[mode_sam] ; input [1:0]reg_q_reg; input mr_int_stat_rbnei_o; input mr_int_stat_bsi_o; input int_mask_i_reg_1; input int_mask_i_reg_2; input [0:0]data_in_IBUF; input int_mask_i_reg_3; wire \adress[2] ; wire \adress[4] ; wire \adress[6] ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0] ; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_mask_i_i_1_n_0; wire [0:0]int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_mask_i_reg_3; wire int_status_reg_0; wire int_status_reg_1; wire int_status_reg_2; wire int_status_reg_3; wire \mr_ctrl_out[mode_sam] ; wire [11:11]mr_int_ena_set_int_ena_set_o; wire mr_int_stat_bsi_o; wire mr_int_stat_rbnei_o; wire mr_int_stat_txbhci_o; wire \r_data[11]_i_7_n_0 ; wire [1:0]reg_q_reg; LUT5 #( .INIT(32'hDFFF5000)) int_ena_i_i_1 (.I0(\adress[6] ), .I1(\adress[2] ), .I2(data_in_IBUF), .I3(int_mask_i_reg_3), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFEFFFFFF)) int_ena_i_i_2 (.I0(adress_IBUF[4]), .I1(adress_IBUF[3]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(adress_IBUF[5]), .O(\adress[6] )); LUT6 #( .INIT(64'hFFFEFFFFFFFFFFFF)) int_ena_i_i_3 (.I0(adress_IBUF[0]), .I1(adress_IBUF[5]), .I2(adress_IBUF[3]), .I3(adress_IBUF[4]), .I4(adress_IBUF[1]), .I5(adress_IBUF[2]), .O(\adress[2] )); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hDFFF5000)) int_mask_i_i_1 (.I0(int_mask_i_reg_1), .I1(int_mask_i_reg_2), .I2(data_in_IBUF), .I3(int_mask_i_reg_3), .I4(int_mask_i_reg_0), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_mask_i_i_1_n_0), .Q(int_mask_i_reg_0)); LUT6 #( .INIT(64'h0000000000000004)) int_status_i_2 (.I0(int_status_reg_2), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(int_status_reg_3), .I4(adress_IBUF[5]), .I5(adress_IBUF[0]), .O(\adress[4] )); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_status_reg_1), .Q(mr_int_stat_txbhci_o)); LUT5 #( .INIT(32'h8B888B8B)) \r_data[11]_i_3__0 (.I0(\r_data[11]_i_7_n_0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[mode_sam] ), .I4(adress_IBUF[0]), .O(\g_bit[0].reg_value_r_reg[0] )); LUT5 #( .INIT(32'hB833B800)) \r_data[11]_i_7 (.I0(int_mask_i_reg_0), .I1(adress_IBUF[1]), .I2(mr_int_ena_set_int_ena_set_o), .I3(adress_IBUF[0]), .I4(mr_int_stat_txbhci_o), .O(\r_data[11]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFF888F888F888)) reg_q_i_4 (.I0(mr_int_stat_txbhci_o), .I1(mr_int_ena_set_int_ena_set_o), .I2(mr_int_stat_rbnei_o), .I3(reg_q_reg[1]), .I4(reg_q_reg[0]), .I5(mr_int_stat_bsi_o), .O(int_status_reg_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_72 (data_overrun_flg_reg, swr, mr_int_ena_set_int_ena_set_o, mr_int_stat_txi_o, adress_IBUF, rx_data_overrun, \mr_ctrl_out[mode_bmm] , swr_IBUF, int_mask_i_reg_0, sbe_IBUF, int_mask_i_reg_1, int_mask_i_reg_2, data_in_IBUF, clk_sys_IBUF_BUFG, int_ena_i_reg_0, \txtb_hw_cmd[valid] , int_status_reg_0, int_ena_i_reg_1, int_ena_i_reg_2); output data_overrun_flg_reg; output swr; output [0:0]mr_int_ena_set_int_ena_set_o; output mr_int_stat_txi_o; input [2:0]adress_IBUF; input rx_data_overrun; input \mr_ctrl_out[mode_bmm] ; input swr_IBUF; input int_mask_i_reg_0; input [0:0]sbe_IBUF; input int_mask_i_reg_1; input int_mask_i_reg_2; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input int_ena_i_reg_0; input \txtb_hw_cmd[valid] ; input int_status_reg_0; input int_ena_i_reg_1; input int_ena_i_reg_2; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire data_overrun_flg_reg; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_ena_i_reg_2; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_status_i_1_n_0; wire int_status_reg_0; wire \mr_ctrl_out[mode_bmm] ; wire [0:0]mr_int_ena_set_int_ena_set_o; wire [1:1]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_txi_o; wire \r_data[1]_i_12_n_0 ; wire rx_data_overrun; wire [0:0]sbe_IBUF; wire swr; wire swr_IBUF; wire \txtb_hw_cmd[valid] ; LUT3 #( .INIT(8'hDF)) \g_bit[0].reg_value_r[0]_i_4 (.I0(swr_IBUF), .I1(int_mask_i_reg_0), .I2(sbe_IBUF), .O(swr)); LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_1), .I1(int_ena_i_reg_2), .I2(data_in_IBUF), .I3(swr), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_1), .I1(int_mask_i_reg_2), .I2(data_in_IBUF), .I3(swr), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'hFFFF4FFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(\txtb_hw_cmd[valid] ), .I2(int_status_reg_0), .I3(data_in_IBUF), .I4(swr), .I5(mr_int_stat_txi_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_status_i_1_n_0), .Q(mr_int_stat_txi_o)); LUT5 #( .INIT(32'h47CC47FF)) \r_data[1]_i_12 (.I0(mr_int_mask_set_int_mask_set_o), .I1(adress_IBUF[1]), .I2(mr_int_ena_set_int_ena_set_o), .I3(adress_IBUF[0]), .I4(mr_int_stat_txi_o), .O(\r_data[1]_i_12_n_0 )); LUT6 #( .INIT(64'hBB8B88BBBB8BBBBB)) \r_data[1]_i_7 (.I0(\r_data[1]_i_12_n_0 ), .I1(adress_IBUF[2]), .I2(rx_data_overrun), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\mr_ctrl_out[mode_bmm] ), .O(data_overrun_flg_reg)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_73 (\g_bit[0].reg_value_r_reg[0] , int_status_reg_0, \mr_ctrl_out[mode_stm] , adress_IBUF, \r_data[2]_i_5 , reg_q_reg, mr_int_stat_txi_o, mr_int_stat_rxi_o, int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_mask_i_reg_3, err_warning_limit_q, int_status_reg_1, int_status_reg_2, int_status_reg_3, int_ena_i_reg_0, int_ena_i_reg_1); output \g_bit[0].reg_value_r_reg[0] ; output int_status_reg_0; input \mr_ctrl_out[mode_stm] ; input [2:0]adress_IBUF; input \r_data[2]_i_5 ; input [1:0]reg_q_reg; input mr_int_stat_txi_o; input mr_int_stat_rxi_o; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_mask_i_reg_3; input err_warning_limit_q; input int_status_reg_1; input int_status_reg_2; input int_status_reg_3; input int_ena_i_reg_0; input int_ena_i_reg_1; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire err_warning_limit_q; wire \g_bit[0].reg_value_r_reg[0] ; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_mask_i_reg_3; wire int_status_i_1_n_0; wire int_status_reg_0; wire int_status_reg_1; wire int_status_reg_2; wire int_status_reg_3; wire \mr_ctrl_out[mode_stm] ; wire [2:2]mr_int_ena_set_int_ena_set_o; wire [2:2]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_ewli_o; wire mr_int_stat_rxi_o; wire mr_int_stat_txi_o; wire \r_data[2]_i_16_n_0 ; wire \r_data[2]_i_5 ; wire [1:0]reg_q_reg; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_0), .I1(int_ena_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'h41FFFFFF41414141)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(err_warning_limit_q), .I2(int_status_reg_1), .I3(int_status_reg_2), .I4(int_status_reg_3), .I5(mr_int_stat_ewli_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_status_i_1_n_0), .Q(mr_int_stat_ewli_o)); LUT6 #( .INIT(64'hFFFFFFFFAAAAFBAA)) \r_data[2]_i_12 (.I0(\r_data[2]_i_16_n_0 ), .I1(\mr_ctrl_out[mode_stm] ), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data[2]_i_5 ), .O(\g_bit[0].reg_value_r_reg[0] )); LUT6 #( .INIT(64'h00F05050F0F03030)) \r_data[2]_i_16 (.I0(mr_int_ena_set_int_ena_set_o), .I1(mr_int_stat_ewli_o), .I2(adress_IBUF[2]), .I3(mr_int_mask_set_int_mask_set_o), .I4(adress_IBUF[1]), .I5(adress_IBUF[0]), .O(\r_data[2]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFF888F888F888)) reg_q_i_3 (.I0(mr_int_stat_ewli_o), .I1(mr_int_ena_set_int_ena_set_o), .I2(mr_int_stat_txi_o), .I3(reg_q_reg[1]), .I4(reg_q_reg[0]), .I5(mr_int_stat_rxi_o), .O(int_status_reg_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_74 (\adress[5] , mr_int_stat_doi_o, mr_int_ena_set_int_ena_set_o, adress_IBUF, \r_data[3]_i_2 , \r_data_reg[3]_i_5_0 , \r_data_reg[3]_i_5_1 , int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_ena_i_reg_0, rx_data_overrun, int_status_reg_0, int_ena_i_reg_1, int_ena_i_reg_2); output \adress[5] ; output mr_int_stat_doi_o; output [0:0]mr_int_ena_set_int_ena_set_o; input [3:0]adress_IBUF; input \r_data[3]_i_2 ; input \r_data_reg[3]_i_5_0 ; input \r_data_reg[3]_i_5_1 ; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_ena_i_reg_0; input rx_data_overrun; input int_status_reg_0; input int_ena_i_reg_1; input int_ena_i_reg_2; wire \adress[5] ; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_ena_i_reg_2; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_status_i_1_n_0; wire int_status_reg_0; wire [0:0]mr_int_ena_set_int_ena_set_o; wire [3:3]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_doi_o; wire \r_data[3]_i_11_n_0 ; wire \r_data[3]_i_2 ; wire \r_data[3]_i_9_n_0 ; wire \r_data_reg[3]_i_5_0 ; wire \r_data_reg[3]_i_5_1 ; wire rx_data_overrun; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_1), .I1(int_ena_i_reg_2), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'hFFFF4FFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(rx_data_overrun), .I2(int_status_reg_0), .I3(data_in_IBUF), .I4(int_mask_i_reg_2), .I5(mr_int_stat_doi_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_status_i_1_n_0), .Q(mr_int_stat_doi_o)); LUT6 #( .INIT(64'h5F5F57F7FFFF57F7)) \r_data[3]_i_11 (.I0(adress_IBUF[2]), .I1(mr_int_stat_doi_o), .I2(adress_IBUF[0]), .I3(mr_int_ena_set_int_ena_set_o), .I4(adress_IBUF[1]), .I5(mr_int_mask_set_int_mask_set_o), .O(\r_data[3]_i_11_n_0 )); LUT6 #( .INIT(64'hA8AAA0A0A8AAA8A8)) \r_data[3]_i_9 (.I0(\r_data[3]_i_11_n_0 ), .I1(adress_IBUF[1]), .I2(adress_IBUF[2]), .I3(\r_data_reg[3]_i_5_0 ), .I4(adress_IBUF[0]), .I5(\r_data_reg[3]_i_5_1 ), .O(\r_data[3]_i_9_n_0 )); MUXF7 \r_data_reg[3]_i_5 (.I0(\r_data[3]_i_9_n_0 ), .I1(\r_data[3]_i_2 ), .O(\adress[5] ), .S(adress_IBUF[3])); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_75 (mr_int_stat_fcsi_o, int_mask_i_reg_0, int_mask_i_reg_1, mr_int_ena_set_int_ena_set_o, int_status_reg_0, clk_sys_IBUF_BUFG, int_mask_i_reg_2, adress_IBUF, int_mask_i_reg_3, int_mask_i_reg_4, data_in_IBUF, int_mask_i_reg_5, int_ena_i_reg_0, int_ena_i_reg_1); output mr_int_stat_fcsi_o; output int_mask_i_reg_0; output [0:0]int_mask_i_reg_1; output [0:0]mr_int_ena_set_int_ena_set_o; input int_status_reg_0; input clk_sys_IBUF_BUFG; input int_mask_i_reg_2; input [1:0]adress_IBUF; input int_mask_i_reg_3; input int_mask_i_reg_4; input [0:0]data_in_IBUF; input int_mask_i_reg_5; input int_ena_i_reg_0; input int_ena_i_reg_1; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire [0:0]int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_mask_i_reg_3; wire int_mask_i_reg_4; wire int_mask_i_reg_5; wire int_status_reg_0; wire [0:0]mr_int_ena_set_int_ena_set_o; wire mr_int_stat_fcsi_o; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_0), .I1(int_ena_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_5), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_2), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_3), .I1(int_mask_i_reg_4), .I2(data_in_IBUF), .I3(int_mask_i_reg_5), .I4(int_mask_i_reg_1), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_2), .D(int_mask_i_i_1_n_0), .Q(int_mask_i_reg_1)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_2), .D(int_status_reg_0), .Q(mr_int_stat_fcsi_o)); LUT5 #( .INIT(32'hB833B800)) \r_data[4]_i_12 (.I0(int_mask_i_reg_1), .I1(adress_IBUF[1]), .I2(mr_int_ena_set_int_ena_set_o), .I3(adress_IBUF[0]), .I4(mr_int_stat_fcsi_o), .O(int_mask_i_reg_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_76 (\g_bit[0].reg_value_r_reg[0] , int_i, adress_IBUF, \cc_stat[is_transmitter] , \mr_ctrl_out[mode_tttm] , reg_q_reg, reg_q_reg_0, reg_q_reg_1, reg_q_reg_2, mr_int_stat_fcsi_o, mr_int_stat_doi_o, int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_ena_i_reg_0, arbitration_lost, int_status_reg_0, int_ena_i_reg_1, int_ena_i_reg_2); output \g_bit[0].reg_value_r_reg[0] ; output int_i; input [2:0]adress_IBUF; input \cc_stat[is_transmitter] ; input \mr_ctrl_out[mode_tttm] ; input [1:0]reg_q_reg; input reg_q_reg_0; input reg_q_reg_1; input reg_q_reg_2; input mr_int_stat_fcsi_o; input mr_int_stat_doi_o; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_ena_i_reg_0; input arbitration_lost; input int_status_reg_0; input int_ena_i_reg_1; input int_ena_i_reg_2; wire [2:0]adress_IBUF; wire arbitration_lost; wire \cc_stat[is_transmitter] ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0] ; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_ena_i_reg_2; wire int_i; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_status_i_1_n_0; wire int_status_reg_0; wire \mr_ctrl_out[mode_tttm] ; wire [5:5]mr_int_ena_set_int_ena_set_o; wire [5:5]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_ali_o; wire mr_int_stat_doi_o; wire mr_int_stat_fcsi_o; wire \r_data[5]_i_12_n_0 ; wire reg_q_i_2__1_n_0; wire [1:0]reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_1), .I1(int_ena_i_reg_2), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'hFFFF4FFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(arbitration_lost), .I2(int_status_reg_0), .I3(data_in_IBUF), .I4(int_mask_i_reg_2), .I5(mr_int_stat_ali_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_status_i_1_n_0), .Q(mr_int_stat_ali_o)); LUT5 #( .INIT(32'hB833B800)) \r_data[5]_i_12 (.I0(mr_int_mask_set_int_mask_set_o), .I1(adress_IBUF[1]), .I2(mr_int_ena_set_int_ena_set_o), .I3(adress_IBUF[0]), .I4(mr_int_stat_ali_o), .O(\r_data[5]_i_12_n_0 )); LUT6 #( .INIT(64'h88BB8888B8BBB8BB)) \r_data[5]_i_7 (.I0(\r_data[5]_i_12_n_0 ), .I1(adress_IBUF[2]), .I2(\cc_stat[is_transmitter] ), .I3(adress_IBUF[1]), .I4(\mr_ctrl_out[mode_tttm] ), .I5(adress_IBUF[0]), .O(\g_bit[0].reg_value_r_reg[0] )); LUT4 #( .INIT(16'hFFFE)) reg_q_i_1__2 (.I0(reg_q_i_2__1_n_0), .I1(reg_q_reg_0), .I2(reg_q_reg_1), .I3(reg_q_reg_2), .O(int_i)); LUT6 #( .INIT(64'hFFFFF888F888F888)) reg_q_i_2__1 (.I0(mr_int_stat_ali_o), .I1(mr_int_ena_set_int_ena_set_o), .I2(mr_int_stat_fcsi_o), .I3(reg_q_reg[1]), .I4(reg_q_reg[0]), .I5(mr_int_stat_doi_o), .O(reg_q_i_2__1_n_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_77 (int_status_reg_0, mr_int_stat_bei_o, mr_int_ena_set_int_ena_set_o, adress_IBUF, int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_mask_i_reg_3, err_detected, int_status_reg_1, int_ena_i_reg_0, int_ena_i_reg_1); output int_status_reg_0; output mr_int_stat_bei_o; output [0:0]mr_int_ena_set_int_ena_set_o; input [2:0]adress_IBUF; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_mask_i_reg_3; input err_detected; input int_status_reg_1; input int_ena_i_reg_0; input int_ena_i_reg_1; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire err_detected; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_mask_i_reg_3; wire int_status_i_1_n_0; wire int_status_reg_0; wire int_status_reg_1; wire [0:0]mr_int_ena_set_int_ena_set_o; wire [6:6]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_bei_o; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_0), .I1(int_ena_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'hFFFF4FFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(err_detected), .I2(int_status_reg_1), .I3(data_in_IBUF), .I4(int_mask_i_reg_2), .I5(mr_int_stat_bei_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_3), .D(int_status_i_1_n_0), .Q(mr_int_stat_bei_o)); LUT6 #( .INIT(64'h5F5F57F7FFFF57F7)) \r_data[6]_i_6 (.I0(adress_IBUF[2]), .I1(mr_int_stat_bei_o), .I2(adress_IBUF[0]), .I3(mr_int_ena_set_int_ena_set_o), .I4(adress_IBUF[1]), .I5(mr_int_mask_set_int_mask_set_o), .O(int_status_reg_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_78 (\adress[5] , mr_int_stat_ofi_o, mr_int_ena_set_int_ena_set_o, adress_IBUF, \r_data[7]_i_2__0 , data_in_IBUF, int_mask_i_reg_0, \mr_ctrl_out[mode_acf] , \r_data_reg[7]_i_6_0 , int_mask_i_reg_1, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_ena_i_reg_0, int_status_reg_0, err_frm_req, int_status_reg_1, int_ena_i_reg_1, int_ena_i_reg_2); output \adress[5] ; output mr_int_stat_ofi_o; output [0:0]mr_int_ena_set_int_ena_set_o; input [3:0]adress_IBUF; input \r_data[7]_i_2__0 ; input [0:0]data_in_IBUF; input int_mask_i_reg_0; input \mr_ctrl_out[mode_acf] ; input \r_data_reg[7]_i_6_0 ; input int_mask_i_reg_1; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_ena_i_reg_0; input int_status_reg_0; input err_frm_req; input int_status_reg_1; input int_ena_i_reg_1; input int_ena_i_reg_2; wire \adress[5] ; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire err_frm_req; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_ena_i_reg_2; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_status_i_1_n_0; wire int_status_i_3_n_0; wire int_status_reg_0; wire int_status_reg_1; wire \mr_ctrl_out[mode_acf] ; wire [0:0]mr_int_ena_set_int_ena_set_o; wire [7:7]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_ofi_o; wire \r_data[7]_i_10_n_0 ; wire \r_data[7]_i_13_n_0 ; wire \r_data[7]_i_2__0 ; wire \r_data_reg[7]_i_6_0 ; LUT5 #( .INIT(32'hFFDF0050)) int_ena_i_i_1 (.I0(int_ena_i_reg_1), .I1(int_ena_i_reg_2), .I2(data_in_IBUF), .I3(int_mask_i_reg_0), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT5 #( .INIT(32'hFFDF0050)) int_mask_i_i_1 (.I0(int_mask_i_reg_1), .I1(int_mask_i_reg_2), .I2(data_in_IBUF), .I3(int_mask_i_reg_0), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'h04FFFFFF04040404)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(int_status_reg_0), .I2(err_frm_req), .I3(int_status_reg_1), .I4(int_status_i_3_n_0), .I5(mr_int_stat_ofi_o), .O(int_status_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT2 #( .INIT(4'h2)) int_status_i_3 (.I0(data_in_IBUF), .I1(int_mask_i_reg_0), .O(int_status_i_3_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_0), .D(int_status_i_1_n_0), .Q(mr_int_stat_ofi_o)); LUT6 #( .INIT(64'h00000000A8AAA8A8)) \r_data[7]_i_10 (.I0(\r_data[7]_i_13_n_0 ), .I1(adress_IBUF[1]), .I2(adress_IBUF[2]), .I3(\mr_ctrl_out[mode_acf] ), .I4(adress_IBUF[0]), .I5(\r_data_reg[7]_i_6_0 ), .O(\r_data[7]_i_10_n_0 )); LUT6 #( .INIT(64'h5F5F57F7FFFF57F7)) \r_data[7]_i_13 (.I0(adress_IBUF[2]), .I1(mr_int_stat_ofi_o), .I2(adress_IBUF[0]), .I3(mr_int_ena_set_int_ena_set_o), .I4(adress_IBUF[1]), .I5(mr_int_mask_set_int_mask_set_o), .O(\r_data[7]_i_13_n_0 )); MUXF7 \r_data_reg[7]_i_6 (.I0(\r_data[7]_i_10_n_0 ), .I1(\r_data[7]_i_2__0 ), .O(\adress[5] ), .S(adress_IBUF[3])); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_79 (D, \sbe[1] , \adress[2] , \adress[6] , int_status_reg_0, sbe_IBUF, adress_IBUF, \r_data_reg[8] , \r_data_reg[8]_0 , \r_data_reg[8]_1 , \r_data_reg[8]_2 , \r_data[8]_i_2_0 , \cc_stat[status_pexs] , \mr_ctrl_out[mode_tstm] , swr_IBUF, int_mask_i_reg_0, reg_q_reg, mr_int_stat_ofi_o, mr_int_stat_bei_o, data_in_IBUF, clk_sys_IBUF_BUFG, int_mask_i_reg_1, rx_full, int_status_reg_1, int_ena_i_reg_0, int_ena_i_reg_1); output [0:0]D; output \sbe[1] ; output \adress[2] ; output \adress[6] ; output int_status_reg_0; input [0:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[8] ; input \r_data_reg[8]_0 ; input \r_data_reg[8]_1 ; input \r_data_reg[8]_2 ; input \r_data[8]_i_2_0 ; input \cc_stat[status_pexs] ; input \mr_ctrl_out[mode_tstm] ; input swr_IBUF; input int_mask_i_reg_0; input [1:0]reg_q_reg; input mr_int_stat_ofi_o; input mr_int_stat_bei_o; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input int_mask_i_reg_1; input rx_full; input int_status_reg_1; input int_ena_i_reg_0; input int_ena_i_reg_1; wire [0:0]D; wire \adress[2] ; wire \adress[6] ; wire [5:0]adress_IBUF; wire \cc_stat[status_pexs] ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire int_ena_i_i_1_n_0; wire int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_status_i_1_n_0; wire int_status_reg_0; wire int_status_reg_1; wire \mr_ctrl_out[mode_tstm] ; wire [8:8]mr_int_ena_set_int_ena_set_o; wire [8:8]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_bei_o; wire mr_int_stat_ofi_o; wire mr_int_stat_rxfi_o; wire \r_data[8]_i_2_0 ; wire \r_data[8]_i_2_n_0 ; wire \r_data[8]_i_6_n_0 ; wire \r_data[8]_i_9_n_0 ; wire \r_data_reg[8] ; wire \r_data_reg[8]_0 ; wire \r_data_reg[8]_1 ; wire \r_data_reg[8]_2 ; wire \r_data_reg[8]_i_4_n_0 ; wire [1:0]reg_q_reg; wire rx_full; wire \sbe[1] ; wire [0:0]sbe_IBUF; wire swr_IBUF; LUT3 #( .INIT(8'h08)) \g_bit[0].reg_value_r[0]_i_2__1 (.I0(sbe_IBUF), .I1(swr_IBUF), .I2(int_mask_i_reg_0), .O(\sbe[1] )); LUT5 #( .INIT(32'hDFFF5000)) int_ena_i_i_1 (.I0(int_ena_i_reg_0), .I1(int_ena_i_reg_1), .I2(data_in_IBUF), .I3(\sbe[1] ), .I4(mr_int_ena_set_int_ena_set_o), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_1), .D(int_ena_i_i_1_n_0), .Q(mr_int_ena_set_int_ena_set_o)); LUT5 #( .INIT(32'hDFFF5000)) int_mask_i_i_1 (.I0(\adress[2] ), .I1(\adress[6] ), .I2(data_in_IBUF), .I3(\sbe[1] ), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFF7FF)) int_mask_i_i_2 (.I0(adress_IBUF[0]), .I1(adress_IBUF[2]), .I2(adress_IBUF[4]), .I3(adress_IBUF[1]), .I4(adress_IBUF[3]), .I5(adress_IBUF[5]), .O(\adress[2] )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) int_mask_i_i_3 (.I0(adress_IBUF[4]), .I1(adress_IBUF[2]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(adress_IBUF[5]), .I5(adress_IBUF[3]), .O(\adress[6] )); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_1), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'h4FFFFFFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(rx_full), .I2(int_status_reg_1), .I3(data_in_IBUF), .I4(\sbe[1] ), .I5(mr_int_stat_rxfi_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_mask_i_reg_1), .D(int_status_i_1_n_0), .Q(mr_int_stat_rxfi_o)); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[8]_i_1 (.I0(sbe_IBUF), .I1(\r_data[8]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[8] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D)); LUT6 #( .INIT(64'hEE2EEE2E0000EE2E)) \r_data[8]_i_2 (.I0(\r_data_reg[8]_i_4_n_0 ), .I1(adress_IBUF[4]), .I2(adress_IBUF[3]), .I3(\r_data_reg[8]_0 ), .I4(\r_data_reg[8]_1 ), .I5(\r_data_reg[8]_2 ), .O(\r_data[8]_i_2_n_0 )); LUT6 #( .INIT(64'hBBBB8B8B88BBBBBB)) \r_data[8]_i_6 (.I0(\r_data[8]_i_9_n_0 ), .I1(adress_IBUF[2]), .I2(\cc_stat[status_pexs] ), .I3(\mr_ctrl_out[mode_tstm] ), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(\r_data[8]_i_6_n_0 )); LUT5 #( .INIT(32'h0F53FF53)) \r_data[8]_i_9 (.I0(mr_int_ena_set_int_ena_set_o), .I1(mr_int_stat_rxfi_o), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(mr_int_mask_set_int_mask_set_o), .O(\r_data[8]_i_9_n_0 )); MUXF7 \r_data_reg[8]_i_4 (.I0(\r_data[8]_i_6_n_0 ), .I1(\r_data[8]_i_2_0 ), .O(\r_data_reg[8]_i_4_n_0 ), .S(adress_IBUF[3])); LUT6 #( .INIT(64'hFFFFF888F888F888)) reg_q_i_5 (.I0(mr_int_stat_rxfi_o), .I1(mr_int_ena_set_int_ena_set_o), .I2(mr_int_stat_ofi_o), .I3(reg_q_reg[1]), .I4(reg_q_reg[0]), .I5(mr_int_stat_bei_o), .O(int_status_reg_0)); endmodule (* ORIG_REF_NAME = "im_channel" *) module im_channel_80 (D, int_ena_i_reg_0, mr_int_stat_bsi_o, sbe_IBUF, adress_IBUF, \r_data_reg[9] , \r_data_reg[9]_0 , \r_data_reg[9]_1 , \r_data_reg[9]_2 , \r_data[9]_i_2__0_0 , \mr_ctrl_out[mode_rxbam] , int_mask_i_reg_0, int_mask_i_reg_1, data_in_IBUF, int_mask_i_reg_2, clk_sys_IBUF_BUFG, int_ena_i_reg_1, br_shifted, int_status_reg_0, int_ena_i_reg_2, int_ena_i_reg_3); output [0:0]D; output [0:0]int_ena_i_reg_0; output mr_int_stat_bsi_o; input [0:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[9] ; input \r_data_reg[9]_0 ; input \r_data_reg[9]_1 ; input \r_data_reg[9]_2 ; input \r_data[9]_i_2__0_0 ; input \mr_ctrl_out[mode_rxbam] ; input int_mask_i_reg_0; input int_mask_i_reg_1; input [0:0]data_in_IBUF; input int_mask_i_reg_2; input clk_sys_IBUF_BUFG; input int_ena_i_reg_1; input br_shifted; input int_status_reg_0; input int_ena_i_reg_2; input int_ena_i_reg_3; wire [0:0]D; wire [5:0]adress_IBUF; wire br_shifted; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire int_ena_i_i_1_n_0; wire [0:0]int_ena_i_reg_0; wire int_ena_i_reg_1; wire int_ena_i_reg_2; wire int_ena_i_reg_3; wire int_mask_i_i_1_n_0; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_mask_i_reg_2; wire int_status_i_1_n_0; wire int_status_reg_0; wire \mr_ctrl_out[mode_rxbam] ; wire [9:9]mr_int_mask_set_int_mask_set_o; wire mr_int_stat_bsi_o; wire \r_data[9]_i_10_n_0 ; wire \r_data[9]_i_2__0_0 ; wire \r_data[9]_i_2__0_n_0 ; wire \r_data[9]_i_7_n_0 ; wire \r_data_reg[9] ; wire \r_data_reg[9]_0 ; wire \r_data_reg[9]_1 ; wire \r_data_reg[9]_2 ; wire \r_data_reg[9]_i_4_n_0 ; wire [0:0]sbe_IBUF; LUT5 #( .INIT(32'hDFFF5000)) int_ena_i_i_1 (.I0(int_ena_i_reg_2), .I1(int_ena_i_reg_3), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(int_ena_i_reg_0), .O(int_ena_i_i_1_n_0)); FDCE int_ena_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_1), .D(int_ena_i_i_1_n_0), .Q(int_ena_i_reg_0)); LUT5 #( .INIT(32'hDFFF5000)) int_mask_i_i_1 (.I0(int_mask_i_reg_0), .I1(int_mask_i_reg_1), .I2(data_in_IBUF), .I3(int_mask_i_reg_2), .I4(mr_int_mask_set_int_mask_set_o), .O(int_mask_i_i_1_n_0)); FDCE int_mask_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_1), .D(int_mask_i_i_1_n_0), .Q(mr_int_mask_set_int_mask_set_o)); LUT6 #( .INIT(64'h4FFFFFFF44444444)) int_status_i_1 (.I0(mr_int_mask_set_int_mask_set_o), .I1(br_shifted), .I2(int_status_reg_0), .I3(data_in_IBUF), .I4(int_mask_i_reg_2), .I5(mr_int_stat_bsi_o), .O(int_status_i_1_n_0)); FDCE int_status_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(int_ena_i_reg_1), .D(int_status_i_1_n_0), .Q(mr_int_stat_bsi_o)); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[9]_i_1 (.I0(sbe_IBUF), .I1(\r_data[9]_i_2__0_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[9] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D)); LUT5 #( .INIT(32'hB833B800)) \r_data[9]_i_10 (.I0(mr_int_mask_set_int_mask_set_o), .I1(adress_IBUF[1]), .I2(int_ena_i_reg_0), .I3(adress_IBUF[0]), .I4(mr_int_stat_bsi_o), .O(\r_data[9]_i_10_n_0 )); LUT6 #( .INIT(64'hF351F3510051F351)) \r_data[9]_i_2__0 (.I0(\r_data_reg[9]_i_4_n_0 ), .I1(\r_data_reg[9]_0 ), .I2(\r_data_reg[9]_1 ), .I3(adress_IBUF[4]), .I4(adress_IBUF[3]), .I5(\r_data_reg[9]_2 ), .O(\r_data[9]_i_2__0_n_0 )); LUT5 #( .INIT(32'h8B888B8B)) \r_data[9]_i_7 (.I0(\r_data[9]_i_10_n_0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[mode_rxbam] ), .I4(adress_IBUF[0]), .O(\r_data[9]_i_7_n_0 )); MUXF7 \r_data_reg[9]_i_4 (.I0(\r_data[9]_i_7_n_0 ), .I1(\r_data[9]_i_2__0_0 ), .O(\r_data_reg[9]_i_4_n_0 ), .S(adress_IBUF[3])); endmodule module im_top (mr_int_stat_fcsi_o, mr_int_stat_txbhci_o, int_OBUF, \g_bit[0].reg_value_r_reg[0] , D, \adress[4] , data_overrun_flg_reg, \adress[5] , \adress[5]_0 , swr, \sbe[1] , int_mask_i_reg, \g_bit[0].reg_value_r_reg[0]_0 , int_status_reg, \g_bit[0].reg_value_r_reg[0]_1 , int_mask_i_reg_0, int_status_reg_0, int_status_reg_1, clk_sys_IBUF_BUFG, reg_q_reg, int_status_reg_2, adress_IBUF, \mr_ctrl_out[mode_stm] , int_status_reg_3, sbe_IBUF, \r_data_reg[8] , \r_data_reg[9] , \r_data_reg[10] , int_mask_i_reg_1, \r_data_reg[8]_0 , \r_data_reg[8]_1 , \r_data_reg[9]_0 , \r_data[8]_i_2 , \cc_stat[status_pexs] , \mr_ctrl_out[mode_tstm] , rx_data_overrun, \mr_ctrl_out[mode_bmm] , \r_data[3]_i_2 , \r_data[7]_i_2__0 , data_in_IBUF, swr_IBUF, \r_data_reg[9]_1 , \r_data_reg[9]_2 , \r_data_reg[10]_0 , \r_data_reg[10]_1 , \r_data[9]_i_2__0 , \r_data[10]_i_2__0 , \mr_ctrl_out[mode_sam] , \mr_ctrl_out[mode_txbbm] , \mr_ctrl_out[mode_rxbam] , \mr_ctrl_out[mode_acf] , \r_data_reg[7]_i_6 , \r_data_reg[3]_i_5 , \r_data_reg[3]_i_5_0 , \cc_stat[is_transmitter] , \mr_ctrl_out[mode_tttm] , rec_valid, \txtb_hw_cmd[valid] , err_warning_limit_q, int_status_reg_4, int_status_reg_5, arbitration_lost, err_detected, int_status_reg_6, err_frm_req, rx_full, br_shifted, int_status_reg_7); output mr_int_stat_fcsi_o; output mr_int_stat_txbhci_o; output int_OBUF; output \g_bit[0].reg_value_r_reg[0] ; output [2:0]D; output \adress[4] ; output data_overrun_flg_reg; output \adress[5] ; output \adress[5]_0 ; output swr; output \sbe[1] ; output [1:0]int_mask_i_reg; output \g_bit[0].reg_value_r_reg[0]_0 ; output int_status_reg; output \g_bit[0].reg_value_r_reg[0]_1 ; output int_mask_i_reg_0; output int_status_reg_0; input int_status_reg_1; input clk_sys_IBUF_BUFG; input reg_q_reg; input int_status_reg_2; input [5:0]adress_IBUF; input \mr_ctrl_out[mode_stm] ; input int_status_reg_3; input [1:0]sbe_IBUF; input \r_data_reg[8] ; input \r_data_reg[9] ; input \r_data_reg[10] ; input int_mask_i_reg_1; input \r_data_reg[8]_0 ; input \r_data_reg[8]_1 ; input \r_data_reg[9]_0 ; input \r_data[8]_i_2 ; input \cc_stat[status_pexs] ; input \mr_ctrl_out[mode_tstm] ; input rx_data_overrun; input \mr_ctrl_out[mode_bmm] ; input \r_data[3]_i_2 ; input \r_data[7]_i_2__0 ; input [11:0]data_in_IBUF; input swr_IBUF; input \r_data_reg[9]_1 ; input \r_data_reg[9]_2 ; input \r_data_reg[10]_0 ; input \r_data_reg[10]_1 ; input \r_data[9]_i_2__0 ; input \r_data[10]_i_2__0 ; input \mr_ctrl_out[mode_sam] ; input \mr_ctrl_out[mode_txbbm] ; input \mr_ctrl_out[mode_rxbam] ; input \mr_ctrl_out[mode_acf] ; input \r_data_reg[7]_i_6 ; input \r_data_reg[3]_i_5 ; input \r_data_reg[3]_i_5_0 ; input \cc_stat[is_transmitter] ; input \mr_ctrl_out[mode_tttm] ; input rec_valid; input \txtb_hw_cmd[valid] ; input err_warning_limit_q; input int_status_reg_4; input int_status_reg_5; input arbitration_lost; input err_detected; input int_status_reg_6; input err_frm_req; input rx_full; input br_shifted; input int_status_reg_7; wire [2:0]D; wire \adress[4] ; wire \adress[5] ; wire \adress[5]_0 ; wire [5:0]adress_IBUF; wire arbitration_lost; wire br_shifted; wire \cc_stat[is_transmitter] ; wire \cc_stat[status_pexs] ; wire clk_sys_IBUF_BUFG; wire [11:0]data_in_IBUF; wire data_overrun_flg_reg; wire err_detected; wire err_frm_req; wire err_warning_limit_q; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_int_module[11].i_im_channel_n_1 ; wire \g_int_module[11].i_im_channel_n_3 ; wire \g_int_module[11].i_im_channel_n_6 ; wire \g_int_module[2].i_im_channel_n_1 ; wire \g_int_module[8].i_im_channel_n_2 ; wire \g_int_module[8].i_im_channel_n_3 ; wire \g_int_module[8].i_im_channel_n_4 ; wire int_OBUF; wire int_i; wire [1:0]int_mask_i_reg; wire int_mask_i_reg_0; wire int_mask_i_reg_1; wire int_status_reg; wire int_status_reg_0; wire int_status_reg_1; wire int_status_reg_2; wire int_status_reg_3; wire int_status_reg_4; wire int_status_reg_5; wire int_status_reg_6; wire int_status_reg_7; wire \mr_ctrl_out[mode_acf] ; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[mode_rxbam] ; wire \mr_ctrl_out[mode_sam] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[mode_tstm] ; wire \mr_ctrl_out[mode_tttm] ; wire \mr_ctrl_out[mode_txbbm] ; wire [10:0]mr_int_ena_set_int_ena_set_o; wire mr_int_stat_bei_o; wire mr_int_stat_bsi_o; wire mr_int_stat_doi_o; wire mr_int_stat_fcsi_o; wire mr_int_stat_ofi_o; wire mr_int_stat_rbnei_o; wire mr_int_stat_rxi_o; wire mr_int_stat_txbhci_o; wire mr_int_stat_txi_o; wire \r_data[10]_i_2__0 ; wire \r_data[3]_i_2 ; wire \r_data[7]_i_2__0 ; wire \r_data[8]_i_2 ; wire \r_data[9]_i_2__0 ; wire \r_data_reg[10] ; wire \r_data_reg[10]_0 ; wire \r_data_reg[10]_1 ; wire \r_data_reg[3]_i_5 ; wire \r_data_reg[3]_i_5_0 ; wire \r_data_reg[7]_i_6 ; wire \r_data_reg[8] ; wire \r_data_reg[8]_0 ; wire \r_data_reg[8]_1 ; wire \r_data_reg[9] ; wire \r_data_reg[9]_0 ; wire \r_data_reg[9]_1 ; wire \r_data_reg[9]_2 ; wire rec_valid; wire reg_q_reg; wire rx_data_overrun; wire rx_full; wire \sbe[1] ; wire [1:0]sbe_IBUF; wire swr; wire swr_IBUF; wire \txtb_hw_cmd[valid] ; im_channel \g_int_module[0].i_im_channel (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[0]), .int_ena_i_reg_0(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(swr), .int_mask_i_reg_3(reg_q_reg), .int_status_reg_0(int_status_reg_0), .int_status_reg_1(\adress[4] ), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[0]), .mr_int_stat_rxi_o(mr_int_stat_rxi_o), .rec_valid(rec_valid)); im_channel_70 \g_int_module[10].i_im_channel (.D(D[2]), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[10]), .int_ena_i_reg_0(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(\sbe[1] ), .int_mask_i_reg_3(reg_q_reg), .int_status_reg_0(int_status_reg_7), .int_status_reg_1(\adress[4] ), .\mr_ctrl_out[mode_txbbm] (\mr_ctrl_out[mode_txbbm] ), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[10]), .mr_int_stat_rbnei_o(mr_int_stat_rbnei_o), .\r_data[10]_i_2__0_0 (\r_data[10]_i_2__0 ), .\r_data_reg[10] (\r_data_reg[10] ), .\r_data_reg[10]_0 (\r_data_reg[10]_0 ), .\r_data_reg[10]_1 (\r_data_reg[9]_0 ), .\r_data_reg[10]_2 (\r_data_reg[10]_1 ), .sbe_IBUF(sbe_IBUF[1])); im_channel_71 \g_int_module[11].i_im_channel (.\adress[2] (\g_int_module[11].i_im_channel_n_3 ), .\adress[4] (\adress[4] ), .\adress[6] (\g_int_module[11].i_im_channel_n_1 ), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[11]), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0]_0 ), .int_ena_i_reg_0(reg_q_reg), .int_mask_i_reg_0(int_mask_i_reg[1]), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_2(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_3(\sbe[1] ), .int_status_reg_0(\g_int_module[11].i_im_channel_n_6 ), .int_status_reg_1(int_status_reg_2), .int_status_reg_2(int_mask_i_reg_1), .int_status_reg_3(int_status_reg_3), .\mr_ctrl_out[mode_sam] (\mr_ctrl_out[mode_sam] ), .mr_int_stat_bsi_o(mr_int_stat_bsi_o), .mr_int_stat_rbnei_o(mr_int_stat_rbnei_o), .mr_int_stat_txbhci_o(mr_int_stat_txbhci_o), .reg_q_reg(mr_int_ena_set_int_ena_set_o[10:9])); im_channel_72 \g_int_module[1].i_im_channel (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[1]), .data_overrun_flg_reg(data_overrun_flg_reg), .int_ena_i_reg_0(reg_q_reg), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_2(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(int_mask_i_reg_1), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_2(\g_int_module[8].i_im_channel_n_3 ), .int_status_reg_0(\adress[4] ), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[1]), .mr_int_stat_txi_o(mr_int_stat_txi_o), .rx_data_overrun(rx_data_overrun), .sbe_IBUF(sbe_IBUF[0]), .swr(swr), .swr_IBUF(swr_IBUF), .\txtb_hw_cmd[valid] (\txtb_hw_cmd[valid] )); im_channel_73 \g_int_module[2].i_im_channel (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[2]), .err_warning_limit_q(err_warning_limit_q), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0] ), .int_ena_i_reg_0(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(swr), .int_mask_i_reg_3(reg_q_reg), .int_status_reg_0(\g_int_module[2].i_im_channel_n_1 ), .int_status_reg_1(int_status_reg_4), .int_status_reg_2(\adress[4] ), .int_status_reg_3(int_status_reg_5), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .mr_int_stat_rxi_o(mr_int_stat_rxi_o), .mr_int_stat_txi_o(mr_int_stat_txi_o), .\r_data[2]_i_5 (int_status_reg_3), .reg_q_reg(mr_int_ena_set_int_ena_set_o[1:0])); im_channel_74 \g_int_module[3].i_im_channel (.\adress[5] (\adress[5] ), .adress_IBUF(adress_IBUF[3:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[3]), .int_ena_i_reg_0(reg_q_reg), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_2(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(swr), .int_status_reg_0(\adress[4] ), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[3]), .mr_int_stat_doi_o(mr_int_stat_doi_o), .\r_data[3]_i_2 (\r_data[3]_i_2 ), .\r_data_reg[3]_i_5_0 (\r_data_reg[3]_i_5 ), .\r_data_reg[3]_i_5_1 (\r_data_reg[3]_i_5_0 ), .rx_data_overrun(rx_data_overrun)); im_channel_75 \g_int_module[4].i_im_channel (.adress_IBUF(adress_IBUF[1:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[4]), .int_ena_i_reg_0(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(int_mask_i_reg_0), .int_mask_i_reg_1(int_mask_i_reg[0]), .int_mask_i_reg_2(reg_q_reg), .int_mask_i_reg_3(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_4(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_5(swr), .int_status_reg_0(int_status_reg_1), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[4]), .mr_int_stat_fcsi_o(mr_int_stat_fcsi_o)); im_channel_76 \g_int_module[5].i_im_channel (.adress_IBUF(adress_IBUF[2:0]), .arbitration_lost(arbitration_lost), .\cc_stat[is_transmitter] (\cc_stat[is_transmitter] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[5]), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0]_1 ), .int_ena_i_reg_0(reg_q_reg), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_2(\g_int_module[11].i_im_channel_n_3 ), .int_i(int_i), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(swr), .int_status_reg_0(\adress[4] ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .mr_int_stat_doi_o(mr_int_stat_doi_o), .mr_int_stat_fcsi_o(mr_int_stat_fcsi_o), .reg_q_reg(mr_int_ena_set_int_ena_set_o[4:3]), .reg_q_reg_0(\g_int_module[2].i_im_channel_n_1 ), .reg_q_reg_1(\g_int_module[11].i_im_channel_n_6 ), .reg_q_reg_2(\g_int_module[8].i_im_channel_n_4 )); im_channel_77 \g_int_module[6].i_im_channel (.adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[6]), .err_detected(err_detected), .int_ena_i_reg_0(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(swr), .int_mask_i_reg_3(reg_q_reg), .int_status_reg_0(int_status_reg), .int_status_reg_1(\adress[4] ), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[6]), .mr_int_stat_bei_o(mr_int_stat_bei_o)); im_channel_78 \g_int_module[7].i_im_channel (.\adress[5] (\adress[5]_0 ), .adress_IBUF(adress_IBUF[3:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7]), .err_frm_req(err_frm_req), .int_ena_i_reg_0(reg_q_reg), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_2(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(swr), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_2(\g_int_module[8].i_im_channel_n_3 ), .int_status_reg_0(int_status_reg_6), .int_status_reg_1(\adress[4] ), .\mr_ctrl_out[mode_acf] (\mr_ctrl_out[mode_acf] ), .mr_int_ena_set_int_ena_set_o(mr_int_ena_set_int_ena_set_o[7]), .mr_int_stat_ofi_o(mr_int_stat_ofi_o), .\r_data[7]_i_2__0 (\r_data[7]_i_2__0 ), .\r_data_reg[7]_i_6_0 (\r_data_reg[7]_i_6 )); im_channel_79 \g_int_module[8].i_im_channel (.D(D[0]), .\adress[2] (\g_int_module[8].i_im_channel_n_2 ), .\adress[6] (\g_int_module[8].i_im_channel_n_3 ), .adress_IBUF(adress_IBUF), .\cc_stat[status_pexs] (\cc_stat[status_pexs] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[8]), .int_ena_i_reg_0(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_1(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(int_mask_i_reg_1), .int_mask_i_reg_1(reg_q_reg), .int_status_reg_0(\g_int_module[8].i_im_channel_n_4 ), .int_status_reg_1(\adress[4] ), .\mr_ctrl_out[mode_tstm] (\mr_ctrl_out[mode_tstm] ), .mr_int_stat_bei_o(mr_int_stat_bei_o), .mr_int_stat_ofi_o(mr_int_stat_ofi_o), .\r_data[8]_i_2_0 (\r_data[8]_i_2 ), .\r_data_reg[8] (\r_data_reg[8] ), .\r_data_reg[8]_0 (\r_data_reg[8]_0 ), .\r_data_reg[8]_1 (\r_data_reg[8]_1 ), .\r_data_reg[8]_2 (\r_data_reg[9]_0 ), .reg_q_reg(mr_int_ena_set_int_ena_set_o[7:6]), .rx_full(rx_full), .\sbe[1] (\sbe[1] ), .sbe_IBUF(sbe_IBUF[1]), .swr_IBUF(swr_IBUF)); im_channel_80 \g_int_module[9].i_im_channel (.D(D[1]), .adress_IBUF(adress_IBUF), .br_shifted(br_shifted), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[9]), .int_ena_i_reg_0(mr_int_ena_set_int_ena_set_o[9]), .int_ena_i_reg_1(reg_q_reg), .int_ena_i_reg_2(\g_int_module[11].i_im_channel_n_1 ), .int_ena_i_reg_3(\g_int_module[11].i_im_channel_n_3 ), .int_mask_i_reg_0(\g_int_module[8].i_im_channel_n_2 ), .int_mask_i_reg_1(\g_int_module[8].i_im_channel_n_3 ), .int_mask_i_reg_2(\sbe[1] ), .int_status_reg_0(\adress[4] ), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .mr_int_stat_bsi_o(mr_int_stat_bsi_o), .\r_data[9]_i_2__0_0 (\r_data[9]_i_2__0 ), .\r_data_reg[9] (\r_data_reg[9] ), .\r_data_reg[9]_0 (\r_data_reg[9]_1 ), .\r_data_reg[9]_1 (\r_data_reg[9]_0 ), .\r_data_reg[9]_2 (\r_data_reg[9]_2 ), .sbe_IBUF(sbe_IBUF[1])); dff_arst_81 i_dff_int_output_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .int_OBUF(int_OBUF), .int_i(int_i), .reg_q_reg_0(reg_q_reg)); endmodule module mac_bit_destuffing (reg_q_reg, stuff_err, reg_q, reg_q_reg_0, reg_q_reg_1, D, rx_trig_req_q_reg, fixed_prev_q, \same_bits_q_reg[2]_0 , reg_q_reg_2, reg_q_reg_3, reg_q_reg_4, reg_q_reg_5, reg_q_reg_6, \dst_ctr_q_reg[1]_0 , \dst_ctr_q_reg[0]_0 , \dst_ctr_q_reg[2]_0 , reg_q_reg_7, reg_q_reg_8, reg_q_reg_9, reg_q_reg_10, destuff_enable, clk_sys_IBUF_BUFG, reg_q_reg_11, stuff_err_d, prev_val_d, q_i, scan_mode_IBUF, rst_n_out_OBUF, reg_q_reg_12, reg_q_reg_13, tran_frame_valid, \crc_q[16]_i_3 , reg_q_reg_14, reg_q_reg_15, \mr_ctrl_out[settings_pex] , \err_capt_err_type_q[2]_i_3 , Q, sync_edge, rx_data_nbs_prev, rec_brs_reg, rec_brs, bds_data_in, \same_bits_q_reg[2]_1 , \same_bits_q_reg[0]_0 , \dst_ctr_q_reg[1]_1 ); output reg_q_reg; output stuff_err; output reg_q; output reg_q_reg_0; output reg_q_reg_1; output [0:0]D; output rx_trig_req_q_reg; output fixed_prev_q; output \same_bits_q_reg[2]_0 ; output reg_q_reg_2; output reg_q_reg_3; output reg_q_reg_4; output reg_q_reg_5; output reg_q_reg_6; output \dst_ctr_q_reg[1]_0 ; output \dst_ctr_q_reg[0]_0 ; output \dst_ctr_q_reg[2]_0 ; output reg_q_reg_7; output reg_q_reg_8; output reg_q_reg_9; output reg_q_reg_10; input destuff_enable; input clk_sys_IBUF_BUFG; input reg_q_reg_11; input stuff_err_d; input prev_val_d; input q_i; input scan_mode_IBUF; input rst_n_out_OBUF; input reg_q_reg_12; input reg_q_reg_13; input tran_frame_valid; input \crc_q[16]_i_3 ; input reg_q_reg_14; input reg_q_reg_15; input \mr_ctrl_out[settings_pex] ; input \err_capt_err_type_q[2]_i_3 ; input [2:0]Q; input sync_edge; input rx_data_nbs_prev; input rec_brs_reg; input rec_brs; input bds_data_in; input \same_bits_q_reg[2]_1 ; input \same_bits_q_reg[0]_0 ; input \dst_ctr_q_reg[1]_1 ; wire [0:0]D; wire [2:0]Q; wire bds_data_in; wire clk_sys_IBUF_BUFG; wire \crc_q[16]_i_3 ; wire destuff_enable; wire destuffed_d0_out; wire [2:2]dst_ctr_d; wire \dst_ctr_q[0]_i_1_n_0 ; wire \dst_ctr_q[1]_i_1_n_0 ; wire \dst_ctr_q[2]_i_1_n_0 ; wire \dst_ctr_q_reg[0]_0 ; wire \dst_ctr_q_reg[1]_0 ; wire \dst_ctr_q_reg[1]_1 ; wire \dst_ctr_q_reg[2]_0 ; wire enable_prev; wire \err_capt_err_type_q[2]_i_3 ; wire fixed_prev_q; wire i_dff_ena_reg_n_1; wire i_dff_fixed_stuff_reg_n_2; wire \mr_ctrl_out[settings_pex] ; wire prev_val_d; wire q_i; wire rec_brs; wire rec_brs_reg; wire reg_q; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_10; wire reg_q_reg_11; wire reg_q_reg_12; wire reg_q_reg_13; wire reg_q_reg_14; wire reg_q_reg_15; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire reg_q_reg_7; wire reg_q_reg_8; wire reg_q_reg_9; wire rst_n_out_OBUF; wire rx_data_nbs_prev; wire rx_trig_req_q_reg; wire \same_bits_q[0]_i_1_n_0 ; wire \same_bits_q[1]_i_1_n_0 ; wire \same_bits_q[2]_i_1_n_0 ; wire \same_bits_q[2]_i_3__0_n_0 ; wire \same_bits_q_reg[0]_0 ; wire \same_bits_q_reg[2]_0 ; wire \same_bits_q_reg[2]_1 ; wire \same_bits_q_reg_n_0_[0] ; wire \same_bits_q_reg_n_0_[1] ; wire \same_bits_q_reg_n_0_[2] ; wire scan_mode_IBUF; wire stuff_err; wire stuff_err_d; wire sync_edge; wire tran_frame_valid; LUT6 #( .INIT(64'hDFFF555520000000)) \dst_ctr_q[0]_i_1 (.I0(destuff_enable), .I1(reg_q_reg_15), .I2(reg_q_reg_14), .I3(\same_bits_q_reg[2]_0 ), .I4(enable_prev), .I5(\dst_ctr_q_reg[0]_0 ), .O(\dst_ctr_q[0]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFF333380000000)) \dst_ctr_q[1]_i_1 (.I0(\dst_ctr_q_reg[0]_0 ), .I1(destuff_enable), .I2(\dst_ctr_q_reg[1]_1 ), .I3(\same_bits_q_reg[2]_0 ), .I4(enable_prev), .I5(\dst_ctr_q_reg[1]_0 ), .O(\dst_ctr_q[1]_i_1_n_0 )); LUT6 #( .INIT(64'hBFFFBBBB80008888)) \dst_ctr_q[2]_i_1 (.I0(dst_ctr_d), .I1(destuff_enable), .I2(\dst_ctr_q_reg[1]_1 ), .I3(\same_bits_q_reg[2]_0 ), .I4(enable_prev), .I5(\dst_ctr_q_reg[2]_0 ), .O(\dst_ctr_q[2]_i_1_n_0 )); FDCE \dst_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_11), .D(\dst_ctr_q[0]_i_1_n_0 ), .Q(\dst_ctr_q_reg[0]_0 )); FDCE \dst_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_11), .D(\dst_ctr_q[1]_i_1_n_0 ), .Q(\dst_ctr_q_reg[1]_0 )); FDCE \dst_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_11), .D(\dst_ctr_q[2]_i_1_n_0 ), .Q(\dst_ctr_q_reg[2]_0 )); dff_arst_ce__parameterized0_65 i_dff_data_out_val_reg (.Q(Q), .bds_data_in(bds_data_in), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\err_capt_err_type_q[2]_i_3 (\err_capt_err_type_q[2]_i_3 ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .rec_brs(rec_brs), .rec_brs_reg(rec_brs_reg), .reg_q_reg_0(reg_q_reg_1), .reg_q_reg_1(D), .reg_q_reg_10(reg_q_reg_14), .reg_q_reg_11(reg_q_reg_11), .reg_q_reg_2(reg_q_reg_3), .reg_q_reg_3(reg_q_reg_4), .reg_q_reg_4(reg_q_reg_5), .reg_q_reg_5(reg_q_reg_6), .reg_q_reg_6(reg_q_reg_7), .reg_q_reg_7(reg_q_reg_8), .reg_q_reg_8(reg_q_reg_9), .reg_q_reg_9(reg_q_reg_10), .rx_data_nbs_prev(rx_data_nbs_prev), .rx_data_nbs_prev_reg(reg_q_reg_12), .rx_data_nbs_prev_reg_0(reg_q_reg), .sync_edge(sync_edge), .tran_frame_valid(tran_frame_valid)); dff_arst_66 i_dff_destuffed_flag_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\crc_q[16]_i_3 (\crc_q[16]_i_3 ), .destuffed_d0_out(destuffed_d0_out), .q_i(q_i), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .reg_q_reg_2(reg_q_reg_2), .reg_q_reg_3(reg_q_reg_11), .reg_q_reg_4(reg_q_reg_12), .reg_q_reg_5(reg_q_reg_13), .reg_q_reg_6(\same_bits_q_reg_n_0_[2] ), .reg_q_reg_7(\same_bits_q_reg_n_0_[0] ), .reg_q_reg_8(\same_bits_q_reg_n_0_[1] ), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_trig_req_q_reg(rx_trig_req_q_reg), .\same_bits_q_reg[2] (\same_bits_q_reg[2]_0 ), .scan_mode_IBUF(scan_mode_IBUF)); dff_arst_67 i_dff_ena_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .destuff_enable(destuff_enable), .dst_ctr_d(dst_ctr_d), .\dst_ctr_q_reg[2] (\dst_ctr_q_reg[1]_0 ), .\dst_ctr_q_reg[2]_0 (\dst_ctr_q_reg[0]_0 ), .\dst_ctr_q_reg[2]_1 (\dst_ctr_q_reg[2]_0 ), .enable_prev(enable_prev), .reg_q_reg_0(i_dff_ena_reg_n_1), .reg_q_reg_1(reg_q_reg_11)); dff_arst_68 i_dff_err_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(reg_q_reg_11), .stuff_err(stuff_err), .stuff_err_d(stuff_err_d)); dff_arst_ce_69 i_dff_fixed_stuff_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .destuff_enable(destuff_enable), .destuffed_d0_out(destuffed_d0_out), .enable_prev(enable_prev), .reg_q_reg_0(fixed_prev_q), .reg_q_reg_1(reg_q_reg_14), .reg_q_reg_2(reg_q_reg_15), .reg_q_reg_3(\same_bits_q_reg[2]_0 ), .reg_q_reg_4(reg_q_reg), .reg_q_reg_5(reg_q_reg_11), .\same_bits_q_reg[0] (\same_bits_q_reg_n_0_[1] ), .\same_bits_q_reg[0]_0 (\same_bits_q_reg_n_0_[0] ), .\same_bits_q_reg[0]_1 (\same_bits_q_reg_n_0_[2] ), .\same_bits_q_reg[1] (i_dff_fixed_stuff_reg_n_2)); dff_arst__parameterized0 i_dff_prev_val_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .prev_val_d(prev_val_d), .reg_q(reg_q), .reg_q_reg_0(reg_q_reg_11)); LUT6 #( .INIT(64'hDDFFDFFFFFCCFFCC)) \same_bits_q[0]_i_1 (.I0(i_dff_fixed_stuff_reg_n_2), .I1(i_dff_ena_reg_n_1), .I2(reg_q_reg_15), .I3(reg_q_reg_14), .I4(\same_bits_q_reg[0]_0 ), .I5(\same_bits_q_reg_n_0_[0] ), .O(\same_bits_q[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000002F00000080)) \same_bits_q[1]_i_1 (.I0(i_dff_fixed_stuff_reg_n_2), .I1(\same_bits_q_reg_n_0_[0] ), .I2(reg_q_reg_14), .I3(i_dff_ena_reg_n_1), .I4(\same_bits_q_reg[2]_1 ), .I5(\same_bits_q_reg_n_0_[1] ), .O(\same_bits_q[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000002F00000020)) \same_bits_q[2]_i_1 (.I0(i_dff_fixed_stuff_reg_n_2), .I1(\same_bits_q[2]_i_3__0_n_0 ), .I2(reg_q_reg_14), .I3(i_dff_ena_reg_n_1), .I4(\same_bits_q_reg[2]_1 ), .I5(\same_bits_q_reg_n_0_[2] ), .O(\same_bits_q[2]_i_1_n_0 )); LUT3 #( .INIT(8'h95)) \same_bits_q[2]_i_3__0 (.I0(\same_bits_q_reg_n_0_[2] ), .I1(\same_bits_q_reg_n_0_[1] ), .I2(\same_bits_q_reg_n_0_[0] ), .O(\same_bits_q[2]_i_3__0_n_0 )); FDPE \same_bits_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\same_bits_q[0]_i_1_n_0 ), .PRE(reg_q_reg_11), .Q(\same_bits_q_reg_n_0_[0] )); FDCE \same_bits_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_11), .D(\same_bits_q[1]_i_1_n_0 ), .Q(\same_bits_q_reg_n_0_[1] )); FDCE \same_bits_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_11), .D(\same_bits_q[2]_i_1_n_0 ), .Q(\same_bits_q_reg_n_0_[2] )); endmodule module mac_bit_stuffing (enable_prev, data_halt_d1_out, \tran_frame_test_reg[fstc] , \bst_ctr_q_reg[1]_0 , \bst_ctr_q_reg[0]_0 , \bst_ctr_q_reg[1]_1 , \cc_stat[bst_ctr] , reg_q_reg, stuff_enable_reg, stuff_enable, clk_sys_IBUF_BUFG, reg_q_reg_0, \shift_regs_reg[29] , \shift_regs_reg[29]_0 , \tran_frame_test[fstc] , \shift_regs_reg[30] , \shift_regs_reg[30]_0 , reg_q_reg_1, reg_q_reg_2, reg_q_reg_3, tx_frame_no_sof, \same_bits_q_reg[2]_0 , \same_bits_q_reg[1]_0 , \bst_ctr_q_reg[0]_1 ); output enable_prev; output data_halt_d1_out; output \tran_frame_test_reg[fstc] ; output \bst_ctr_q_reg[1]_0 ; output \bst_ctr_q_reg[0]_0 ; output \bst_ctr_q_reg[1]_1 ; output [0:0]\cc_stat[bst_ctr] ; output reg_q_reg; output stuff_enable_reg; input stuff_enable; input clk_sys_IBUF_BUFG; input reg_q_reg_0; input \shift_regs_reg[29] ; input \shift_regs_reg[29]_0 ; input \tran_frame_test[fstc] ; input \shift_regs_reg[30] ; input \shift_regs_reg[30]_0 ; input reg_q_reg_1; input reg_q_reg_2; input reg_q_reg_3; input tx_frame_no_sof; input \same_bits_q_reg[2]_0 ; input \same_bits_q_reg[1]_0 ; input \bst_ctr_q_reg[0]_1 ; wire \bst_ctr_q[0]_i_1_n_0 ; wire \bst_ctr_q[1]_i_1_n_0 ; wire \bst_ctr_q[1]_i_2_n_0 ; wire \bst_ctr_q[2]_i_1_n_0 ; wire \bst_ctr_q_reg[0]_0 ; wire \bst_ctr_q_reg[0]_1 ; wire \bst_ctr_q_reg[1]_0 ; wire \bst_ctr_q_reg[1]_1 ; wire [0:0]\cc_stat[bst_ctr] ; wire clk_sys_IBUF_BUFG; wire data_halt_d1_out; wire data_halt_q; wire enable_prev; wire i_dff_data_out_reg_n_0; wire i_dff_ena_reg_n_2; wire i_dff_fixed_stuff_reg_n_1; wire i_dff_fixed_stuff_reg_n_2; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire \same_bits_q[0]_i_1_n_0 ; wire \same_bits_q[1]_i_1_n_0 ; wire \same_bits_q[2]_i_1_n_0 ; wire \same_bits_q[2]_i_3_n_0 ; wire \same_bits_q_reg[1]_0 ; wire \same_bits_q_reg[2]_0 ; wire \same_bits_q_reg_n_0_[0] ; wire \same_bits_q_reg_n_0_[1] ; wire \same_bits_q_reg_n_0_[2] ; wire \shift_regs_reg[29] ; wire \shift_regs_reg[29]_0 ; wire \shift_regs_reg[30] ; wire \shift_regs_reg[30]_0 ; wire stuff_enable; wire stuff_enable_reg; wire \tran_frame_test[fstc] ; wire \tran_frame_test_reg[fstc] ; wire tx_frame_no_sof; LUT5 #( .INIT(32'h73F38000)) \bst_ctr_q[0]_i_1 (.I0(\bst_ctr_q_reg[0]_1 ), .I1(stuff_enable), .I2(enable_prev), .I3(\bst_ctr_q[1]_i_2_n_0 ), .I4(\bst_ctr_q_reg[0]_0 ), .O(\bst_ctr_q[0]_i_1_n_0 )); LUT6 #( .INIT(64'h7F0FFF0F80000000)) \bst_ctr_q[1]_i_1 (.I0(\bst_ctr_q_reg[0]_0 ), .I1(\bst_ctr_q_reg[0]_1 ), .I2(stuff_enable), .I3(enable_prev), .I4(\bst_ctr_q[1]_i_2_n_0 ), .I5(\bst_ctr_q_reg[1]_0 ), .O(\bst_ctr_q[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT3 #( .INIT(8'h08)) \bst_ctr_q[1]_i_2 (.I0(\same_bits_q_reg_n_0_[2] ), .I1(\same_bits_q_reg_n_0_[0] ), .I2(\same_bits_q_reg_n_0_[1] ), .O(\bst_ctr_q[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFF70F000008000)) \bst_ctr_q[2]_i_1 (.I0(\bst_ctr_q_reg[1]_0 ), .I1(\bst_ctr_q_reg[0]_0 ), .I2(enable_prev), .I3(\bst_ctr_q_reg[0]_1 ), .I4(i_dff_ena_reg_n_2), .I5(\cc_stat[bst_ctr] ), .O(\bst_ctr_q[2]_i_1_n_0 )); FDCE \bst_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(\bst_ctr_q[0]_i_1_n_0 ), .Q(\bst_ctr_q_reg[0]_0 )); FDCE \bst_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(\bst_ctr_q[1]_i_1_n_0 ), .Q(\bst_ctr_q_reg[1]_0 )); FDCE \bst_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(\bst_ctr_q[2]_i_1_n_0 ), .Q(\cc_stat[bst_ctr] )); dff_arst_ce__parameterized0 i_dff_data_out_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(i_dff_data_out_reg_n_0), .reg_q_reg_1(reg_q_reg), .reg_q_reg_2(reg_q_reg_1), .reg_q_reg_3(reg_q_reg_3), .reg_q_reg_4(i_dff_fixed_stuff_reg_n_2), .reg_q_reg_5(reg_q_reg_0), .\same_bits_q_reg[0] (reg_q_reg_2), .\same_bits_q_reg[0]_0 (enable_prev), .\same_bits_q_reg[0]_1 (i_dff_fixed_stuff_reg_n_1), .stuff_enable(stuff_enable)); dff_arst_62 i_dff_ena_reg (.\bst_ctr_q_reg[2] (\same_bits_q_reg_n_0_[2] ), .\bst_ctr_q_reg[2]_0 (\same_bits_q_reg_n_0_[0] ), .\bst_ctr_q_reg[2]_1 (\same_bits_q_reg_n_0_[1] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\crc_q_reg[0] (i_dff_fixed_stuff_reg_n_1), .\crc_q_reg[0]_0 (reg_q_reg_3), .reg_q_reg_0(enable_prev), .reg_q_reg_1(reg_q_reg_0), .\same_bits_q_reg[2] (i_dff_ena_reg_n_2), .stuff_enable(stuff_enable), .stuff_enable_reg(stuff_enable_reg)); dff_arst_ce_63 i_dff_fixed_stuff_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_halt_d1_out(data_halt_d1_out), .data_halt_q(data_halt_q), .reg_q_reg_0(i_dff_fixed_stuff_reg_n_2), .reg_q_reg_1(reg_q_reg_3), .reg_q_reg_2(enable_prev), .reg_q_reg_3(reg_q_reg_2), .reg_q_reg_4(\same_bits_q_reg_n_0_[2] ), .reg_q_reg_5(\same_bits_q_reg_n_0_[0] ), .reg_q_reg_6(\same_bits_q_reg_n_0_[1] ), .reg_q_reg_7(reg_q_reg_0), .\same_bits_q_reg[1] (i_dff_fixed_stuff_reg_n_1), .stuff_enable(stuff_enable)); dff_arst_64 i_dff_halt_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_halt_d1_out(data_halt_d1_out), .data_halt_q(data_halt_q), .reg_q_reg_0(reg_q_reg_0)); LUT5 #( .INIT(32'hABFFBB00)) \same_bits_q[0]_i_1 (.I0(\same_bits_q_reg[1]_0 ), .I1(tx_frame_no_sof), .I2(i_dff_data_out_reg_n_0), .I3(\same_bits_q_reg[2]_0 ), .I4(\same_bits_q_reg_n_0_[0] ), .O(\same_bits_q[0]_i_1_n_0 )); LUT6 #( .INIT(64'h00F2FFFF00F80000)) \same_bits_q[1]_i_1 (.I0(i_dff_data_out_reg_n_0), .I1(\same_bits_q_reg_n_0_[0] ), .I2(tx_frame_no_sof), .I3(\same_bits_q_reg[1]_0 ), .I4(\same_bits_q_reg[2]_0 ), .I5(\same_bits_q_reg_n_0_[1] ), .O(\same_bits_q[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0080FFFF00800000)) \same_bits_q[2]_i_1 (.I0(stuff_enable), .I1(i_dff_data_out_reg_n_0), .I2(\same_bits_q[2]_i_3_n_0 ), .I3(tx_frame_no_sof), .I4(\same_bits_q_reg[2]_0 ), .I5(\same_bits_q_reg_n_0_[2] ), .O(\same_bits_q[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT3 #( .INIT(8'h6A)) \same_bits_q[2]_i_3 (.I0(\same_bits_q_reg_n_0_[2] ), .I1(\same_bits_q_reg_n_0_[1] ), .I2(\same_bits_q_reg_n_0_[0] ), .O(\same_bits_q[2]_i_3_n_0 )); FDPE \same_bits_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\same_bits_q[0]_i_1_n_0 ), .PRE(reg_q_reg_0), .Q(\same_bits_q_reg_n_0_[0] )); FDCE \same_bits_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(\same_bits_q[1]_i_1_n_0 ), .Q(\same_bits_q_reg_n_0_[1] )); FDCE \same_bits_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_0), .D(\same_bits_q[2]_i_1_n_0 ), .Q(\same_bits_q_reg_n_0_[2] )); LUT5 #( .INIT(32'h208A8A20)) \shift_regs[29]_i_3 (.I0(\shift_regs_reg[29] ), .I1(\shift_regs_reg[29]_0 ), .I2(\tran_frame_test[fstc] ), .I3(\bst_ctr_q_reg[1]_0 ), .I4(\bst_ctr_q_reg[0]_0 ), .O(\tran_frame_test_reg[fstc] )); LUT5 #( .INIT(32'hEBBEEBEB)) \shift_regs[30]_i_5 (.I0(\shift_regs_reg[30] ), .I1(\bst_ctr_q_reg[1]_0 ), .I2(\cc_stat[bst_ctr] ), .I3(\shift_regs_reg[30]_0 ), .I4(\tran_frame_test[fstc] ), .O(\bst_ctr_q_reg[1]_1 )); endmodule module mac_crc_calc (Q, \crc_q_reg[3]_0 , \crc_q_reg[4]_0 , \crc_q_reg[5]_0 , \crc_q_reg[6]_0 , \tran_frame_test_reg[fcrc] , \crc_q_reg[14]_0 , \crc_q_reg[11]_0 , \crc_q_reg[10]_0 , \crc_q_reg[9]_0 , \crc_q_reg[8]_0 , \crc_q_reg[7]_0 , \crc_q_reg[2]_0 , \crc_q_reg[1]_0 , \crc_q_reg[0]_0 , \crc_q_reg[11]_1 , \crc_q_reg[14]_1 , \crc_q_reg[1]_1 , \shift_regs_reg[20] , \shift_regs_reg[20]_0 , \shift_regs_reg[20]_1 , \shift_regs_reg[21] , \shift_regs_reg[22] , \shift_regs_reg[23] , \shift_regs_reg[30] , \tran_frame_test[fcrc] , \shift_regs_reg[31] , \shift_regs[30]_i_2_0 , \shift_regs[31]_i_9_0 , \shift_regs[17]_i_2 , \shift_regs[31]_i_9_1 , \shift_regs[28]_i_4 , \crc_match_c6_inferred__0/i__carry , E, D, clk_sys_IBUF_BUFG, \crc_q_reg[14]_2 ); output [9:0]Q; output \crc_q_reg[3]_0 ; output \crc_q_reg[4]_0 ; output \crc_q_reg[5]_0 ; output \crc_q_reg[6]_0 ; output \tran_frame_test_reg[fcrc] ; output \crc_q_reg[14]_0 ; output \crc_q_reg[11]_0 ; output \crc_q_reg[10]_0 ; output \crc_q_reg[9]_0 ; output \crc_q_reg[8]_0 ; output \crc_q_reg[7]_0 ; output \crc_q_reg[2]_0 ; output \crc_q_reg[1]_0 ; output \crc_q_reg[0]_0 ; output [2:0]\crc_q_reg[11]_1 ; output [0:0]\crc_q_reg[14]_1 ; input \crc_q_reg[1]_1 ; input \shift_regs_reg[20] ; input \shift_regs_reg[20]_0 ; input \shift_regs_reg[20]_1 ; input \shift_regs_reg[21] ; input \shift_regs_reg[22] ; input \shift_regs_reg[23] ; input \shift_regs_reg[30] ; input \tran_frame_test[fcrc] ; input \shift_regs_reg[31] ; input \shift_regs[30]_i_2_0 ; input [13:0]\shift_regs[31]_i_9_0 ; input \shift_regs[17]_i_2 ; input [13:0]\shift_regs[31]_i_9_1 ; input \shift_regs[28]_i_4 ; input [11:0]\crc_match_c6_inferred__0/i__carry ; input [0:0]E; input [6:0]D; input clk_sys_IBUF_BUFG; input \crc_q_reg[14]_2 ; wire [6:0]D; wire [0:0]E; wire [9:0]Q; wire clk_sys_IBUF_BUFG; wire [11:0]crc_15; wire [13:1]crc_d; wire [11:0]\crc_match_c6_inferred__0/i__carry ; wire \crc_q_reg[0]_0 ; wire \crc_q_reg[10]_0 ; wire \crc_q_reg[11]_0 ; wire [2:0]\crc_q_reg[11]_1 ; wire \crc_q_reg[14]_0 ; wire [0:0]\crc_q_reg[14]_1 ; wire \crc_q_reg[14]_2 ; wire \crc_q_reg[1]_0 ; wire \crc_q_reg[1]_1 ; wire \crc_q_reg[2]_0 ; wire \crc_q_reg[3]_0 ; wire \crc_q_reg[4]_0 ; wire \crc_q_reg[5]_0 ; wire \crc_q_reg[6]_0 ; wire \crc_q_reg[7]_0 ; wire \crc_q_reg[8]_0 ; wire \crc_q_reg[9]_0 ; wire \shift_regs[17]_i_2 ; wire \shift_regs[20]_i_4_n_0 ; wire \shift_regs[21]_i_4_n_0 ; wire \shift_regs[22]_i_4_n_0 ; wire \shift_regs[23]_i_4_n_0 ; wire \shift_regs[28]_i_4 ; wire \shift_regs[30]_i_2_0 ; wire \shift_regs[30]_i_7_n_0 ; wire \shift_regs[31]_i_18_n_0 ; wire [13:0]\shift_regs[31]_i_9_0 ; wire [13:0]\shift_regs[31]_i_9_1 ; wire \shift_regs_reg[20] ; wire \shift_regs_reg[20]_0 ; wire \shift_regs_reg[20]_1 ; wire \shift_regs_reg[21] ; wire \shift_regs_reg[22] ; wire \shift_regs_reg[23] ; wire \shift_regs_reg[30] ; wire \shift_regs_reg[31] ; wire \tran_frame_test[fcrc] ; wire \tran_frame_test_reg[fcrc] ; (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h2)) \crc_q[11]_i_1__1 (.I0(crc_15[10]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[11])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h2)) \crc_q[12]_i_1 (.I0(crc_15[11]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[12])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h2)) \crc_q[13]_i_1__1 (.I0(Q[7]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[13])); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT2 #( .INIT(4'h2)) \crc_q[1]_i_1__0 (.I0(crc_15[0]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[1])); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT2 #( .INIT(4'h2)) \crc_q[2]_i_1 (.I0(crc_15[1]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[2])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT2 #( .INIT(4'h2)) \crc_q[5]_i_1 (.I0(Q[2]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[5])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT2 #( .INIT(4'h2)) \crc_q[6]_i_1__0 (.I0(Q[3]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[6])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h2)) \crc_q[9]_i_1 (.I0(crc_15[8]), .I1(\crc_q_reg[1]_1 ), .O(crc_d[9])); FDCE \crc_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[0]), .Q(crc_15[0])); FDCE \crc_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[5]), .Q(crc_15[10])); FDCE \crc_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[11]), .Q(crc_15[11])); FDCE \crc_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[12]), .Q(Q[7])); FDCE \crc_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[13]), .Q(Q[8])); FDCE \crc_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[6]), .Q(Q[9])); FDCE \crc_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[1]), .Q(crc_15[1])); FDCE \crc_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[2]), .Q(Q[0])); FDCE \crc_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[1]), .Q(Q[1])); FDCE \crc_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[2]), .Q(Q[2])); FDCE \crc_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[5]), .Q(Q[3])); FDCE \crc_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[6]), .Q(Q[4])); FDCE \crc_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[3]), .Q(Q[5])); FDCE \crc_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(D[4]), .Q(crc_15[8])); FDCE \crc_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\crc_q_reg[14]_2 ), .D(crc_d[9]), .Q(Q[6])); LUT6 #( .INIT(64'h9009000000009009)) i__carry__0_i_1 (.I0(Q[9]), .I1(\crc_match_c6_inferred__0/i__carry [4]), .I2(\crc_match_c6_inferred__0/i__carry [2]), .I3(Q[7]), .I4(\crc_match_c6_inferred__0/i__carry [3]), .I5(Q[8]), .O(\crc_q_reg[14]_1 )); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_1 (.I0(crc_15[11]), .I1(\crc_match_c6_inferred__0/i__carry [1]), .I2(\crc_match_c6_inferred__0/i__carry [11]), .I3(Q[6]), .I4(\crc_match_c6_inferred__0/i__carry [0]), .I5(crc_15[10]), .O(\crc_q_reg[11]_1 [2])); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_2 (.I0(crc_15[8]), .I1(\crc_match_c6_inferred__0/i__carry [10]), .I2(\crc_match_c6_inferred__0/i__carry [8]), .I3(Q[4]), .I4(\crc_match_c6_inferred__0/i__carry [9]), .I5(Q[5]), .O(\crc_q_reg[11]_1 [1])); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_4 (.I0(crc_15[1]), .I1(\crc_match_c6_inferred__0/i__carry [6]), .I2(\crc_match_c6_inferred__0/i__carry [7]), .I3(Q[0]), .I4(\crc_match_c6_inferred__0/i__carry [5]), .I5(crc_15[0]), .O(\crc_q_reg[11]_1 [0])); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[17]_i_4 (.I0(crc_15[0]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [0]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [0]), .O(\crc_q_reg[0]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[18]_i_4 (.I0(crc_15[1]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [1]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [1]), .O(\crc_q_reg[1]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[19]_i_4 (.I0(Q[0]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [2]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [2]), .O(\crc_q_reg[2]_0 )); LUT4 #( .INIT(16'h009A)) \shift_regs[20]_i_2 (.I0(\shift_regs[20]_i_4_n_0 ), .I1(\shift_regs_reg[20] ), .I2(\shift_regs_reg[20]_0 ), .I3(\shift_regs_reg[20]_1 ), .O(\crc_q_reg[3]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[20]_i_4 (.I0(Q[1]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [3]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [3]), .O(\shift_regs[20]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT3 #( .INIT(8'h06)) \shift_regs[21]_i_2 (.I0(\shift_regs[21]_i_4_n_0 ), .I1(\shift_regs_reg[21] ), .I2(\shift_regs_reg[20]_1 ), .O(\crc_q_reg[4]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[21]_i_4 (.I0(Q[2]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [4]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [4]), .O(\shift_regs[21]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT3 #( .INIT(8'h06)) \shift_regs[22]_i_2 (.I0(\shift_regs[22]_i_4_n_0 ), .I1(\shift_regs_reg[22] ), .I2(\shift_regs_reg[20]_1 ), .O(\crc_q_reg[5]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[22]_i_4 (.I0(Q[3]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [5]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [5]), .O(\shift_regs[22]_i_4_n_0 )); LUT4 #( .INIT(16'h00A9)) \shift_regs[23]_i_2 (.I0(\shift_regs[23]_i_4_n_0 ), .I1(\shift_regs_reg[20] ), .I2(\shift_regs_reg[23] ), .I3(\shift_regs_reg[20]_1 ), .O(\crc_q_reg[6]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[23]_i_4 (.I0(Q[4]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [6]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [6]), .O(\shift_regs[23]_i_4_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[24]_i_4 (.I0(Q[5]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [7]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [7]), .O(\crc_q_reg[7]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[25]_i_4 (.I0(crc_15[8]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [8]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [8]), .O(\crc_q_reg[8]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[26]_i_4 (.I0(Q[6]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [9]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [9]), .O(\crc_q_reg[9]_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[27]_i_4 (.I0(crc_15[10]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [10]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [10]), .O(\crc_q_reg[10]_0 )); LUT6 #( .INIT(64'h7707770700007707)) \shift_regs[28]_i_8 (.I0(\shift_regs[30]_i_2_0 ), .I1(crc_15[11]), .I2(\shift_regs[31]_i_9_0 [11]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_1 [11]), .I5(\shift_regs[28]_i_4 ), .O(\crc_q_reg[11]_0 )); LUT4 #( .INIT(16'h0065)) \shift_regs[30]_i_2 (.I0(\shift_regs[30]_i_7_n_0 ), .I1(\shift_regs_reg[30] ), .I2(\tran_frame_test[fcrc] ), .I3(\shift_regs_reg[20]_1 ), .O(\tran_frame_test_reg[fcrc] )); LUT6 #( .INIT(64'h7707770700007707)) \shift_regs[30]_i_7 (.I0(\shift_regs[30]_i_2_0 ), .I1(Q[8]), .I2(\shift_regs[31]_i_9_1 [12]), .I3(\shift_regs[28]_i_4 ), .I4(\shift_regs[31]_i_9_0 [12]), .I5(\shift_regs[17]_i_2 ), .O(\shift_regs[30]_i_7_n_0 )); LUT5 #( .INIT(32'hB8FFB800)) \shift_regs[31]_i_18 (.I0(Q[9]), .I1(\shift_regs[28]_i_4 ), .I2(\shift_regs[31]_i_9_1 [13]), .I3(\shift_regs[17]_i_2 ), .I4(\shift_regs[31]_i_9_0 [13]), .O(\shift_regs[31]_i_18_n_0 )); LUT4 #( .INIT(16'h009A)) \shift_regs[31]_i_9 (.I0(\shift_regs[31]_i_18_n_0 ), .I1(\shift_regs_reg[23] ), .I2(\shift_regs_reg[31] ), .I3(\shift_regs_reg[20]_1 ), .O(\crc_q_reg[14]_0 )); endmodule (* ORIG_REF_NAME = "mac_crc_calc" *) module mac_crc_calc__parameterized0 (Q, \crc_q_reg[14]_0 , S, \crc_q_reg[16]_0 , \crc_q_reg[1]_0 , \mr_ctrl_out[settings_nisofd] , \crc_q_reg[0]_0 , \shift_regs[29]_i_4 , \shift_regs[29]_i_4_0 , \shift_regs[29]_i_4_1 , \shift_regs[29]_i_4_2 , \shift_regs[29]_i_4_3 , crc_data_rx_wbs, \crc_q_reg[0]_1 , \crc_q_reg[0]_2 , crc_match_c6_carry, \crc_q_reg[0]_3 , clk_sys_IBUF_BUFG, \crc_q_reg[16]_1 ); output [16:0]Q; output \crc_q_reg[14]_0 ; output [2:0]S; output [0:0]\crc_q_reg[16]_0 ; input \crc_q_reg[1]_0 ; input \mr_ctrl_out[settings_nisofd] ; input \crc_q_reg[0]_0 ; input \shift_regs[29]_i_4 ; input [0:0]\shift_regs[29]_i_4_0 ; input \shift_regs[29]_i_4_1 ; input [0:0]\shift_regs[29]_i_4_2 ; input \shift_regs[29]_i_4_3 ; input crc_data_rx_wbs; input \crc_q_reg[0]_1 ; input \crc_q_reg[0]_2 ; input [10:0]crc_match_c6_carry; input [0:0]\crc_q_reg[0]_3 ; input clk_sys_IBUF_BUFG; input \crc_q_reg[16]_1 ; wire [16:0]Q; wire [2:0]S; wire clk_sys_IBUF_BUFG; wire crc_data_rx_wbs; wire [10:0]crc_match_c6_carry; wire \crc_q[0]_i_1_n_0 ; wire \crc_q[10]_i_1_n_0 ; wire \crc_q[11]_i_1_n_0 ; wire \crc_q[12]_i_1__0_n_0 ; wire \crc_q[13]_i_1_n_0 ; wire \crc_q[14]_i_1_n_0 ; wire \crc_q[15]_i_1_n_0 ; wire \crc_q[16]_i_2_n_0 ; wire \crc_q[16]_i_4_n_0 ; wire \crc_q[1]_i_1_n_0 ; wire \crc_q[2]_i_1__0_n_0 ; wire \crc_q[3]_i_1_n_0 ; wire \crc_q[4]_i_1_n_0 ; wire \crc_q[5]_i_1__0_n_0 ; wire \crc_q[6]_i_1_n_0 ; wire \crc_q[7]_i_1__0_n_0 ; wire \crc_q[8]_i_1_n_0 ; wire \crc_q[9]_i_1__0_n_0 ; wire \crc_q_reg[0]_0 ; wire \crc_q_reg[0]_1 ; wire \crc_q_reg[0]_2 ; wire [0:0]\crc_q_reg[0]_3 ; wire \crc_q_reg[14]_0 ; wire [0:0]\crc_q_reg[16]_0 ; wire \crc_q_reg[16]_1 ; wire \crc_q_reg[1]_0 ; wire \mr_ctrl_out[settings_nisofd] ; wire \shift_regs[29]_i_4 ; wire [0:0]\shift_regs[29]_i_4_0 ; wire \shift_regs[29]_i_4_1 ; wire [0:0]\shift_regs[29]_i_4_2 ; wire \shift_regs[29]_i_4_3 ; LUT4 #( .INIT(16'h9009)) crc_match_c6_carry__0_i_1 (.I0(Q[16]), .I1(crc_match_c6_carry[3]), .I2(Q[15]), .I3(crc_match_c6_carry[2]), .O(\crc_q_reg[16]_0 )); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c6_carry_i_1 (.I0(Q[11]), .I1(crc_match_c6_carry[1]), .I2(crc_match_c6_carry[10]), .I3(Q[9]), .I4(crc_match_c6_carry[0]), .I5(Q[10]), .O(S[2])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c6_carry_i_2 (.I0(Q[8]), .I1(crc_match_c6_carry[9]), .I2(crc_match_c6_carry[7]), .I3(Q[6]), .I4(crc_match_c6_carry[8]), .I5(Q[7]), .O(S[1])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c6_carry_i_3 (.I0(Q[5]), .I1(crc_match_c6_carry[6]), .I2(crc_match_c6_carry[4]), .I3(Q[3]), .I4(crc_match_c6_carry[5]), .I5(Q[4]), .O(S[0])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h2)) \crc_q[0]_i_1 (.I0(\crc_q[16]_i_4_n_0 ), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT2 #( .INIT(4'h2)) \crc_q[10]_i_1 (.I0(Q[9]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT3 #( .INIT(8'h28)) \crc_q[11]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[10]), .O(\crc_q[11]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT2 #( .INIT(4'h2)) \crc_q[12]_i_1__0 (.I0(Q[11]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[12]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT3 #( .INIT(8'h28)) \crc_q[13]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[12]), .O(\crc_q[13]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT3 #( .INIT(8'h28)) \crc_q[14]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[13]), .O(\crc_q[14]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT2 #( .INIT(4'h2)) \crc_q[15]_i_1 (.I0(Q[14]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[15]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT4 #( .INIT(16'h4774)) \crc_q[16]_i_2 (.I0(\mr_ctrl_out[settings_nisofd] ), .I1(\crc_q_reg[0]_0 ), .I2(Q[15]), .I3(\crc_q[16]_i_4_n_0 ), .O(\crc_q[16]_i_2_n_0 )); LUT4 #( .INIT(16'h56A6)) \crc_q[16]_i_4 (.I0(Q[16]), .I1(crc_data_rx_wbs), .I2(\crc_q_reg[0]_1 ), .I3(\crc_q_reg[0]_2 ), .O(\crc_q[16]_i_4_n_0 )); LUT3 #( .INIT(8'h28)) \crc_q[1]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[0]), .O(\crc_q[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT2 #( .INIT(4'h2)) \crc_q[2]_i_1__0 (.I0(Q[1]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT3 #( .INIT(8'h28)) \crc_q[3]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[2]), .O(\crc_q[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT3 #( .INIT(8'h28)) \crc_q[4]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[3]), .O(\crc_q[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT2 #( .INIT(4'h2)) \crc_q[5]_i_1__0 (.I0(Q[4]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[5]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT3 #( .INIT(8'h28)) \crc_q[6]_i_1 (.I0(\crc_q_reg[1]_0 ), .I1(\crc_q[16]_i_4_n_0 ), .I2(Q[5]), .O(\crc_q[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT2 #( .INIT(4'h2)) \crc_q[7]_i_1__0 (.I0(Q[6]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[7]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT2 #( .INIT(4'h2)) \crc_q[8]_i_1 (.I0(Q[7]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT2 #( .INIT(4'h2)) \crc_q[9]_i_1__0 (.I0(Q[8]), .I1(\crc_q_reg[0]_0 ), .O(\crc_q[9]_i_1__0_n_0 )); FDCE \crc_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[0]_i_1_n_0 ), .Q(Q[0])); FDCE \crc_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[10]_i_1_n_0 ), .Q(Q[10])); FDCE \crc_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[11]_i_1_n_0 ), .Q(Q[11])); FDCE \crc_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[12]_i_1__0_n_0 ), .Q(Q[12])); FDCE \crc_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[13]_i_1_n_0 ), .Q(Q[13])); FDCE \crc_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[14]_i_1_n_0 ), .Q(Q[14])); FDCE \crc_q_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[15]_i_1_n_0 ), .Q(Q[15])); FDCE \crc_q_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[16]_i_2_n_0 ), .Q(Q[16])); FDCE \crc_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[1]_i_1_n_0 ), .Q(Q[1])); FDCE \crc_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[2]_i_1__0_n_0 ), .Q(Q[2])); FDCE \crc_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[3]_i_1_n_0 ), .Q(Q[3])); FDCE \crc_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[4]_i_1_n_0 ), .Q(Q[4])); FDCE \crc_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[5]_i_1__0_n_0 ), .Q(Q[5])); FDCE \crc_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[6]_i_1_n_0 ), .Q(Q[6])); FDCE \crc_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[7]_i_1__0_n_0 ), .Q(Q[7])); FDCE \crc_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[8]_i_1_n_0 ), .Q(Q[8])); FDCE \crc_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[0]_3 ), .CLR(\crc_q_reg[16]_1 ), .D(\crc_q[9]_i_1__0_n_0 ), .Q(Q[9])); LUT6 #( .INIT(64'h0000DD0DDD0DDD0D)) \shift_regs[29]_i_8 (.I0(Q[14]), .I1(\shift_regs[29]_i_4 ), .I2(\shift_regs[29]_i_4_0 ), .I3(\shift_regs[29]_i_4_1 ), .I4(\shift_regs[29]_i_4_2 ), .I5(\shift_regs[29]_i_4_3 ), .O(\crc_q_reg[14]_0 )); endmodule (* ORIG_REF_NAME = "mac_crc_calc" *) module mac_crc_calc__parameterized1 (Q, \crc_q_reg[20]_0 , \crc_q_reg[2]_0 , \crc_q_reg[3]_0 , \crc_q_reg[4]_0 , \crc_q_reg[5]_0 , \crc_q_reg[11]_0 , \crc_q_reg[20]_1 , \crc_q_reg[3]_1 , \mr_ctrl_out[settings_nisofd] , \crc_q_reg[1]_0 , \shift_regs_reg[13] , \shift_regs_reg[13]_0 , \shift_regs_reg[13]_1 , \shift_regs_reg[14] , \shift_regs_reg[16] , \shift_regs_reg[16]_0 , \shift_regs_reg[15] , \shift_regs_reg[16]_1 , crc_match_c5_carry, store_data_word, crc_data_rx_wbs, \crc_q_reg[3]_2 , \crc_q_reg[3]_3 , \crc_q_reg[20]_2 , clk_sys_IBUF_BUFG, \crc_q_reg[20]_3 , \crc_q_reg[0]_0 ); output [16:0]Q; output \crc_q_reg[20]_0 ; output \crc_q_reg[2]_0 ; output \crc_q_reg[3]_0 ; output \crc_q_reg[4]_0 ; output \crc_q_reg[5]_0 ; output [3:0]\crc_q_reg[11]_0 ; output [1:0]\crc_q_reg[20]_1 ; input \crc_q_reg[3]_1 ; input \mr_ctrl_out[settings_nisofd] ; input \crc_q_reg[1]_0 ; input \shift_regs_reg[13] ; input \shift_regs_reg[13]_0 ; input \shift_regs_reg[13]_1 ; input \shift_regs_reg[14] ; input [1:0]\shift_regs_reg[16] ; input \shift_regs_reg[16]_0 ; input \shift_regs_reg[15] ; input \shift_regs_reg[16]_1 ; input [14:0]crc_match_c5_carry; input [2:0]store_data_word; input crc_data_rx_wbs; input \crc_q_reg[3]_2 ; input \crc_q_reg[3]_3 ; input [0:0]\crc_q_reg[20]_2 ; input clk_sys_IBUF_BUFG; input \crc_q_reg[20]_3 ; input [0:0]\crc_q_reg[0]_0 ; wire [16:0]Q; wire clk_sys_IBUF_BUFG; wire [5:2]crc_21; wire crc_data_rx_wbs; wire [14:0]crc_match_c5_carry; wire \crc_q[10]_i_1__0_n_0 ; wire \crc_q[11]_i_1__0_n_0 ; wire \crc_q[12]_i_1__1_n_0 ; wire \crc_q[13]_i_1__0_n_0 ; wire \crc_q[14]_i_1__1_n_0 ; wire \crc_q[15]_i_1__0_n_0 ; wire \crc_q[16]_i_1__0_n_0 ; wire \crc_q[17]_i_1_n_0 ; wire \crc_q[18]_i_1_n_0 ; wire \crc_q[19]_i_1_n_0 ; wire \crc_q[1]_i_1__1_n_0 ; wire \crc_q[20]_i_1_n_0 ; wire \crc_q[2]_i_1__1_n_0 ; wire \crc_q[3]_i_1__0_n_0 ; wire \crc_q[4]_i_1__0_n_0 ; wire \crc_q[5]_i_1__1_n_0 ; wire \crc_q[6]_i_1__1_n_0 ; wire \crc_q[7]_i_1_n_0 ; wire \crc_q[8]_i_1__0_n_0 ; wire \crc_q[9]_i_1__1_n_0 ; wire [0:0]\crc_q_reg[0]_0 ; wire [3:0]\crc_q_reg[11]_0 ; wire \crc_q_reg[1]_0 ; wire \crc_q_reg[20]_0 ; wire [1:0]\crc_q_reg[20]_1 ; wire [0:0]\crc_q_reg[20]_2 ; wire \crc_q_reg[20]_3 ; wire \crc_q_reg[2]_0 ; wire \crc_q_reg[3]_0 ; wire \crc_q_reg[3]_1 ; wire \crc_q_reg[3]_2 ; wire \crc_q_reg[3]_3 ; wire \crc_q_reg[4]_0 ; wire \crc_q_reg[5]_0 ; wire \mr_ctrl_out[settings_nisofd] ; wire \shift_regs_reg[13] ; wire \shift_regs_reg[13]_0 ; wire \shift_regs_reg[13]_1 ; wire \shift_regs_reg[14] ; wire \shift_regs_reg[15] ; wire [1:0]\shift_regs_reg[16] ; wire \shift_regs_reg[16]_0 ; wire \shift_regs_reg[16]_1 ; wire [2:0]store_data_word; LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry__0_i_1 (.I0(Q[16]), .I1(store_data_word[2]), .I2(store_data_word[0]), .I3(Q[14]), .I4(store_data_word[1]), .I5(Q[15]), .O(\crc_q_reg[20]_1 [1])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry__0_i_3 (.I0(Q[10]), .I1(crc_match_c5_carry[4]), .I2(crc_match_c5_carry[2]), .I3(Q[8]), .I4(crc_match_c5_carry[3]), .I5(Q[9]), .O(\crc_q_reg[20]_1 [0])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry_i_1 (.I0(Q[7]), .I1(crc_match_c5_carry[1]), .I2(crc_match_c5_carry[0]), .I3(Q[6]), .I4(crc_match_c5_carry[14]), .I5(Q[5]), .O(\crc_q_reg[11]_0 [3])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry_i_2 (.I0(Q[4]), .I1(crc_match_c5_carry[13]), .I2(crc_match_c5_carry[11]), .I3(Q[2]), .I4(crc_match_c5_carry[12]), .I5(Q[3]), .O(\crc_q_reg[11]_0 [2])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry_i_3 (.I0(crc_21[5]), .I1(crc_match_c5_carry[10]), .I2(crc_match_c5_carry[8]), .I3(crc_21[3]), .I4(crc_match_c5_carry[9]), .I5(crc_21[4]), .O(\crc_q_reg[11]_0 [1])); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry_i_4 (.I0(Q[1]), .I1(crc_match_c5_carry[6]), .I2(crc_match_c5_carry[7]), .I3(crc_21[2]), .I4(crc_match_c5_carry[5]), .I5(Q[0]), .O(\crc_q_reg[11]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT2 #( .INIT(4'h2)) \crc_q[10]_i_1__0 (.I0(Q[5]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[10]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT3 #( .INIT(8'h82)) \crc_q[11]_i_1__0 (.I0(\crc_q_reg[3]_1 ), .I1(\crc_q_reg[20]_0 ), .I2(Q[6]), .O(\crc_q[11]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT2 #( .INIT(4'h2)) \crc_q[12]_i_1__1 (.I0(Q[7]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[12]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT3 #( .INIT(8'h82)) \crc_q[13]_i_1__0 (.I0(\crc_q_reg[3]_1 ), .I1(\crc_q_reg[20]_0 ), .I2(Q[8]), .O(\crc_q[13]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT2 #( .INIT(4'h2)) \crc_q[14]_i_1__1 (.I0(Q[9]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[14]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT2 #( .INIT(4'h2)) \crc_q[15]_i_1__0 (.I0(Q[10]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[15]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT2 #( .INIT(4'h2)) \crc_q[16]_i_1__0 (.I0(Q[11]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[16]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT2 #( .INIT(4'h2)) \crc_q[17]_i_1 (.I0(Q[12]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[17]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT2 #( .INIT(4'h2)) \crc_q[18]_i_1 (.I0(Q[13]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[18]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT2 #( .INIT(4'h2)) \crc_q[19]_i_1 (.I0(Q[14]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[19]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT2 #( .INIT(4'h2)) \crc_q[1]_i_1__1 (.I0(Q[0]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT4 #( .INIT(16'h909F)) \crc_q[20]_i_1 (.I0(Q[15]), .I1(\crc_q_reg[20]_0 ), .I2(\crc_q_reg[3]_1 ), .I3(\mr_ctrl_out[settings_nisofd] ), .O(\crc_q[20]_i_1_n_0 )); LUT4 #( .INIT(16'hA959)) \crc_q[20]_i_2 (.I0(Q[16]), .I1(crc_data_rx_wbs), .I2(\crc_q_reg[3]_2 ), .I3(\crc_q_reg[3]_3 ), .O(\crc_q_reg[20]_0 )); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT2 #( .INIT(4'h2)) \crc_q[2]_i_1__1 (.I0(Q[1]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT3 #( .INIT(8'h82)) \crc_q[3]_i_1__0 (.I0(\crc_q_reg[3]_1 ), .I1(\crc_q_reg[20]_0 ), .I2(crc_21[2]), .O(\crc_q[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT3 #( .INIT(8'h82)) \crc_q[4]_i_1__0 (.I0(\crc_q_reg[3]_1 ), .I1(\crc_q_reg[20]_0 ), .I2(crc_21[3]), .O(\crc_q[4]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT2 #( .INIT(4'h2)) \crc_q[5]_i_1__1 (.I0(crc_21[4]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[5]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT2 #( .INIT(4'h2)) \crc_q[6]_i_1__1 (.I0(crc_21[5]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[6]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT3 #( .INIT(8'h82)) \crc_q[7]_i_1 (.I0(\crc_q_reg[3]_1 ), .I1(\crc_q_reg[20]_0 ), .I2(Q[2]), .O(\crc_q[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT2 #( .INIT(4'h2)) \crc_q[8]_i_1__0 (.I0(Q[3]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[8]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT2 #( .INIT(4'h2)) \crc_q[9]_i_1__1 (.I0(Q[4]), .I1(\crc_q_reg[1]_0 ), .O(\crc_q[9]_i_1__1_n_0 )); FDCE \crc_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q_reg[0]_0 ), .Q(Q[0])); FDCE \crc_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[10]_i_1__0_n_0 ), .Q(Q[6])); FDCE \crc_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[11]_i_1__0_n_0 ), .Q(Q[7])); FDCE \crc_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[12]_i_1__1_n_0 ), .Q(Q[8])); FDCE \crc_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[13]_i_1__0_n_0 ), .Q(Q[9])); FDCE \crc_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[14]_i_1__1_n_0 ), .Q(Q[10])); FDCE \crc_q_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[15]_i_1__0_n_0 ), .Q(Q[11])); FDCE \crc_q_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[16]_i_1__0_n_0 ), .Q(Q[12])); FDCE \crc_q_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[17]_i_1_n_0 ), .Q(Q[13])); FDCE \crc_q_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[18]_i_1_n_0 ), .Q(Q[14])); FDCE \crc_q_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[19]_i_1_n_0 ), .Q(Q[15])); FDCE \crc_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[1]_i_1__1_n_0 ), .Q(Q[1])); FDCE \crc_q_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[20]_i_1_n_0 ), .Q(Q[16])); FDCE \crc_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[2]_i_1__1_n_0 ), .Q(crc_21[2])); FDCE \crc_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[3]_i_1__0_n_0 ), .Q(crc_21[3])); FDCE \crc_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[4]_i_1__0_n_0 ), .Q(crc_21[4])); FDCE \crc_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[5]_i_1__1_n_0 ), .Q(crc_21[5])); FDCE \crc_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[6]_i_1__1_n_0 ), .Q(Q[2])); FDCE \crc_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[7]_i_1_n_0 ), .Q(Q[3])); FDCE \crc_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[8]_i_1__0_n_0 ), .Q(Q[4])); FDCE \crc_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(\crc_q_reg[20]_2 ), .CLR(\crc_q_reg[20]_3 ), .D(\crc_q[9]_i_1__1_n_0 ), .Q(Q[5])); LUT4 #( .INIT(16'h00D2)) \shift_regs[13]_i_2 (.I0(crc_21[2]), .I1(\shift_regs_reg[13] ), .I2(\shift_regs_reg[13]_0 ), .I3(\shift_regs_reg[13]_1 ), .O(\crc_q_reg[2]_0 )); LUT4 #( .INIT(16'h00D2)) \shift_regs[14]_i_2 (.I0(crc_21[3]), .I1(\shift_regs_reg[13] ), .I2(\shift_regs_reg[14] ), .I3(\shift_regs_reg[13]_1 ), .O(\crc_q_reg[3]_0 )); LUT6 #( .INIT(64'h00000000DD0D22F2)) \shift_regs[15]_i_2 (.I0(crc_21[4]), .I1(\shift_regs_reg[13] ), .I2(\shift_regs_reg[16] [0]), .I3(\shift_regs_reg[16]_0 ), .I4(\shift_regs_reg[15] ), .I5(\shift_regs_reg[13]_1 ), .O(\crc_q_reg[4]_0 )); LUT6 #( .INIT(64'h00000000DD0D22F2)) \shift_regs[16]_i_2 (.I0(crc_21[5]), .I1(\shift_regs_reg[13] ), .I2(\shift_regs_reg[16] [1]), .I3(\shift_regs_reg[16]_0 ), .I4(\shift_regs_reg[16]_1 ), .I5(\shift_regs_reg[13]_1 ), .O(\crc_q_reg[5]_0 )); endmodule module mac_crc_top (Q, \crc_q_reg[17] , \crc_q_reg[20] , \crc_q_reg[14] , \crc_q_reg[2] , \crc_q_reg[3] , \crc_q_reg[4] , \crc_q_reg[5] , \crc_q_reg[3]_0 , \crc_q_reg[4]_0 , \crc_q_reg[5]_0 , \crc_q_reg[6] , \tran_frame_test_reg[fcrc] , \crc_q_reg[14]_0 , \crc_q_reg[11] , \crc_q_reg[14]_1 , \crc_q_reg[10] , \crc_q_reg[9] , \crc_q_reg[8] , \crc_q_reg[7] , \crc_q_reg[2]_0 , \crc_q_reg[1] , \crc_q_reg[0] , S, \crc_q_reg[16] , \crc_q_reg[11]_0 , \crc_q_reg[20]_0 , \crc_q_reg[11]_1 , \crc_q_reg[14]_2 , \crc_q_reg[3]_1 , \mr_ctrl_out[settings_nisofd] , D, \crc_q_reg[1]_0 , \shift_regs_reg[13] , \shift_regs_reg[13]_0 , \shift_regs_reg[13]_1 , \shift_regs_reg[14] , \shift_regs_reg[16] , \shift_regs_reg[15] , \shift_regs_reg[16]_0 , \shift_regs_reg[20] , \shift_regs_reg[20]_0 , \shift_regs_reg[21] , \shift_regs_reg[22] , \shift_regs_reg[23] , \shift_regs_reg[30] , \tran_frame_test[fcrc] , \shift_regs_reg[31] , \shift_regs[30]_i_2 , crc_data_rx_wbs, \crc_q_reg[3]_2 , \crc_q_reg[3]_3 , \crc_match_c6_inferred__0/i__carry , store_data_word, E, clk_sys_IBUF_BUFG, \crc_q_reg[20]_1 , \crc_q_reg[20]_2 , \crc_q_reg[0]_0 ); output [5:0]Q; output [4:0]\crc_q_reg[17] ; output \crc_q_reg[20] ; output [8:0]\crc_q_reg[14] ; output \crc_q_reg[2] ; output \crc_q_reg[3] ; output \crc_q_reg[4] ; output \crc_q_reg[5] ; output \crc_q_reg[3]_0 ; output \crc_q_reg[4]_0 ; output \crc_q_reg[5]_0 ; output \crc_q_reg[6] ; output \tran_frame_test_reg[fcrc] ; output \crc_q_reg[14]_0 ; output \crc_q_reg[11] ; output \crc_q_reg[14]_1 ; output \crc_q_reg[10] ; output \crc_q_reg[9] ; output \crc_q_reg[8] ; output \crc_q_reg[7] ; output \crc_q_reg[2]_0 ; output \crc_q_reg[1] ; output \crc_q_reg[0] ; output [2:0]S; output [0:0]\crc_q_reg[16] ; output [3:0]\crc_q_reg[11]_0 ; output [1:0]\crc_q_reg[20]_0 ; output [2:0]\crc_q_reg[11]_1 ; output [0:0]\crc_q_reg[14]_2 ; input \crc_q_reg[3]_1 ; input \mr_ctrl_out[settings_nisofd] ; input [6:0]D; input \crc_q_reg[1]_0 ; input \shift_regs_reg[13] ; input \shift_regs_reg[13]_0 ; input \shift_regs_reg[13]_1 ; input \shift_regs_reg[14] ; input \shift_regs_reg[16] ; input \shift_regs_reg[15] ; input \shift_regs_reg[16]_0 ; input \shift_regs_reg[20] ; input \shift_regs_reg[20]_0 ; input \shift_regs_reg[21] ; input \shift_regs_reg[22] ; input \shift_regs_reg[23] ; input \shift_regs_reg[30] ; input \tran_frame_test[fcrc] ; input \shift_regs_reg[31] ; input \shift_regs[30]_i_2 ; input crc_data_rx_wbs; input \crc_q_reg[3]_2 ; input \crc_q_reg[3]_3 ; input [16:0]\crc_match_c6_inferred__0/i__carry ; input [2:0]store_data_word; input [0:0]E; input clk_sys_IBUF_BUFG; input \crc_q_reg[20]_1 ; input [0:0]\crc_q_reg[20]_2 ; input [0:0]\crc_q_reg[0]_0 ; wire [6:0]D; wire [0:0]E; wire [5:0]Q; wire [2:0]S; wire clk_sys_IBUF_BUFG; wire [12:12]crc_15; wire [16:3]crc_17; wire [20:6]crc_21; wire crc_data_rx_wbs; wire [16:0]\crc_match_c6_inferred__0/i__carry ; wire \crc_q_reg[0] ; wire [0:0]\crc_q_reg[0]_0 ; wire \crc_q_reg[10] ; wire \crc_q_reg[11] ; wire [3:0]\crc_q_reg[11]_0 ; wire [2:0]\crc_q_reg[11]_1 ; wire [8:0]\crc_q_reg[14] ; wire \crc_q_reg[14]_0 ; wire \crc_q_reg[14]_1 ; wire [0:0]\crc_q_reg[14]_2 ; wire [0:0]\crc_q_reg[16] ; wire [4:0]\crc_q_reg[17] ; wire \crc_q_reg[1] ; wire \crc_q_reg[1]_0 ; wire \crc_q_reg[20] ; wire [1:0]\crc_q_reg[20]_0 ; wire \crc_q_reg[20]_1 ; wire [0:0]\crc_q_reg[20]_2 ; wire \crc_q_reg[2] ; wire \crc_q_reg[2]_0 ; wire \crc_q_reg[3] ; wire \crc_q_reg[3]_0 ; wire \crc_q_reg[3]_1 ; wire \crc_q_reg[3]_2 ; wire \crc_q_reg[3]_3 ; wire \crc_q_reg[4] ; wire \crc_q_reg[4]_0 ; wire \crc_q_reg[5] ; wire \crc_q_reg[5]_0 ; wire \crc_q_reg[6] ; wire \crc_q_reg[7] ; wire \crc_q_reg[8] ; wire \crc_q_reg[9] ; wire \mr_ctrl_out[settings_nisofd] ; wire \shift_regs[30]_i_2 ; wire \shift_regs_reg[13] ; wire \shift_regs_reg[13]_0 ; wire \shift_regs_reg[13]_1 ; wire \shift_regs_reg[14] ; wire \shift_regs_reg[15] ; wire \shift_regs_reg[16] ; wire \shift_regs_reg[16]_0 ; wire \shift_regs_reg[20] ; wire \shift_regs_reg[20]_0 ; wire \shift_regs_reg[21] ; wire \shift_regs_reg[22] ; wire \shift_regs_reg[23] ; wire \shift_regs_reg[30] ; wire \shift_regs_reg[31] ; wire [2:0]store_data_word; wire \tran_frame_test[fcrc] ; wire \tran_frame_test_reg[fcrc] ; mac_crc_calc i_mac_crc_calc_15 (.D(D), .E(E), .Q({\crc_q_reg[14] [8:7],crc_15,\crc_q_reg[14] [6:0]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\crc_match_c6_inferred__0/i__carry ({\crc_match_c6_inferred__0/i__carry [16:13],\crc_match_c6_inferred__0/i__carry [9:7],\crc_match_c6_inferred__0/i__carry [4:0]}), .\crc_q_reg[0]_0 (\crc_q_reg[0] ), .\crc_q_reg[10]_0 (\crc_q_reg[10] ), .\crc_q_reg[11]_0 (\crc_q_reg[11] ), .\crc_q_reg[11]_1 (\crc_q_reg[11]_1 ), .\crc_q_reg[14]_0 (\crc_q_reg[14]_0 ), .\crc_q_reg[14]_1 (\crc_q_reg[14]_2 ), .\crc_q_reg[14]_2 (\crc_q_reg[20]_1 ), .\crc_q_reg[1]_0 (\crc_q_reg[1] ), .\crc_q_reg[1]_1 (\crc_q_reg[1]_0 ), .\crc_q_reg[2]_0 (\crc_q_reg[2]_0 ), .\crc_q_reg[3]_0 (\crc_q_reg[3]_0 ), .\crc_q_reg[4]_0 (\crc_q_reg[4]_0 ), .\crc_q_reg[5]_0 (\crc_q_reg[5]_0 ), .\crc_q_reg[6]_0 (\crc_q_reg[6] ), .\crc_q_reg[7]_0 (\crc_q_reg[7] ), .\crc_q_reg[8]_0 (\crc_q_reg[8] ), .\crc_q_reg[9]_0 (\crc_q_reg[9] ), .\shift_regs[17]_i_2 (\shift_regs_reg[13] ), .\shift_regs[28]_i_4 (\shift_regs_reg[16] ), .\shift_regs[30]_i_2_0 (\shift_regs[30]_i_2 ), .\shift_regs[31]_i_9_0 ({crc_21[20:19],\crc_q_reg[17] [4:2],crc_21[14:6]}), .\shift_regs[31]_i_9_1 ({crc_17[16:15],Q[4:3],crc_17[11:3],Q[2]}), .\shift_regs_reg[20] (\shift_regs_reg[20] ), .\shift_regs_reg[20]_0 (\shift_regs_reg[20]_0 ), .\shift_regs_reg[20]_1 (\shift_regs_reg[13]_1 ), .\shift_regs_reg[21] (\shift_regs_reg[21] ), .\shift_regs_reg[22] (\shift_regs_reg[22] ), .\shift_regs_reg[23] (\shift_regs_reg[23] ), .\shift_regs_reg[30] (\shift_regs_reg[30] ), .\shift_regs_reg[31] (\shift_regs_reg[31] ), .\tran_frame_test[fcrc] (\tran_frame_test[fcrc] ), .\tran_frame_test_reg[fcrc] (\tran_frame_test_reg[fcrc] )); mac_crc_calc__parameterized0 i_mac_crc_calc_17_rx (.Q({crc_17[16:15],Q[5:3],crc_17[11:3],Q[2:0]}), .S(S), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_rx_wbs(crc_data_rx_wbs), .crc_match_c6_carry({\crc_match_c6_inferred__0/i__carry [16:10],\crc_match_c6_inferred__0/i__carry [6:5],\crc_match_c6_inferred__0/i__carry [1:0]}), .\crc_q_reg[0]_0 (\crc_q_reg[1]_0 ), .\crc_q_reg[0]_1 (\crc_q_reg[3]_2 ), .\crc_q_reg[0]_2 (\crc_q_reg[3]_3 ), .\crc_q_reg[0]_3 (\crc_q_reg[20]_2 ), .\crc_q_reg[14]_0 (\crc_q_reg[14]_1 ), .\crc_q_reg[16]_0 (\crc_q_reg[16] ), .\crc_q_reg[16]_1 (\crc_q_reg[20]_1 ), .\crc_q_reg[1]_0 (\crc_q_reg[3]_1 ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\shift_regs[29]_i_4 (\shift_regs_reg[16] ), .\shift_regs[29]_i_4_0 (crc_21[18]), .\shift_regs[29]_i_4_1 (\shift_regs_reg[13] ), .\shift_regs[29]_i_4_2 (crc_15), .\shift_regs[29]_i_4_3 (\shift_regs[30]_i_2 )); mac_crc_calc__parameterized1 i_mac_crc_calc_21_rx (.Q({crc_21[20:18],\crc_q_reg[17] [4:2],crc_21[14:6],\crc_q_reg[17] [1:0]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_rx_wbs(crc_data_rx_wbs), .crc_match_c5_carry({\crc_match_c6_inferred__0/i__carry [16:7],\crc_match_c6_inferred__0/i__carry [4:0]}), .\crc_q_reg[0]_0 (\crc_q_reg[0]_0 ), .\crc_q_reg[11]_0 (\crc_q_reg[11]_0 ), .\crc_q_reg[1]_0 (\crc_q_reg[1]_0 ), .\crc_q_reg[20]_0 (\crc_q_reg[20] ), .\crc_q_reg[20]_1 (\crc_q_reg[20]_0 ), .\crc_q_reg[20]_2 (\crc_q_reg[20]_2 ), .\crc_q_reg[20]_3 (\crc_q_reg[20]_1 ), .\crc_q_reg[2]_0 (\crc_q_reg[2] ), .\crc_q_reg[3]_0 (\crc_q_reg[3] ), .\crc_q_reg[3]_1 (\crc_q_reg[3]_1 ), .\crc_q_reg[3]_2 (\crc_q_reg[3]_2 ), .\crc_q_reg[3]_3 (\crc_q_reg[3]_3 ), .\crc_q_reg[4]_0 (\crc_q_reg[4] ), .\crc_q_reg[5]_0 (\crc_q_reg[5] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\shift_regs_reg[13] (\shift_regs_reg[13] ), .\shift_regs_reg[13]_0 (\shift_regs_reg[13]_0 ), .\shift_regs_reg[13]_1 (\shift_regs_reg[13]_1 ), .\shift_regs_reg[14] (\shift_regs_reg[14] ), .\shift_regs_reg[15] (\shift_regs_reg[15] ), .\shift_regs_reg[16] (Q[1:0]), .\shift_regs_reg[16]_0 (\shift_regs_reg[16] ), .\shift_regs_reg[16]_1 (\shift_regs_reg[16]_0 ), .store_data_word(store_data_word)); endmodule module mac_fc_err_counters (mr_ctr_pres_ptx_q_reg_0, mr_ctr_pres_enorm_q_reg_0, mr_ctr_pres_efd_q_reg_0, \cc_stat[tx_err_ctr] , \tx_err_ctr_q_reg[7]_0 , \tx_err_ctr_q_reg[6]_0 , \tx_err_ctr_q_reg[5]_0 , \tx_err_ctr_q_reg[4]_0 , \tx_err_ctr_q_reg[3]_0 , \tx_err_ctr_q_reg[2]_0 , \tx_err_ctr_q_reg[1]_0 , \tx_err_ctr_q_reg[0]_0 , D, Q, \data_err_ctr_q_reg[2]_0 , \tx_err_ctr_q_reg[3]_1 , \tx_err_ctr_q_reg[6]_1 , \tx_err_ctr_q_reg[7]_1 , \nom_err_ctr_q_reg[0]_0 , \rx_err_ctr_q_reg[1]_0 , \rx_err_ctr_q_reg[3]_0 , \rx_err_ctr_q_reg[5]_0 , \rx_err_ctr_q_reg[7]_0 , \rx_err_ctr_q_reg[8]_0 , \nom_err_ctr_q_reg[11]_0 , \data_err_ctr_q_reg[15]_0 , \nom_err_ctr_q_reg[13]_0 , \tx_err_ctr_q_reg[8]_0 , \FSM_sequential_curr_state_reg[0] , \cc_stat[status_ewl] , \rx_err_ctr_q_reg[8]_1 , \tx_err_ctr_q_reg[8]_1 , \rx_err_ctr_q_reg[8]_2 , DI, \tx_err_ctr_q_reg[7]_2 , \rx_err_ctr_q_reg[7]_1 , \tx_err_ctr_q_reg[7]_3 , \rx_err_ctr_q_reg[8]_3 , \rx_err_ctr_q_reg[8]_4 , \tx_err_ctr_q_reg[8]_2 , \data_err_ctr_q_reg[4]_0 , \data_err_ctr_q_reg[5]_0 , \data_err_ctr_q_reg[8]_0 , \nom_err_ctr_q_reg[2]_0 , \data_err_ctr_q_reg[0]_0 , \nom_err_ctr_q_reg[15]_0 , \mr_ctrl_out[ctr_pres_prx] , clk_sys_IBUF_BUFG, reg_q_reg, \mr_ctrl_out[ctr_pres_ptx] , reg_q_reg_0, \mr_ctrl_out[ctr_pres_enorm] , \mr_ctrl_out[ctr_pres_efd] , tx_err_ctr_q, S, sbe_IBUF, adress_IBUF, \r_data_reg[4] , \r_data_reg[4]_0 , \r_data_reg[4]_1 , \r_data_reg[6] , \r_data_reg[14] , \r_data_reg[17] , \r_data_reg[6]_0 , \r_data_reg[6]_1 , \r_data[6]_i_2_0 , \r_data_reg[16] , \r_data[18]_i_2 , \r_data_reg[20] , \r_data_reg[20]_0 , \r_data[19]_i_2 , \r_data_reg[22] , \r_data_reg[23] , \r_data_reg[20]_1 , \r_data[0]_i_2 , \r_data[1]_i_2__0 , \r_data_reg[3]_i_5 , \r_data[4]_i_2_0 , \r_data[5]_i_2 , \r_data_reg[7]_i_6 , \r_data_reg[8]_i_4 , \r_data_reg[17]_0 , \r_data_reg[17]_1 , \r_data[17]_i_2_0 , \r_data_reg[14]_0 , \r_data[11]_i_2__0 , CO, err_warning_limit_q_reg, \mr_ctrl_out[mode_rom] , \mr_ctrl_out[ctr_pres_ctpv] , \rx_err_ctr_q_reg[1]_1 , \rx_err_ctr_q_reg[4]_0 , \rx_err_ctr_q_reg[0]_0 , \rx_err_ctr_q_reg[0]_1 , \cc_stat[is_receiver] , \rx_err_ctr_q_reg[3]_1 , E, \rx_err_ctr_q[2]_i_2_0 , \nom_err_ctr_q_reg[0]_1 , \FSM_sequential_curr_state_reg[1] , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , \mr_ctrl_out[ewl_ew_limit] , \mr_ctrl_out[erp_erp_limit] , scan_mode_IBUF, rst_n_out_OBUF, \r_data_reg[20]_2 , \r_data_reg[21] , \r_data_reg[24] , \r_data_reg[2] , \r_data_reg[16]_0 , \r_data_reg[14]_i_2_0 , \r_data_reg[15] , \FSM_sequential_curr_state_reg[0]_0 , \nom_err_ctr_q_reg[0]_2 , \data_err_ctr_q_reg[0]_1 ); output mr_ctr_pres_ptx_q_reg_0; output mr_ctr_pres_enorm_q_reg_0; output mr_ctr_pres_efd_q_reg_0; output [0:0]\cc_stat[tx_err_ctr] ; output \tx_err_ctr_q_reg[7]_0 ; output \tx_err_ctr_q_reg[6]_0 ; output \tx_err_ctr_q_reg[5]_0 ; output \tx_err_ctr_q_reg[4]_0 ; output \tx_err_ctr_q_reg[3]_0 ; output \tx_err_ctr_q_reg[2]_0 ; output \tx_err_ctr_q_reg[1]_0 ; output \tx_err_ctr_q_reg[0]_0 ; output [3:0]D; output [8:0]Q; output \data_err_ctr_q_reg[2]_0 ; output \tx_err_ctr_q_reg[3]_1 ; output \tx_err_ctr_q_reg[6]_1 ; output \tx_err_ctr_q_reg[7]_1 ; output \nom_err_ctr_q_reg[0]_0 ; output \rx_err_ctr_q_reg[1]_0 ; output \rx_err_ctr_q_reg[3]_0 ; output \rx_err_ctr_q_reg[5]_0 ; output \rx_err_ctr_q_reg[7]_0 ; output \rx_err_ctr_q_reg[8]_0 ; output \nom_err_ctr_q_reg[11]_0 ; output [6:0]\data_err_ctr_q_reg[15]_0 ; output [3:0]\nom_err_ctr_q_reg[13]_0 ; output \tx_err_ctr_q_reg[8]_0 ; output [1:0]\FSM_sequential_curr_state_reg[0] ; output \cc_stat[status_ewl] ; output \rx_err_ctr_q_reg[8]_1 ; output [0:0]\tx_err_ctr_q_reg[8]_1 ; output [0:0]\rx_err_ctr_q_reg[8]_2 ; output [3:0]DI; output [3:0]\tx_err_ctr_q_reg[7]_2 ; output [3:0]\rx_err_ctr_q_reg[7]_1 ; output [3:0]\tx_err_ctr_q_reg[7]_3 ; output \rx_err_ctr_q_reg[8]_3 ; output [0:0]\rx_err_ctr_q_reg[8]_4 ; output [0:0]\tx_err_ctr_q_reg[8]_2 ; output \data_err_ctr_q_reg[4]_0 ; output \data_err_ctr_q_reg[5]_0 ; output \data_err_ctr_q_reg[8]_0 ; output \nom_err_ctr_q_reg[2]_0 ; output \data_err_ctr_q_reg[0]_0 ; output \nom_err_ctr_q_reg[15]_0 ; input \mr_ctrl_out[ctr_pres_prx] ; input clk_sys_IBUF_BUFG; input reg_q_reg; input \mr_ctrl_out[ctr_pres_ptx] ; input reg_q_reg_0; input \mr_ctrl_out[ctr_pres_enorm] ; input \mr_ctrl_out[ctr_pres_efd] ; input [0:0]tx_err_ctr_q; input [0:0]S; input [2:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[4] ; input \r_data_reg[4]_0 ; input \r_data_reg[4]_1 ; input \r_data_reg[6] ; input \r_data_reg[14] ; input \r_data_reg[17] ; input \r_data_reg[6]_0 ; input \r_data_reg[6]_1 ; input \r_data[6]_i_2_0 ; input \r_data_reg[16] ; input \r_data[18]_i_2 ; input \r_data_reg[20] ; input \r_data_reg[20]_0 ; input \r_data[19]_i_2 ; input \r_data_reg[22] ; input \r_data_reg[23] ; input \r_data_reg[20]_1 ; input \r_data[0]_i_2 ; input \r_data[1]_i_2__0 ; input \r_data_reg[3]_i_5 ; input \r_data[4]_i_2_0 ; input \r_data[5]_i_2 ; input \r_data_reg[7]_i_6 ; input \r_data_reg[8]_i_4 ; input \r_data_reg[17]_0 ; input \r_data_reg[17]_1 ; input \r_data[17]_i_2_0 ; input \r_data_reg[14]_0 ; input \r_data[11]_i_2__0 ; input [0:0]CO; input [0:0]err_warning_limit_q_reg; input \mr_ctrl_out[mode_rom] ; input [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; input \rx_err_ctr_q_reg[1]_1 ; input \rx_err_ctr_q_reg[4]_0 ; input \rx_err_ctr_q_reg[0]_0 ; input \rx_err_ctr_q_reg[0]_1 ; input \cc_stat[is_receiver] ; input \rx_err_ctr_q_reg[3]_1 ; input [0:0]E; input \rx_err_ctr_q[2]_i_2_0 ; input \nom_err_ctr_q_reg[0]_1 ; input [0:0]\FSM_sequential_curr_state_reg[1] ; input [0:0]\FSM_sequential_curr_state_reg[1]_0 ; input [1:0]\FSM_sequential_curr_state_reg[1]_1 ; input [7:0]\mr_ctrl_out[ewl_ew_limit] ; input [7:0]\mr_ctrl_out[erp_erp_limit] ; input scan_mode_IBUF; input rst_n_out_OBUF; input \r_data_reg[20]_2 ; input \r_data_reg[21] ; input \r_data_reg[24] ; input \r_data_reg[2] ; input \r_data_reg[16]_0 ; input \r_data_reg[14]_i_2_0 ; input \r_data_reg[15] ; input \FSM_sequential_curr_state_reg[0]_0 ; input [0:0]\nom_err_ctr_q_reg[0]_2 ; input [0:0]\data_err_ctr_q_reg[0]_1 ; wire [0:0]CO; wire [3:0]D; wire [3:0]DI; wire [0:0]E; wire [1:0]\FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire [0:0]\FSM_sequential_curr_state_reg[1] ; wire [0:0]\FSM_sequential_curr_state_reg[1]_0 ; wire [1:0]\FSM_sequential_curr_state_reg[1]_1 ; wire [8:0]Q; wire [0:0]S; wire [5:0]adress_IBUF; wire [8:0]\cc_stat[data_err_ctr] ; wire \cc_stat[is_receiver] ; wire [15:0]\cc_stat[norm_err_ctr] ; wire \cc_stat[status_ewl] ; wire [0:0]\cc_stat[tx_err_ctr] ; wire clk_sys_IBUF_BUFG; wire [15:0]data_err_ctr_d; wire \data_err_ctr_q_reg[0]_0 ; wire [0:0]\data_err_ctr_q_reg[0]_1 ; wire [6:0]\data_err_ctr_q_reg[15]_0 ; wire \data_err_ctr_q_reg[2]_0 ; wire \data_err_ctr_q_reg[4]_0 ; wire \data_err_ctr_q_reg[5]_0 ; wire \data_err_ctr_q_reg[8]_0 ; wire [0:0]err_warning_limit_q_reg; wire i__carry__0_i_1__1_n_0; wire i__carry__0_i_2_n_0; wire i__carry__0_i_3_n_0; wire i__carry__0_i_4_n_0; wire i__carry__0_i_5_n_0; wire i__carry__0_i_6_n_0; wire i__carry__0_i_7_n_0; wire i__carry__0_i_8_n_0; wire i__carry__1_i_1_n_0; wire i__carry_i_1__0_n_0; wire i__carry_i_2__0_n_0; wire i__carry_i_3__0_n_0; wire i__carry_i_4__0_n_0; wire i__carry_i_5__1_n_0; wire i__carry_i_6__1_n_0; wire i__carry_i_7__1_n_0; wire i__carry_i_8__1_n_0; wire i_rst_reg_n_0; wire mr_ctr_pres_efd_q_reg_0; wire mr_ctr_pres_enorm_q_reg_0; wire mr_ctr_pres_prx_q; wire mr_ctr_pres_ptx_q_reg_0; wire [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire [7:0]\mr_ctrl_out[erp_erp_limit] ; wire [7:0]\mr_ctrl_out[ewl_ew_limit] ; wire \mr_ctrl_out[mode_rom] ; wire [15:0]nom_dat_sel_ctr; wire [15:0]nom_err_ctr_d; wire \nom_err_ctr_q_reg[0]_0 ; wire \nom_err_ctr_q_reg[0]_1 ; wire [0:0]\nom_err_ctr_q_reg[0]_2 ; wire \nom_err_ctr_q_reg[11]_0 ; wire [3:0]\nom_err_ctr_q_reg[13]_0 ; wire \nom_err_ctr_q_reg[15]_0 ; wire \nom_err_ctr_q_reg[2]_0 ; wire plusOp_carry__0_n_0; wire plusOp_carry__0_n_4; wire plusOp_carry__0_n_5; wire plusOp_carry__0_n_6; wire plusOp_carry__0_n_7; wire plusOp_carry__1_n_0; wire plusOp_carry__1_n_4; wire plusOp_carry__1_n_5; wire plusOp_carry__1_n_6; wire plusOp_carry__1_n_7; wire plusOp_carry__2_n_5; wire plusOp_carry__2_n_6; wire plusOp_carry__2_n_7; wire plusOp_carry_n_0; wire plusOp_carry_n_4; wire plusOp_carry_n_5; wire plusOp_carry_n_6; wire plusOp_carry_n_7; wire \r_data[0]_i_2 ; wire \r_data[11]_i_2__0 ; wire \r_data[14]_i_4__0_n_0 ; wire \r_data[17]_i_2_0 ; wire \r_data[17]_i_2_n_0 ; wire \r_data[17]_i_4_n_0 ; wire \r_data[18]_i_2 ; wire \r_data[19]_i_2 ; wire \r_data[1]_i_2__0 ; wire \r_data[4]_i_2_0 ; wire \r_data[4]_i_2_n_0 ; wire \r_data[4]_i_4_n_0 ; wire \r_data[5]_i_2 ; wire \r_data[6]_i_2_0 ; wire \r_data[6]_i_2_n_0 ; wire \r_data[6]_i_5_n_0 ; wire \r_data[6]_i_7_n_0 ; wire \r_data_reg[14] ; wire \r_data_reg[14]_0 ; wire \r_data_reg[14]_i_2_0 ; wire \r_data_reg[14]_i_2_n_0 ; wire \r_data_reg[15] ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[17] ; wire \r_data_reg[17]_0 ; wire \r_data_reg[17]_1 ; wire \r_data_reg[20] ; wire \r_data_reg[20]_0 ; wire \r_data_reg[20]_1 ; wire \r_data_reg[20]_2 ; wire \r_data_reg[21] ; wire \r_data_reg[22] ; wire \r_data_reg[23] ; wire \r_data_reg[24] ; wire \r_data_reg[2] ; wire \r_data_reg[3]_i_5 ; wire \r_data_reg[4] ; wire \r_data_reg[4]_0 ; wire \r_data_reg[4]_1 ; wire \r_data_reg[6] ; wire \r_data_reg[6]_0 ; wire \r_data_reg[6]_1 ; wire \r_data_reg[7]_i_6 ; wire \r_data_reg[8]_i_4 ; wire reg_q_reg; wire reg_q_reg_0; wire rst_n_out_OBUF; wire [8:0]rx_err_ctr_d; wire [0:0]rx_err_ctr_q; wire \rx_err_ctr_q[0]_i_2_n_0 ; wire \rx_err_ctr_q[1]_i_2_n_0 ; wire \rx_err_ctr_q[2]_i_2_0 ; wire \rx_err_ctr_q[2]_i_2_n_0 ; wire \rx_err_ctr_q[2]_i_3_n_0 ; wire \rx_err_ctr_q[2]_i_4_n_0 ; wire \rx_err_ctr_q[2]_i_5_n_0 ; wire \rx_err_ctr_q[3]_i_2_n_0 ; wire \rx_err_ctr_q[3]_i_3_n_0 ; wire \rx_err_ctr_q[4]_i_2_n_0 ; wire \rx_err_ctr_q[4]_i_3_n_0 ; wire \rx_err_ctr_q[4]_i_4_n_0 ; wire \rx_err_ctr_q[5]_i_2_n_0 ; wire \rx_err_ctr_q[5]_i_3_n_0 ; wire \rx_err_ctr_q[6]_i_2_n_0 ; wire \rx_err_ctr_q[6]_i_3_n_0 ; wire \rx_err_ctr_q[6]_i_4_n_0 ; wire \rx_err_ctr_q[7]_i_2_n_0 ; wire \rx_err_ctr_q[8]_i_6_n_0 ; wire \rx_err_ctr_q[8]_i_7_n_0 ; wire \rx_err_ctr_q_reg[0]_0 ; wire \rx_err_ctr_q_reg[0]_1 ; wire \rx_err_ctr_q_reg[1]_0 ; wire \rx_err_ctr_q_reg[1]_1 ; wire \rx_err_ctr_q_reg[3]_0 ; wire \rx_err_ctr_q_reg[3]_1 ; wire \rx_err_ctr_q_reg[4]_0 ; wire \rx_err_ctr_q_reg[5]_0 ; wire \rx_err_ctr_q_reg[7]_0 ; wire [3:0]\rx_err_ctr_q_reg[7]_1 ; wire \rx_err_ctr_q_reg[8]_0 ; wire \rx_err_ctr_q_reg[8]_1 ; wire [0:0]\rx_err_ctr_q_reg[8]_2 ; wire \rx_err_ctr_q_reg[8]_3 ; wire [0:0]\rx_err_ctr_q_reg[8]_4 ; wire rx_err_ctr_sat1; wire rx_err_ctr_sat1_carry__0_i_1_n_0; wire rx_err_ctr_sat1_carry__0_i_2_n_0; wire rx_err_ctr_sat1_carry_i_1_n_0; wire rx_err_ctr_sat1_carry_i_2_n_0; wire rx_err_ctr_sat1_carry_i_3_n_0; wire rx_err_ctr_sat1_carry_i_4_n_0; wire rx_err_ctr_sat1_carry_i_5_n_0; wire rx_err_ctr_sat1_carry_i_6_n_0; wire rx_err_ctr_sat1_carry_i_7_n_0; wire rx_err_ctr_sat1_carry_i_9_n_0; wire rx_err_ctr_sat1_carry_n_0; wire [2:0]sbe_IBUF; wire scan_mode_IBUF; wire \tx_err_ctr_d_inferred__0/i__carry__0_n_0 ; wire \tx_err_ctr_d_inferred__0/i__carry__0_n_4 ; wire \tx_err_ctr_d_inferred__0/i__carry__0_n_5 ; wire \tx_err_ctr_d_inferred__0/i__carry__0_n_6 ; wire \tx_err_ctr_d_inferred__0/i__carry__0_n_7 ; wire \tx_err_ctr_d_inferred__0/i__carry__1_n_7 ; wire \tx_err_ctr_d_inferred__0/i__carry_n_0 ; wire \tx_err_ctr_d_inferred__0/i__carry_n_4 ; wire \tx_err_ctr_d_inferred__0/i__carry_n_5 ; wire \tx_err_ctr_d_inferred__0/i__carry_n_6 ; wire \tx_err_ctr_d_inferred__0/i__carry_n_7 ; wire [0:0]tx_err_ctr_q; wire \tx_err_ctr_q[8]_i_4_n_0 ; wire \tx_err_ctr_q_reg[0]_0 ; wire \tx_err_ctr_q_reg[1]_0 ; wire \tx_err_ctr_q_reg[2]_0 ; wire \tx_err_ctr_q_reg[3]_0 ; wire \tx_err_ctr_q_reg[3]_1 ; wire \tx_err_ctr_q_reg[4]_0 ; wire \tx_err_ctr_q_reg[5]_0 ; wire \tx_err_ctr_q_reg[6]_0 ; wire \tx_err_ctr_q_reg[6]_1 ; wire \tx_err_ctr_q_reg[7]_0 ; wire \tx_err_ctr_q_reg[7]_1 ; wire [3:0]\tx_err_ctr_q_reg[7]_2 ; wire [3:0]\tx_err_ctr_q_reg[7]_3 ; wire \tx_err_ctr_q_reg[8]_0 ; wire [0:0]\tx_err_ctr_q_reg[8]_1 ; wire [0:0]\tx_err_ctr_q_reg[8]_2 ; wire [2:0]NLW_plusOp_carry_CO_UNCONNECTED; wire [2:0]NLW_plusOp_carry__0_CO_UNCONNECTED; wire [2:0]NLW_plusOp_carry__1_CO_UNCONNECTED; wire [3:0]NLW_plusOp_carry__2_CO_UNCONNECTED; wire [3:3]NLW_plusOp_carry__2_O_UNCONNECTED; wire [2:0]NLW_rx_err_ctr_sat1_carry_CO_UNCONNECTED; wire [3:0]NLW_rx_err_ctr_sat1_carry_O_UNCONNECTED; wire [3:1]NLW_rx_err_ctr_sat1_carry__0_CO_UNCONNECTED; wire [3:0]NLW_rx_err_ctr_sat1_carry__0_O_UNCONNECTED; wire [2:0]\NLW_tx_err_ctr_d_inferred__0/i__carry_CO_UNCONNECTED ; wire [2:0]\NLW_tx_err_ctr_d_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:0]\NLW_tx_err_ctr_d_inferred__0/i__carry__1_CO_UNCONNECTED ; wire [3:1]\NLW_tx_err_ctr_d_inferred__0/i__carry__1_O_UNCONNECTED ; LUT6 #( .INIT(64'h0202020202020E3E)) \FSM_sequential_curr_state[0]_i_1__5 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_1 [0]), .I2(\FSM_sequential_curr_state_reg[1]_1 [1]), .I3(\cc_stat[tx_err_ctr] ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[1] ), .O(\FSM_sequential_curr_state_reg[0] [0])); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT5 #( .INIT(32'h00E00EE0)) \FSM_sequential_curr_state[1]_i_1__4 (.I0(\FSM_sequential_curr_state_reg[1] ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_1 [0]), .I3(\FSM_sequential_curr_state_reg[1]_1 [1]), .I4(\cc_stat[tx_err_ctr] ), .O(\FSM_sequential_curr_state_reg[0] [1])); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT4 #( .INIT(16'h0151)) \data_err_ctr_q[0]_i_1 (.I0(mr_ctr_pres_efd_q_reg_0), .I1(\cc_stat[data_err_ctr] [0]), .I2(\nom_err_ctr_q_reg[0]_1 ), .I3(\cc_stat[norm_err_ctr] [0]), .O(data_err_ctr_d[0])); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[10]_i_1 (.I0(plusOp_carry__1_n_6), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[10])); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[11]_i_1 (.I0(plusOp_carry__1_n_5), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[11])); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[12]_i_1 (.I0(plusOp_carry__1_n_4), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[12])); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[13]_i_1 (.I0(plusOp_carry__2_n_7), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[13])); (* SOFT_HLUTNM = "soft_lutpair160" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[14]_i_1 (.I0(plusOp_carry__2_n_6), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[14])); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[15]_i_2 (.I0(plusOp_carry__2_n_5), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[15])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[1]_i_1 (.I0(plusOp_carry_n_7), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[1])); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[2]_i_1 (.I0(plusOp_carry_n_6), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[2])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[3]_i_1 (.I0(plusOp_carry_n_5), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[3])); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[4]_i_1 (.I0(plusOp_carry_n_4), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[4])); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[5]_i_1 (.I0(plusOp_carry__0_n_7), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[5])); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[6]_i_1 (.I0(plusOp_carry__0_n_6), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[6])); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[7]_i_1 (.I0(plusOp_carry__0_n_5), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[7])); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[8]_i_1 (.I0(plusOp_carry__0_n_4), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[8])); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT2 #( .INIT(4'h2)) \data_err_ctr_q[9]_i_1 (.I0(plusOp_carry__1_n_7), .I1(mr_ctr_pres_efd_q_reg_0), .O(data_err_ctr_d[9])); FDCE \data_err_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[0]), .Q(\cc_stat[data_err_ctr] [0])); FDCE \data_err_ctr_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[10]), .Q(\data_err_ctr_q_reg[15]_0 [1])); FDCE \data_err_ctr_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[11]), .Q(\data_err_ctr_q_reg[15]_0 [2])); FDCE \data_err_ctr_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[12]), .Q(\data_err_ctr_q_reg[15]_0 [3])); FDCE \data_err_ctr_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[13]), .Q(\data_err_ctr_q_reg[15]_0 [4])); FDCE \data_err_ctr_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[14]), .Q(\data_err_ctr_q_reg[15]_0 [5])); FDCE \data_err_ctr_q_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[15]), .Q(\data_err_ctr_q_reg[15]_0 [6])); FDCE \data_err_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[1]), .Q(\cc_stat[data_err_ctr] [1])); FDCE \data_err_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[2]), .Q(\cc_stat[data_err_ctr] [2])); FDCE \data_err_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[3]), .Q(\cc_stat[data_err_ctr] [3])); FDCE \data_err_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[4]), .Q(\cc_stat[data_err_ctr] [4])); FDCE \data_err_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[5]), .Q(\cc_stat[data_err_ctr] [5])); FDCE \data_err_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[6]), .Q(\cc_stat[data_err_ctr] [6])); FDCE \data_err_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[7]), .Q(\cc_stat[data_err_ctr] [7])); FDCE \data_err_ctr_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[8]), .Q(\cc_stat[data_err_ctr] [8])); FDCE \data_err_ctr_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(\data_err_ctr_q_reg[0]_1 ), .CLR(i_rst_reg_n_0), .D(data_err_ctr_d[9]), .Q(\data_err_ctr_q_reg[15]_0 [0])); LUT1 #( .INIT(2'h1)) err_warning_limit_q1_carry__0_i_1 (.I0(Q[8]), .O(\rx_err_ctr_q_reg[8]_4 )); LUT4 #( .INIT(16'h22B2)) err_warning_limit_q1_carry_i_1 (.I0(Q[7]), .I1(\mr_ctrl_out[ewl_ew_limit] [7]), .I2(Q[6]), .I3(\mr_ctrl_out[ewl_ew_limit] [6]), .O(DI[3])); LUT4 #( .INIT(16'h22B2)) err_warning_limit_q1_carry_i_2 (.I0(Q[5]), .I1(\mr_ctrl_out[ewl_ew_limit] [5]), .I2(Q[4]), .I3(\mr_ctrl_out[ewl_ew_limit] [4]), .O(DI[2])); LUT4 #( .INIT(16'h22B2)) err_warning_limit_q1_carry_i_3 (.I0(Q[3]), .I1(\mr_ctrl_out[ewl_ew_limit] [3]), .I2(Q[2]), .I3(\mr_ctrl_out[ewl_ew_limit] [2]), .O(DI[1])); LUT4 #( .INIT(16'h22B2)) err_warning_limit_q1_carry_i_4 (.I0(Q[1]), .I1(\mr_ctrl_out[ewl_ew_limit] [1]), .I2(Q[0]), .I3(\mr_ctrl_out[ewl_ew_limit] [0]), .O(DI[0])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT2 #( .INIT(4'hE)) err_warning_limit_q_i_1 (.I0(err_warning_limit_q_reg), .I1(CO), .O(\cc_stat[status_ewl] )); LUT1 #( .INIT(2'h1)) i__carry__0_i_1__0 (.I0(\cc_stat[tx_err_ctr] ), .O(\tx_err_ctr_q_reg[8]_1 )); LUT2 #( .INIT(4'h2)) i__carry__0_i_1__1 (.I0(\tx_err_ctr_q_reg[7]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry__0_i_1__1_n_0)); LUT1 #( .INIT(2'h1)) i__carry__0_i_1__2 (.I0(\cc_stat[tx_err_ctr] ), .O(\tx_err_ctr_q_reg[8]_2 )); LUT2 #( .INIT(4'h2)) i__carry__0_i_2 (.I0(\tx_err_ctr_q_reg[6]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry__0_i_2_n_0)); LUT2 #( .INIT(4'h2)) i__carry__0_i_3 (.I0(\tx_err_ctr_q_reg[5]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry__0_i_3_n_0)); LUT2 #( .INIT(4'h2)) i__carry__0_i_4 (.I0(\tx_err_ctr_q_reg[4]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry__0_i_4_n_0)); LUT4 #( .INIT(16'hF606)) i__carry__0_i_5 (.I0(\tx_err_ctr_q_reg[7]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [7]), .O(i__carry__0_i_5_n_0)); LUT4 #( .INIT(16'hF606)) i__carry__0_i_6 (.I0(\tx_err_ctr_q_reg[6]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [6]), .O(i__carry__0_i_6_n_0)); LUT4 #( .INIT(16'hF606)) i__carry__0_i_7 (.I0(\tx_err_ctr_q_reg[5]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [5]), .O(i__carry__0_i_7_n_0)); LUT4 #( .INIT(16'hF606)) i__carry__0_i_8 (.I0(\tx_err_ctr_q_reg[4]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [4]), .O(i__carry__0_i_8_n_0)); LUT4 #( .INIT(16'h8BB8)) i__carry__1_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [8]), .I1(mr_ctr_pres_ptx_q_reg_0), .I2(\cc_stat[tx_err_ctr] ), .I3(\rx_err_ctr_q_reg[1]_1 ), .O(i__carry__1_i_1_n_0)); LUT2 #( .INIT(4'h2)) i__carry_i_1__0 (.I0(\tx_err_ctr_q_reg[3]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry_i_1__0_n_0)); LUT4 #( .INIT(16'h22B2)) i__carry_i_1__2 (.I0(\tx_err_ctr_q_reg[7]_0 ), .I1(\mr_ctrl_out[erp_erp_limit] [7]), .I2(\tx_err_ctr_q_reg[6]_0 ), .I3(\mr_ctrl_out[erp_erp_limit] [6]), .O(\tx_err_ctr_q_reg[7]_3 [3])); LUT2 #( .INIT(4'h2)) i__carry_i_2__0 (.I0(\tx_err_ctr_q_reg[2]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry_i_2__0_n_0)); LUT4 #( .INIT(16'h22B2)) i__carry_i_2__2 (.I0(\tx_err_ctr_q_reg[5]_0 ), .I1(\mr_ctrl_out[erp_erp_limit] [5]), .I2(\tx_err_ctr_q_reg[4]_0 ), .I3(\mr_ctrl_out[erp_erp_limit] [4]), .O(\tx_err_ctr_q_reg[7]_3 [2])); LUT2 #( .INIT(4'h2)) i__carry_i_3__0 (.I0(\tx_err_ctr_q_reg[1]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry_i_3__0_n_0)); LUT4 #( .INIT(16'h22B2)) i__carry_i_3__2 (.I0(\tx_err_ctr_q_reg[3]_0 ), .I1(\mr_ctrl_out[erp_erp_limit] [3]), .I2(\tx_err_ctr_q_reg[2]_0 ), .I3(\mr_ctrl_out[erp_erp_limit] [2]), .O(\tx_err_ctr_q_reg[7]_3 [1])); LUT2 #( .INIT(4'h2)) i__carry_i_4__0 (.I0(\tx_err_ctr_q_reg[0]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .O(i__carry_i_4__0_n_0)); LUT4 #( .INIT(16'h22B2)) i__carry_i_4__2 (.I0(\tx_err_ctr_q_reg[1]_0 ), .I1(\mr_ctrl_out[erp_erp_limit] [1]), .I2(\tx_err_ctr_q_reg[0]_0 ), .I3(\mr_ctrl_out[erp_erp_limit] [0]), .O(\tx_err_ctr_q_reg[7]_3 [0])); LUT4 #( .INIT(16'h9009)) i__carry_i_5 (.I0(\tx_err_ctr_q_reg[7]_0 ), .I1(\mr_ctrl_out[ewl_ew_limit] [7]), .I2(\tx_err_ctr_q_reg[6]_0 ), .I3(\mr_ctrl_out[ewl_ew_limit] [6]), .O(\tx_err_ctr_q_reg[7]_2 [3])); LUT3 #( .INIT(8'hD1)) i__carry_i_5__1 (.I0(\tx_err_ctr_q_reg[3]_0 ), .I1(mr_ctr_pres_ptx_q_reg_0), .I2(\mr_ctrl_out[ctr_pres_ctpv] [3]), .O(i__carry_i_5__1_n_0)); LUT4 #( .INIT(16'h9009)) i__carry_i_6 (.I0(\tx_err_ctr_q_reg[5]_0 ), .I1(\mr_ctrl_out[ewl_ew_limit] [5]), .I2(\tx_err_ctr_q_reg[4]_0 ), .I3(\mr_ctrl_out[ewl_ew_limit] [4]), .O(\tx_err_ctr_q_reg[7]_2 [2])); LUT4 #( .INIT(16'hF606)) i__carry_i_6__1 (.I0(\tx_err_ctr_q_reg[2]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [2]), .O(i__carry_i_6__1_n_0)); LUT4 #( .INIT(16'h9009)) i__carry_i_7 (.I0(\tx_err_ctr_q_reg[3]_0 ), .I1(\mr_ctrl_out[ewl_ew_limit] [3]), .I2(\tx_err_ctr_q_reg[2]_0 ), .I3(\mr_ctrl_out[ewl_ew_limit] [2]), .O(\tx_err_ctr_q_reg[7]_2 [1])); LUT4 #( .INIT(16'hF606)) i__carry_i_7__1 (.I0(\tx_err_ctr_q_reg[1]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [1]), .O(i__carry_i_7__1_n_0)); LUT4 #( .INIT(16'h9009)) i__carry_i_8 (.I0(\tx_err_ctr_q_reg[1]_0 ), .I1(\mr_ctrl_out[ewl_ew_limit] [1]), .I2(\tx_err_ctr_q_reg[0]_0 ), .I3(\mr_ctrl_out[ewl_ew_limit] [0]), .O(\tx_err_ctr_q_reg[7]_2 [0])); LUT4 #( .INIT(16'hF606)) i__carry_i_8__1 (.I0(\tx_err_ctr_q_reg[0]_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(mr_ctr_pres_ptx_q_reg_0), .I3(\mr_ctrl_out[ctr_pres_ctpv] [0]), .O(i__carry_i_8__1_n_0)); rst_reg_60 i_rst_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg(i_rst_reg_n_0), .reg_q_reg_0(reg_q_reg_0), .reg_q_reg_1(reg_q_reg), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT2 #( .INIT(4'h1)) int_status_i_2__4 (.I0(CO), .I1(err_warning_limit_q_reg), .O(\rx_err_ctr_q_reg[8]_1 )); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT2 #( .INIT(4'h1)) int_status_i_3__2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[1] ), .O(\rx_err_ctr_q_reg[8]_3 )); FDCE mr_ctr_pres_efd_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg), .D(\mr_ctrl_out[ctr_pres_efd] ), .Q(mr_ctr_pres_efd_q_reg_0)); FDCE mr_ctr_pres_enorm_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg), .D(\mr_ctrl_out[ctr_pres_enorm] ), .Q(mr_ctr_pres_enorm_q_reg_0)); FDCE mr_ctr_pres_prx_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg), .D(\mr_ctrl_out[ctr_pres_prx] ), .Q(mr_ctr_pres_prx_q)); FDCE mr_ctr_pres_ptx_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg), .D(\mr_ctrl_out[ctr_pres_ptx] ), .Q(mr_ctr_pres_ptx_q_reg_0)); LUT1 #( .INIT(2'h1)) next_state2_carry__0_i_1 (.I0(Q[8]), .O(\rx_err_ctr_q_reg[8]_2 )); LUT4 #( .INIT(16'h22B2)) next_state2_carry_i_1 (.I0(Q[7]), .I1(\mr_ctrl_out[erp_erp_limit] [7]), .I2(Q[6]), .I3(\mr_ctrl_out[erp_erp_limit] [6]), .O(\rx_err_ctr_q_reg[7]_1 [3])); LUT4 #( .INIT(16'h22B2)) next_state2_carry_i_2 (.I0(Q[5]), .I1(\mr_ctrl_out[erp_erp_limit] [5]), .I2(Q[4]), .I3(\mr_ctrl_out[erp_erp_limit] [4]), .O(\rx_err_ctr_q_reg[7]_1 [2])); LUT4 #( .INIT(16'h22B2)) next_state2_carry_i_3 (.I0(Q[3]), .I1(\mr_ctrl_out[erp_erp_limit] [3]), .I2(Q[2]), .I3(\mr_ctrl_out[erp_erp_limit] [2]), .O(\rx_err_ctr_q_reg[7]_1 [1])); LUT4 #( .INIT(16'h22B2)) next_state2_carry_i_4 (.I0(Q[1]), .I1(\mr_ctrl_out[erp_erp_limit] [1]), .I2(Q[0]), .I3(\mr_ctrl_out[erp_erp_limit] [0]), .O(\rx_err_ctr_q_reg[7]_1 [0])); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h0151)) \nom_err_ctr_q[0]_i_1 (.I0(mr_ctr_pres_enorm_q_reg_0), .I1(\cc_stat[data_err_ctr] [0]), .I2(\nom_err_ctr_q_reg[0]_1 ), .I3(\cc_stat[norm_err_ctr] [0]), .O(nom_err_ctr_d[0])); (* SOFT_HLUTNM = "soft_lutpair164" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[10]_i_1 (.I0(plusOp_carry__1_n_6), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[10])); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[11]_i_1 (.I0(plusOp_carry__1_n_5), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[11])); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[12]_i_1 (.I0(plusOp_carry__1_n_4), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[12])); (* SOFT_HLUTNM = "soft_lutpair164" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[13]_i_1 (.I0(plusOp_carry__2_n_7), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[13])); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[14]_i_1 (.I0(plusOp_carry__2_n_6), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[14])); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[15]_i_2 (.I0(plusOp_carry__2_n_5), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[15])); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[1]_i_1 (.I0(plusOp_carry_n_7), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[1])); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[2]_i_1 (.I0(plusOp_carry_n_6), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[2])); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[3]_i_1 (.I0(plusOp_carry_n_5), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[3])); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[4]_i_1 (.I0(plusOp_carry_n_4), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[4])); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[5]_i_1 (.I0(plusOp_carry__0_n_7), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[5])); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[6]_i_1 (.I0(plusOp_carry__0_n_6), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[6])); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[7]_i_1 (.I0(plusOp_carry__0_n_5), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[7])); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[8]_i_1 (.I0(plusOp_carry__0_n_4), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[8])); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT2 #( .INIT(4'h2)) \nom_err_ctr_q[9]_i_1 (.I0(plusOp_carry__1_n_7), .I1(mr_ctr_pres_enorm_q_reg_0), .O(nom_err_ctr_d[9])); FDCE \nom_err_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[0]), .Q(\cc_stat[norm_err_ctr] [0])); FDCE \nom_err_ctr_q_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[10]), .Q(\nom_err_ctr_q_reg[13]_0 [1])); FDCE \nom_err_ctr_q_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[11]), .Q(\cc_stat[norm_err_ctr] [11])); FDCE \nom_err_ctr_q_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[12]), .Q(\nom_err_ctr_q_reg[13]_0 [2])); FDCE \nom_err_ctr_q_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[13]), .Q(\nom_err_ctr_q_reg[13]_0 [3])); FDCE \nom_err_ctr_q_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[14]), .Q(\cc_stat[norm_err_ctr] [14])); FDCE \nom_err_ctr_q_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[15]), .Q(\cc_stat[norm_err_ctr] [15])); FDCE \nom_err_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[1]), .Q(\cc_stat[norm_err_ctr] [1])); FDCE \nom_err_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[2]), .Q(\cc_stat[norm_err_ctr] [2])); FDCE \nom_err_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[3]), .Q(\cc_stat[norm_err_ctr] [3])); FDCE \nom_err_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[4]), .Q(\cc_stat[norm_err_ctr] [4])); FDCE \nom_err_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[5]), .Q(\cc_stat[norm_err_ctr] [5])); FDCE \nom_err_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[6]), .Q(\cc_stat[norm_err_ctr] [6])); FDCE \nom_err_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[7]), .Q(\cc_stat[norm_err_ctr] [7])); FDCE \nom_err_ctr_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[8]), .Q(\cc_stat[norm_err_ctr] [8])); FDCE \nom_err_ctr_q_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(\nom_err_ctr_q_reg[0]_2 ), .CLR(i_rst_reg_n_0), .D(nom_err_ctr_d[9]), .Q(\nom_err_ctr_q_reg[13]_0 [0])); (* ADDER_THRESHOLD = "35" *) CARRY4 plusOp_carry (.CI(1'b0), .CO({plusOp_carry_n_0,NLW_plusOp_carry_CO_UNCONNECTED[2:0]}), .CYINIT(nom_dat_sel_ctr[0]), .DI({1'b0,1'b0,1'b0,1'b0}), .O({plusOp_carry_n_4,plusOp_carry_n_5,plusOp_carry_n_6,plusOp_carry_n_7}), .S(nom_dat_sel_ctr[4:1])); (* ADDER_THRESHOLD = "35" *) CARRY4 plusOp_carry__0 (.CI(plusOp_carry_n_0), .CO({plusOp_carry__0_n_0,NLW_plusOp_carry__0_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({plusOp_carry__0_n_4,plusOp_carry__0_n_5,plusOp_carry__0_n_6,plusOp_carry__0_n_7}), .S(nom_dat_sel_ctr[8:5])); LUT3 #( .INIT(8'hB8)) plusOp_carry__0_i_1 (.I0(\cc_stat[norm_err_ctr] [8]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [8]), .O(nom_dat_sel_ctr[8])); LUT3 #( .INIT(8'hB8)) plusOp_carry__0_i_2 (.I0(\cc_stat[norm_err_ctr] [7]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [7]), .O(nom_dat_sel_ctr[7])); LUT3 #( .INIT(8'hB8)) plusOp_carry__0_i_3 (.I0(\cc_stat[norm_err_ctr] [6]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [6]), .O(nom_dat_sel_ctr[6])); LUT3 #( .INIT(8'hB8)) plusOp_carry__0_i_4 (.I0(\cc_stat[norm_err_ctr] [5]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [5]), .O(nom_dat_sel_ctr[5])); (* ADDER_THRESHOLD = "35" *) CARRY4 plusOp_carry__1 (.CI(plusOp_carry__0_n_0), .CO({plusOp_carry__1_n_0,NLW_plusOp_carry__1_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({plusOp_carry__1_n_4,plusOp_carry__1_n_5,plusOp_carry__1_n_6,plusOp_carry__1_n_7}), .S(nom_dat_sel_ctr[12:9])); LUT3 #( .INIT(8'hB8)) plusOp_carry__1_i_1 (.I0(\nom_err_ctr_q_reg[13]_0 [2]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [3]), .O(nom_dat_sel_ctr[12])); LUT3 #( .INIT(8'hB8)) plusOp_carry__1_i_2 (.I0(\cc_stat[norm_err_ctr] [11]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [2]), .O(nom_dat_sel_ctr[11])); LUT3 #( .INIT(8'hB8)) plusOp_carry__1_i_3 (.I0(\nom_err_ctr_q_reg[13]_0 [1]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [1]), .O(nom_dat_sel_ctr[10])); LUT3 #( .INIT(8'hB8)) plusOp_carry__1_i_4 (.I0(\nom_err_ctr_q_reg[13]_0 [0]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [0]), .O(nom_dat_sel_ctr[9])); (* ADDER_THRESHOLD = "35" *) CARRY4 plusOp_carry__2 (.CI(plusOp_carry__1_n_0), .CO(NLW_plusOp_carry__2_CO_UNCONNECTED[3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({NLW_plusOp_carry__2_O_UNCONNECTED[3],plusOp_carry__2_n_5,plusOp_carry__2_n_6,plusOp_carry__2_n_7}), .S({1'b0,nom_dat_sel_ctr[15:13]})); LUT3 #( .INIT(8'hB8)) plusOp_carry__2_i_1 (.I0(\cc_stat[norm_err_ctr] [15]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [6]), .O(nom_dat_sel_ctr[15])); LUT3 #( .INIT(8'hB8)) plusOp_carry__2_i_2 (.I0(\cc_stat[norm_err_ctr] [14]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [5]), .O(nom_dat_sel_ctr[14])); LUT3 #( .INIT(8'hB8)) plusOp_carry__2_i_3 (.I0(\nom_err_ctr_q_reg[13]_0 [3]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\data_err_ctr_q_reg[15]_0 [4]), .O(nom_dat_sel_ctr[13])); LUT3 #( .INIT(8'hB8)) plusOp_carry_i_1 (.I0(\cc_stat[norm_err_ctr] [0]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [0]), .O(nom_dat_sel_ctr[0])); LUT3 #( .INIT(8'hB8)) plusOp_carry_i_2 (.I0(\cc_stat[norm_err_ctr] [4]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [4]), .O(nom_dat_sel_ctr[4])); LUT3 #( .INIT(8'hB8)) plusOp_carry_i_3 (.I0(\cc_stat[norm_err_ctr] [3]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [3]), .O(nom_dat_sel_ctr[3])); LUT3 #( .INIT(8'hB8)) plusOp_carry_i_4 (.I0(\cc_stat[norm_err_ctr] [2]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [2]), .O(nom_dat_sel_ctr[2])); LUT3 #( .INIT(8'hB8)) plusOp_carry_i_5 (.I0(\cc_stat[norm_err_ctr] [1]), .I1(\nom_err_ctr_q_reg[0]_1 ), .I2(\cc_stat[data_err_ctr] [1]), .O(nom_dat_sel_ctr[1])); LUT6 #( .INIT(64'hA8080000AAAAAAAA)) \r_data[0]_i_6 (.I0(\r_data_reg[20]_1 ), .I1(\cc_stat[norm_err_ctr] [0]), .I2(\r_data_reg[20]_0 ), .I3(Q[0]), .I4(\r_data_reg[20] ), .I5(\r_data[0]_i_2 ), .O(\nom_err_ctr_q_reg[0]_0 )); LUT5 #( .INIT(32'h0000DFFF)) \r_data[11]_i_6 (.I0(\cc_stat[norm_err_ctr] [11]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(adress_IBUF[2]), .I4(\r_data[11]_i_2__0 ), .O(\nom_err_ctr_q_reg[11]_0 )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[14]_i_1 (.I0(sbe_IBUF[1]), .I1(\r_data_reg[14]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[14] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[2])); LUT6 #( .INIT(64'h0000DFFFFFFCFFFC)) \r_data[14]_i_4__0 (.I0(\cc_stat[norm_err_ctr] [14]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(adress_IBUF[2]), .I4(\r_data_reg[14]_i_2_0 ), .I5(adress_IBUF[3]), .O(\r_data[14]_i_4__0_n_0 )); LUT6 #( .INIT(64'h0000DFFFFFFCFFFC)) \r_data[15]_i_3__0 (.I0(\cc_stat[norm_err_ctr] [15]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(adress_IBUF[2]), .I4(\r_data_reg[15] ), .I5(adress_IBUF[3]), .O(\nom_err_ctr_q_reg[15]_0 )); LUT6 #( .INIT(64'h1DFF0000FFFFFFFF)) \r_data[16]_i_4__0 (.I0(\cc_stat[data_err_ctr] [0]), .I1(\r_data_reg[20]_0 ), .I2(\tx_err_ctr_q_reg[0]_0 ), .I3(\r_data_reg[20] ), .I4(\r_data_reg[16]_0 ), .I5(\r_data_reg[16] ), .O(\data_err_ctr_q_reg[0]_0 )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[17]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data[17]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[17] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[3])); LUT6 #( .INIT(64'h3333223303332233)) \r_data[17]_i_2 (.I0(\r_data[17]_i_4_n_0 ), .I1(\r_data_reg[17]_0 ), .I2(\r_data_reg[17]_1 ), .I3(adress_IBUF[3]), .I4(adress_IBUF[4]), .I5(adress_IBUF[2]), .O(\r_data[17]_i_2_n_0 )); LUT6 #( .INIT(64'hD1D1D1DDDDDDD1DD)) \r_data[17]_i_4 (.I0(\r_data[17]_i_2_0 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(\tx_err_ctr_q_reg[1]_0 ), .I4(adress_IBUF[0]), .I5(\cc_stat[data_err_ctr] [1]), .O(\r_data[17]_i_4_n_0 )); LUT6 #( .INIT(64'hA2A2A2020202A202)) \r_data[18]_i_8 (.I0(\r_data_reg[16] ), .I1(\r_data[18]_i_2 ), .I2(\r_data_reg[20] ), .I3(\cc_stat[data_err_ctr] [2]), .I4(\r_data_reg[20]_0 ), .I5(\tx_err_ctr_q_reg[2]_0 ), .O(\data_err_ctr_q_reg[2]_0 )); LUT6 #( .INIT(64'hFFFF1DFF00001D00)) \r_data[19]_i_5 (.I0(\tx_err_ctr_q_reg[3]_0 ), .I1(adress_IBUF[0]), .I2(\cc_stat[data_err_ctr] [3]), .I3(adress_IBUF[2]), .I4(adress_IBUF[1]), .I5(\r_data[19]_i_2 ), .O(\tx_err_ctr_q_reg[3]_1 )); LUT6 #( .INIT(64'h00000000F3F7FFF7)) \r_data[1]_i_6 (.I0(Q[1]), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\cc_stat[norm_err_ctr] [1]), .I5(\r_data[1]_i_2__0 ), .O(\rx_err_ctr_q_reg[1]_0 )); LUT6 #( .INIT(64'h222EEE2EFFFFFFFF)) \r_data[20]_i_3__0 (.I0(\r_data_reg[20]_2 ), .I1(\r_data_reg[20] ), .I2(\cc_stat[data_err_ctr] [4]), .I3(\r_data_reg[20]_0 ), .I4(\tx_err_ctr_q_reg[4]_0 ), .I5(\r_data_reg[20]_1 ), .O(\data_err_ctr_q_reg[4]_0 )); LUT6 #( .INIT(64'h222EEE2EFFFFFFFF)) \r_data[21]_i_3__0 (.I0(\r_data_reg[21] ), .I1(\r_data_reg[20] ), .I2(\cc_stat[data_err_ctr] [5]), .I3(\r_data_reg[20]_0 ), .I4(\tx_err_ctr_q_reg[5]_0 ), .I5(\r_data_reg[20]_1 ), .O(\data_err_ctr_q_reg[5]_0 )); LUT6 #( .INIT(64'hFFFF1DFF00001D00)) \r_data[22]_i_3 (.I0(\tx_err_ctr_q_reg[6]_0 ), .I1(adress_IBUF[0]), .I2(\cc_stat[data_err_ctr] [6]), .I3(adress_IBUF[2]), .I4(adress_IBUF[1]), .I5(\r_data_reg[22] ), .O(\tx_err_ctr_q_reg[6]_1 )); LUT6 #( .INIT(64'hFFFF1DFF00001D00)) \r_data[23]_i_3 (.I0(\tx_err_ctr_q_reg[7]_0 ), .I1(adress_IBUF[0]), .I2(\cc_stat[data_err_ctr] [7]), .I3(adress_IBUF[2]), .I4(adress_IBUF[1]), .I5(\r_data_reg[23] ), .O(\tx_err_ctr_q_reg[7]_1 )); LUT6 #( .INIT(64'h222EEE2EFFFFFFFF)) \r_data[24]_i_3__0 (.I0(\r_data_reg[24] ), .I1(\r_data_reg[20] ), .I2(\cc_stat[data_err_ctr] [8]), .I3(\r_data_reg[20]_0 ), .I4(\cc_stat[tx_err_ctr] ), .I5(\r_data_reg[20]_1 ), .O(\data_err_ctr_q_reg[8]_0 )); LUT6 #( .INIT(64'h11155515FFFFFFFF)) \r_data[2]_i_3__0 (.I0(\r_data_reg[2] ), .I1(\r_data_reg[20] ), .I2(\cc_stat[norm_err_ctr] [2]), .I3(\r_data_reg[20]_0 ), .I4(Q[2]), .I5(\r_data_reg[20]_1 ), .O(\nom_err_ctr_q_reg[2]_0 )); LUT6 #( .INIT(64'hA2A2A2AAAAAAA2AA)) \r_data[3]_i_10 (.I0(\r_data_reg[3]_i_5 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(Q[3]), .I4(adress_IBUF[0]), .I5(\cc_stat[norm_err_ctr] [3]), .O(\rx_err_ctr_q_reg[3]_0 )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[4]_i_1 (.I0(sbe_IBUF[0]), .I1(\r_data[4]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[4] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[0])); LUT5 #( .INIT(32'h33223303)) \r_data[4]_i_2 (.I0(\r_data[4]_i_4_n_0 ), .I1(\r_data_reg[4]_0 ), .I2(\r_data_reg[4]_1 ), .I3(adress_IBUF[4]), .I4(adress_IBUF[3]), .O(\r_data[4]_i_2_n_0 )); LUT6 #( .INIT(64'h00000000F3F7FFF7)) \r_data[4]_i_4 (.I0(Q[4]), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\cc_stat[norm_err_ctr] [4]), .I5(\r_data[4]_i_2_0 ), .O(\r_data[4]_i_4_n_0 )); LUT6 #( .INIT(64'hA2A2A2AAAAAAA2AA)) \r_data[5]_i_6 (.I0(\r_data[5]_i_2 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(Q[5]), .I4(adress_IBUF[0]), .I5(\cc_stat[norm_err_ctr] [5]), .O(\rx_err_ctr_q_reg[5]_0 )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[6]_i_1 (.I0(sbe_IBUF[0]), .I1(\r_data[6]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[6] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[1])); LUT6 #( .INIT(64'hB888B888B8BBB888)) \r_data[6]_i_2 (.I0(\r_data_reg[6]_0 ), .I1(adress_IBUF[4]), .I2(\r_data[6]_i_5_n_0 ), .I3(adress_IBUF[3]), .I4(\r_data_reg[6]_1 ), .I5(\r_data[6]_i_7_n_0 ), .O(\r_data[6]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFF1DFF00001D00)) \r_data[6]_i_5 (.I0(Q[6]), .I1(adress_IBUF[0]), .I2(\cc_stat[norm_err_ctr] [6]), .I3(adress_IBUF[2]), .I4(adress_IBUF[1]), .I5(\r_data[6]_i_2_0 ), .O(\r_data[6]_i_5_n_0 )); LUT6 #( .INIT(64'h00000E0E0000FF0F)) \r_data[6]_i_7 (.I0(CO), .I1(err_warning_limit_q_reg), .I2(adress_IBUF[0]), .I3(\mr_ctrl_out[mode_rom] ), .I4(adress_IBUF[2]), .I5(adress_IBUF[1]), .O(\r_data[6]_i_7_n_0 )); LUT6 #( .INIT(64'hA2A2A2AAAAAAA2AA)) \r_data[7]_i_11 (.I0(\r_data_reg[7]_i_6 ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(Q[7]), .I4(adress_IBUF[0]), .I5(\cc_stat[norm_err_ctr] [7]), .O(\rx_err_ctr_q_reg[7]_0 )); LUT6 #( .INIT(64'h00000000F3F7FFF7)) \r_data[8]_i_7 (.I0(Q[8]), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\cc_stat[norm_err_ctr] [8]), .I5(\r_data_reg[8]_i_4 ), .O(\rx_err_ctr_q_reg[8]_0 )); MUXF7 \r_data_reg[14]_i_2 (.I0(\r_data[14]_i_4__0_n_0 ), .I1(\r_data_reg[14]_0 ), .O(\r_data_reg[14]_i_2_n_0 ), .S(adress_IBUF[4])); (* SOFT_HLUTNM = "soft_lutpair162" *) LUT3 #( .INIT(8'hB8)) \rx_err_ctr_q[0]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [0]), .I1(mr_ctr_pres_prx_q), .I2(\rx_err_ctr_q[0]_i_2_n_0 ), .O(rx_err_ctr_d[0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0FFF0F001FFF10FF)) \rx_err_ctr_q[0]_i_2 (.I0(Q[7]), .I1(Q[8]), .I2(\rx_err_ctr_q_reg[1]_1 ), .I3(\rx_err_ctr_q_reg[4]_0 ), .I4(rx_err_ctr_sat1), .I5(Q[0]), .O(\rx_err_ctr_q[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair162" *) LUT3 #( .INIT(8'hB8)) \rx_err_ctr_q[1]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [1]), .I1(mr_ctr_pres_prx_q), .I2(\rx_err_ctr_q[1]_i_2_n_0 ), .O(rx_err_ctr_d[1])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hBFB03F3F3F0FBF80)) \rx_err_ctr_q[1]_i_2 (.I0(\rx_err_ctr_q[2]_i_3_n_0 ), .I1(\rx_err_ctr_q_reg[1]_1 ), .I2(\rx_err_ctr_q_reg[4]_0 ), .I3(rx_err_ctr_sat1), .I4(Q[0]), .I5(Q[1]), .O(\rx_err_ctr_q[1]_i_2_n_0 )); LUT3 #( .INIT(8'hB8)) \rx_err_ctr_q[2]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [2]), .I1(mr_ctr_pres_prx_q), .I2(\rx_err_ctr_q[2]_i_2_n_0 ), .O(rx_err_ctr_d[2])); LUT6 #( .INIT(64'h2F2F2F208F808F8F)) \rx_err_ctr_q[2]_i_2 (.I0(\rx_err_ctr_q[2]_i_3_n_0 ), .I1(\rx_err_ctr_q[2]_i_4_n_0 ), .I2(\rx_err_ctr_q_reg[0]_0 ), .I3(rx_err_ctr_sat1), .I4(\rx_err_ctr_q[2]_i_5_n_0 ), .I5(Q[2]), .O(\rx_err_ctr_q[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair163" *) LUT2 #( .INIT(4'h1)) \rx_err_ctr_q[2]_i_3 (.I0(Q[8]), .I1(Q[7]), .O(\rx_err_ctr_q[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair161" *) LUT2 #( .INIT(4'h1)) \rx_err_ctr_q[2]_i_4 (.I0(Q[0]), .I1(Q[1]), .O(\rx_err_ctr_q[2]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFF7FFFFFFFFFF)) \rx_err_ctr_q[2]_i_5 (.I0(Q[1]), .I1(Q[0]), .I2(\rx_err_ctr_q[2]_i_2_0 ), .I3(\cc_stat[is_receiver] ), .I4(\mr_ctrl_out[mode_rom] ), .I5(E), .O(\rx_err_ctr_q[2]_i_5_n_0 )); LUT6 #( .INIT(64'hBBB88888BBB8BBB8)) \rx_err_ctr_q[3]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [3]), .I1(mr_ctr_pres_prx_q), .I2(\rx_err_ctr_q[6]_i_2_n_0 ), .I3(\rx_err_ctr_q[3]_i_2_n_0 ), .I4(\rx_err_ctr_q[3]_i_3_n_0 ), .I5(\rx_err_ctr_q[4]_i_4_n_0 ), .O(rx_err_ctr_d[3])); LUT6 #( .INIT(64'h00007F00FFFF80FF)) \rx_err_ctr_q[3]_i_2 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(E), .I4(\rx_err_ctr_q_reg[3]_1 ), .I5(Q[3]), .O(\rx_err_ctr_q[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair161" *) LUT4 #( .INIT(16'hAAA9)) \rx_err_ctr_q[3]_i_3 (.I0(Q[3]), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .O(\rx_err_ctr_q[3]_i_3_n_0 )); LUT6 #( .INIT(64'hBBB88888BBB8BBB8)) \rx_err_ctr_q[4]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [4]), .I1(mr_ctr_pres_prx_q), .I2(\rx_err_ctr_q[6]_i_2_n_0 ), .I3(\rx_err_ctr_q[4]_i_2_n_0 ), .I4(\rx_err_ctr_q[4]_i_3_n_0 ), .I5(\rx_err_ctr_q[4]_i_4_n_0 ), .O(rx_err_ctr_d[4])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h666666666AAAAAAA)) \rx_err_ctr_q[4]_i_2 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(\rx_err_ctr_q_reg[4]_0 ), .O(\rx_err_ctr_q[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT5 #( .INIT(32'hAAAAAAA9)) \rx_err_ctr_q[4]_i_3 (.I0(Q[4]), .I1(Q[2]), .I2(Q[3]), .I3(Q[0]), .I4(Q[1]), .O(\rx_err_ctr_q[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT3 #( .INIT(8'h02)) \rx_err_ctr_q[4]_i_4 (.I0(\rx_err_ctr_q_reg[0]_0 ), .I1(Q[7]), .I2(Q[8]), .O(\rx_err_ctr_q[4]_i_4_n_0 )); LUT6 #( .INIT(64'h88888888BBBBB88B)) \rx_err_ctr_q[5]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [5]), .I1(mr_ctr_pres_prx_q), .I2(Q[5]), .I3(\rx_err_ctr_q[5]_i_2_n_0 ), .I4(\rx_err_ctr_q[6]_i_2_n_0 ), .I5(\rx_err_ctr_q[5]_i_3_n_0 ), .O(rx_err_ctr_d[5])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h55557FFFFFFFFFFF)) \rx_err_ctr_q[5]_i_2 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(\rx_err_ctr_q_reg[4]_0 ), .I5(Q[4]), .O(\rx_err_ctr_q[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT5 #( .INIT(32'h10000010)) \rx_err_ctr_q[5]_i_3 (.I0(Q[8]), .I1(Q[7]), .I2(\rx_err_ctr_q_reg[0]_0 ), .I3(\rx_err_ctr_q[6]_i_4_n_0 ), .I4(Q[5]), .O(\rx_err_ctr_q[5]_i_3_n_0 )); LUT6 #( .INIT(64'h88888888B8BBBBB8)) \rx_err_ctr_q[6]_i_1 (.I0(\mr_ctrl_out[ctr_pres_ctpv] [6]), .I1(mr_ctr_pres_prx_q), .I2(\rx_err_ctr_q[6]_i_2_n_0 ), .I3(Q[6]), .I4(rx_err_ctr_sat1_carry_i_2_n_0), .I5(\rx_err_ctr_q[6]_i_3_n_0 ), .O(rx_err_ctr_d[6])); LUT2 #( .INIT(4'hE)) \rx_err_ctr_q[6]_i_2 (.I0(rx_err_ctr_sat1), .I1(\rx_err_ctr_q_reg[0]_0 ), .O(\rx_err_ctr_q[6]_i_2_n_0 )); LUT6 #( .INIT(64'h0000100010100010)) \rx_err_ctr_q[6]_i_3 (.I0(Q[8]), .I1(Q[7]), .I2(\rx_err_ctr_q_reg[0]_0 ), .I3(\rx_err_ctr_q[6]_i_4_n_0 ), .I4(Q[5]), .I5(Q[6]), .O(\rx_err_ctr_q[6]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT5 #( .INIT(32'h00000001)) \rx_err_ctr_q[6]_i_4 (.I0(Q[2]), .I1(Q[3]), .I2(Q[0]), .I3(Q[1]), .I4(Q[4]), .O(\rx_err_ctr_q[6]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFF000000F900F9)) \rx_err_ctr_q[7]_i_1 (.I0(\rx_err_ctr_q[7]_i_2_n_0 ), .I1(Q[7]), .I2(rx_err_ctr_sat1), .I3(\rx_err_ctr_q_reg[0]_0 ), .I4(\mr_ctrl_out[ctr_pres_ctpv] [7]), .I5(mr_ctr_pres_prx_q), .O(rx_err_ctr_d[7])); LUT4 #( .INIT(16'hDFFF)) \rx_err_ctr_q[7]_i_2 (.I0(Q[6]), .I1(rx_err_ctr_sat1_carry_i_9_n_0), .I2(Q[4]), .I3(Q[5]), .O(\rx_err_ctr_q[7]_i_2_n_0 )); LUT6 #( .INIT(64'hEFAAEFAAAFAAEFAA)) \rx_err_ctr_q[8]_i_1 (.I0(mr_ctr_pres_prx_q), .I1(\rx_err_ctr_q_reg[0]_1 ), .I2(\rx_err_ctr_q_reg[0]_0 ), .I3(\cc_stat[is_receiver] ), .I4(\rx_err_ctr_q[8]_i_6_n_0 ), .I5(\rx_err_ctr_q[8]_i_7_n_0 ), .O(rx_err_ctr_q)); LUT6 #( .INIT(64'hFFFF000000BE00BE)) \rx_err_ctr_q[8]_i_2 (.I0(rx_err_ctr_sat1), .I1(rx_err_ctr_sat1_carry_i_1_n_0), .I2(Q[8]), .I3(\rx_err_ctr_q_reg[0]_0 ), .I4(\mr_ctrl_out[ctr_pres_ctpv] [8]), .I5(mr_ctr_pres_prx_q), .O(rx_err_ctr_d[8])); (* SOFT_HLUTNM = "soft_lutpair163" *) LUT3 #( .INIT(8'h01)) \rx_err_ctr_q[8]_i_6 (.I0(Q[7]), .I1(Q[8]), .I2(Q[0]), .O(\rx_err_ctr_q[8]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \rx_err_ctr_q[8]_i_7 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[4]), .I4(Q[5]), .I5(Q[6]), .O(\rx_err_ctr_q[8]_i_7_n_0 )); FDCE \rx_err_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[0]), .Q(Q[0])); FDCE \rx_err_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[1]), .Q(Q[1])); FDCE \rx_err_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[2]), .Q(Q[2])); FDCE \rx_err_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[3]), .Q(Q[3])); FDCE \rx_err_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[4]), .Q(Q[4])); FDCE \rx_err_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[5]), .Q(Q[5])); FDCE \rx_err_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[6]), .Q(Q[6])); FDCE \rx_err_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[7]), .Q(Q[7])); FDCE \rx_err_ctr_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(rx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(rx_err_ctr_d[8]), .Q(Q[8])); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 rx_err_ctr_sat1_carry (.CI(1'b0), .CO({rx_err_ctr_sat1_carry_n_0,NLW_rx_err_ctr_sat1_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b0), .DI({rx_err_ctr_sat1_carry_i_1_n_0,rx_err_ctr_sat1_carry_i_2_n_0,rx_err_ctr_sat1_carry_i_3_n_0,rx_err_ctr_sat1_carry_i_4_n_0}), .O(NLW_rx_err_ctr_sat1_carry_O_UNCONNECTED[3:0]), .S({rx_err_ctr_sat1_carry_i_5_n_0,rx_err_ctr_sat1_carry_i_6_n_0,rx_err_ctr_sat1_carry_i_7_n_0,S})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 rx_err_ctr_sat1_carry__0 (.CI(rx_err_ctr_sat1_carry_n_0), .CO({NLW_rx_err_ctr_sat1_carry__0_CO_UNCONNECTED[3:1],rx_err_ctr_sat1}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,rx_err_ctr_sat1_carry__0_i_1_n_0}), .O(NLW_rx_err_ctr_sat1_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,rx_err_ctr_sat1_carry__0_i_2_n_0})); LUT4 #( .INIT(16'h8000)) rx_err_ctr_sat1_carry__0_i_1 (.I0(Q[6]), .I1(rx_err_ctr_sat1_carry_i_2_n_0), .I2(Q[7]), .I3(Q[8]), .O(rx_err_ctr_sat1_carry__0_i_1_n_0)); LUT3 #( .INIT(8'h7F)) rx_err_ctr_sat1_carry__0_i_2 (.I0(Q[7]), .I1(rx_err_ctr_sat1_carry_i_2_n_0), .I2(Q[6]), .O(rx_err_ctr_sat1_carry__0_i_2_n_0)); LUT5 #( .INIT(32'h00800000)) rx_err_ctr_sat1_carry_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(Q[4]), .I3(rx_err_ctr_sat1_carry_i_9_n_0), .I4(Q[6]), .O(rx_err_ctr_sat1_carry_i_1_n_0)); LUT3 #( .INIT(8'h08)) rx_err_ctr_sat1_carry_i_2 (.I0(Q[5]), .I1(Q[4]), .I2(rx_err_ctr_sat1_carry_i_9_n_0), .O(rx_err_ctr_sat1_carry_i_2_n_0)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hAAAA8000)) rx_err_ctr_sat1_carry_i_3 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(\rx_err_ctr_q_reg[4]_0 ), .O(rx_err_ctr_sat1_carry_i_3_n_0)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'h40)) rx_err_ctr_sat1_carry_i_4 (.I0(\rx_err_ctr_q_reg[4]_0 ), .I1(Q[0]), .I2(Q[1]), .O(rx_err_ctr_sat1_carry_i_4_n_0)); LUT1 #( .INIT(2'h1)) rx_err_ctr_sat1_carry_i_5 (.I0(rx_err_ctr_sat1_carry_i_2_n_0), .O(rx_err_ctr_sat1_carry_i_5_n_0)); LUT6 #( .INIT(64'h04444444FFFFFFFF)) rx_err_ctr_sat1_carry_i_6 (.I0(\rx_err_ctr_q_reg[3]_1 ), .I1(E), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(Q[3]), .O(rx_err_ctr_sat1_carry_i_6_n_0)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'h15)) rx_err_ctr_sat1_carry_i_7 (.I0(\rx_err_ctr_q_reg[4]_0 ), .I1(Q[0]), .I2(Q[1]), .O(rx_err_ctr_sat1_carry_i_7_n_0)); LUT6 #( .INIT(64'h04444444FFFFFFFF)) rx_err_ctr_sat1_carry_i_9 (.I0(\rx_err_ctr_q_reg[3]_1 ), .I1(E), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(Q[3]), .O(rx_err_ctr_sat1_carry_i_9_n_0)); CARRY4 \tx_err_ctr_d_inferred__0/i__carry (.CI(1'b0), .CO({\tx_err_ctr_d_inferred__0/i__carry_n_0 ,\NLW_tx_err_ctr_d_inferred__0/i__carry_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__0_n_0}), .O({\tx_err_ctr_d_inferred__0/i__carry_n_4 ,\tx_err_ctr_d_inferred__0/i__carry_n_5 ,\tx_err_ctr_d_inferred__0/i__carry_n_6 ,\tx_err_ctr_d_inferred__0/i__carry_n_7 }), .S({i__carry_i_5__1_n_0,i__carry_i_6__1_n_0,i__carry_i_7__1_n_0,i__carry_i_8__1_n_0})); CARRY4 \tx_err_ctr_d_inferred__0/i__carry__0 (.CI(\tx_err_ctr_d_inferred__0/i__carry_n_0 ), .CO({\tx_err_ctr_d_inferred__0/i__carry__0_n_0 ,\NLW_tx_err_ctr_d_inferred__0/i__carry__0_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({i__carry__0_i_1__1_n_0,i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0}), .O({\tx_err_ctr_d_inferred__0/i__carry__0_n_4 ,\tx_err_ctr_d_inferred__0/i__carry__0_n_5 ,\tx_err_ctr_d_inferred__0/i__carry__0_n_6 ,\tx_err_ctr_d_inferred__0/i__carry__0_n_7 }), .S({i__carry__0_i_5_n_0,i__carry__0_i_6_n_0,i__carry__0_i_7_n_0,i__carry__0_i_8_n_0})); CARRY4 \tx_err_ctr_d_inferred__0/i__carry__1 (.CI(\tx_err_ctr_d_inferred__0/i__carry__0_n_0 ), .CO(\NLW_tx_err_ctr_d_inferred__0/i__carry__1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_tx_err_ctr_d_inferred__0/i__carry__1_O_UNCONNECTED [3:1],\tx_err_ctr_d_inferred__0/i__carry__1_n_7 }), .S({1'b0,1'b0,1'b0,i__carry__1_i_1_n_0})); LUT5 #( .INIT(32'hAAAAAAA8)) \tx_err_ctr_q[8]_i_2 (.I0(\rx_err_ctr_q_reg[0]_1 ), .I1(\tx_err_ctr_q[8]_i_4_n_0 ), .I2(\cc_stat[tx_err_ctr] ), .I3(\tx_err_ctr_q_reg[3]_0 ), .I4(\tx_err_ctr_q_reg[0]_0 ), .O(\tx_err_ctr_q_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \tx_err_ctr_q[8]_i_4 (.I0(\tx_err_ctr_q_reg[2]_0 ), .I1(\tx_err_ctr_q_reg[1]_0 ), .I2(\tx_err_ctr_q_reg[5]_0 ), .I3(\tx_err_ctr_q_reg[6]_0 ), .I4(\tx_err_ctr_q_reg[4]_0 ), .I5(\tx_err_ctr_q_reg[7]_0 ), .O(\tx_err_ctr_q[8]_i_4_n_0 )); FDCE \tx_err_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry_n_7 ), .Q(\tx_err_ctr_q_reg[0]_0 )); FDCE \tx_err_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry_n_6 ), .Q(\tx_err_ctr_q_reg[1]_0 )); FDCE \tx_err_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry_n_5 ), .Q(\tx_err_ctr_q_reg[2]_0 )); FDCE \tx_err_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry_n_4 ), .Q(\tx_err_ctr_q_reg[3]_0 )); FDCE \tx_err_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry__0_n_7 ), .Q(\tx_err_ctr_q_reg[4]_0 )); FDCE \tx_err_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry__0_n_6 ), .Q(\tx_err_ctr_q_reg[5]_0 )); FDCE \tx_err_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry__0_n_5 ), .Q(\tx_err_ctr_q_reg[6]_0 )); FDCE \tx_err_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry__0_n_4 ), .Q(\tx_err_ctr_q_reg[7]_0 )); FDCE \tx_err_ctr_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(tx_err_ctr_q), .CLR(i_rst_reg_n_0), .D(\tx_err_ctr_d_inferred__0/i__carry__1_n_7 ), .Q(\cc_stat[tx_err_ctr] )); endmodule module mac_fc_fsm (err_warning_limit_q, CO, \tx_err_ctr_q_reg[8] , \rx_err_ctr_q_reg[8] , \tx_err_ctr_q_reg[8]_0 , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , reg_q_reg, \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state_reg[0]_3 , \cc_stat[is_err_passive] , \FSM_sequential_curr_state_reg[1]_3 , reg_q_reg_0, \FSM_sequential_curr_state_reg[0]_4 , \cc_stat[is_bus_off] , \FSM_sequential_curr_state_reg[0]_5 , reg_q_reg_1, \FSM_sequential_curr_state_reg[1]_4 , reg_q_reg_2, reg_q_reg_3, \curr_state_reg[0] , reg_q_reg_4, \FSM_sequential_curr_state_reg[0]_6 , int_status_reg, \cc_stat[status_ewl] , clk_sys_IBUF_BUFG, err_warning_limit_q_reg_0, DI, err_warning_limit_q1_carry__0_0, Q, err_warning_limit_q_reg_1, \err_warning_limit_q1_inferred__0/i__carry__0_0 , \err_warning_limit_q1_inferred__0/i__carry__0_1 , \cc_stat[tx_err_ctr] , err_warning_limit_q_reg_2, next_state2_carry__0_0, next_state2_carry__0_1, \FSM_sequential_curr_state_reg[1]_5 , \next_state2_inferred__0/i__carry__0_0 , \next_state2_inferred__0/i__carry__0_1 , \FSM_sequential_curr_state_reg[1]_6 , adress_IBUF, \mr_ctrl_out[btr_ph2] , \mr_ctrl_out[btr_fd_ph2_fd] , \FSM_sequential_curr_state[1]_i_11 , destuff_enable_i_4, tx_frame_no_sof_q_i_2, \curr_state[5]_i_18 , \FSM_sequential_curr_state_reg[0]_7 , \FSM_sequential_curr_state_reg[0]_8 , \mr_ctrl_out[settings_ena] , \ctrl_ctr_q[8]_i_21 , \curr_state[0]_i_7 , \mr_ctrl_out[mode_rom] , tran_frame_valid, \mr_ctrl_out[settings_tbfbo] , int_status_reg_0, int_status_reg_1, int_status_reg_2, int_status_reg_3, data_in_IBUF, int_status_reg_4, mr_int_stat_fcsi_o, D); output err_warning_limit_q; output [0:0]CO; output [0:0]\tx_err_ctr_q_reg[8] ; output [0:0]\rx_err_ctr_q_reg[8] ; output [0:0]\tx_err_ctr_q_reg[8]_0 ; output \FSM_sequential_curr_state_reg[0]_0 ; output [1:0]\FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output reg_q_reg; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[0]_2 ; output \FSM_sequential_curr_state_reg[0]_3 ; output \cc_stat[is_err_passive] ; output \FSM_sequential_curr_state_reg[1]_3 ; output reg_q_reg_0; output \FSM_sequential_curr_state_reg[0]_4 ; output \cc_stat[is_bus_off] ; output \FSM_sequential_curr_state_reg[0]_5 ; output reg_q_reg_1; output \FSM_sequential_curr_state_reg[1]_4 ; output reg_q_reg_2; output reg_q_reg_3; output \curr_state_reg[0] ; output reg_q_reg_4; output \FSM_sequential_curr_state_reg[0]_6 ; output int_status_reg; input \cc_stat[status_ewl] ; input clk_sys_IBUF_BUFG; input err_warning_limit_q_reg_0; input [3:0]DI; input [3:0]err_warning_limit_q1_carry__0_0; input [0:0]Q; input [0:0]err_warning_limit_q_reg_1; input [3:0]\err_warning_limit_q1_inferred__0/i__carry__0_0 ; input [3:0]\err_warning_limit_q1_inferred__0/i__carry__0_1 ; input [0:0]\cc_stat[tx_err_ctr] ; input [0:0]err_warning_limit_q_reg_2; input [3:0]next_state2_carry__0_0; input [3:0]next_state2_carry__0_1; input [0:0]\FSM_sequential_curr_state_reg[1]_5 ; input [3:0]\next_state2_inferred__0/i__carry__0_0 ; input [3:0]\next_state2_inferred__0/i__carry__0_1 ; input [0:0]\FSM_sequential_curr_state_reg[1]_6 ; input [2:0]adress_IBUF; input [1:0]\mr_ctrl_out[btr_ph2] ; input [0:0]\mr_ctrl_out[btr_fd_ph2_fd] ; input \FSM_sequential_curr_state[1]_i_11 ; input destuff_enable_i_4; input [0:0]tx_frame_no_sof_q_i_2; input \curr_state[5]_i_18 ; input \FSM_sequential_curr_state_reg[0]_7 ; input \FSM_sequential_curr_state_reg[0]_8 ; input \mr_ctrl_out[settings_ena] ; input [1:0]\ctrl_ctr_q[8]_i_21 ; input \curr_state[0]_i_7 ; input \mr_ctrl_out[mode_rom] ; input tran_frame_valid; input \mr_ctrl_out[settings_tbfbo] ; input int_status_reg_0; input int_status_reg_1; input [0:0]int_status_reg_2; input int_status_reg_3; input [0:0]data_in_IBUF; input int_status_reg_4; input mr_int_stat_fcsi_o; input [1:0]D; wire [0:0]CO; wire [1:0]D; wire [3:0]DI; wire \FSM_sequential_curr_state[1]_i_11 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[0]_6 ; wire \FSM_sequential_curr_state_reg[0]_7 ; wire \FSM_sequential_curr_state_reg[0]_8 ; wire [1:0]\FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire [0:0]\FSM_sequential_curr_state_reg[1]_5 ; wire [0:0]\FSM_sequential_curr_state_reg[1]_6 ; wire [0:0]Q; wire [2:0]adress_IBUF; wire \cc_stat[is_bus_off] ; wire \cc_stat[is_err_passive] ; wire \cc_stat[status_ewl] ; wire [0:0]\cc_stat[tx_err_ctr] ; wire clk_sys_IBUF_BUFG; wire [1:0]\ctrl_ctr_q[8]_i_21 ; wire \curr_state[0]_i_7 ; wire \curr_state[5]_i_18 ; wire \curr_state_reg[0] ; wire [0:0]data_in_IBUF; wire destuff_enable_i_4; wire err_warning_limit_q; wire [3:0]err_warning_limit_q1_carry__0_0; wire err_warning_limit_q1_carry_n_0; wire [3:0]\err_warning_limit_q1_inferred__0/i__carry__0_0 ; wire [3:0]\err_warning_limit_q1_inferred__0/i__carry__0_1 ; wire \err_warning_limit_q1_inferred__0/i__carry_n_0 ; wire err_warning_limit_q_reg_0; wire [0:0]err_warning_limit_q_reg_1; wire [0:0]err_warning_limit_q_reg_2; wire int_status_i_2__6_n_0; wire int_status_reg; wire int_status_reg_0; wire int_status_reg_1; wire [0:0]int_status_reg_2; wire int_status_reg_3; wire int_status_reg_4; wire [0:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [1:0]\mr_ctrl_out[btr_ph2] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_tbfbo] ; wire mr_int_stat_fcsi_o; wire [3:0]next_state2_carry__0_0; wire [3:0]next_state2_carry__0_1; wire next_state2_carry_n_0; wire [3:0]\next_state2_inferred__0/i__carry__0_0 ; wire [3:0]\next_state2_inferred__0/i__carry__0_1 ; wire \next_state2_inferred__0/i__carry_n_0 ; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire [0:0]\rx_err_ctr_q_reg[8] ; wire tran_frame_valid; wire [0:0]\tx_err_ctr_q_reg[8] ; wire [0:0]\tx_err_ctr_q_reg[8]_0 ; wire [0:0]tx_frame_no_sof_q_i_2; wire [2:0]NLW_err_warning_limit_q1_carry_CO_UNCONNECTED; wire [3:0]NLW_err_warning_limit_q1_carry_O_UNCONNECTED; wire [3:1]NLW_err_warning_limit_q1_carry__0_CO_UNCONNECTED; wire [3:0]NLW_err_warning_limit_q1_carry__0_O_UNCONNECTED; wire [2:0]\NLW_err_warning_limit_q1_inferred__0/i__carry_CO_UNCONNECTED ; wire [3:0]\NLW_err_warning_limit_q1_inferred__0/i__carry_O_UNCONNECTED ; wire [3:1]\NLW_err_warning_limit_q1_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:0]\NLW_err_warning_limit_q1_inferred__0/i__carry__0_O_UNCONNECTED ; wire [2:0]NLW_next_state2_carry_CO_UNCONNECTED; wire [3:0]NLW_next_state2_carry_O_UNCONNECTED; wire [3:1]NLW_next_state2_carry__0_CO_UNCONNECTED; wire [3:0]NLW_next_state2_carry__0_O_UNCONNECTED; wire [2:0]\NLW_next_state2_inferred__0/i__carry_CO_UNCONNECTED ; wire [3:0]\NLW_next_state2_inferred__0/i__carry_O_UNCONNECTED ; wire [3:1]\NLW_next_state2_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:0]\NLW_next_state2_inferred__0/i__carry__0_O_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair181" *) LUT4 #( .INIT(16'h0010)) \FSM_sequential_curr_state[0]_i_2__4 (.I0(\FSM_sequential_curr_state_reg[1]_0 [0]), .I1(\FSM_sequential_curr_state_reg[1]_0 [1]), .I2(\FSM_sequential_curr_state_reg[0]_7 ), .I3(\FSM_sequential_curr_state_reg[0]_8 ), .O(\FSM_sequential_curr_state_reg[0]_3 )); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT5 #( .INIT(32'h0004FFFF)) \FSM_sequential_curr_state[1]_i_18 (.I0(\FSM_sequential_curr_state_reg[0]_8 ), .I1(\FSM_sequential_curr_state_reg[0]_7 ), .I2(\FSM_sequential_curr_state_reg[1]_0 [1]), .I3(\FSM_sequential_curr_state_reg[1]_0 [0]), .I4(\FSM_sequential_curr_state[1]_i_11 ), .O(reg_q_reg_2)); (* FSM_ENCODED_STATES = "s_fc_err_passive:10,s_fc_bus_off:00,s_fc_err_active:01" *) FDCE #( .INIT(1'b1)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(err_warning_limit_q_reg_0), .D(D[0]), .Q(\FSM_sequential_curr_state_reg[1]_0 [0])); (* FSM_ENCODED_STATES = "s_fc_err_passive:10,s_fc_bus_off:00,s_fc_err_active:01" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(err_warning_limit_q_reg_0), .D(D[1]), .Q(\FSM_sequential_curr_state_reg[1]_0 [1])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT4 #( .INIT(16'h1F11)) \ctrl_ctr_q[3]_i_20 (.I0(\FSM_sequential_curr_state_reg[1]_0 [0]), .I1(\FSM_sequential_curr_state_reg[1]_0 [1]), .I2(\mr_ctrl_out[mode_rom] ), .I3(\curr_state[0]_i_7 ), .O(\FSM_sequential_curr_state_reg[0]_4 )); LUT6 #( .INIT(64'h00FF0011FF0F000F)) \ctrl_ctr_q[8]_i_32 (.I0(\FSM_sequential_curr_state_reg[1]_0 [1]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\mr_ctrl_out[settings_ena] ), .I3(\ctrl_ctr_q[8]_i_21 [0]), .I4(tx_frame_no_sof_q_i_2), .I5(\ctrl_ctr_q[8]_i_21 [1]), .O(\FSM_sequential_curr_state_reg[1]_3 )); LUT6 #( .INIT(64'h5151510000000000)) \curr_state[0]_i_10 (.I0(\curr_state[0]_i_7 ), .I1(tx_frame_no_sof_q_i_2), .I2(\FSM_sequential_curr_state_reg[1]_4 ), .I3(\FSM_sequential_curr_state_reg[1]_0 [0]), .I4(\FSM_sequential_curr_state_reg[1]_0 [1]), .I5(\ctrl_ctr_q[8]_i_21 [0]), .O(reg_q_reg_1)); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT2 #( .INIT(4'h2)) \curr_state[0]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 [0]), .I1(\FSM_sequential_curr_state_reg[1]_0 [1]), .O(\FSM_sequential_curr_state_reg[0]_5 )); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT5 #( .INIT(32'hD1D1D100)) \curr_state[1]_i_9 (.I0(tx_frame_no_sof_q_i_2), .I1(\curr_state[0]_i_7 ), .I2(\mr_ctrl_out[mode_rom] ), .I3(\FSM_sequential_curr_state_reg[1]_0 [1]), .I4(\FSM_sequential_curr_state_reg[1]_0 [0]), .O(reg_q_reg_3)); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT2 #( .INIT(4'h1)) \curr_state[5]_i_19 (.I0(\FSM_sequential_curr_state_reg[1]_0 [1]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .O(\cc_stat[is_bus_off] )); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT3 #( .INIT(8'hA8)) \curr_state[5]_i_22 (.I0(\curr_state[5]_i_18 ), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\FSM_sequential_curr_state_reg[1]_0 [1]), .O(\FSM_sequential_curr_state_reg[0]_2 )); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT4 #( .INIT(16'h8880)) \curr_state[5]_i_25 (.I0(\curr_state[0]_i_7 ), .I1(tx_frame_no_sof_q_i_2), .I2(\FSM_sequential_curr_state_reg[1]_0 [0]), .I3(\FSM_sequential_curr_state_reg[1]_0 [1]), .O(reg_q_reg_0)); LUT6 #( .INIT(64'h55555500FF7FFFFF)) destuff_enable_i_11 (.I0(tx_frame_no_sof_q_i_2), .I1(\FSM_sequential_curr_state[1]_i_11 ), .I2(destuff_enable_i_4), .I3(\FSM_sequential_curr_state_reg[1]_0 [0]), .I4(\FSM_sequential_curr_state_reg[1]_0 [1]), .I5(\FSM_sequential_curr_state_reg[0]_1 ), .O(reg_q_reg)); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT2 #( .INIT(4'h2)) err_capt_err_erp_i_1 (.I0(\FSM_sequential_curr_state_reg[1]_0 [1]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .O(\cc_stat[is_err_passive] )); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 err_warning_limit_q1_carry (.CI(1'b0), .CO({err_warning_limit_q1_carry_n_0,NLW_err_warning_limit_q1_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI(DI), .O(NLW_err_warning_limit_q1_carry_O_UNCONNECTED[3:0]), .S(err_warning_limit_q1_carry__0_0)); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 err_warning_limit_q1_carry__0 (.CI(err_warning_limit_q1_carry_n_0), .CO({NLW_err_warning_limit_q1_carry__0_CO_UNCONNECTED[3:1],CO}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,Q}), .O(NLW_err_warning_limit_q1_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,err_warning_limit_q_reg_1})); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \err_warning_limit_q1_inferred__0/i__carry (.CI(1'b0), .CO({\err_warning_limit_q1_inferred__0/i__carry_n_0 ,\NLW_err_warning_limit_q1_inferred__0/i__carry_CO_UNCONNECTED [2:0]}), .CYINIT(1'b1), .DI(\err_warning_limit_q1_inferred__0/i__carry__0_0 ), .O(\NLW_err_warning_limit_q1_inferred__0/i__carry_O_UNCONNECTED [3:0]), .S(\err_warning_limit_q1_inferred__0/i__carry__0_1 )); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \err_warning_limit_q1_inferred__0/i__carry__0 (.CI(\err_warning_limit_q1_inferred__0/i__carry_n_0 ), .CO({\NLW_err_warning_limit_q1_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],\tx_err_ctr_q_reg[8] }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\cc_stat[tx_err_ctr] }), .O(\NLW_err_warning_limit_q1_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), .S({1'b0,1'b0,1'b0,err_warning_limit_q_reg_2})); FDCE err_warning_limit_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(err_warning_limit_q_reg_0), .D(\cc_stat[status_ewl] ), .Q(err_warning_limit_q)); LUT5 #( .INIT(32'hFFBFAAAA)) \g_int_module[4].i_im_channel/int_status_i_1 (.I0(int_status_i_2__6_n_0), .I1(int_status_reg_3), .I2(data_in_IBUF), .I3(int_status_reg_4), .I4(mr_int_stat_fcsi_o), .O(int_status_reg)); LUT6 #( .INIT(64'h00000000323E320E)) int_status_i_2__6 (.I0(int_status_reg_0), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\FSM_sequential_curr_state_reg[1]_0 [1]), .I3(int_status_reg_1), .I4(\cc_stat[tx_err_ctr] ), .I5(int_status_reg_2), .O(int_status_i_2__6_n_0)); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT3 #( .INIT(8'hEF)) int_status_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 [0]), .I1(\FSM_sequential_curr_state_reg[1]_0 [1]), .I2(\mr_ctrl_out[settings_tbfbo] ), .O(\FSM_sequential_curr_state_reg[0]_6 )); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 next_state2_carry (.CI(1'b0), .CO({next_state2_carry_n_0,NLW_next_state2_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI(next_state2_carry__0_0), .O(NLW_next_state2_carry_O_UNCONNECTED[3:0]), .S(next_state2_carry__0_1)); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 next_state2_carry__0 (.CI(next_state2_carry_n_0), .CO({NLW_next_state2_carry__0_CO_UNCONNECTED[3:1],\rx_err_ctr_q_reg[8] }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,Q}), .O(NLW_next_state2_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,\FSM_sequential_curr_state_reg[1]_5 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \next_state2_inferred__0/i__carry (.CI(1'b0), .CO({\next_state2_inferred__0/i__carry_n_0 ,\NLW_next_state2_inferred__0/i__carry_CO_UNCONNECTED [2:0]}), .CYINIT(1'b1), .DI(\next_state2_inferred__0/i__carry__0_0 ), .O(\NLW_next_state2_inferred__0/i__carry_O_UNCONNECTED [3:0]), .S(\next_state2_inferred__0/i__carry__0_1 )); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \next_state2_inferred__0/i__carry__0 (.CI(\next_state2_inferred__0/i__carry_n_0 ), .CO({\NLW_next_state2_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],\tx_err_ctr_q_reg[8]_0 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,\cc_stat[tx_err_ctr] }), .O(\NLW_next_state2_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), .S({1'b0,1'b0,1'b0,\FSM_sequential_curr_state_reg[1]_6 })); LUT6 #( .INIT(64'h22FFF0002200F000)) \r_data[17]_i_8 (.I0(\FSM_sequential_curr_state_reg[1]_0 [1]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\mr_ctrl_out[btr_fd_ph2_fd] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\mr_ctrl_out[btr_ph2] [0]), .O(\FSM_sequential_curr_state_reg[1]_1 )); LUT6 #( .INIT(64'hFE00FFFFFEFFFFFF)) \r_data[18]_i_11 (.I0(adress_IBUF[2]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\FSM_sequential_curr_state_reg[1]_0 [1]), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\mr_ctrl_out[btr_ph2] [1]), .O(\FSM_sequential_curr_state_reg[0]_0 )); LUT6 #( .INIT(64'h00000000000011F1)) \r_data[7]_i_14 (.I0(\FSM_sequential_curr_state_reg[1]_0 [1]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\FSM_sequential_curr_state[1]_i_11 ), .I3(destuff_enable_i_4), .I4(adress_IBUF[0]), .I5(adress_IBUF[2]), .O(\FSM_sequential_curr_state_reg[1]_2 )); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT3 #( .INIT(8'h54)) rec_ivld_q_i_6 (.I0(tx_frame_no_sof_q_i_2), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(\FSM_sequential_curr_state_reg[1]_0 [1]), .O(reg_q_reg_4)); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT4 #( .INIT(16'h5501)) \timestamp_capture[63]_i_5 (.I0(\ctrl_ctr_q[8]_i_21 [0]), .I1(\FSM_sequential_curr_state_reg[1]_0 [1]), .I2(\FSM_sequential_curr_state_reg[1]_0 [0]), .I3(tx_frame_no_sof_q_i_2), .O(\curr_state_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT5 #( .INIT(32'h2000FFFF)) tx_frame_no_sof_q_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 [1]), .I1(\FSM_sequential_curr_state_reg[1]_0 [0]), .I2(destuff_enable_i_4), .I3(\FSM_sequential_curr_state[1]_i_11 ), .I4(tran_frame_valid), .O(\FSM_sequential_curr_state_reg[1]_4 )); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT3 #( .INIT(8'h1F)) \txtb_hw_cmd_q[lock]_i_7 (.I0(\FSM_sequential_curr_state_reg[1]_0 [0]), .I1(\FSM_sequential_curr_state_reg[1]_0 [1]), .I2(tran_frame_valid), .O(\FSM_sequential_curr_state_reg[0]_1 )); endmodule module mac_fc_top (mr_ctr_pres_ptx_q, err_warning_limit_q, mr_ctr_pres_enorm_q, mr_ctr_pres_efd_q, \tx_err_ctr_q_reg[7] , \tx_err_ctr_q_reg[6] , \tx_err_ctr_q_reg[5] , \tx_err_ctr_q_reg[4] , \tx_err_ctr_q_reg[3] , \tx_err_ctr_q_reg[2] , \tx_err_ctr_q_reg[1] , \tx_err_ctr_q_reg[0] , D, Q, \nom_err_ctr_q_reg[13] , \data_err_ctr_q_reg[2] , \FSM_sequential_curr_state_reg[1] , \tx_err_ctr_q_reg[3]_0 , \tx_err_ctr_q_reg[6]_0 , \tx_err_ctr_q_reg[7]_0 , \nom_err_ctr_q_reg[0] , \rx_err_ctr_q_reg[1] , \rx_err_ctr_q_reg[3] , \rx_err_ctr_q_reg[5] , \rx_err_ctr_q_reg[7] , \rx_err_ctr_q_reg[8] , \nom_err_ctr_q_reg[11] , \FSM_sequential_curr_state_reg[1]_0 , reg_q_reg, \FSM_sequential_curr_state_reg[0] , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[0]_1 , \data_err_ctr_q_reg[15] , \tx_err_ctr_q_reg[8] , \cc_stat[is_err_passive] , \FSM_sequential_curr_state_reg[1]_1 , reg_q_reg_0, \FSM_sequential_curr_state_reg[0]_2 , \cc_stat[is_bus_off] , \FSM_sequential_curr_state_reg[0]_3 , \rx_err_ctr_q_reg[8]_0 , \data_err_ctr_q_reg[4] , \data_err_ctr_q_reg[5] , \data_err_ctr_q_reg[8] , \nom_err_ctr_q_reg[2] , \data_err_ctr_q_reg[0] , \nom_err_ctr_q_reg[15] , reg_q_reg_1, \FSM_sequential_curr_state_reg[1]_2 , reg_q_reg_2, reg_q_reg_3, \curr_state_reg[0] , reg_q_reg_4, \FSM_sequential_curr_state_reg[0]_4 , int_status_reg, \mr_ctrl_out[ctr_pres_prx] , clk_sys_IBUF_BUFG, err_warning_limit_q_reg, \mr_ctrl_out[ctr_pres_ptx] , reg_q_reg_5, \mr_ctrl_out[ctr_pres_enorm] , \mr_ctrl_out[ctr_pres_efd] , tx_err_ctr_q, S, err_warning_limit_q1_carry__0, DI, next_state2_carry__0, \next_state2_inferred__0/i__carry__0 , sbe_IBUF, adress_IBUF, \r_data_reg[4] , \r_data_reg[4]_0 , \r_data_reg[4]_1 , \r_data_reg[6] , \r_data_reg[14] , \r_data_reg[17] , \r_data_reg[6]_0 , \r_data_reg[6]_1 , \r_data[6]_i_2 , \r_data_reg[16] , \r_data_reg[20] , \r_data_reg[20]_0 , \mr_ctrl_out[btr_ph2] , \r_data[19]_i_2 , \r_data_reg[22] , \r_data_reg[23] , \r_data_reg[20]_1 , \r_data[0]_i_2 , \r_data[1]_i_2__0 , \r_data_reg[3]_i_5 , \r_data[4]_i_2 , \r_data[5]_i_2 , \r_data_reg[7]_i_6 , \r_data_reg[8]_i_4 , \r_data_reg[17]_0 , \r_data_reg[17]_1 , \r_data_reg[14]_0 , \r_data[11]_i_2__0 , \mr_ctrl_out[btr_fd_ph2_fd] , \mr_ctrl_out[mode_rom] , \FSM_sequential_curr_state[1]_i_11 , destuff_enable_i_4, tx_frame_no_sof_q_i_2, \curr_state[5]_i_18 , \mr_ctrl_out[ctr_pres_ctpv] , \rx_err_ctr_q_reg[1]_0 , \rx_err_ctr_q_reg[4] , \rx_err_ctr_q_reg[0] , \rx_err_ctr_q_reg[0]_0 , \cc_stat[is_receiver] , \rx_err_ctr_q_reg[3]_0 , E, \rx_err_ctr_q[2]_i_2 , \FSM_sequential_curr_state_reg[0]_5 , \FSM_sequential_curr_state_reg[0]_6 , \nom_err_ctr_q_reg[0]_0 , \mr_ctrl_out[settings_ena] , \ctrl_ctr_q[8]_i_21 , \curr_state[0]_i_7 , \mr_ctrl_out[ewl_ew_limit] , \mr_ctrl_out[erp_erp_limit] , scan_mode_IBUF, rst_n_out_OBUF, \r_data_reg[20]_2 , \r_data_reg[21] , \r_data_reg[24] , \r_data_reg[2] , \r_data_reg[16]_0 , \r_data_reg[14]_i_2 , \r_data_reg[15] , tran_frame_valid, \mr_ctrl_out[settings_tbfbo] , \FSM_sequential_curr_state_reg[0]_7 , int_status_reg_0, int_status_reg_1, data_in_IBUF, int_status_reg_2, mr_int_stat_fcsi_o, \nom_err_ctr_q_reg[0]_1 , \data_err_ctr_q_reg[0]_0 ); output mr_ctr_pres_ptx_q; output err_warning_limit_q; output mr_ctr_pres_enorm_q; output mr_ctr_pres_efd_q; output \tx_err_ctr_q_reg[7] ; output \tx_err_ctr_q_reg[6] ; output \tx_err_ctr_q_reg[5] ; output \tx_err_ctr_q_reg[4] ; output \tx_err_ctr_q_reg[3] ; output \tx_err_ctr_q_reg[2] ; output \tx_err_ctr_q_reg[1] ; output \tx_err_ctr_q_reg[0] ; output [3:0]D; output [7:0]Q; output [3:0]\nom_err_ctr_q_reg[13] ; output \data_err_ctr_q_reg[2] ; output [1:0]\FSM_sequential_curr_state_reg[1] ; output \tx_err_ctr_q_reg[3]_0 ; output \tx_err_ctr_q_reg[6]_0 ; output \tx_err_ctr_q_reg[7]_0 ; output \nom_err_ctr_q_reg[0] ; output \rx_err_ctr_q_reg[1] ; output \rx_err_ctr_q_reg[3] ; output \rx_err_ctr_q_reg[5] ; output \rx_err_ctr_q_reg[7] ; output \rx_err_ctr_q_reg[8] ; output \nom_err_ctr_q_reg[11] ; output \FSM_sequential_curr_state_reg[1]_0 ; output reg_q_reg; output \FSM_sequential_curr_state_reg[0] ; output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[0]_1 ; output [6:0]\data_err_ctr_q_reg[15] ; output \tx_err_ctr_q_reg[8] ; output \cc_stat[is_err_passive] ; output \FSM_sequential_curr_state_reg[1]_1 ; output reg_q_reg_0; output \FSM_sequential_curr_state_reg[0]_2 ; output \cc_stat[is_bus_off] ; output \FSM_sequential_curr_state_reg[0]_3 ; output \rx_err_ctr_q_reg[8]_0 ; output \data_err_ctr_q_reg[4] ; output \data_err_ctr_q_reg[5] ; output \data_err_ctr_q_reg[8] ; output \nom_err_ctr_q_reg[2] ; output \data_err_ctr_q_reg[0] ; output \nom_err_ctr_q_reg[15] ; output reg_q_reg_1; output \FSM_sequential_curr_state_reg[1]_2 ; output reg_q_reg_2; output reg_q_reg_3; output \curr_state_reg[0] ; output reg_q_reg_4; output \FSM_sequential_curr_state_reg[0]_4 ; output int_status_reg; input \mr_ctrl_out[ctr_pres_prx] ; input clk_sys_IBUF_BUFG; input err_warning_limit_q_reg; input \mr_ctrl_out[ctr_pres_ptx] ; input reg_q_reg_5; input \mr_ctrl_out[ctr_pres_enorm] ; input \mr_ctrl_out[ctr_pres_efd] ; input [0:0]tx_err_ctr_q; input [0:0]S; input [3:0]err_warning_limit_q1_carry__0; input [3:0]DI; input [3:0]next_state2_carry__0; input [3:0]\next_state2_inferred__0/i__carry__0 ; input [2:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[4] ; input \r_data_reg[4]_0 ; input \r_data_reg[4]_1 ; input \r_data_reg[6] ; input \r_data_reg[14] ; input \r_data_reg[17] ; input \r_data_reg[6]_0 ; input \r_data_reg[6]_1 ; input \r_data[6]_i_2 ; input \r_data_reg[16] ; input \r_data_reg[20] ; input \r_data_reg[20]_0 ; input [1:0]\mr_ctrl_out[btr_ph2] ; input \r_data[19]_i_2 ; input \r_data_reg[22] ; input \r_data_reg[23] ; input \r_data_reg[20]_1 ; input \r_data[0]_i_2 ; input \r_data[1]_i_2__0 ; input \r_data_reg[3]_i_5 ; input \r_data[4]_i_2 ; input \r_data[5]_i_2 ; input \r_data_reg[7]_i_6 ; input \r_data_reg[8]_i_4 ; input \r_data_reg[17]_0 ; input \r_data_reg[17]_1 ; input \r_data_reg[14]_0 ; input \r_data[11]_i_2__0 ; input [0:0]\mr_ctrl_out[btr_fd_ph2_fd] ; input \mr_ctrl_out[mode_rom] ; input \FSM_sequential_curr_state[1]_i_11 ; input destuff_enable_i_4; input [0:0]tx_frame_no_sof_q_i_2; input \curr_state[5]_i_18 ; input [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; input \rx_err_ctr_q_reg[1]_0 ; input \rx_err_ctr_q_reg[4] ; input \rx_err_ctr_q_reg[0] ; input \rx_err_ctr_q_reg[0]_0 ; input \cc_stat[is_receiver] ; input \rx_err_ctr_q_reg[3]_0 ; input [0:0]E; input \rx_err_ctr_q[2]_i_2 ; input \FSM_sequential_curr_state_reg[0]_5 ; input \FSM_sequential_curr_state_reg[0]_6 ; input \nom_err_ctr_q_reg[0]_0 ; input \mr_ctrl_out[settings_ena] ; input [1:0]\ctrl_ctr_q[8]_i_21 ; input \curr_state[0]_i_7 ; input [7:0]\mr_ctrl_out[ewl_ew_limit] ; input [7:0]\mr_ctrl_out[erp_erp_limit] ; input scan_mode_IBUF; input rst_n_out_OBUF; input \r_data_reg[20]_2 ; input \r_data_reg[21] ; input \r_data_reg[24] ; input \r_data_reg[2] ; input \r_data_reg[16]_0 ; input \r_data_reg[14]_i_2 ; input \r_data_reg[15] ; input tran_frame_valid; input \mr_ctrl_out[settings_tbfbo] ; input \FSM_sequential_curr_state_reg[0]_7 ; input [0:0]int_status_reg_0; input int_status_reg_1; input [0:0]data_in_IBUF; input int_status_reg_2; input mr_int_stat_fcsi_o; input [0:0]\nom_err_ctr_q_reg[0]_1 ; input [0:0]\data_err_ctr_q_reg[0]_0 ; wire [3:0]D; wire [3:0]DI; wire [0:0]E; wire \FSM_sequential_curr_state[1]_i_11 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[0]_6 ; wire \FSM_sequential_curr_state_reg[0]_7 ; wire [1:0]\FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire [7:0]Q; wire [0:0]S; wire [5:0]adress_IBUF; wire \cc_stat[is_bus_off] ; wire \cc_stat[is_err_passive] ; wire \cc_stat[is_receiver] ; wire [8:8]\cc_stat[rx_err_ctr] ; wire \cc_stat[status_ewl] ; wire [8:8]\cc_stat[tx_err_ctr] ; wire clk_sys_IBUF_BUFG; wire [1:0]\ctrl_ctr_q[8]_i_21 ; wire \curr_state[0]_i_7 ; wire \curr_state[5]_i_18 ; wire \curr_state_reg[0] ; wire \data_err_ctr_q_reg[0] ; wire [0:0]\data_err_ctr_q_reg[0]_0 ; wire [6:0]\data_err_ctr_q_reg[15] ; wire \data_err_ctr_q_reg[2] ; wire \data_err_ctr_q_reg[4] ; wire \data_err_ctr_q_reg[5] ; wire \data_err_ctr_q_reg[8] ; wire [0:0]data_in_IBUF; wire destuff_enable_i_4; wire err_warning_limit_q; wire [3:0]err_warning_limit_q1_carry__0; wire err_warning_limit_q_reg; wire i_mac_fc_err_counters_n_52; wire i_mac_fc_err_counters_n_53; wire i_mac_fc_err_counters_n_54; wire i_mac_fc_err_counters_n_55; wire i_mac_fc_err_counters_n_56; wire i_mac_fc_err_counters_n_57; wire i_mac_fc_err_counters_n_58; wire i_mac_fc_err_counters_n_59; wire i_mac_fc_err_counters_n_60; wire i_mac_fc_err_counters_n_61; wire i_mac_fc_err_counters_n_62; wire i_mac_fc_err_counters_n_63; wire i_mac_fc_err_counters_n_64; wire i_mac_fc_err_counters_n_65; wire i_mac_fc_err_counters_n_66; wire i_mac_fc_err_counters_n_67; wire i_mac_fc_err_counters_n_68; wire i_mac_fc_err_counters_n_69; wire i_mac_fc_err_counters_n_70; wire i_mac_fc_err_counters_n_71; wire i_mac_fc_err_counters_n_72; wire i_mac_fc_fsm_n_5; wire i_mac_fc_fsm_n_8; wire int_status_reg; wire [0:0]int_status_reg_0; wire int_status_reg_1; wire int_status_reg_2; wire mr_ctr_pres_efd_q; wire mr_ctr_pres_enorm_q; wire mr_ctr_pres_ptx_q; wire [0:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [1:0]\mr_ctrl_out[btr_ph2] ; wire [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire [7:0]\mr_ctrl_out[erp_erp_limit] ; wire [7:0]\mr_ctrl_out[ewl_ew_limit] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_tbfbo] ; wire mr_int_stat_fcsi_o; wire [3:0]next_state2_carry__0; wire [3:0]\next_state2_inferred__0/i__carry__0 ; wire [1:0]next_state__0; wire \nom_err_ctr_q_reg[0] ; wire \nom_err_ctr_q_reg[0]_0 ; wire [0:0]\nom_err_ctr_q_reg[0]_1 ; wire \nom_err_ctr_q_reg[11] ; wire [3:0]\nom_err_ctr_q_reg[13] ; wire \nom_err_ctr_q_reg[15] ; wire \nom_err_ctr_q_reg[2] ; wire \r_data[0]_i_2 ; wire \r_data[11]_i_2__0 ; wire \r_data[19]_i_2 ; wire \r_data[1]_i_2__0 ; wire \r_data[4]_i_2 ; wire \r_data[5]_i_2 ; wire \r_data[6]_i_2 ; wire \r_data_reg[14] ; wire \r_data_reg[14]_0 ; wire \r_data_reg[14]_i_2 ; wire \r_data_reg[15] ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[17] ; wire \r_data_reg[17]_0 ; wire \r_data_reg[17]_1 ; wire \r_data_reg[20] ; wire \r_data_reg[20]_0 ; wire \r_data_reg[20]_1 ; wire \r_data_reg[20]_2 ; wire \r_data_reg[21] ; wire \r_data_reg[22] ; wire \r_data_reg[23] ; wire \r_data_reg[24] ; wire \r_data_reg[2] ; wire \r_data_reg[3]_i_5 ; wire \r_data_reg[4] ; wire \r_data_reg[4]_0 ; wire \r_data_reg[4]_1 ; wire \r_data_reg[6] ; wire \r_data_reg[6]_0 ; wire \r_data_reg[6]_1 ; wire \r_data_reg[7]_i_6 ; wire \r_data_reg[8]_i_4 ; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire rst_n_out_OBUF; wire rx_err_ctr_mt_erp; wire rx_err_ctr_mt_ewl; wire \rx_err_ctr_q[2]_i_2 ; wire \rx_err_ctr_q_reg[0] ; wire \rx_err_ctr_q_reg[0]_0 ; wire \rx_err_ctr_q_reg[1] ; wire \rx_err_ctr_q_reg[1]_0 ; wire \rx_err_ctr_q_reg[3] ; wire \rx_err_ctr_q_reg[3]_0 ; wire \rx_err_ctr_q_reg[4] ; wire \rx_err_ctr_q_reg[5] ; wire \rx_err_ctr_q_reg[7] ; wire \rx_err_ctr_q_reg[8] ; wire \rx_err_ctr_q_reg[8]_0 ; wire [2:0]sbe_IBUF; wire scan_mode_IBUF; wire tran_frame_valid; wire tx_err_ctr_mt_erp; wire tx_err_ctr_mt_ewl; wire [0:0]tx_err_ctr_q; wire \tx_err_ctr_q_reg[0] ; wire \tx_err_ctr_q_reg[1] ; wire \tx_err_ctr_q_reg[2] ; wire \tx_err_ctr_q_reg[3] ; wire \tx_err_ctr_q_reg[3]_0 ; wire \tx_err_ctr_q_reg[4] ; wire \tx_err_ctr_q_reg[5] ; wire \tx_err_ctr_q_reg[6] ; wire \tx_err_ctr_q_reg[6]_0 ; wire \tx_err_ctr_q_reg[7] ; wire \tx_err_ctr_q_reg[7]_0 ; wire \tx_err_ctr_q_reg[8] ; wire [0:0]tx_frame_no_sof_q_i_2; mac_fc_err_counters i_mac_fc_err_counters (.CO(rx_err_ctr_mt_ewl), .D(D), .DI({i_mac_fc_err_counters_n_54,i_mac_fc_err_counters_n_55,i_mac_fc_err_counters_n_56,i_mac_fc_err_counters_n_57}), .E(E), .\FSM_sequential_curr_state_reg[0] (next_state__0), .\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0]_7 ), .\FSM_sequential_curr_state_reg[1] (tx_err_ctr_mt_erp), .\FSM_sequential_curr_state_reg[1]_0 (rx_err_ctr_mt_erp), .\FSM_sequential_curr_state_reg[1]_1 (\FSM_sequential_curr_state_reg[1] ), .Q({\cc_stat[rx_err_ctr] ,Q}), .S(S), .adress_IBUF(adress_IBUF), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .\cc_stat[status_ewl] (\cc_stat[status_ewl] ), .\cc_stat[tx_err_ctr] (\cc_stat[tx_err_ctr] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\data_err_ctr_q_reg[0]_0 (\data_err_ctr_q_reg[0] ), .\data_err_ctr_q_reg[0]_1 (\data_err_ctr_q_reg[0]_0 ), .\data_err_ctr_q_reg[15]_0 (\data_err_ctr_q_reg[15] ), .\data_err_ctr_q_reg[2]_0 (\data_err_ctr_q_reg[2] ), .\data_err_ctr_q_reg[4]_0 (\data_err_ctr_q_reg[4] ), .\data_err_ctr_q_reg[5]_0 (\data_err_ctr_q_reg[5] ), .\data_err_ctr_q_reg[8]_0 (\data_err_ctr_q_reg[8] ), .err_warning_limit_q_reg(tx_err_ctr_mt_ewl), .mr_ctr_pres_efd_q_reg_0(mr_ctr_pres_efd_q), .mr_ctr_pres_enorm_q_reg_0(mr_ctr_pres_enorm_q), .mr_ctr_pres_ptx_q_reg_0(mr_ctr_pres_ptx_q), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] ), .\mr_ctrl_out[ctr_pres_efd] (\mr_ctrl_out[ctr_pres_efd] ), .\mr_ctrl_out[ctr_pres_enorm] (\mr_ctrl_out[ctr_pres_enorm] ), .\mr_ctrl_out[ctr_pres_prx] (\mr_ctrl_out[ctr_pres_prx] ), .\mr_ctrl_out[ctr_pres_ptx] (\mr_ctrl_out[ctr_pres_ptx] ), .\mr_ctrl_out[erp_erp_limit] (\mr_ctrl_out[erp_erp_limit] ), .\mr_ctrl_out[ewl_ew_limit] (\mr_ctrl_out[ewl_ew_limit] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\nom_err_ctr_q_reg[0]_0 (\nom_err_ctr_q_reg[0] ), .\nom_err_ctr_q_reg[0]_1 (\nom_err_ctr_q_reg[0]_0 ), .\nom_err_ctr_q_reg[0]_2 (\nom_err_ctr_q_reg[0]_1 ), .\nom_err_ctr_q_reg[11]_0 (\nom_err_ctr_q_reg[11] ), .\nom_err_ctr_q_reg[13]_0 (\nom_err_ctr_q_reg[13] ), .\nom_err_ctr_q_reg[15]_0 (\nom_err_ctr_q_reg[15] ), .\nom_err_ctr_q_reg[2]_0 (\nom_err_ctr_q_reg[2] ), .\r_data[0]_i_2 (\r_data[0]_i_2 ), .\r_data[11]_i_2__0 (\r_data[11]_i_2__0 ), .\r_data[17]_i_2_0 (i_mac_fc_fsm_n_8), .\r_data[18]_i_2 (i_mac_fc_fsm_n_5), .\r_data[19]_i_2 (\r_data[19]_i_2 ), .\r_data[1]_i_2__0 (\r_data[1]_i_2__0 ), .\r_data[4]_i_2_0 (\r_data[4]_i_2 ), .\r_data[5]_i_2 (\r_data[5]_i_2 ), .\r_data[6]_i_2_0 (\r_data[6]_i_2 ), .\r_data_reg[14] (\r_data_reg[14] ), .\r_data_reg[14]_0 (\r_data_reg[14]_0 ), .\r_data_reg[14]_i_2_0 (\r_data_reg[14]_i_2 ), .\r_data_reg[15] (\r_data_reg[15] ), .\r_data_reg[16] (\r_data_reg[16] ), .\r_data_reg[16]_0 (\r_data_reg[16]_0 ), .\r_data_reg[17] (\r_data_reg[17] ), .\r_data_reg[17]_0 (\r_data_reg[17]_0 ), .\r_data_reg[17]_1 (\r_data_reg[17]_1 ), .\r_data_reg[20] (\r_data_reg[20] ), .\r_data_reg[20]_0 (\r_data_reg[20]_0 ), .\r_data_reg[20]_1 (\r_data_reg[20]_1 ), .\r_data_reg[20]_2 (\r_data_reg[20]_2 ), .\r_data_reg[21] (\r_data_reg[21] ), .\r_data_reg[22] (\r_data_reg[22] ), .\r_data_reg[23] (\r_data_reg[23] ), .\r_data_reg[24] (\r_data_reg[24] ), .\r_data_reg[2] (\r_data_reg[2] ), .\r_data_reg[3]_i_5 (\r_data_reg[3]_i_5 ), .\r_data_reg[4] (\r_data_reg[4] ), .\r_data_reg[4]_0 (\r_data_reg[4]_0 ), .\r_data_reg[4]_1 (\r_data_reg[4]_1 ), .\r_data_reg[6] (\r_data_reg[6] ), .\r_data_reg[6]_0 (\r_data_reg[6]_0 ), .\r_data_reg[6]_1 (\r_data_reg[6]_1 ), .\r_data_reg[7]_i_6 (\r_data_reg[7]_i_6 ), .\r_data_reg[8]_i_4 (\r_data_reg[8]_i_4 ), .reg_q_reg(err_warning_limit_q_reg), .reg_q_reg_0(reg_q_reg_5), .rst_n_out_OBUF(rst_n_out_OBUF), .\rx_err_ctr_q[2]_i_2_0 (\rx_err_ctr_q[2]_i_2 ), .\rx_err_ctr_q_reg[0]_0 (\rx_err_ctr_q_reg[0] ), .\rx_err_ctr_q_reg[0]_1 (\rx_err_ctr_q_reg[0]_0 ), .\rx_err_ctr_q_reg[1]_0 (\rx_err_ctr_q_reg[1] ), .\rx_err_ctr_q_reg[1]_1 (\rx_err_ctr_q_reg[1]_0 ), .\rx_err_ctr_q_reg[3]_0 (\rx_err_ctr_q_reg[3] ), .\rx_err_ctr_q_reg[3]_1 (\rx_err_ctr_q_reg[3]_0 ), .\rx_err_ctr_q_reg[4]_0 (\rx_err_ctr_q_reg[4] ), .\rx_err_ctr_q_reg[5]_0 (\rx_err_ctr_q_reg[5] ), .\rx_err_ctr_q_reg[7]_0 (\rx_err_ctr_q_reg[7] ), .\rx_err_ctr_q_reg[7]_1 ({i_mac_fc_err_counters_n_62,i_mac_fc_err_counters_n_63,i_mac_fc_err_counters_n_64,i_mac_fc_err_counters_n_65}), .\rx_err_ctr_q_reg[8]_0 (\rx_err_ctr_q_reg[8] ), .\rx_err_ctr_q_reg[8]_1 (\rx_err_ctr_q_reg[8]_0 ), .\rx_err_ctr_q_reg[8]_2 (i_mac_fc_err_counters_n_53), .\rx_err_ctr_q_reg[8]_3 (i_mac_fc_err_counters_n_70), .\rx_err_ctr_q_reg[8]_4 (i_mac_fc_err_counters_n_71), .sbe_IBUF(sbe_IBUF), .scan_mode_IBUF(scan_mode_IBUF), .tx_err_ctr_q(tx_err_ctr_q), .\tx_err_ctr_q_reg[0]_0 (\tx_err_ctr_q_reg[0] ), .\tx_err_ctr_q_reg[1]_0 (\tx_err_ctr_q_reg[1] ), .\tx_err_ctr_q_reg[2]_0 (\tx_err_ctr_q_reg[2] ), .\tx_err_ctr_q_reg[3]_0 (\tx_err_ctr_q_reg[3] ), .\tx_err_ctr_q_reg[3]_1 (\tx_err_ctr_q_reg[3]_0 ), .\tx_err_ctr_q_reg[4]_0 (\tx_err_ctr_q_reg[4] ), .\tx_err_ctr_q_reg[5]_0 (\tx_err_ctr_q_reg[5] ), .\tx_err_ctr_q_reg[6]_0 (\tx_err_ctr_q_reg[6] ), .\tx_err_ctr_q_reg[6]_1 (\tx_err_ctr_q_reg[6]_0 ), .\tx_err_ctr_q_reg[7]_0 (\tx_err_ctr_q_reg[7] ), .\tx_err_ctr_q_reg[7]_1 (\tx_err_ctr_q_reg[7]_0 ), .\tx_err_ctr_q_reg[7]_2 ({i_mac_fc_err_counters_n_58,i_mac_fc_err_counters_n_59,i_mac_fc_err_counters_n_60,i_mac_fc_err_counters_n_61}), .\tx_err_ctr_q_reg[7]_3 ({i_mac_fc_err_counters_n_66,i_mac_fc_err_counters_n_67,i_mac_fc_err_counters_n_68,i_mac_fc_err_counters_n_69}), .\tx_err_ctr_q_reg[8]_0 (\tx_err_ctr_q_reg[8] ), .\tx_err_ctr_q_reg[8]_1 (i_mac_fc_err_counters_n_52), .\tx_err_ctr_q_reg[8]_2 (i_mac_fc_err_counters_n_72)); mac_fc_fsm i_mac_fc_fsm (.CO(rx_err_ctr_mt_ewl), .D(next_state__0), .DI({i_mac_fc_err_counters_n_54,i_mac_fc_err_counters_n_55,i_mac_fc_err_counters_n_56,i_mac_fc_err_counters_n_57}), .\FSM_sequential_curr_state[1]_i_11 (\FSM_sequential_curr_state[1]_i_11 ), .\FSM_sequential_curr_state_reg[0]_0 (i_mac_fc_fsm_n_5), .\FSM_sequential_curr_state_reg[0]_1 (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_2 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_3 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[0]_4 (\FSM_sequential_curr_state_reg[0]_2 ), .\FSM_sequential_curr_state_reg[0]_5 (\FSM_sequential_curr_state_reg[0]_3 ), .\FSM_sequential_curr_state_reg[0]_6 (\FSM_sequential_curr_state_reg[0]_4 ), .\FSM_sequential_curr_state_reg[0]_7 (\FSM_sequential_curr_state_reg[0]_5 ), .\FSM_sequential_curr_state_reg[0]_8 (\FSM_sequential_curr_state_reg[0]_6 ), .\FSM_sequential_curr_state_reg[1]_0 (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_1 (i_mac_fc_fsm_n_8), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_5 (i_mac_fc_err_counters_n_53), .\FSM_sequential_curr_state_reg[1]_6 (i_mac_fc_err_counters_n_52), .Q(\cc_stat[rx_err_ctr] ), .adress_IBUF(adress_IBUF[2:0]), .\cc_stat[is_bus_off] (\cc_stat[is_bus_off] ), .\cc_stat[is_err_passive] (\cc_stat[is_err_passive] ), .\cc_stat[status_ewl] (\cc_stat[status_ewl] ), .\cc_stat[tx_err_ctr] (\cc_stat[tx_err_ctr] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\ctrl_ctr_q[8]_i_21 (\ctrl_ctr_q[8]_i_21 ), .\curr_state[0]_i_7 (\curr_state[0]_i_7 ), .\curr_state[5]_i_18 (\curr_state[5]_i_18 ), .\curr_state_reg[0] (\curr_state_reg[0] ), .data_in_IBUF(data_in_IBUF), .destuff_enable_i_4(destuff_enable_i_4), .err_warning_limit_q(err_warning_limit_q), .err_warning_limit_q1_carry__0_0(err_warning_limit_q1_carry__0), .\err_warning_limit_q1_inferred__0/i__carry__0_0 (DI), .\err_warning_limit_q1_inferred__0/i__carry__0_1 ({i_mac_fc_err_counters_n_58,i_mac_fc_err_counters_n_59,i_mac_fc_err_counters_n_60,i_mac_fc_err_counters_n_61}), .err_warning_limit_q_reg_0(err_warning_limit_q_reg), .err_warning_limit_q_reg_1(i_mac_fc_err_counters_n_71), .err_warning_limit_q_reg_2(i_mac_fc_err_counters_n_72), .int_status_reg(int_status_reg), .int_status_reg_0(\FSM_sequential_curr_state_reg[0]_7 ), .int_status_reg_1(i_mac_fc_err_counters_n_70), .int_status_reg_2(int_status_reg_0), .int_status_reg_3(int_status_reg_1), .int_status_reg_4(int_status_reg_2), .\mr_ctrl_out[btr_fd_ph2_fd] (\mr_ctrl_out[btr_fd_ph2_fd] ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_tbfbo] (\mr_ctrl_out[settings_tbfbo] ), .mr_int_stat_fcsi_o(mr_int_stat_fcsi_o), .next_state2_carry__0_0({i_mac_fc_err_counters_n_62,i_mac_fc_err_counters_n_63,i_mac_fc_err_counters_n_64,i_mac_fc_err_counters_n_65}), .next_state2_carry__0_1(next_state2_carry__0), .\next_state2_inferred__0/i__carry__0_0 ({i_mac_fc_err_counters_n_66,i_mac_fc_err_counters_n_67,i_mac_fc_err_counters_n_68,i_mac_fc_err_counters_n_69}), .\next_state2_inferred__0/i__carry__0_1 (\next_state2_inferred__0/i__carry__0 ), .reg_q_reg(reg_q_reg), .reg_q_reg_0(reg_q_reg_0), .reg_q_reg_1(reg_q_reg_1), .reg_q_reg_2(reg_q_reg_2), .reg_q_reg_3(reg_q_reg_3), .reg_q_reg_4(reg_q_reg_4), .\rx_err_ctr_q_reg[8] (rx_err_ctr_mt_erp), .tran_frame_valid(tran_frame_valid), .\tx_err_ctr_q_reg[8] (tx_err_ctr_mt_ewl), .\tx_err_ctr_q_reg[8]_0 (tx_err_ctr_mt_erp), .tx_frame_no_sof_q_i_2(tx_frame_no_sof_q_i_2)); endmodule module mac_operation_control (\adress[4] , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[1]_0 , tx_err_ctr_q, \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \g_bit[0].reg_value_r_reg[0] , \cc_stat[is_receiver] , \FSM_sequential_curr_state_reg[1]_4 , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , rec_frame_type_i_reg, tran_ident_type_com_reg, \g_bit[0].reg_value_r_reg[0]_2 , \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state_reg[1]_5 , \tran_dlc_com_reg[0] , \FSM_sequential_curr_state_reg[1]_6 , \g_bit[0].reg_value_r_reg[0]_3 , \g_bit[0].reg_value_r_reg[0]_4 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[0]_3 , \g_bit[0].reg_value_r_reg[0]_5 , adress_IBUF, \r_data[4]_i_2 , \mr_ctrl_out[mode_fde] , \tx_err_ctr_q_reg[0] , \tx_err_ctr_q_reg[0]_0 , mr_ctr_pres_ptx_q, \exp_seg_length_q[8]_i_9 , \exp_seg_length_q[8]_i_9_0 , \mr_ctrl_out[ssp_cfg_ssp_src] , can_tx_OBUF, D, \txtb_hw_cmd_q[arbl]_i_2 , \txtb_hw_cmd_q[arbl]_i_2_0 , E, \mr_ctrl_out[settings_ilbp] , \mr_ctrl_out[mode_rom] , Q, \FSM_sequential_curr_state[1]_i_6 , rx_err_ctr_sat1_carry_i_9, \mr_ctrl_out[settings_nisofd] , \shift_regs[31]_i_15 , tran_frame_type, \shift_regs[28]_i_8 , tran_ident_type, \FSM_sequential_curr_state[1]_i_16 , \ctrl_ctr_q_reg[6] , \ctrl_ctr_q_reg[6]_0 , \ctrl_ctr_q[3]_i_10 , \ctrl_ctr_q[4]_i_4 , p_131_in, rec_lbpf, \FSM_sequential_curr_state_reg[1]_8 , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[0]_4 , \FSM_sequential_curr_state_reg[0]_5 ); output \adress[4] ; output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[1]_0 ; output [0:0]tx_err_ctr_q; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \g_bit[0].reg_value_r_reg[0] ; output \cc_stat[is_receiver] ; output \FSM_sequential_curr_state_reg[1]_4 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output rec_frame_type_i_reg; output tran_ident_type_com_reg; output \g_bit[0].reg_value_r_reg[0]_2 ; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[0]_2 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \tran_dlc_com_reg[0] ; output \FSM_sequential_curr_state_reg[1]_6 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \g_bit[0].reg_value_r_reg[0]_4 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[0]_3 ; output \g_bit[0].reg_value_r_reg[0]_5 ; input [2:0]adress_IBUF; input \r_data[4]_i_2 ; input \mr_ctrl_out[mode_fde] ; input \tx_err_ctr_q_reg[0] ; input \tx_err_ctr_q_reg[0]_0 ; input mr_ctr_pres_ptx_q; input \exp_seg_length_q[8]_i_9 ; input \exp_seg_length_q[8]_i_9_0 ; input [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; input can_tx_OBUF; input [2:0]D; input \txtb_hw_cmd_q[arbl]_i_2 ; input \txtb_hw_cmd_q[arbl]_i_2_0 ; input [0:0]E; input \mr_ctrl_out[settings_ilbp] ; input \mr_ctrl_out[mode_rom] ; input [0:0]Q; input \FSM_sequential_curr_state[1]_i_6 ; input rx_err_ctr_sat1_carry_i_9; input \mr_ctrl_out[settings_nisofd] ; input \shift_regs[31]_i_15 ; input tran_frame_type; input \shift_regs[28]_i_8 ; input tran_ident_type; input [1:0]\FSM_sequential_curr_state[1]_i_16 ; input \ctrl_ctr_q_reg[6] ; input \ctrl_ctr_q_reg[6]_0 ; input [2:0]\ctrl_ctr_q[3]_i_10 ; input \ctrl_ctr_q[4]_i_4 ; input p_131_in; input rec_lbpf; input \FSM_sequential_curr_state_reg[1]_8 ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[0]_4 ; input \FSM_sequential_curr_state_reg[0]_5 ; wire [2:0]D; wire [0:0]E; wire [1:0]\FSM_sequential_curr_state[1]_i_16 ; wire \FSM_sequential_curr_state[1]_i_6 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire [0:0]Q; wire \adress[4] ; wire [2:0]adress_IBUF; wire can_tx_OBUF; wire \cc_stat[is_receiver] ; wire clk_sys_IBUF_BUFG; wire \ctrl_ctr_q[2]_i_14_n_0 ; wire [2:0]\ctrl_ctr_q[3]_i_10 ; wire \ctrl_ctr_q[4]_i_4 ; wire \ctrl_ctr_q[4]_i_7_n_0 ; wire \ctrl_ctr_q_reg[6] ; wire \ctrl_ctr_q_reg[6]_0 ; wire \exp_seg_length_q[8]_i_9 ; wire \exp_seg_length_q[8]_i_9_0 ; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[0].reg_value_r_reg[0]_5 ; wire mr_ctr_pres_ptx_q; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; wire p_131_in; wire \r_data[4]_i_11_n_0 ; wire \r_data[4]_i_2 ; wire rec_frame_type_i_reg; wire rec_lbpf; wire rx_err_ctr_sat1_carry_i_9; wire \shift_regs[28]_i_8 ; wire \shift_regs[31]_i_15 ; wire \tran_dlc_com_reg[0] ; wire tran_frame_type; wire tran_ident_type; wire tran_ident_type_com_reg; wire [0:0]tx_err_ctr_q; wire \tx_err_ctr_q_reg[0] ; wire \tx_err_ctr_q_reg[0]_0 ; wire \txtb_hw_cmd_q[arbl]_i_2 ; wire \txtb_hw_cmd_q[arbl]_i_2_0 ; (* FSM_ENCODED_STATES = "s_oc_off:00,s_oc_receiver:10,s_oc_transmitter:11,s_oc_idle:01" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_4 ), .D(\FSM_sequential_curr_state_reg[0]_5 ), .Q(\FSM_sequential_curr_state_reg[0]_0 )); (* FSM_ENCODED_STATES = "s_oc_off:00,s_oc_receiver:10,s_oc_transmitter:11,s_oc_idle:01" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_4 ), .D(\FSM_sequential_curr_state_reg[1]_8 ), .Q(\FSM_sequential_curr_state_reg[1]_0 )); LUT6 #( .INIT(64'h37FFF7FFF7FFF7FF)) crc_match_q_i_4 (.I0(\shift_regs[31]_i_15 ), .I1(\shift_regs[28]_i_8 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(tran_frame_type), .I5(\mr_ctrl_out[mode_fde] ), .O(rec_frame_type_i_reg)); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT3 #( .INIT(8'h80)) \crc_q[14]_i_16 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(Q), .O(\FSM_sequential_curr_state_reg[0]_3 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT4 #( .INIT(16'h0888)) \crc_q[14]_i_20 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(tran_frame_type), .I3(\mr_ctrl_out[mode_fde] ), .O(\FSM_sequential_curr_state_reg[0]_2 )); LUT6 #( .INIT(64'hA080200020002000)) \ctrl_ctr_q[1]_i_11 (.I0(\mr_ctrl_out[settings_nisofd] ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\shift_regs[31]_i_15 ), .I4(tran_frame_type), .I5(\mr_ctrl_out[mode_fde] ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000000C5555)) \ctrl_ctr_q[2]_i_10 (.I0(\ctrl_ctr_q[2]_i_14_n_0 ), .I1(\cc_stat[is_receiver] ), .I2(\mr_ctrl_out[mode_rom] ), .I3(D[0]), .I4(Q), .I5(\FSM_sequential_curr_state[1]_i_6 ), .O(\g_bit[0].reg_value_r_reg[0] )); LUT3 #( .INIT(8'h1F)) \ctrl_ctr_q[2]_i_14 (.I0(\g_bit[0].reg_value_r_reg[0]_1 ), .I1(\mr_ctrl_out[settings_nisofd] ), .I2(rec_frame_type_i_reg), .O(\ctrl_ctr_q[2]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT4 #( .INIT(16'h0400)) \ctrl_ctr_q[3]_i_19 (.I0(\FSM_sequential_curr_state[1]_i_6 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\mr_ctrl_out[mode_rom] ), .O(\FSM_sequential_curr_state_reg[1]_7 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT5 #( .INIT(32'h77FF0FFF)) \ctrl_ctr_q[4]_i_5 (.I0(\mr_ctrl_out[mode_fde] ), .I1(tran_frame_type), .I2(\shift_regs[31]_i_15 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'h5504000400045504)) \ctrl_ctr_q[4]_i_6 (.I0(\FSM_sequential_curr_state[1]_i_6 ), .I1(\mr_ctrl_out[settings_nisofd] ), .I2(\g_bit[0].reg_value_r_reg[0]_1 ), .I3(\ctrl_ctr_q[4]_i_4 ), .I4(\tran_dlc_com_reg[0] ), .I5(\ctrl_ctr_q[4]_i_7_n_0 ), .O(\g_bit[0].reg_value_r_reg[0]_4 )); LUT6 #( .INIT(64'h200020002FFF2000)) \ctrl_ctr_q[4]_i_7 (.I0(\ctrl_ctr_q[3]_i_10 [1]), .I1(\ctrl_ctr_q[3]_i_10 [2]), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(D[1]), .I5(D[2]), .O(\ctrl_ctr_q[4]_i_7_n_0 )); LUT6 #( .INIT(64'h200020002FFF2000)) \ctrl_ctr_q[5]_i_6 (.I0(\ctrl_ctr_q[3]_i_10 [0]), .I1(\ctrl_ctr_q[3]_i_10 [2]), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(D[0]), .I5(D[2]), .O(\tran_dlc_com_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT4 #( .INIT(16'hBF80)) \ctrl_ctr_q[6]_i_3 (.I0(\ctrl_ctr_q_reg[6] ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\ctrl_ctr_q_reg[6]_0 ), .O(\FSM_sequential_curr_state_reg[1]_5 )); LUT6 #( .INIT(64'h5040100010001000)) \curr_state[1]_i_8 (.I0(\mr_ctrl_out[settings_nisofd] ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\shift_regs[31]_i_15 ), .I4(tran_frame_type), .I5(\mr_ctrl_out[mode_fde] ), .O(\g_bit[0].reg_value_r_reg[0]_3 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT4 #( .INIT(16'h0800)) \curr_state[4]_i_9 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state[1]_i_16 [0]), .I3(\FSM_sequential_curr_state[1]_i_16 [1]), .O(\FSM_sequential_curr_state_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT3 #( .INIT(8'h45)) \err_capt_err_pos_q[0]_i_3 (.I0(tran_ident_type), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(tran_ident_type_com_reg)); LUT5 #( .INIT(32'h0F004F4F)) \r_data[4]_i_11 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[mode_fde] ), .I4(adress_IBUF[0]), .O(\r_data[4]_i_11_n_0 )); MUXF7 \r_data_reg[4]_i_6 (.I0(\r_data[4]_i_11_n_0 ), .I1(\r_data[4]_i_2 ), .O(\adress[4] ), .S(adress_IBUF[2])); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT5 #( .INIT(32'h80FF8000)) rec_lbpf_q_i_1 (.I0(\mr_ctrl_out[settings_ilbp] ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(p_131_in), .I4(rec_lbpf), .O(\g_bit[0].reg_value_r_reg[0]_5 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT3 #( .INIT(8'h45)) rec_valid_i_3 (.I0(\mr_ctrl_out[settings_ilbp] ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(\g_bit[0].reg_value_r_reg[0]_2 )); LUT6 #( .INIT(64'h0080000000800080)) rx_data_sync_prev_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\exp_seg_length_q[8]_i_9 ), .I3(\exp_seg_length_q[8]_i_9_0 ), .I4(\mr_ctrl_out[ssp_cfg_ssp_src] [1]), .I5(\mr_ctrl_out[ssp_cfg_ssp_src] [0]), .O(\FSM_sequential_curr_state_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT4 #( .INIT(16'hFFFB)) rx_err_ctr_sat1_carry_i_11 (.I0(rx_err_ctr_sat1_carry_i_9), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\mr_ctrl_out[mode_rom] ), .O(\FSM_sequential_curr_state_reg[1]_4 )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT2 #( .INIT(4'h2)) store_data_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .O(\cc_stat[is_receiver] )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT4 #( .INIT(16'hAA08)) store_metadata_i_1 (.I0(E), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\mr_ctrl_out[settings_ilbp] ), .O(\FSM_sequential_curr_state_reg[1]_3 )); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT5 #( .INIT(32'hFFFF8088)) \tx_err_ctr_q[8]_i_1 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\tx_err_ctr_q_reg[0] ), .I3(\tx_err_ctr_q_reg[0]_0 ), .I4(mr_ctr_pres_ptx_q), .O(tx_err_ctr_q)); LUT6 #( .INIT(64'h0000000000800000)) \txtb_hw_cmd_q[arbl]_i_4 (.I0(can_tx_OBUF), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(D[0]), .I4(\txtb_hw_cmd_q[arbl]_i_2 ), .I5(\txtb_hw_cmd_q[arbl]_i_2_0 ), .O(\FSM_sequential_curr_state_reg[1]_2 )); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT2 #( .INIT(4'h8)) \txtb_hw_cmd_q[valid]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state_reg[1]_6 )); endmodule module mac_pc_control_counter (D, \alc_alc_bit_reg[2]_0 , rx_shift_cmd, Q, \compl_ctr_q_reg[3]_0 , \ctrl_ctr_q_reg[1]_0 , \g_bit[0].reg_value_r_reg[0] , \ctrl_ctr_q_reg[7]_0 , \g_bit[0].reg_value_r_reg[0]_0 , reg_q_reg, reg_q_reg_0, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , reg_q_reg_1, E, \compl_ctr_q_reg[7]_0 , \txtb_ptr_q_reg[4] , \txtb_ptr_q_reg[0] , \compl_ctr_q_reg[5]_0 , \ctrl_ctr_q_reg[1]_1 , \ctrl_ctr_q_reg[8]_0 , rx_data_nbs_prev_reg, \ctrl_ctr_q_reg[4]_0 , \ctrl_ctr_q_reg[3]_0 , \curr_state_reg[3] , \g_bit[0].reg_value_r_reg[0]_3 , rx_data_nbs_prev_reg_0, reg_q_reg_2, \curr_state_reg[2] , \curr_state_reg[5] , \alc_alc_bit_reg[4]_0 , \alc_alc_id_field_reg[2]_0 , sbe_IBUF, adress_IBUF, \r_data_reg[19] , \r_data_reg[19]_0 , \r_data_reg[19]_1 , \mr_ctrl_out[settings_rtrth] , \r_data[19]_i_2_0 , \r_data[19]_i_2_1 , \r_data_reg[18] , \r_data_reg[18]_0 , \g_byte_shift_reg[0].shift_reg_q_reg[0][0] , \g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 , \compl_ctr_q_reg[0]_0 , \compl_ctr_q_reg[1]_0 , \ctrl_ctr_q_reg[8]_1 , \ctrl_ctr_q_reg[2]_0 , \ctrl_ctr_q_reg[2]_1 , \ctrl_ctr_q_reg[5]_0 , \ctrl_ctr_q_reg[5]_1 , \ctrl_ctr_q_reg[5]_2 , \ctrl_ctr_q_reg[6]_0 , \ctrl_ctr_q_reg[6]_1 , \ctrl_ctr_q_reg[7]_1 , \ctrl_ctr_q_reg[7]_2 , store_data_reg, store_data_reg_0, \mr_ctrl_out[settings_ilbp] , \cc_stat[is_receiver] , \mr_ctrl_out[settings_pex] , \ctrl_ctr_q[1]_i_9 , \mr_ctrl_out[mode_fde] , \ctrl_ctr_q[2]_i_4 , \FSM_sequential_curr_state[0]_i_3__1 , \FSM_sequential_curr_state[0]_i_3__1_0 , \ctrl_ctr_q[1]_i_9_0 , \ctrl_ctr_q[1]_i_12 , \mr_ctrl_out[settings_nisofd] , \mr_ctrl_out[settings_ena] , \ctrl_ctr_q[2]_i_4_0 , \cc_stat[is_bus_off] , \mr_ctrl_out[mode_rom] , \txtb_ptr_q_reg[4]_0 , \txtb_ptr_q_reg[4]_1 , \txtb_ptr_q_reg[4]_2 , \txtb_ptr_q_reg[4]_3 , \txtb_ptr_q[4]_i_3 , \txtb_ptr_q_reg[4]_4 , \txtb_ptr_q_reg[2] , \txtb_ptr_q_reg[2]_0 , \ctrl_ctr_q[1]_i_9_1 , \ctrl_ctr_q[0]_i_4 , \ctrl_ctr_q[0]_i_4_0 , sync_edge, \ctrl_ctr_q_reg[8]_2 , clk_sys_IBUF_BUFG, \alc_alc_bit_reg[4]_1 , \compl_ctr_q_reg[8]_0 , \alc_alc_bit_reg[0]_0 , \alc_alc_id_field_reg[2]_1 ); output [0:0]D; output \alc_alc_bit_reg[2]_0 ; output [3:0]rx_shift_cmd; output [0:0]Q; output \compl_ctr_q_reg[3]_0 ; output [1:0]\ctrl_ctr_q_reg[1]_0 ; output \g_bit[0].reg_value_r_reg[0] ; output \ctrl_ctr_q_reg[7]_0 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output reg_q_reg; output reg_q_reg_0; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[0].reg_value_r_reg[0]_2 ; output reg_q_reg_1; output [0:0]E; output [3:0]\compl_ctr_q_reg[7]_0 ; output \txtb_ptr_q_reg[4] ; output \txtb_ptr_q_reg[0] ; output \compl_ctr_q_reg[5]_0 ; output \ctrl_ctr_q_reg[1]_1 ; output \ctrl_ctr_q_reg[8]_0 ; output rx_data_nbs_prev_reg; output \ctrl_ctr_q_reg[4]_0 ; output \ctrl_ctr_q_reg[3]_0 ; output \curr_state_reg[3] ; output \g_bit[0].reg_value_r_reg[0]_3 ; output rx_data_nbs_prev_reg_0; output reg_q_reg_2; output \curr_state_reg[2] ; output \curr_state_reg[5] ; output [2:0]\alc_alc_bit_reg[4]_0 ; output [2:0]\alc_alc_id_field_reg[2]_0 ; input [0:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[19] ; input \r_data_reg[19]_0 ; input \r_data_reg[19]_1 ; input [0:0]\mr_ctrl_out[settings_rtrth] ; input \r_data[19]_i_2_0 ; input \r_data[19]_i_2_1 ; input \r_data_reg[18] ; input \r_data_reg[18]_0 ; input \g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; input \g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ; input [0:0]\compl_ctr_q_reg[0]_0 ; input \compl_ctr_q_reg[1]_0 ; input [4:0]\ctrl_ctr_q_reg[8]_1 ; input \ctrl_ctr_q_reg[2]_0 ; input \ctrl_ctr_q_reg[2]_1 ; input \ctrl_ctr_q_reg[5]_0 ; input \ctrl_ctr_q_reg[5]_1 ; input \ctrl_ctr_q_reg[5]_2 ; input \ctrl_ctr_q_reg[6]_0 ; input \ctrl_ctr_q_reg[6]_1 ; input \ctrl_ctr_q_reg[7]_1 ; input \ctrl_ctr_q_reg[7]_2 ; input store_data_reg; input store_data_reg_0; input \mr_ctrl_out[settings_ilbp] ; input \cc_stat[is_receiver] ; input \mr_ctrl_out[settings_pex] ; input [0:0]\ctrl_ctr_q[1]_i_9 ; input \mr_ctrl_out[mode_fde] ; input [3:0]\ctrl_ctr_q[2]_i_4 ; input \FSM_sequential_curr_state[0]_i_3__1 ; input \FSM_sequential_curr_state[0]_i_3__1_0 ; input \ctrl_ctr_q[1]_i_9_0 ; input \ctrl_ctr_q[1]_i_12 ; input \mr_ctrl_out[settings_nisofd] ; input \mr_ctrl_out[settings_ena] ; input \ctrl_ctr_q[2]_i_4_0 ; input \cc_stat[is_bus_off] ; input \mr_ctrl_out[mode_rom] ; input \txtb_ptr_q_reg[4]_0 ; input \txtb_ptr_q_reg[4]_1 ; input \txtb_ptr_q_reg[4]_2 ; input \txtb_ptr_q_reg[4]_3 ; input [3:0]\txtb_ptr_q[4]_i_3 ; input \txtb_ptr_q_reg[4]_4 ; input \txtb_ptr_q_reg[2] ; input \txtb_ptr_q_reg[2]_0 ; input \ctrl_ctr_q[1]_i_9_1 ; input \ctrl_ctr_q[0]_i_4 ; input \ctrl_ctr_q[0]_i_4_0 ; input sync_edge; input [0:0]\ctrl_ctr_q_reg[8]_2 ; input clk_sys_IBUF_BUFG; input \alc_alc_bit_reg[4]_1 ; input [0:0]\compl_ctr_q_reg[8]_0 ; input \alc_alc_bit_reg[0]_0 ; input [2:0]\alc_alc_id_field_reg[2]_1 ; wire [0:0]D; wire [0:0]E; wire \FSM_sequential_curr_state[0]_i_3__1 ; wire \FSM_sequential_curr_state[0]_i_3__1_0 ; wire [0:0]Q; wire [5:0]adress_IBUF; wire \alc_alc_bit_reg[0]_0 ; wire \alc_alc_bit_reg[2]_0 ; wire [2:0]\alc_alc_bit_reg[4]_0 ; wire \alc_alc_bit_reg[4]_1 ; wire [2:0]\alc_alc_id_field_reg[2]_0 ; wire [2:0]\alc_alc_id_field_reg[2]_1 ; wire [3:2]\cc_stat[alc_bit] ; wire \cc_stat[is_bus_off] ; wire \cc_stat[is_receiver] ; wire clk_sys_IBUF_BUFG; wire [8:1]compl_ctr_d; wire [3:0]compl_ctr_div_32; wire [0:0]\compl_ctr_q_reg[0]_0 ; wire \compl_ctr_q_reg[1]_0 ; wire \compl_ctr_q_reg[3]_0 ; wire \compl_ctr_q_reg[5]_0 ; wire [3:0]\compl_ctr_q_reg[7]_0 ; wire [0:0]\compl_ctr_q_reg[8]_0 ; wire \compl_ctr_q_reg_n_0_[1] ; wire \compl_ctr_q_reg_n_0_[2] ; wire [1:0]ctrl_counted_byte_index; wire [7:2]ctrl_ctr_d; wire \ctrl_ctr_q[0]_i_4 ; wire \ctrl_ctr_q[0]_i_4_0 ; wire \ctrl_ctr_q[1]_i_12 ; wire [0:0]\ctrl_ctr_q[1]_i_9 ; wire \ctrl_ctr_q[1]_i_9_0 ; wire \ctrl_ctr_q[1]_i_9_1 ; wire [3:0]\ctrl_ctr_q[2]_i_4 ; wire \ctrl_ctr_q[2]_i_4_0 ; wire \ctrl_ctr_q[5]_i_2_n_0 ; wire \ctrl_ctr_q[6]_i_2_n_0 ; wire \ctrl_ctr_q[7]_i_2_n_0 ; wire [1:0]\ctrl_ctr_q_reg[1]_0 ; wire \ctrl_ctr_q_reg[1]_1 ; wire \ctrl_ctr_q_reg[2]_0 ; wire \ctrl_ctr_q_reg[2]_1 ; wire \ctrl_ctr_q_reg[3]_0 ; wire \ctrl_ctr_q_reg[4]_0 ; wire \ctrl_ctr_q_reg[5]_0 ; wire \ctrl_ctr_q_reg[5]_1 ; wire \ctrl_ctr_q_reg[5]_2 ; wire \ctrl_ctr_q_reg[6]_0 ; wire \ctrl_ctr_q_reg[6]_1 ; wire \ctrl_ctr_q_reg[7]_0 ; wire \ctrl_ctr_q_reg[7]_1 ; wire \ctrl_ctr_q_reg[7]_2 ; wire \ctrl_ctr_q_reg[8]_0 ; wire [4:0]\ctrl_ctr_q_reg[8]_1 ; wire [0:0]\ctrl_ctr_q_reg[8]_2 ; wire \ctrl_ctr_q_reg_n_0_[2] ; wire \ctrl_ctr_q_reg_n_0_[3] ; wire \ctrl_ctr_q_reg_n_0_[4] ; wire \ctrl_ctr_q_reg_n_0_[5] ; wire \ctrl_ctr_q_reg_n_0_[6] ; wire \ctrl_ctr_q_reg_n_0_[7] ; wire \ctrl_ctr_q_reg_n_0_[8] ; wire \curr_state_reg[2] ; wire \curr_state_reg[3] ; wire \curr_state_reg[5] ; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire [0:0]\mr_ctrl_out[settings_rtrth] ; wire \r_data[19]_i_2_0 ; wire \r_data[19]_i_2_1 ; wire \r_data[19]_i_2_n_0 ; wire \r_data[19]_i_4_n_0 ; wire \r_data_reg[18] ; wire \r_data_reg[18]_0 ; wire \r_data_reg[19] ; wire \r_data_reg[19]_0 ; wire \r_data_reg[19]_1 ; wire rec_valid_i_7_n_0; wire rec_valid_i_8_n_0; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire rx_data_nbs_prev_reg; wire rx_data_nbs_prev_reg_0; wire [3:0]rx_shift_cmd; wire [0:0]sbe_IBUF; wire store_data_reg; wire store_data_reg_0; wire sync_edge; wire [3:0]\txtb_ptr_q[4]_i_3 ; wire \txtb_ptr_q_reg[0] ; wire \txtb_ptr_q_reg[2] ; wire \txtb_ptr_q_reg[2]_0 ; wire \txtb_ptr_q_reg[4] ; wire \txtb_ptr_q_reg[4]_0 ; wire \txtb_ptr_q_reg[4]_1 ; wire \txtb_ptr_q_reg[4]_2 ; wire \txtb_ptr_q_reg[4]_3 ; wire \txtb_ptr_q_reg[4]_4 ; (* SOFT_HLUTNM = "soft_lutpair200" *) LUT4 #( .INIT(16'h0010)) \FSM_sequential_curr_state[0]_i_5__1 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\FSM_sequential_curr_state[0]_i_3__1 ), .I2(\FSM_sequential_curr_state[0]_i_3__1_0 ), .I3(\ctrl_ctr_q[1]_i_9_0 ), .O(reg_q_reg_0)); FDCE \alc_alc_bit_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[1]_0 [0]), .Q(\alc_alc_bit_reg[4]_0 [0])); FDCE \alc_alc_bit_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[1]_0 [1]), .Q(\alc_alc_bit_reg[4]_0 [1])); FDCE \alc_alc_bit_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg_n_0_[2] ), .Q(\cc_stat[alc_bit] [2])); FDCE \alc_alc_bit_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg_n_0_[3] ), .Q(\cc_stat[alc_bit] [3])); FDCE \alc_alc_bit_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg_n_0_[4] ), .Q(\alc_alc_bit_reg[4]_0 [2])); FDCE \alc_alc_id_field_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\alc_alc_id_field_reg[2]_1 [0]), .Q(\alc_alc_id_field_reg[2]_0 [0])); FDCE \alc_alc_id_field_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\alc_alc_id_field_reg[2]_1 [1]), .Q(\alc_alc_id_field_reg[2]_0 [1])); FDCE \alc_alc_id_field_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\alc_alc_bit_reg[0]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\alc_alc_id_field_reg[2]_1 [2]), .Q(\alc_alc_id_field_reg[2]_0 [2])); (* SOFT_HLUTNM = "soft_lutpair205" *) LUT3 #( .INIT(8'h28)) \compl_ctr_q[1]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(\compl_ctr_q_reg_n_0_[1] ), .I2(Q), .O(compl_ctr_d[1])); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT4 #( .INIT(16'h2A80)) \compl_ctr_q[2]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(Q), .I2(\compl_ctr_q_reg_n_0_[1] ), .I3(\compl_ctr_q_reg_n_0_[2] ), .O(compl_ctr_d[2])); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h2AAA8000)) \compl_ctr_q[3]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(\compl_ctr_q_reg_n_0_[1] ), .I2(Q), .I3(\compl_ctr_q_reg_n_0_[2] ), .I4(ctrl_counted_byte_index[0]), .O(compl_ctr_d[3])); LUT6 #( .INIT(64'h2AAAAAAA80000000)) \compl_ctr_q[4]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(ctrl_counted_byte_index[0]), .I2(\compl_ctr_q_reg_n_0_[2] ), .I3(Q), .I4(\compl_ctr_q_reg_n_0_[1] ), .I5(ctrl_counted_byte_index[1]), .O(compl_ctr_d[4])); (* SOFT_HLUTNM = "soft_lutpair205" *) LUT3 #( .INIT(8'h82)) \compl_ctr_q[5]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(\compl_ctr_q_reg[3]_0 ), .I2(compl_ctr_div_32[0]), .O(compl_ctr_d[5])); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT4 #( .INIT(16'hA208)) \compl_ctr_q[6]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(compl_ctr_div_32[0]), .I2(\compl_ctr_q_reg[3]_0 ), .I3(compl_ctr_div_32[1]), .O(compl_ctr_d[6])); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT5 #( .INIT(32'hAA2A0080)) \compl_ctr_q[7]_i_1 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(compl_ctr_div_32[1]), .I2(compl_ctr_div_32[0]), .I3(\compl_ctr_q_reg[3]_0 ), .I4(compl_ctr_div_32[2]), .O(compl_ctr_d[7])); LUT6 #( .INIT(64'h8AAAAAAA20000000)) \compl_ctr_q[8]_i_2 (.I0(\compl_ctr_q_reg[1]_0 ), .I1(\compl_ctr_q_reg[3]_0 ), .I2(compl_ctr_div_32[0]), .I3(compl_ctr_div_32[1]), .I4(compl_ctr_div_32[2]), .I5(compl_ctr_div_32[3]), .O(compl_ctr_d[8])); FDCE \compl_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\compl_ctr_q_reg[0]_0 ), .Q(Q)); FDCE \compl_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[1]), .Q(\compl_ctr_q_reg_n_0_[1] )); FDCE \compl_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[2]), .Q(\compl_ctr_q_reg_n_0_[2] )); FDCE \compl_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[3]), .Q(ctrl_counted_byte_index[0])); FDCE \compl_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[4]), .Q(ctrl_counted_byte_index[1])); FDCE \compl_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[5]), .Q(compl_ctr_div_32[0])); FDCE \compl_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[6]), .Q(compl_ctr_div_32[1])); FDCE \compl_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[7]), .Q(compl_ctr_div_32[2])); FDCE \compl_ctr_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\compl_ctr_q_reg[8]_0 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(compl_ctr_d[8]), .Q(compl_ctr_div_32[3])); (* SOFT_HLUTNM = "soft_lutpair206" *) LUT3 #( .INIT(8'hFE)) \ctrl_ctr_q[0]_i_12 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[1]_i_12 ), .I2(\mr_ctrl_out[settings_nisofd] ), .O(\g_bit[0].reg_value_r_reg[0]_3 )); LUT6 #( .INIT(64'h0000000400000000)) \ctrl_ctr_q[0]_i_8 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[2]_i_4 [1]), .I2(\ctrl_ctr_q[1]_i_9 ), .I3(\mr_ctrl_out[mode_rom] ), .I4(\ctrl_ctr_q[0]_i_4 ), .I5(\ctrl_ctr_q[0]_i_4_0 ), .O(\curr_state_reg[3] )); (* SOFT_HLUTNM = "soft_lutpair207" *) LUT3 #( .INIT(8'h41)) \ctrl_ctr_q[1]_i_16 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[1]_i_9_1 ), .I2(\ctrl_ctr_q[1]_i_9 ), .O(rx_data_nbs_prev_reg_0)); LUT6 #( .INIT(64'h0D0D0D0D0000FF00)) \ctrl_ctr_q[1]_i_19 (.I0(\mr_ctrl_out[settings_nisofd] ), .I1(\ctrl_ctr_q[1]_i_12 ), .I2(\ctrl_ctr_q_reg[7]_0 ), .I3(\mr_ctrl_out[settings_ena] ), .I4(\ctrl_ctr_q[1]_i_9 ), .I5(\ctrl_ctr_q[2]_i_4 [2]), .O(\g_bit[0].reg_value_r_reg[0]_2 )); LUT6 #( .INIT(64'hA900A900A900A9FF)) \ctrl_ctr_q[2]_i_1 (.I0(\ctrl_ctr_q_reg_n_0_[2] ), .I1(\ctrl_ctr_q_reg[1]_0 [1]), .I2(\ctrl_ctr_q_reg[1]_0 [0]), .I3(\compl_ctr_q_reg[1]_0 ), .I4(\ctrl_ctr_q_reg[2]_0 ), .I5(\ctrl_ctr_q_reg[2]_1 ), .O(ctrl_ctr_d[2])); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT3 #( .INIT(8'h82)) \ctrl_ctr_q[2]_i_15 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[1]_i_9_1 ), .I2(\ctrl_ctr_q[1]_i_9 ), .O(rx_data_nbs_prev_reg)); (* SOFT_HLUTNM = "soft_lutpair207" *) LUT3 #( .INIT(8'hD0)) \ctrl_ctr_q[2]_i_5 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[1]_i_9 ), .I2(\ctrl_ctr_q[2]_i_4 [3]), .O(reg_q_reg_2)); LUT2 #( .INIT(4'hB)) \ctrl_ctr_q[2]_i_8 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[2]_i_4 [3]), .O(\curr_state_reg[5] )); LUT6 #( .INIT(64'hFFCFFF55FCCFFF55)) \ctrl_ctr_q[2]_i_9 (.I0(\ctrl_ctr_q[2]_i_4_0 ), .I1(\cc_stat[is_bus_off] ), .I2(\ctrl_ctr_q[1]_i_9 ), .I3(\ctrl_ctr_q_reg[7]_0 ), .I4(\ctrl_ctr_q[2]_i_4 [1]), .I5(\mr_ctrl_out[mode_rom] ), .O(reg_q_reg_1)); LUT5 #( .INIT(32'hFF00F7F7)) \ctrl_ctr_q[3]_i_11 (.I0(\mr_ctrl_out[settings_pex] ), .I1(\ctrl_ctr_q[1]_i_9 ), .I2(\mr_ctrl_out[mode_fde] ), .I3(reg_q_reg), .I4(\ctrl_ctr_q[2]_i_4 [2]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair204" *) LUT4 #( .INIT(16'hAAA9)) \ctrl_ctr_q[3]_i_2 (.I0(\ctrl_ctr_q_reg_n_0_[3] ), .I1(\ctrl_ctr_q_reg[1]_0 [0]), .I2(\ctrl_ctr_q_reg[1]_0 [1]), .I3(\ctrl_ctr_q_reg_n_0_[2] ), .O(\ctrl_ctr_q_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT4 #( .INIT(16'h2022)) \ctrl_ctr_q[3]_i_22 (.I0(\ctrl_ctr_q[1]_i_9 ), .I1(sync_edge), .I2(\ctrl_ctr_q_reg[7]_0 ), .I3(\ctrl_ctr_q[1]_i_9_0 ), .O(reg_q_reg)); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'hAAAAAAA9)) \ctrl_ctr_q[4]_i_2 (.I0(\ctrl_ctr_q_reg_n_0_[4] ), .I1(\ctrl_ctr_q_reg_n_0_[3] ), .I2(\ctrl_ctr_q_reg_n_0_[2] ), .I3(\ctrl_ctr_q_reg[1]_0 [1]), .I4(\ctrl_ctr_q_reg[1]_0 [0]), .O(\ctrl_ctr_q_reg[4]_0 )); LUT6 #( .INIT(64'h9F90909090909F90)) \ctrl_ctr_q[5]_i_1 (.I0(\ctrl_ctr_q[5]_i_2_n_0 ), .I1(\ctrl_ctr_q_reg_n_0_[5] ), .I2(\compl_ctr_q_reg[1]_0 ), .I3(\ctrl_ctr_q_reg[5]_0 ), .I4(\ctrl_ctr_q_reg[5]_1 ), .I5(\ctrl_ctr_q_reg[5]_2 ), .O(ctrl_ctr_d[5])); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'hFFFFFFFE)) \ctrl_ctr_q[5]_i_2 (.I0(\ctrl_ctr_q_reg[1]_0 [1]), .I1(\ctrl_ctr_q_reg[1]_0 [0]), .I2(\ctrl_ctr_q_reg_n_0_[3] ), .I3(\ctrl_ctr_q_reg_n_0_[2] ), .I4(\ctrl_ctr_q_reg_n_0_[4] ), .O(\ctrl_ctr_q[5]_i_2_n_0 )); LUT6 #( .INIT(64'h60606F606F606060)) \ctrl_ctr_q[6]_i_1 (.I0(\ctrl_ctr_q_reg_n_0_[6] ), .I1(\ctrl_ctr_q[6]_i_2_n_0 ), .I2(\compl_ctr_q_reg[1]_0 ), .I3(\ctrl_ctr_q_reg[5]_0 ), .I4(\ctrl_ctr_q_reg[6]_0 ), .I5(\ctrl_ctr_q_reg[6]_1 ), .O(ctrl_ctr_d[6])); LUT6 #( .INIT(64'h0000000000000001)) \ctrl_ctr_q[6]_i_2 (.I0(\ctrl_ctr_q_reg_n_0_[5] ), .I1(\ctrl_ctr_q_reg_n_0_[4] ), .I2(\ctrl_ctr_q_reg_n_0_[2] ), .I3(\ctrl_ctr_q_reg_n_0_[3] ), .I4(\ctrl_ctr_q_reg[1]_0 [0]), .I5(\ctrl_ctr_q_reg[1]_0 [1]), .O(\ctrl_ctr_q[6]_i_2_n_0 )); LUT6 #( .INIT(64'h60606F606F606060)) \ctrl_ctr_q[7]_i_1 (.I0(\ctrl_ctr_q_reg_n_0_[7] ), .I1(\ctrl_ctr_q[7]_i_2_n_0 ), .I2(\compl_ctr_q_reg[1]_0 ), .I3(\ctrl_ctr_q_reg[5]_0 ), .I4(\ctrl_ctr_q_reg[7]_1 ), .I5(\ctrl_ctr_q_reg[7]_2 ), .O(ctrl_ctr_d[7])); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT3 #( .INIT(8'h01)) \ctrl_ctr_q[7]_i_2 (.I0(\ctrl_ctr_q_reg_n_0_[6] ), .I1(\ctrl_ctr_q_reg_n_0_[5] ), .I2(\ctrl_ctr_q[5]_i_2_n_0 ), .O(\ctrl_ctr_q[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT5 #( .INIT(32'hAAAAAAA9)) \ctrl_ctr_q[8]_i_8 (.I0(\ctrl_ctr_q_reg_n_0_[8] ), .I1(\ctrl_ctr_q_reg_n_0_[7] ), .I2(\ctrl_ctr_q_reg_n_0_[6] ), .I3(\ctrl_ctr_q_reg_n_0_[5] ), .I4(\ctrl_ctr_q[5]_i_2_n_0 ), .O(\ctrl_ctr_q_reg[8]_0 )); FDCE \ctrl_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[8]_1 [0]), .Q(\ctrl_ctr_q_reg[1]_0 [0])); FDCE \ctrl_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[8]_1 [1]), .Q(\ctrl_ctr_q_reg[1]_0 [1])); FDCE \ctrl_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(ctrl_ctr_d[2]), .Q(\ctrl_ctr_q_reg_n_0_[2] )); FDCE \ctrl_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[8]_1 [2]), .Q(\ctrl_ctr_q_reg_n_0_[3] )); FDCE \ctrl_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[8]_1 [3]), .Q(\ctrl_ctr_q_reg_n_0_[4] )); FDCE \ctrl_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(ctrl_ctr_d[5]), .Q(\ctrl_ctr_q_reg_n_0_[5] )); FDCE \ctrl_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(ctrl_ctr_d[6]), .Q(\ctrl_ctr_q_reg_n_0_[6] )); FDCE \ctrl_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(ctrl_ctr_d[7]), .Q(\ctrl_ctr_q_reg_n_0_[7] )); FDCE \ctrl_ctr_q_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\ctrl_ctr_q_reg[8]_2 ), .CLR(\alc_alc_bit_reg[4]_1 ), .D(\ctrl_ctr_q_reg[8]_1 [4]), .Q(\ctrl_ctr_q_reg_n_0_[8] )); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT2 #( .INIT(4'h2)) \curr_state[5]_i_17 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[2]_i_4 [0]), .O(\curr_state_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT4 #( .INIT(16'h02AA)) \g_byte_shift_reg[0].shift_reg_q[0][7]_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(ctrl_counted_byte_index[1]), .I2(ctrl_counted_byte_index[0]), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .O(rx_shift_cmd[0])); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT4 #( .INIT(16'h08AA)) \g_byte_shift_reg[1].shift_reg_q[1][7]_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(ctrl_counted_byte_index[0]), .I2(ctrl_counted_byte_index[1]), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .O(rx_shift_cmd[1])); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT4 #( .INIT(16'h08AA)) \g_byte_shift_reg[2].shift_reg_q[2][7]_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(ctrl_counted_byte_index[1]), .I2(ctrl_counted_byte_index[0]), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .O(rx_shift_cmd[2])); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT4 #( .INIT(16'hA222)) \g_byte_shift_reg[3].shift_reg_q[3][7]_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .I2(ctrl_counted_byte_index[1]), .I3(ctrl_counted_byte_index[0]), .O(rx_shift_cmd[3])); LUT6 #( .INIT(64'hFFFFFFFF0D000000)) \r_data[18]_i_3 (.I0(adress_IBUF[1]), .I1(\cc_stat[alc_bit] [2]), .I2(\r_data_reg[18] ), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[18]_0 ), .O(\alc_alc_bit_reg[2]_0 )); LUT6 #( .INIT(64'h020202020202A202)) \r_data[19]_i_1 (.I0(sbe_IBUF), .I1(\r_data[19]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[19] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D)); LUT6 #( .INIT(64'h5455000054555455)) \r_data[19]_i_2 (.I0(\r_data[19]_i_4_n_0 ), .I1(\r_data_reg[19]_0 ), .I2(adress_IBUF[4]), .I3(adress_IBUF[3]), .I4(\r_data_reg[19]_1 ), .I5(\mr_ctrl_out[settings_rtrth] ), .O(\r_data[19]_i_2_n_0 )); LUT6 #( .INIT(64'h4F00000040000000)) \r_data[19]_i_4 (.I0(\r_data[19]_i_2_0 ), .I1(\cc_stat[alc_bit] [3]), .I2(adress_IBUF[2]), .I3(adress_IBUF[4]), .I4(adress_IBUF[3]), .I5(\r_data[19]_i_2_1 ), .O(\r_data[19]_i_4_n_0 )); LUT5 #( .INIT(32'h00002000)) rec_valid_i_2 (.I0(rec_valid_i_7_n_0), .I1(\ctrl_ctr_q_reg[1]_0 [1]), .I2(\ctrl_ctr_q_reg[1]_0 [0]), .I3(\ctrl_ctr_q[2]_i_4 [2]), .I4(rec_valid_i_8_n_0), .O(\ctrl_ctr_q_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair204" *) LUT3 #( .INIT(8'h01)) rec_valid_i_7 (.I0(\ctrl_ctr_q_reg_n_0_[4] ), .I1(\ctrl_ctr_q_reg_n_0_[2] ), .I2(\ctrl_ctr_q_reg_n_0_[3] ), .O(rec_valid_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT4 #( .INIT(16'hFFFE)) rec_valid_i_8 (.I0(\ctrl_ctr_q_reg_n_0_[6] ), .I1(\ctrl_ctr_q_reg_n_0_[5] ), .I2(\ctrl_ctr_q_reg_n_0_[8] ), .I3(\ctrl_ctr_q_reg_n_0_[7] ), .O(rec_valid_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair206" *) LUT3 #( .INIT(8'hAB)) \shift_regs[31]_i_24 (.I0(\ctrl_ctr_q_reg[7]_0 ), .I1(\ctrl_ctr_q[1]_i_12 ), .I2(\mr_ctrl_out[settings_nisofd] ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'h0070007000700000)) store_data_i_1 (.I0(\compl_ctr_q_reg[3]_0 ), .I1(\ctrl_ctr_q_reg[7]_0 ), .I2(store_data_reg), .I3(store_data_reg_0), .I4(\mr_ctrl_out[settings_ilbp] ), .I5(\cc_stat[is_receiver] ), .O(\g_bit[0].reg_value_r_reg[0] )); LUT5 #( .INIT(32'h7FFFFFFF)) store_data_i_2 (.I0(ctrl_counted_byte_index[0]), .I1(ctrl_counted_byte_index[1]), .I2(\compl_ctr_q_reg_n_0_[2] ), .I3(Q), .I4(\compl_ctr_q_reg_n_0_[1] ), .O(\compl_ctr_q_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT5 #( .INIT(32'hFFFFFFFE)) store_data_i_3 (.I0(\ctrl_ctr_q_reg_n_0_[7] ), .I1(\ctrl_ctr_q_reg_n_0_[8] ), .I2(\ctrl_ctr_q_reg_n_0_[5] ), .I3(\ctrl_ctr_q_reg_n_0_[6] ), .I4(\ctrl_ctr_q[5]_i_2_n_0 ), .O(\ctrl_ctr_q_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT5 #( .INIT(32'h8000AAAA)) \txtb_ptr_q[0]_i_1 (.I0(\txtb_ptr_q_reg[4]_4 ), .I1(compl_ctr_div_32[3]), .I2(compl_ctr_div_32[2]), .I3(compl_ctr_div_32[1]), .I4(compl_ctr_div_32[0]), .O(\compl_ctr_q_reg[7]_0 [0])); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT5 #( .INIT(32'hA8282828)) \txtb_ptr_q[1]_i_1 (.I0(\txtb_ptr_q_reg[4]_4 ), .I1(compl_ctr_div_32[0]), .I2(compl_ctr_div_32[1]), .I3(compl_ctr_div_32[3]), .I4(compl_ctr_div_32[2]), .O(\compl_ctr_q_reg[7]_0 [1])); LUT6 #( .INIT(64'h0000250F00000000)) \txtb_ptr_q[2]_i_2 (.I0(compl_ctr_div_32[0]), .I1(compl_ctr_div_32[3]), .I2(compl_ctr_div_32[2]), .I3(compl_ctr_div_32[1]), .I4(\txtb_ptr_q_reg[2] ), .I5(\txtb_ptr_q_reg[2]_0 ), .O(\compl_ctr_q_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT5 #( .INIT(32'h15EA0000)) \txtb_ptr_q[3]_i_1 (.I0(compl_ctr_div_32[2]), .I1(compl_ctr_div_32[1]), .I2(compl_ctr_div_32[0]), .I3(compl_ctr_div_32[3]), .I4(\txtb_ptr_q_reg[4]_4 ), .O(\compl_ctr_q_reg[7]_0 [2])); LUT6 #( .INIT(64'h088A088A088A0AAA)) \txtb_ptr_q[4]_i_1 (.I0(\txtb_ptr_q_reg[4]_0 ), .I1(\txtb_ptr_q_reg[4]_1 ), .I2(\txtb_ptr_q_reg[4]_2 ), .I3(\compl_ctr_q_reg[7]_0 [3]), .I4(\txtb_ptr_q_reg[4]_3 ), .I5(\compl_ctr_q_reg[7]_0 [2]), .O(E)); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT5 #( .INIT(32'hEA000000)) \txtb_ptr_q[4]_i_2 (.I0(compl_ctr_div_32[2]), .I1(compl_ctr_div_32[1]), .I2(compl_ctr_div_32[0]), .I3(compl_ctr_div_32[3]), .I4(\txtb_ptr_q_reg[4]_4 ), .O(\compl_ctr_q_reg[7]_0 [3])); LUT6 #( .INIT(64'h4F44FFFFFFFF4F44)) \txtb_ptr_q[4]_i_8 (.I0(\compl_ctr_q_reg[7]_0 [0]), .I1(\txtb_ptr_q[4]_i_3 [0]), .I2(\txtb_ptr_q[4]_i_3 [1]), .I3(\compl_ctr_q_reg[7]_0 [1]), .I4(\compl_ctr_q_reg[7]_0 [2]), .I5(\txtb_ptr_q[4]_i_3 [2]), .O(\txtb_ptr_q_reg[0] )); LUT6 #( .INIT(64'h66F666F6FFFF66F6)) \txtb_ptr_q[4]_i_9 (.I0(\compl_ctr_q_reg[7]_0 [3]), .I1(\txtb_ptr_q[4]_i_3 [3]), .I2(\compl_ctr_q_reg[7]_0 [0]), .I3(\txtb_ptr_q[4]_i_3 [0]), .I4(\txtb_ptr_q[4]_i_3 [1]), .I5(\compl_ctr_q_reg[7]_0 [1]), .O(\txtb_ptr_q_reg[4] )); endmodule module mac_pc_err_detector (\cc_stat[err_erp] , err_frm_req_reg_0, \err_capt_err_type_q_reg[0]_0 , \err_capt_err_type_q_reg[2]_0 , err_capt_err_erp_reg_0, \err_capt_err_pos_q_reg[0]_0 , \err_capt_err_pos_q_reg[3]_0 , crc_match_q_reg_0, err_frm_req_reg_1, crc_match, err_frm_req_reg_2, reg_q_reg, reg_q_reg_0, err_frm_req_reg_3, err_frm_req_reg_4, err_frm_req_reg_5, err_frm_req_reg_6, err_frm_req_reg_7, err_capt_err_erp_reg_1, \cc_stat[is_err_passive] , clk_sys_IBUF_BUFG, crc_match_q_reg_1, S, crc_match_q_i_2_0, crc_match_c5_carry__0_0, crc_match_q_i_3_0, \crc_match_c6_inferred__0/i__carry__0_0 , crc_match_q_i_2_1, \mr_tx_priority[1] , adress_IBUF, \r_data_reg[5]_i_5 , \mr_tx_priority[0] , \r_data[0]_i_5 , err_capt_err_erp_reg_2, \cc_stat[is_receiver] , err_capt_err_erp_reg_3, ack_err_flag_reg, stuff_err, ack_err_flag_reg_0, \pc_dbg[is_arbitration] , ack_err_flag_reg_1, ack_err_flag_reg_2, ack_err_flag_reg_3, \g_byte_shift_reg[0].shift_reg_q_reg[0][0] , crc_match_q_reg_2, crc_match_q_reg_3, crc_match_q_i_2_2, crc_match_q_i_2_3, crc_match_q_reg_4, Q, \mr_ctrl_out[mode_rom] , reg_q_reg_1, D, \err_capt_err_pos_q_reg[3]_1 , crc_match_q_reg_5, crc_match_q_reg_6); output \cc_stat[err_erp] ; output err_frm_req_reg_0; output \err_capt_err_type_q_reg[0]_0 ; output [2:0]\err_capt_err_type_q_reg[2]_0 ; output err_capt_err_erp_reg_0; output \err_capt_err_pos_q_reg[0]_0 ; output [3:0]\err_capt_err_pos_q_reg[3]_0 ; output crc_match_q_reg_0; output err_frm_req_reg_1; output crc_match; output err_frm_req_reg_2; output reg_q_reg; output reg_q_reg_0; output err_frm_req_reg_3; output err_frm_req_reg_4; output err_frm_req_reg_5; output err_frm_req_reg_6; output err_frm_req_reg_7; input err_capt_err_erp_reg_1; input \cc_stat[is_err_passive] ; input clk_sys_IBUF_BUFG; input crc_match_q_reg_1; input [3:0]S; input [1:0]crc_match_q_i_2_0; input [3:0]crc_match_c5_carry__0_0; input [2:0]crc_match_q_i_3_0; input [3:0]\crc_match_c6_inferred__0/i__carry__0_0 ; input [0:0]crc_match_q_i_2_1; input [1:0]\mr_tx_priority[1] ; input [1:0]adress_IBUF; input [1:0]\r_data_reg[5]_i_5 ; input [0:0]\mr_tx_priority[0] ; input [0:0]\r_data[0]_i_5 ; input err_capt_err_erp_reg_2; input \cc_stat[is_receiver] ; input err_capt_err_erp_reg_3; input ack_err_flag_reg; input stuff_err; input [0:0]ack_err_flag_reg_0; input \pc_dbg[is_arbitration] ; input ack_err_flag_reg_1; input ack_err_flag_reg_2; input ack_err_flag_reg_3; input \g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; input crc_match_q_reg_2; input crc_match_q_reg_3; input crc_match_q_i_2_2; input crc_match_q_i_2_3; input crc_match_q_reg_4; input [2:0]Q; input \mr_ctrl_out[mode_rom] ; input reg_q_reg_1; input [2:0]D; input [3:0]\err_capt_err_pos_q_reg[3]_1 ; input crc_match_q_reg_5; input crc_match_q_reg_6; wire [2:0]D; wire [2:0]Q; wire [3:0]S; wire ack_err_flag_reg; wire [0:0]ack_err_flag_reg_0; wire ack_err_flag_reg_1; wire ack_err_flag_reg_2; wire ack_err_flag_reg_3; wire [1:0]adress_IBUF; wire \cc_stat[err_erp] ; wire \cc_stat[is_err_passive] ; wire \cc_stat[is_receiver] ; wire clk_sys_IBUF_BUFG; wire crc_15_ok; wire crc_17_ok; wire crc_21_ok; wire crc_match; wire [3:0]crc_match_c5_carry__0_0; wire crc_match_c5_carry_n_0; wire crc_match_c6_carry_n_0; wire [3:0]\crc_match_c6_inferred__0/i__carry__0_0 ; wire \crc_match_c6_inferred__0/i__carry_n_0 ; wire crc_match_d; wire crc_match_q_i_1_n_0; wire [1:0]crc_match_q_i_2_0; wire [0:0]crc_match_q_i_2_1; wire crc_match_q_i_2_2; wire crc_match_q_i_2_3; wire [2:0]crc_match_q_i_3_0; wire crc_match_q_i_3_n_0; wire crc_match_q_reg_0; wire crc_match_q_reg_1; wire crc_match_q_reg_2; wire crc_match_q_reg_3; wire crc_match_q_reg_4; wire crc_match_q_reg_5; wire crc_match_q_reg_6; wire err_capt_err_erp_reg_0; wire err_capt_err_erp_reg_1; wire err_capt_err_erp_reg_2; wire err_capt_err_erp_reg_3; wire \err_capt_err_pos_q_reg[0]_0 ; wire [3:0]\err_capt_err_pos_q_reg[3]_0 ; wire [3:0]\err_capt_err_pos_q_reg[3]_1 ; wire \err_capt_err_type_q_reg[0]_0 ; wire [2:0]\err_capt_err_type_q_reg[2]_0 ; wire err_frm_req_reg_0; wire err_frm_req_reg_1; wire err_frm_req_reg_2; wire err_frm_req_reg_3; wire err_frm_req_reg_4; wire err_frm_req_reg_5; wire err_frm_req_reg_6; wire err_frm_req_reg_7; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; wire \mr_ctrl_out[mode_rom] ; wire [0:0]\mr_tx_priority[0] ; wire [1:0]\mr_tx_priority[1] ; wire \pc_dbg[is_arbitration] ; wire [0:0]\r_data[0]_i_5 ; wire [1:0]\r_data_reg[5]_i_5 ; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire stuff_err; wire [2:0]NLW_crc_match_c5_carry_CO_UNCONNECTED; wire [3:0]NLW_crc_match_c5_carry_O_UNCONNECTED; wire [3:0]NLW_crc_match_c5_carry__0_CO_UNCONNECTED; wire [3:0]NLW_crc_match_c5_carry__0_O_UNCONNECTED; wire [2:0]NLW_crc_match_c6_carry_CO_UNCONNECTED; wire [3:0]NLW_crc_match_c6_carry_O_UNCONNECTED; wire [3:0]NLW_crc_match_c6_carry__0_CO_UNCONNECTED; wire [3:0]NLW_crc_match_c6_carry__0_O_UNCONNECTED; wire [2:0]\NLW_crc_match_c6_inferred__0/i__carry_CO_UNCONNECTED ; wire [3:0]\NLW_crc_match_c6_inferred__0/i__carry_O_UNCONNECTED ; wire [3:1]\NLW_crc_match_c6_inferred__0/i__carry__0_CO_UNCONNECTED ; wire [3:0]\NLW_crc_match_c6_inferred__0/i__carry__0_O_UNCONNECTED ; LUT6 #( .INIT(64'h0000000000400000)) ack_err_flag_i_2 (.I0(err_frm_req_reg_0), .I1(ack_err_flag_reg), .I2(ack_err_flag_reg_1), .I3(ack_err_flag_reg_2), .I4(ack_err_flag_reg_0), .I5(ack_err_flag_reg_3), .O(err_frm_req_reg_1)); CARRY4 crc_match_c5_carry (.CI(1'b0), .CO({crc_match_c5_carry_n_0,NLW_crc_match_c5_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_crc_match_c5_carry_O_UNCONNECTED[3:0]), .S(crc_match_c5_carry__0_0)); CARRY4 crc_match_c5_carry__0 (.CI(crc_match_c5_carry_n_0), .CO({NLW_crc_match_c5_carry__0_CO_UNCONNECTED[3],crc_21_ok,NLW_crc_match_c5_carry__0_CO_UNCONNECTED[1:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_crc_match_c5_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,crc_match_q_i_3_0})); CARRY4 crc_match_c6_carry (.CI(1'b0), .CO({crc_match_c6_carry_n_0,NLW_crc_match_c6_carry_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_crc_match_c6_carry_O_UNCONNECTED[3:0]), .S(S)); CARRY4 crc_match_c6_carry__0 (.CI(crc_match_c6_carry_n_0), .CO({NLW_crc_match_c6_carry__0_CO_UNCONNECTED[3:2],crc_17_ok,NLW_crc_match_c6_carry__0_CO_UNCONNECTED[0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(NLW_crc_match_c6_carry__0_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,crc_match_q_i_2_0})); CARRY4 \crc_match_c6_inferred__0/i__carry (.CI(1'b0), .CO({\crc_match_c6_inferred__0/i__carry_n_0 ,\NLW_crc_match_c6_inferred__0/i__carry_CO_UNCONNECTED [2:0]}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_crc_match_c6_inferred__0/i__carry_O_UNCONNECTED [3:0]), .S(\crc_match_c6_inferred__0/i__carry__0_0 )); CARRY4 \crc_match_c6_inferred__0/i__carry__0 (.CI(\crc_match_c6_inferred__0/i__carry_n_0 ), .CO({\NLW_crc_match_c6_inferred__0/i__carry__0_CO_UNCONNECTED [3:1],crc_15_ok}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_crc_match_c6_inferred__0/i__carry__0_O_UNCONNECTED [3:0]), .S({1'b0,1'b0,1'b0,crc_match_q_i_2_1})); LUT6 #( .INIT(64'hBABBBABA8A888A8A)) crc_match_q_i_1 (.I0(crc_match_d), .I1(crc_match_q_reg_4), .I2(crc_match_q_reg_5), .I3(err_frm_req_reg_0), .I4(crc_match_q_reg_6), .I5(crc_match), .O(crc_match_q_i_1_n_0)); LUT5 #( .INIT(32'h0D0D0D00)) crc_match_q_i_2 (.I0(crc_match_q_reg_2), .I1(crc_15_ok), .I2(crc_match_q_i_3_n_0), .I3(crc_17_ok), .I4(crc_match_q_reg_3), .O(crc_match_d)); LUT5 #( .INIT(32'hFFFFFFF1)) crc_match_q_i_3 (.I0(crc_match_q_i_2_2), .I1(crc_21_ok), .I2(crc_match_q_i_2_3), .I3(err_frm_req_reg_0), .I4(crc_match_q_reg_4), .O(crc_match_q_i_3_n_0)); FDCE crc_match_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(crc_match_q_reg_1), .D(crc_match_q_i_1_n_0), .Q(crc_match)); (* SOFT_HLUTNM = "soft_lutpair210" *) LUT2 #( .INIT(4'h8)) \ctrl_ctr_q[2]_i_2 (.I0(err_frm_req_reg_0), .I1(\mr_ctrl_out[mode_rom] ), .O(err_frm_req_reg_6)); (* SOFT_HLUTNM = "soft_lutpair210" *) LUT2 #( .INIT(4'h1)) \curr_state[4]_i_6 (.I0(err_frm_req_reg_0), .I1(Q[2]), .O(err_frm_req_reg_5)); FDCE err_capt_err_erp_reg (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .CLR(crc_match_q_reg_1), .D(\cc_stat[is_err_passive] ), .Q(\cc_stat[err_erp] )); FDPE \err_capt_err_pos_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .D(\err_capt_err_pos_q_reg[3]_1 [0]), .PRE(crc_match_q_reg_1), .Q(\err_capt_err_pos_q_reg[3]_0 [0])); FDPE \err_capt_err_pos_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .D(\err_capt_err_pos_q_reg[3]_1 [1]), .PRE(crc_match_q_reg_1), .Q(\err_capt_err_pos_q_reg[3]_0 [1])); FDPE \err_capt_err_pos_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .D(\err_capt_err_pos_q_reg[3]_1 [2]), .PRE(crc_match_q_reg_1), .Q(\err_capt_err_pos_q_reg[3]_0 [2])); FDPE \err_capt_err_pos_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .D(\err_capt_err_pos_q_reg[3]_1 [3]), .PRE(crc_match_q_reg_1), .Q(\err_capt_err_pos_q_reg[3]_0 [3])); LUT6 #( .INIT(64'hAABAAAAAAAAAAAAA)) \err_capt_err_type_q[2]_i_5 (.I0(err_frm_req_reg_1), .I1(err_capt_err_erp_reg_2), .I2(\cc_stat[is_receiver] ), .I3(crc_match), .I4(err_frm_req_reg_2), .I5(err_capt_err_erp_reg_3), .O(crc_match_q_reg_0)); FDCE \err_capt_err_type_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .CLR(crc_match_q_reg_1), .D(D[0]), .Q(\err_capt_err_type_q_reg[2]_0 [0])); FDCE \err_capt_err_type_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .CLR(crc_match_q_reg_1), .D(D[1]), .Q(\err_capt_err_type_q_reg[2]_0 [1])); FDCE \err_capt_err_type_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(err_capt_err_erp_reg_1), .CLR(crc_match_q_reg_1), .D(D[2]), .Q(\err_capt_err_type_q_reg[2]_0 [2])); FDCE err_frm_req_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(crc_match_q_reg_1), .D(err_capt_err_erp_reg_1), .Q(err_frm_req_reg_0)); (* SOFT_HLUTNM = "soft_lutpair208" *) LUT4 #( .INIT(16'h0004)) \g_byte_shift_reg[1].shift_reg_q[1][7]_i_3 (.I0(ack_err_flag_reg_2), .I1(ack_err_flag_reg_1), .I2(err_frm_req_reg_0), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .O(reg_q_reg_0)); (* SOFT_HLUTNM = "soft_lutpair209" *) LUT2 #( .INIT(4'h1)) mr_command_ercrst_q_i_4 (.I0(err_frm_req_reg_0), .I1(Q[0]), .O(err_frm_req_reg_3)); LUT5 #( .INIT(32'hA0A0CFC0)) \r_data[0]_i_10 (.I0(\err_capt_err_pos_q_reg[3]_0 [0]), .I1(\mr_tx_priority[0] ), .I2(adress_IBUF[1]), .I3(\r_data[0]_i_5 ), .I4(adress_IBUF[0]), .O(\err_capt_err_pos_q_reg[0]_0 )); LUT5 #( .INIT(32'hA0A0CFC0)) \r_data[4]_i_10 (.I0(\cc_stat[err_erp] ), .I1(\mr_tx_priority[1] [0]), .I2(adress_IBUF[1]), .I3(\r_data_reg[5]_i_5 [0]), .I4(adress_IBUF[0]), .O(err_capt_err_erp_reg_0)); LUT5 #( .INIT(32'hA0A0CFC0)) \r_data[5]_i_10 (.I0(\err_capt_err_type_q_reg[2]_0 [0]), .I1(\mr_tx_priority[1] [1]), .I2(adress_IBUF[1]), .I3(\r_data_reg[5]_i_5 [1]), .I4(adress_IBUF[0]), .O(\err_capt_err_type_q_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair208" *) LUT3 #( .INIT(8'h04)) rec_valid_i_6 (.I0(err_frm_req_reg_0), .I1(ack_err_flag_reg_1), .I2(ack_err_flag_reg_2), .O(err_frm_req_reg_2)); (* SOFT_HLUTNM = "soft_lutpair209" *) LUT2 #( .INIT(4'h1)) reg_q_i_2__8 (.I0(err_frm_req_reg_0), .I1(reg_q_reg_1), .O(err_frm_req_reg_7)); LUT2 #( .INIT(4'h1)) reg_q_i_3__0 (.I0(err_frm_req_reg_0), .I1(Q[1]), .O(err_frm_req_reg_4)); LUT6 #( .INIT(64'hD5D5FFD5D5D5D5D5)) \rx_err_ctr_q[8]_i_9 (.I0(ack_err_flag_reg), .I1(\cc_stat[is_err_passive] ), .I2(err_frm_req_reg_1), .I3(stuff_err), .I4(ack_err_flag_reg_0), .I5(\pc_dbg[is_arbitration] ), .O(reg_q_reg)); endmodule module mac_pc_fsm (store_metadata_reg_0, rec_valid_reg_0, rec_abort_reg_0, \txtb_hw_cmd_q_reg[lock]_0 , \txtb_hw_cmd_q_reg[valid]_0 , \txtb_hw_cmd_q_reg[failed]_0 , rx_data_nbs_prev_reg_0, rec_lbpf, D, \curr_state_reg[2]_0 , \timestamp[8] , err_frm_req_reg, \timestamp[14] , \timestamp[17] , \timestamp[7] , Q, \timestamp[41] , \timestamp[42] , \timestamp[43] , \curr_state_reg[1]_0 , rec_abort_reg_1, rec_valid_reg_1, \FSM_onehot_curr_state_reg[5] , \FSM_onehot_curr_state_reg[5]_0 , \g_bit[0].reg_value_r_reg[0] , ident_valid_q_reg, \txtb_hw_cmd_q_reg[failed]_1 , \txtb_hw_cmd_q_reg[err]_0 , \txtb_hw_cmd_q_reg[failed]_2 , \txtb_hw_cmd_q_reg[failed]_3 , \txtb_hw_cmd_q_reg[failed]_4 , \txtb_hw_cmd_q_reg[lock]_1 , \txtb_hw_cmd_q_reg[failed]_5 , \txtb_hw_cmd_q_reg[failed]_6 , \txtb_hw_cmd_q_reg[failed]_7 , \txtb_hw_cmd_q_reg[lock]_2 , \FSM_sequential_curr_state_reg[0] , \txtb_hw_cmd_q_reg[valid]_1 , \txtb_hw_cmd_q_reg[valid]_2 , rec_abort_f, \bst_ctr_q_reg[2] , \curr_state_reg[2]_1 , \curr_state_reg[0]_0 , err_frm_req_reg_0, reg_q_reg, \curr_state_reg[1]_1 , \curr_state_reg[2]_2 , reg_q_reg_0, \curr_state_reg[0]_1 , E, \curr_state_reg[5]_0 , err_frm_req_reg_1, retr_ctr_add, mr_ctr_pres_efd_q_reg, \g_bit[0].reg_value_r_reg[0]_0 , mr_ctr_pres_enorm_q_reg, \sp_control_q_i_reg[1]_0 , \curr_state_reg[1]_2 , reg_q_reg_1, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , \retr_ctr_q_reg[0] , reg_q_reg_2, \curr_state_reg[0]_2 , \curr_state_reg[5]_1 , \curr_state_reg[3]_0 , \curr_state_reg[2]_3 , \curr_state_reg[3]_1 , reinteg_ctr_ce, \curr_state_reg[4]_0 , err_frm_req_reg_2, \compl_ctr_q_reg[0] , reg_q_reg_3, reg_q_reg_4, reg_q_reg_5, \curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1] , reg_q_reg_6, reg_q_reg_7, stuff_enable_reg_0, tx_frame_no_sof_q_reg_0, \FSM_onehot_current_state_reg[2] , \sp_control_q_i_reg[0]_0 , reg_q_reg_8, stuff_err_d, destuff_enable, prev_val_d, bds_data_in, br_shifted, \curr_state_reg[0]_3 , \curr_state_reg[3]_2 , \curr_state_reg[4]_1 , \curr_state_reg[5]_2 , \curr_state_reg[5]_3 , \curr_state_reg[2]_4 , \curr_state_reg[0]_4 , err_frm_req_reg_3, \curr_state_reg[0]_5 , bit_err_enable, \pc_dbg[is_arbitration] , \txtb_hw_cmd_q_reg[valid]_3 , tx_frame_no_sof_q_reg_1, err_frm_req_reg_4, err_frm_req_reg_5, p_131_in, tran_delay_meas, \txtb_ptr_q_reg[2]_0 , \curr_state_reg[3]_3 , \txtb_ptr_q_reg[4]_0 , \curr_state_reg[3]_4 , \curr_state_reg[1]_4 , \curr_state_reg[5]_4 , reg_q_reg_9, reg_q_reg_10, reg_q_reg_11, \curr_state_reg[0]_6 , err_frm_req_reg_6, \curr_state_reg[5]_5 , \g_bit[0].reg_value_r_reg[0]_4 , \curr_state_reg[3]_5 , \curr_state_reg[1]_5 , \curr_state_reg[1]_6 , err_frm_req_reg_7, \curr_state_reg[5]_6 , \tq_counter_q_reg[7] , \sync_control_q_reg[0]_0 , \sync_control_q_reg[1]_0 , \sp_control_q_i_reg[0]_1 , first_ssp_q0, p_0_out, \txtb_hw_cmd_q_reg[lock]_3 , \curr_state_reg[5]_7 , \g_bit[1].reg_value_r_reg[1] , reg_q_reg_12, err_frm_req_reg_8, \curr_state_reg[0]_7 , \curr_state_reg[0]_8 , \curr_state_reg[3]_6 , \curr_state_reg[2]_5 , err_frm_req_reg_9, err_frm_req_reg_10, \curr_state_reg[3]_7 , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , reg_q_reg_13, \crc_q_reg[14] , \sync_control_q_reg[0]_1 , int_status_reg, sspc_ena_q_reg, btmc_meas_running_q_reg, \cc_stat[status_pexs] , rec_ivld, store_metadata_reg_1, clk_sys_IBUF_BUFG, \sp_control_q_i_reg[1]_1 , store_data_reg_0, rec_abort_reg_2, \txtb_hw_cmd_q[err] , rx_data_nbs_prev_reg_1, rec_lbpf_q_reg_0, sbe_IBUF, \r_data_reg[16] , adress_IBUF, \r_data_reg[16]_0 , \r_data_reg[16]_1 , \r_data_reg[15] , \r_data_reg[15]_0 , \r_data_reg[15]_1 , \r_data_reg[15]_2 , \r_data_reg[13] , \r_data_reg[13]_0 , \r_data_reg[13]_1 , \r_data_reg[13]_2 , \r_data_reg[13]_3 , \r_data_reg[13]_4 , \r_data_reg[18] , \r_data_reg[18]_0 , \r_data_reg[18]_1 , \r_data_reg[18]_2 , \r_data_reg[18]_3 , \r_data_reg[18]_4 , \r_data_reg[12] , \r_data_reg[12]_0 , timestamp_IBUF, \err_capt_err_pos_q_reg[0] , \r_data[7]_i_3__0_0 , \mr_ctrl_out[ssp_cfg_ssp_offset] , mr_command_ercrst_q_reg_0, \FSM_onehot_curr_state_reg[6] , ident_valid_q, \FSM_onehot_curr_state_reg[1] , \mr_ctrl_out[mode_erfm] , \mr_ctrl_out[rx_settings_rtsop] , curr_state_0, int_status_i_4_0, \FSM_sequential_curr_state_reg[2] , abort_or_skipped, \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , curr_state_1, abort_applied, \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state[1]_i_2__0 , txtb_hw_cmd_cs, curr_state_2, \FSM_sequential_curr_state_reg[2]_1 , abort_or_skipped_3, \FSM_sequential_curr_state_reg[1]_4 , curr_state_4, abort_applied_5, \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state[1]_i_2__2 , curr_state_6, \FSM_sequential_curr_state[0]_i_7 , \FSM_sequential_curr_state[2]_i_3__3 , \FSM_sequential_curr_state[2]_i_3__3_0 , \FSM_sequential_curr_state[0]_i_7_0 , \shift_regs_reg[24] , tran_word, \crc_q[14]_i_6_0 , \shift_regs_reg[25] , \shift_regs_reg[25]_0 , \shift_regs_reg[26] , \shift_regs_reg[26]_0 , \shift_regs_reg[27] , \shift_regs_reg[28] , \shift_regs_reg[28]_0 , \shift_regs_reg[29] , \shift_regs_reg[29]_0 , \shift_regs_reg[30] , \shift_regs_reg[30]_0 , \shift_regs_reg[31] , \shift_regs_reg[31]_0 , \shift_regs_reg[31]_1 , \shift_regs_reg[16] , \shift_regs_reg[16]_0 , \shift_regs_reg[16]_1 , \shift_regs_reg[17] , \shift_regs_reg[17]_0 , \shift_regs_reg[18] , \shift_regs_reg[18]_0 , \shift_regs_reg[19] , \shift_regs_reg[19]_0 , \shift_regs_reg[20] , \shift_regs_reg[20]_0 , \shift_regs_reg[21] , \shift_regs_reg[21]_0 , \shift_regs_reg[22] , \shift_regs_reg[22]_0 , \shift_regs_reg[23] , \shift_regs_reg[11] , \shift_regs_reg[11]_0 , \shift_regs_reg[12] , \shift_regs_reg[12]_0 , \shift_regs_reg[13] , \shift_regs_reg[14] , \shift_regs_reg[14]_0 , \shift_regs_reg[15] , \shift_regs_reg[15]_0 , \shift_regs_reg[1] , \shift_regs_reg[2] , \shift_regs_reg[0] , \shift_regs_reg[0]_0 , \rec_dlc_reg[0] , \cc_stat[is_bus_off] , \FSM_sequential_curr_state[1]_i_4__2_0 , \txtb_hw_cmd_q_reg[lock]_4 , \rx_stuff_count_reg[3] , tran_frame_valid, \curr_state_reg[4]_2 , \txtb_hw_cmd_q_reg[valid]_4 , tx_frame_no_sof_q_reg_2, tx_frame_no_sof_q_reg_3, rec_ivld_q_reg_0, \mr_ctrl_out[mode_rom] , \curr_state_reg[0]_9 , \curr_state[0]_i_3_0 , \txtb_hw_cmd_q_reg[lock]_5 , destuff_enable_reg_0, destuff_enable_reg_1, \shift_regs_reg[27]_0 , \shift_regs_reg[30]_1 , \shift_regs_reg[31]_2 , \crc_q_reg[0] , \ctrl_ctr_q_reg[0] , \FSM_sequential_curr_state[1]_i_2__4_0 , \curr_state[5]_i_5_0 , \retr_ctr_q_reg[3] , mr_ctr_pres_efd_q, mr_ctr_pres_enorm_q, \nom_err_ctr_q_reg[0] , \cc_stat[is_receiver] , stuff_err, err_capt_err_erp_reg, \retr_ctr_q_reg[0]_0 , \mr_ctrl_out[settings_rtrle] , \sp_control_q_i_reg[1]_2 , tx_frame_no_sof_q_reg_4, tx_frame_no_sof_q_reg_5, rec_valid_reg_2, rec_valid_reg_3, bit_err, can_tx_OBUF, \err_capt_err_type_q_reg[1] , \shift_regs_reg[28]_1 , \shift_regs_reg[28]_2 , \shift_regs_reg[28]_3 , \tran_frame_test[fcrc] , \shift_regs_reg[29]_1 , \shift_regs_reg[29]_2 , \shift_regs_reg[30]_2 , \ctrl_ctr_q_reg[1] , \compl_ctr_q_reg[0]_0 , \ctrl_ctr_q_reg[3] , \ctrl_ctr_q_reg[4] , data_halt_d1_out, tx_trigger_q, crc_data_rx_wbs, \crc_q_reg[20] , enable_prev, btmc_meas_running_q_reg_0, is_tseg2, \same_bits_q_reg[2] , is_tseg1, reg_q_reg_14, fixed_prev_q, reg_q_reg_15, reg_q, sync_edge, \mr_ctrl_out[mode_fde] , \mr_ctrl_out[settings_pex] , \ctrl_ctr_q[3]_i_3_0 , \ctrl_ctr_q_reg[1]_0 , \ctrl_ctr_q_reg[1]_1 , \ctrl_ctr_q[1]_i_3_0 , \ctrl_ctr_q[1]_i_3_1 , \mr_ctrl_out[ssp_cfg_ssp_src] , \curr_state[5]_i_10_0 , \FSM_sequential_curr_state[1]_i_8_0 , \txtb_hw_cmd_q_reg[arbl]_0 , \alc_alc_bit_reg[0] , tran_ident_type, \err_capt_err_type_q[2]_i_8_0 , \shift_regs[27]_i_2 , \ctrl_ctr_q_reg[2] , \ctrl_ctr_q[2]_i_3_0 , \ctrl_ctr_q_reg[0]_0 , \shift_regs[31]_i_7_0 , \ctrl_ctr_q[0]_i_4_0 , \mr_ctrl_out[settings_ena] , \curr_state_reg[1]_7 , \ctrl_ctr_q_reg[4]_0 , \mr_ctrl_out[settings_nisofd] , \curr_state[0]_i_3_1 , destuff_enable_reg_2, \ctrl_ctr_q[2]_i_3_1 , \ctrl_ctr_q[2]_i_3_2 , \ctrl_ctr_q[2]_i_4_0 , \ctrl_ctr_q[3]_i_4_0 , \ctrl_ctr_q[1]_i_4_0 , \curr_state_reg[4]_3 , \crc_q[14]_i_6_1 , tran_brs, bit_err_q_i_2_0, crc_match, \crc_q[14]_i_11_0 , \mr_ctrl_out[mode_bmm] , reg_q_reg_16, tran_is_rtr, \txtb_ptr_q_reg[4]_1 , \txtb_ptr_q_reg[4]_2 , \txtb_ptr_q_reg[2]_1 , \curr_state_reg[4]_4 , \ctrl_ctr_q[8]_i_11_0 , \ctrl_ctr_q[8]_i_11_1 , destuff_enable_reg_3, \g_byte_shift_reg[1].shift_reg_q_reg[1][0] , store_data_word, \timestamp_capture_reg[63] , \curr_state[5]_i_4_0 , \mr_ctrl_out[mode_stm] , \curr_state[1]_i_4_0 , \ctrl_ctr_q[2]_i_6_0 , reg_q_reg_17, rx_data_wbs, \segm_counter_q_reg[0] , \segm_counter_q_reg[0]_0 , \segm_counter_q_reg[0]_1 , \exp_seg_length_q_reg[0] , \exp_seg_length_q_reg[0]_0 , sync_edge3__0, \segm_counter_q_reg[0]_2 , rx_data_sync_prev_reg, tx_data_prev, \curr_state_reg[0]_10 , \ctrl_ctr_q_reg[3]_0 , \crc_q_reg[0]_0 , \ctrl_ctr_q_reg[4]_1 , \ctrl_ctr_q[3]_i_3_1 , reg_q_reg_18, \FSM_sequential_curr_state_reg[0]_0 , ack_err_flag_reg_0, \crc_q_reg[14]_0 , sync_flag, int_status_reg_0, data_in_IBUF, int_status_reg_1, mr_int_stat_txbhci_o, sspc_ena_q, btmc_meas_running_q, mr_status_pexs_reg_0, mr_status_pexs_reg_1, \txtb_ptr_q_reg[4]_3 , \txtb_ptr_q_reg[4]_4 , txtb_allow_bb, int_status_i_2__1_0, int_status_i_2__1_1, int_status_reg_2); output store_metadata_reg_0; output rec_valid_reg_0; output rec_abort_reg_0; output \txtb_hw_cmd_q_reg[lock]_0 ; output \txtb_hw_cmd_q_reg[valid]_0 ; output \txtb_hw_cmd_q_reg[failed]_0 ; output rx_data_nbs_prev_reg_0; output rec_lbpf; output [3:0]D; output \curr_state_reg[2]_0 ; output \timestamp[8] ; output err_frm_req_reg; output \timestamp[14] ; output \timestamp[17] ; output \timestamp[7] ; output [5:0]Q; output \timestamp[41] ; output \timestamp[42] ; output \timestamp[43] ; output \curr_state_reg[1]_0 ; output rec_abort_reg_1; output [2:0]rec_valid_reg_1; output \FSM_onehot_curr_state_reg[5] ; output \FSM_onehot_curr_state_reg[5]_0 ; output \g_bit[0].reg_value_r_reg[0] ; output [0:0]ident_valid_q_reg; output \txtb_hw_cmd_q_reg[failed]_1 ; output \txtb_hw_cmd_q_reg[err]_0 ; output \txtb_hw_cmd_q_reg[failed]_2 ; output \txtb_hw_cmd_q_reg[failed]_3 ; output \txtb_hw_cmd_q_reg[failed]_4 ; output \txtb_hw_cmd_q_reg[lock]_1 ; output \txtb_hw_cmd_q_reg[failed]_5 ; output \txtb_hw_cmd_q_reg[failed]_6 ; output \txtb_hw_cmd_q_reg[failed]_7 ; output \txtb_hw_cmd_q_reg[lock]_2 ; output \FSM_sequential_curr_state_reg[0] ; output \txtb_hw_cmd_q_reg[valid]_1 ; output \txtb_hw_cmd_q_reg[valid]_2 ; output rec_abort_f; output [30:0]\bst_ctr_q_reg[2] ; output \curr_state_reg[2]_1 ; output \curr_state_reg[0]_0 ; output err_frm_req_reg_0; output reg_q_reg; output \curr_state_reg[1]_1 ; output \curr_state_reg[2]_2 ; output reg_q_reg_0; output \curr_state_reg[0]_1 ; output [0:0]E; output \curr_state_reg[5]_0 ; output [0:0]err_frm_req_reg_1; output retr_ctr_add; output [0:0]mr_ctr_pres_efd_q_reg; output \g_bit[0].reg_value_r_reg[0]_0 ; output [0:0]mr_ctr_pres_enorm_q_reg; output \sp_control_q_i_reg[1]_0 ; output \curr_state_reg[1]_2 ; output reg_q_reg_1; output \g_bit[0].reg_value_r_reg[0]_1 ; output [0:0]\g_bit[0].reg_value_r_reg[0]_2 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output [0:0]\retr_ctr_q_reg[0] ; output reg_q_reg_2; output \curr_state_reg[0]_2 ; output [0:0]\curr_state_reg[5]_1 ; output \curr_state_reg[3]_0 ; output \curr_state_reg[2]_3 ; output \curr_state_reg[3]_1 ; output reinteg_ctr_ce; output \curr_state_reg[4]_0 ; output [3:0]err_frm_req_reg_2; output [0:0]\compl_ctr_q_reg[0] ; output [0:0]reg_q_reg_3; output [0:0]reg_q_reg_4; output reg_q_reg_5; output \curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1] ; output [0:0]reg_q_reg_6; output reg_q_reg_7; output stuff_enable_reg_0; output tx_frame_no_sof_q_reg_0; output \FSM_onehot_current_state_reg[2] ; output \sp_control_q_i_reg[0]_0 ; output reg_q_reg_8; output stuff_err_d; output destuff_enable; output prev_val_d; output bds_data_in; output br_shifted; output [0:0]\curr_state_reg[0]_3 ; output \curr_state_reg[3]_2 ; output \curr_state_reg[4]_1 ; output [1:0]\curr_state_reg[5]_2 ; output \curr_state_reg[5]_3 ; output \curr_state_reg[2]_4 ; output [0:0]\curr_state_reg[0]_4 ; output err_frm_req_reg_3; output [3:0]\curr_state_reg[0]_5 ; output bit_err_enable; output \pc_dbg[is_arbitration] ; output \txtb_hw_cmd_q_reg[valid]_3 ; output tx_frame_no_sof_q_reg_1; output err_frm_req_reg_4; output err_frm_req_reg_5; output p_131_in; output tran_delay_meas; output \txtb_ptr_q_reg[2]_0 ; output [0:0]\curr_state_reg[3]_3 ; output [4:0]\txtb_ptr_q_reg[4]_0 ; output \curr_state_reg[3]_4 ; output \curr_state_reg[1]_4 ; output [0:0]\curr_state_reg[5]_4 ; output [0:0]reg_q_reg_9; output [0:0]reg_q_reg_10; output [0:0]reg_q_reg_11; output \curr_state_reg[0]_6 ; output [0:0]err_frm_req_reg_6; output \curr_state_reg[5]_5 ; output \g_bit[0].reg_value_r_reg[0]_4 ; output \curr_state_reg[3]_5 ; output \curr_state_reg[1]_5 ; output [2:0]\curr_state_reg[1]_6 ; output [0:0]err_frm_req_reg_7; output [0:0]\curr_state_reg[5]_6 ; output \tq_counter_q_reg[7] ; output \sync_control_q_reg[0]_0 ; output [1:0]\sync_control_q_reg[1]_0 ; output \sp_control_q_i_reg[0]_1 ; output first_ssp_q0; output p_0_out; output \txtb_hw_cmd_q_reg[lock]_3 ; output \curr_state_reg[5]_7 ; output \g_bit[1].reg_value_r_reg[1] ; output [0:0]reg_q_reg_12; output err_frm_req_reg_8; output \curr_state_reg[0]_7 ; output \curr_state_reg[0]_8 ; output \curr_state_reg[3]_6 ; output \curr_state_reg[2]_5 ; output err_frm_req_reg_9; output err_frm_req_reg_10; output \curr_state_reg[3]_7 ; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output [2:0]reg_q_reg_13; output [6:0]\crc_q_reg[14] ; output \sync_control_q_reg[0]_1 ; output int_status_reg; output sspc_ena_q_reg; output btmc_meas_running_q_reg; output \cc_stat[status_pexs] ; output rec_ivld; input store_metadata_reg_1; input clk_sys_IBUF_BUFG; input \sp_control_q_i_reg[1]_1 ; input store_data_reg_0; input rec_abort_reg_2; input \txtb_hw_cmd_q[err] ; input rx_data_nbs_prev_reg_1; input rec_lbpf_q_reg_0; input [1:0]sbe_IBUF; input \r_data_reg[16] ; input [3:0]adress_IBUF; input \r_data_reg[16]_0 ; input \r_data_reg[16]_1 ; input \r_data_reg[15] ; input \r_data_reg[15]_0 ; input \r_data_reg[15]_1 ; input \r_data_reg[15]_2 ; input \r_data_reg[13] ; input \r_data_reg[13]_0 ; input [0:0]\r_data_reg[13]_1 ; input \r_data_reg[13]_2 ; input \r_data_reg[13]_3 ; input \r_data_reg[13]_4 ; input \r_data_reg[18] ; input \r_data_reg[18]_0 ; input \r_data_reg[18]_1 ; input \r_data_reg[18]_2 ; input \r_data_reg[18]_3 ; input \r_data_reg[18]_4 ; input \r_data_reg[12] ; input \r_data_reg[12]_0 ; input [19:0]timestamp_IBUF; input \err_capt_err_pos_q_reg[0] ; input [0:0]\r_data[7]_i_3__0_0 ; input [2:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; input mr_command_ercrst_q_reg_0; input [4:0]\FSM_onehot_curr_state_reg[6] ; input ident_valid_q; input \FSM_onehot_curr_state_reg[1] ; input \mr_ctrl_out[mode_erfm] ; input \mr_ctrl_out[rx_settings_rtsop] ; input [0:0]curr_state_0; input [1:0]int_status_i_4_0; input \FSM_sequential_curr_state_reg[2] ; input abort_or_skipped; input \FSM_sequential_curr_state_reg[1]_2 ; input \FSM_sequential_curr_state_reg[1]_3 ; input [0:0]curr_state_1; input abort_applied; input \FSM_sequential_curr_state_reg[2]_0 ; input \FSM_sequential_curr_state[1]_i_2__0 ; input [1:0]txtb_hw_cmd_cs; input [0:0]curr_state_2; input \FSM_sequential_curr_state_reg[2]_1 ; input abort_or_skipped_3; input \FSM_sequential_curr_state_reg[1]_4 ; input [0:0]curr_state_4; input abort_applied_5; input \FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state[1]_i_2__2 ; input [0:0]curr_state_6; input \FSM_sequential_curr_state[0]_i_7 ; input \FSM_sequential_curr_state[2]_i_3__3 ; input \FSM_sequential_curr_state[2]_i_3__3_0 ; input \FSM_sequential_curr_state[0]_i_7_0 ; input \shift_regs_reg[24] ; input [20:0]tran_word; input [31:0]\crc_q[14]_i_6_0 ; input \shift_regs_reg[25] ; input \shift_regs_reg[25]_0 ; input \shift_regs_reg[26] ; input \shift_regs_reg[26]_0 ; input \shift_regs_reg[27] ; input \shift_regs_reg[28] ; input \shift_regs_reg[28]_0 ; input \shift_regs_reg[29] ; input \shift_regs_reg[29]_0 ; input \shift_regs_reg[30] ; input \shift_regs_reg[30]_0 ; input \shift_regs_reg[31] ; input \shift_regs_reg[31]_0 ; input \shift_regs_reg[31]_1 ; input \shift_regs_reg[16] ; input \shift_regs_reg[16]_0 ; input \shift_regs_reg[16]_1 ; input \shift_regs_reg[17] ; input \shift_regs_reg[17]_0 ; input \shift_regs_reg[18] ; input \shift_regs_reg[18]_0 ; input \shift_regs_reg[19] ; input \shift_regs_reg[19]_0 ; input \shift_regs_reg[20] ; input \shift_regs_reg[20]_0 ; input \shift_regs_reg[21] ; input \shift_regs_reg[21]_0 ; input \shift_regs_reg[22] ; input \shift_regs_reg[22]_0 ; input \shift_regs_reg[23] ; input \shift_regs_reg[11] ; input \shift_regs_reg[11]_0 ; input \shift_regs_reg[12] ; input \shift_regs_reg[12]_0 ; input \shift_regs_reg[13] ; input \shift_regs_reg[14] ; input \shift_regs_reg[14]_0 ; input \shift_regs_reg[15] ; input \shift_regs_reg[15]_0 ; input \shift_regs_reg[1] ; input \shift_regs_reg[2] ; input \shift_regs_reg[0] ; input \shift_regs_reg[0]_0 ; input \rec_dlc_reg[0] ; input \cc_stat[is_bus_off] ; input \FSM_sequential_curr_state[1]_i_4__2_0 ; input \txtb_hw_cmd_q_reg[lock]_4 ; input \rx_stuff_count_reg[3] ; input tran_frame_valid; input \curr_state_reg[4]_2 ; input [0:0]\txtb_hw_cmd_q_reg[valid]_4 ; input tx_frame_no_sof_q_reg_2; input tx_frame_no_sof_q_reg_3; input rec_ivld_q_reg_0; input \mr_ctrl_out[mode_rom] ; input \curr_state_reg[0]_9 ; input \curr_state[0]_i_3_0 ; input \txtb_hw_cmd_q_reg[lock]_5 ; input destuff_enable_reg_0; input destuff_enable_reg_1; input [13:0]\shift_regs_reg[27]_0 ; input \shift_regs_reg[30]_1 ; input \shift_regs_reg[31]_2 ; input \crc_q_reg[0] ; input \ctrl_ctr_q_reg[0] ; input \FSM_sequential_curr_state[1]_i_2__4_0 ; input \curr_state[5]_i_5_0 ; input \retr_ctr_q_reg[3] ; input mr_ctr_pres_efd_q; input mr_ctr_pres_enorm_q; input \nom_err_ctr_q_reg[0] ; input \cc_stat[is_receiver] ; input stuff_err; input err_capt_err_erp_reg; input [0:0]\retr_ctr_q_reg[0]_0 ; input \mr_ctrl_out[settings_rtrle] ; input \sp_control_q_i_reg[1]_2 ; input tx_frame_no_sof_q_reg_4; input tx_frame_no_sof_q_reg_5; input rec_valid_reg_2; input rec_valid_reg_3; input bit_err; input can_tx_OBUF; input \err_capt_err_type_q_reg[1] ; input \shift_regs_reg[28]_1 ; input \shift_regs_reg[28]_2 ; input \shift_regs_reg[28]_3 ; input \tran_frame_test[fcrc] ; input \shift_regs_reg[29]_1 ; input \shift_regs_reg[29]_2 ; input \shift_regs_reg[30]_2 ; input [1:0]\ctrl_ctr_q_reg[1] ; input [0:0]\compl_ctr_q_reg[0]_0 ; input \ctrl_ctr_q_reg[3] ; input \ctrl_ctr_q_reg[4] ; input data_halt_d1_out; input tx_trigger_q; input crc_data_rx_wbs; input \crc_q_reg[20] ; input enable_prev; input btmc_meas_running_q_reg_0; input is_tseg2; input \same_bits_q_reg[2] ; input is_tseg1; input reg_q_reg_14; input fixed_prev_q; input reg_q_reg_15; input reg_q; input sync_edge; input \mr_ctrl_out[mode_fde] ; input \mr_ctrl_out[settings_pex] ; input \ctrl_ctr_q[3]_i_3_0 ; input \ctrl_ctr_q_reg[1]_0 ; input \ctrl_ctr_q_reg[1]_1 ; input \ctrl_ctr_q[1]_i_3_0 ; input \ctrl_ctr_q[1]_i_3_1 ; input [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; input \curr_state[5]_i_10_0 ; input \FSM_sequential_curr_state[1]_i_8_0 ; input \txtb_hw_cmd_q_reg[arbl]_0 ; input \alc_alc_bit_reg[0] ; input tran_ident_type; input \err_capt_err_type_q[2]_i_8_0 ; input \shift_regs[27]_i_2 ; input \ctrl_ctr_q_reg[2] ; input \ctrl_ctr_q[2]_i_3_0 ; input \ctrl_ctr_q_reg[0]_0 ; input \shift_regs[31]_i_7_0 ; input \ctrl_ctr_q[0]_i_4_0 ; input \mr_ctrl_out[settings_ena] ; input [1:0]\curr_state_reg[1]_7 ; input \ctrl_ctr_q_reg[4]_0 ; input \mr_ctrl_out[settings_nisofd] ; input \curr_state[0]_i_3_1 ; input destuff_enable_reg_2; input \ctrl_ctr_q[2]_i_3_1 ; input \ctrl_ctr_q[2]_i_3_2 ; input \ctrl_ctr_q[2]_i_4_0 ; input \ctrl_ctr_q[3]_i_4_0 ; input \ctrl_ctr_q[1]_i_4_0 ; input \curr_state_reg[4]_3 ; input \crc_q[14]_i_6_1 ; input tran_brs; input bit_err_q_i_2_0; input crc_match; input \crc_q[14]_i_11_0 ; input \mr_ctrl_out[mode_bmm] ; input reg_q_reg_16; input tran_is_rtr; input \txtb_ptr_q_reg[4]_1 ; input \txtb_ptr_q_reg[4]_2 ; input \txtb_ptr_q_reg[2]_1 ; input \curr_state_reg[4]_4 ; input \ctrl_ctr_q[8]_i_11_0 ; input \ctrl_ctr_q[8]_i_11_1 ; input destuff_enable_reg_3; input [1:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][0] ; input [0:0]store_data_word; input \timestamp_capture_reg[63] ; input \curr_state[5]_i_4_0 ; input \mr_ctrl_out[mode_stm] ; input \curr_state[1]_i_4_0 ; input \ctrl_ctr_q[2]_i_6_0 ; input reg_q_reg_17; input rx_data_wbs; input \segm_counter_q_reg[0] ; input \segm_counter_q_reg[0]_0 ; input \segm_counter_q_reg[0]_1 ; input \exp_seg_length_q_reg[0] ; input \exp_seg_length_q_reg[0]_0 ; input sync_edge3__0; input \segm_counter_q_reg[0]_2 ; input rx_data_sync_prev_reg; input tx_data_prev; input \curr_state_reg[0]_10 ; input \ctrl_ctr_q_reg[3]_0 ; input \crc_q_reg[0]_0 ; input \ctrl_ctr_q_reg[4]_1 ; input \ctrl_ctr_q[3]_i_3_1 ; input reg_q_reg_18; input \FSM_sequential_curr_state_reg[0]_0 ; input ack_err_flag_reg_0; input [6:0]\crc_q_reg[14]_0 ; input sync_flag; input int_status_reg_0; input [2:0]data_in_IBUF; input int_status_reg_1; input mr_int_stat_txbhci_o; input sspc_ena_q; input btmc_meas_running_q; input mr_status_pexs_reg_0; input mr_status_pexs_reg_1; input [0:0]\txtb_ptr_q_reg[4]_3 ; input [3:0]\txtb_ptr_q_reg[4]_4 ; input [3:0]txtb_allow_bb; input int_status_i_2__1_0; input int_status_i_2__1_1; input [0:0]int_status_reg_2; wire [3:0]D; wire [0:0]E; wire \FSM_onehot_curr_state[1]_i_2_n_0 ; wire \FSM_onehot_curr_state_reg[1] ; wire \FSM_onehot_curr_state_reg[5] ; wire \FSM_onehot_curr_state_reg[5]_0 ; wire [4:0]\FSM_onehot_curr_state_reg[6] ; wire \FSM_onehot_current_state_reg[2] ; wire \FSM_sequential_curr_state[0]_i_3__1_n_0 ; wire \FSM_sequential_curr_state[0]_i_4__4_n_0 ; wire \FSM_sequential_curr_state[0]_i_7 ; wire \FSM_sequential_curr_state[0]_i_7_0 ; wire \FSM_sequential_curr_state[1]_i_10_n_0 ; wire \FSM_sequential_curr_state[1]_i_11_n_0 ; wire \FSM_sequential_curr_state[1]_i_12_n_0 ; wire \FSM_sequential_curr_state[1]_i_13_n_0 ; wire \FSM_sequential_curr_state[1]_i_14_n_0 ; wire \FSM_sequential_curr_state[1]_i_15_n_0 ; wire \FSM_sequential_curr_state[1]_i_16_n_0 ; wire \FSM_sequential_curr_state[1]_i_17_n_0 ; wire \FSM_sequential_curr_state[1]_i_19_n_0 ; wire \FSM_sequential_curr_state[1]_i_2__0 ; wire \FSM_sequential_curr_state[1]_i_2__2 ; wire \FSM_sequential_curr_state[1]_i_2__4_0 ; wire \FSM_sequential_curr_state[1]_i_2__4_n_0 ; wire \FSM_sequential_curr_state[1]_i_3__1_n_0 ; wire \FSM_sequential_curr_state[1]_i_4__2_0 ; wire \FSM_sequential_curr_state[1]_i_4__2_n_0 ; wire \FSM_sequential_curr_state[1]_i_4__3_n_0 ; wire \FSM_sequential_curr_state[1]_i_5_n_0 ; wire \FSM_sequential_curr_state[1]_i_6_n_0 ; wire \FSM_sequential_curr_state[1]_i_7_n_0 ; wire \FSM_sequential_curr_state[1]_i_8_0 ; wire \FSM_sequential_curr_state[1]_i_8_n_0 ; wire \FSM_sequential_curr_state[1]_i_9_n_0 ; wire \FSM_sequential_curr_state[2]_i_3__3 ; wire \FSM_sequential_curr_state[2]_i_3__3_0 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire [5:0]Q; wire abort_applied; wire abort_applied_5; wire abort_or_skipped; wire abort_or_skipped_3; wire ack_err_flag; wire ack_err_flag_i_1_n_0; wire ack_err_flag_i_3_n_0; wire ack_err_flag_i_4_n_0; wire ack_err_flag_i_5_n_0; wire ack_err_flag_i_7_n_0; wire ack_err_flag_reg_0; wire [3:0]adress_IBUF; wire \alc_alc_bit_reg[0] ; wire bds_data_in; wire bit_err; wire bit_err_enable; wire bit_err_q_i_2_0; wire bit_err_q_i_5_n_0; wire bit_err_q_i_6_n_0; wire bit_err_q_i_7_n_0; wire bit_err_q_i_8_n_0; wire bit_err_q_i_9_n_0; wire br_shifted; wire [30:0]\bst_ctr_q_reg[2] ; wire btmc_meas_running_q; wire btmc_meas_running_q_reg; wire btmc_meas_running_q_reg_0; wire can_tx_OBUF; wire \cc_stat[is_bus_off] ; wire \cc_stat[is_receiver] ; wire \cc_stat[status_pexs] ; wire clk_sys_IBUF_BUFG; wire [0:0]\compl_ctr_q_reg[0] ; wire [0:0]\compl_ctr_q_reg[0]_0 ; wire crc_data_rx_wbs; wire crc_match; wire \crc_q[14]_i_10_n_0 ; wire \crc_q[14]_i_11_0 ; wire \crc_q[14]_i_11_n_0 ; wire \crc_q[14]_i_12_n_0 ; wire \crc_q[14]_i_13_n_0 ; wire \crc_q[14]_i_14_n_0 ; wire \crc_q[14]_i_15_n_0 ; wire \crc_q[14]_i_17_n_0 ; wire \crc_q[14]_i_18_n_0 ; wire \crc_q[14]_i_19_n_0 ; wire \crc_q[14]_i_21_n_0 ; wire \crc_q[14]_i_22_n_0 ; wire \crc_q[14]_i_3_n_0 ; wire [31:0]\crc_q[14]_i_6_0 ; wire \crc_q[14]_i_6_1 ; wire \crc_q[14]_i_8_n_0 ; wire \crc_q[14]_i_9_n_0 ; wire \crc_q[16]_i_3_n_0 ; wire \crc_q_reg[0] ; wire \crc_q_reg[0]_0 ; wire [6:0]\crc_q_reg[14] ; wire [6:0]\crc_q_reg[14]_0 ; wire \crc_q_reg[20] ; wire \ctrl_ctr_q[0]_i_10_n_0 ; wire \ctrl_ctr_q[0]_i_11_n_0 ; wire \ctrl_ctr_q[0]_i_2_n_0 ; wire \ctrl_ctr_q[0]_i_3_n_0 ; wire \ctrl_ctr_q[0]_i_4_0 ; wire \ctrl_ctr_q[0]_i_4_n_0 ; wire \ctrl_ctr_q[0]_i_5_n_0 ; wire \ctrl_ctr_q[0]_i_6_n_0 ; wire \ctrl_ctr_q[0]_i_7_n_0 ; wire \ctrl_ctr_q[0]_i_9_n_0 ; wire \ctrl_ctr_q[1]_i_10_n_0 ; wire \ctrl_ctr_q[1]_i_12_n_0 ; wire \ctrl_ctr_q[1]_i_13_n_0 ; wire \ctrl_ctr_q[1]_i_14_n_0 ; wire \ctrl_ctr_q[1]_i_15_n_0 ; wire \ctrl_ctr_q[1]_i_17_n_0 ; wire \ctrl_ctr_q[1]_i_18_n_0 ; wire \ctrl_ctr_q[1]_i_2_n_0 ; wire \ctrl_ctr_q[1]_i_3_0 ; wire \ctrl_ctr_q[1]_i_3_1 ; wire \ctrl_ctr_q[1]_i_3_n_0 ; wire \ctrl_ctr_q[1]_i_4_0 ; wire \ctrl_ctr_q[1]_i_4_n_0 ; wire \ctrl_ctr_q[1]_i_5_n_0 ; wire \ctrl_ctr_q[1]_i_6_n_0 ; wire \ctrl_ctr_q[1]_i_7_n_0 ; wire \ctrl_ctr_q[1]_i_8_n_0 ; wire \ctrl_ctr_q[1]_i_9_n_0 ; wire \ctrl_ctr_q[2]_i_11_n_0 ; wire \ctrl_ctr_q[2]_i_12_n_0 ; wire \ctrl_ctr_q[2]_i_13_n_0 ; wire \ctrl_ctr_q[2]_i_3_0 ; wire \ctrl_ctr_q[2]_i_3_1 ; wire \ctrl_ctr_q[2]_i_3_2 ; wire \ctrl_ctr_q[2]_i_4_0 ; wire \ctrl_ctr_q[2]_i_4_n_0 ; wire \ctrl_ctr_q[2]_i_6_0 ; wire \ctrl_ctr_q[2]_i_6_n_0 ; wire \ctrl_ctr_q[2]_i_7_n_0 ; wire \ctrl_ctr_q[3]_i_10_n_0 ; wire \ctrl_ctr_q[3]_i_12_n_0 ; wire \ctrl_ctr_q[3]_i_13_n_0 ; wire \ctrl_ctr_q[3]_i_15_n_0 ; wire \ctrl_ctr_q[3]_i_16_n_0 ; wire \ctrl_ctr_q[3]_i_17_n_0 ; wire \ctrl_ctr_q[3]_i_18_n_0 ; wire \ctrl_ctr_q[3]_i_21_n_0 ; wire \ctrl_ctr_q[3]_i_3_0 ; wire \ctrl_ctr_q[3]_i_3_1 ; wire \ctrl_ctr_q[3]_i_3_n_0 ; wire \ctrl_ctr_q[3]_i_4_0 ; wire \ctrl_ctr_q[3]_i_4_n_0 ; wire \ctrl_ctr_q[3]_i_5_n_0 ; wire \ctrl_ctr_q[3]_i_6_n_0 ; wire \ctrl_ctr_q[3]_i_7_n_0 ; wire \ctrl_ctr_q[3]_i_8_n_0 ; wire \ctrl_ctr_q[3]_i_9_n_0 ; wire \ctrl_ctr_q[4]_i_3_n_0 ; wire \ctrl_ctr_q[4]_i_4_n_0 ; wire \ctrl_ctr_q[8]_i_11_0 ; wire \ctrl_ctr_q[8]_i_11_1 ; wire \ctrl_ctr_q[8]_i_11_n_0 ; wire \ctrl_ctr_q[8]_i_12_n_0 ; wire \ctrl_ctr_q[8]_i_13_n_0 ; wire \ctrl_ctr_q[8]_i_14_n_0 ; wire \ctrl_ctr_q[8]_i_19_n_0 ; wire \ctrl_ctr_q[8]_i_20_n_0 ; wire \ctrl_ctr_q[8]_i_21_n_0 ; wire \ctrl_ctr_q[8]_i_22_n_0 ; wire \ctrl_ctr_q[8]_i_23_n_0 ; wire \ctrl_ctr_q[8]_i_24_n_0 ; wire \ctrl_ctr_q[8]_i_28_n_0 ; wire \ctrl_ctr_q[8]_i_29_n_0 ; wire \ctrl_ctr_q[8]_i_30_n_0 ; wire \ctrl_ctr_q[8]_i_31_n_0 ; wire \ctrl_ctr_q[8]_i_33_n_0 ; wire \ctrl_ctr_q[8]_i_5_n_0 ; wire \ctrl_ctr_q_reg[0] ; wire \ctrl_ctr_q_reg[0]_0 ; wire [1:0]\ctrl_ctr_q_reg[1] ; wire \ctrl_ctr_q_reg[1]_0 ; wire \ctrl_ctr_q_reg[1]_1 ; wire \ctrl_ctr_q_reg[2] ; wire \ctrl_ctr_q_reg[3] ; wire \ctrl_ctr_q_reg[3]_0 ; wire \ctrl_ctr_q_reg[4] ; wire \ctrl_ctr_q_reg[4]_0 ; wire \ctrl_ctr_q_reg[4]_1 ; wire [0:0]curr_state; wire \curr_state[0]_i_11_n_0 ; wire \curr_state[0]_i_1_n_0 ; wire \curr_state[0]_i_3_0 ; wire \curr_state[0]_i_3_1 ; wire \curr_state[0]_i_3_n_0 ; wire \curr_state[0]_i_4_n_0 ; wire \curr_state[0]_i_5_n_0 ; wire \curr_state[0]_i_6_n_0 ; wire \curr_state[0]_i_7_n_0 ; wire \curr_state[0]_i_8_n_0 ; wire \curr_state[0]_i_9_n_0 ; wire \curr_state[1]_i_1_n_0 ; wire \curr_state[1]_i_2_n_0 ; wire \curr_state[1]_i_3_n_0 ; wire \curr_state[1]_i_4_0 ; wire \curr_state[1]_i_4_n_0 ; wire \curr_state[1]_i_5_n_0 ; wire \curr_state[1]_i_6_n_0 ; wire \curr_state[1]_i_7_n_0 ; wire \curr_state[2]_i_1_n_0 ; wire \curr_state[2]_i_2_n_0 ; wire \curr_state[2]_i_4_n_0 ; wire \curr_state[2]_i_5_n_0 ; wire \curr_state[2]_i_6_n_0 ; wire \curr_state[2]_i_7_n_0 ; wire \curr_state[3]_i_1_n_0 ; wire \curr_state[3]_i_3_n_0 ; wire \curr_state[3]_i_4_n_0 ; wire \curr_state[3]_i_5_n_0 ; wire \curr_state[3]_i_6_n_0 ; wire \curr_state[3]_i_7_n_0 ; wire \curr_state[4]_i_11_n_0 ; wire \curr_state[4]_i_1_n_0 ; wire \curr_state[4]_i_2_n_0 ; wire \curr_state[4]_i_3_n_0 ; wire \curr_state[4]_i_4_n_0 ; wire \curr_state[4]_i_5_n_0 ; wire \curr_state[4]_i_7_n_0 ; wire \curr_state[4]_i_8_n_0 ; wire \curr_state[5]_i_10_0 ; wire \curr_state[5]_i_10_n_0 ; wire \curr_state[5]_i_11_n_0 ; wire \curr_state[5]_i_12_n_0 ; wire \curr_state[5]_i_13_n_0 ; wire \curr_state[5]_i_14_n_0 ; wire \curr_state[5]_i_15_n_0 ; wire \curr_state[5]_i_16_n_0 ; wire \curr_state[5]_i_18_n_0 ; wire \curr_state[5]_i_20_n_0 ; wire \curr_state[5]_i_21_n_0 ; wire \curr_state[5]_i_26_n_0 ; wire \curr_state[5]_i_27_n_0 ; wire \curr_state[5]_i_2_n_0 ; wire \curr_state[5]_i_3_n_0 ; wire \curr_state[5]_i_4_0 ; wire \curr_state[5]_i_4_n_0 ; wire \curr_state[5]_i_5_0 ; wire \curr_state[5]_i_5_n_0 ; wire \curr_state[5]_i_6_n_0 ; wire \curr_state[5]_i_7_n_0 ; wire \curr_state[5]_i_9_n_0 ; wire [0:0]curr_state_0; wire [0:0]curr_state_1; wire [0:0]curr_state_2; wire [0:0]curr_state_4; wire [0:0]curr_state_6; wire \curr_state_reg[0]_0 ; wire \curr_state_reg[0]_1 ; wire \curr_state_reg[0]_10 ; wire \curr_state_reg[0]_2 ; wire [0:0]\curr_state_reg[0]_3 ; wire [0:0]\curr_state_reg[0]_4 ; wire [3:0]\curr_state_reg[0]_5 ; wire \curr_state_reg[0]_6 ; wire \curr_state_reg[0]_7 ; wire \curr_state_reg[0]_8 ; wire \curr_state_reg[0]_9 ; wire \curr_state_reg[1]_0 ; wire \curr_state_reg[1]_1 ; wire \curr_state_reg[1]_2 ; wire \curr_state_reg[1]_3 ; wire \curr_state_reg[1]_4 ; wire \curr_state_reg[1]_5 ; wire [2:0]\curr_state_reg[1]_6 ; wire [1:0]\curr_state_reg[1]_7 ; wire \curr_state_reg[2]_0 ; wire \curr_state_reg[2]_1 ; wire \curr_state_reg[2]_2 ; wire \curr_state_reg[2]_3 ; wire \curr_state_reg[2]_4 ; wire \curr_state_reg[2]_5 ; wire \curr_state_reg[2]_i_3_n_0 ; wire \curr_state_reg[3]_0 ; wire \curr_state_reg[3]_1 ; wire \curr_state_reg[3]_2 ; wire [0:0]\curr_state_reg[3]_3 ; wire \curr_state_reg[3]_4 ; wire \curr_state_reg[3]_5 ; wire \curr_state_reg[3]_6 ; wire \curr_state_reg[3]_7 ; wire \curr_state_reg[3]_i_2_n_0 ; wire \curr_state_reg[4]_0 ; wire \curr_state_reg[4]_1 ; wire \curr_state_reg[4]_2 ; wire \curr_state_reg[4]_3 ; wire \curr_state_reg[4]_4 ; wire \curr_state_reg[5]_0 ; wire [0:0]\curr_state_reg[5]_1 ; wire [1:0]\curr_state_reg[5]_2 ; wire \curr_state_reg[5]_3 ; wire [0:0]\curr_state_reg[5]_4 ; wire \curr_state_reg[5]_5 ; wire [0:0]\curr_state_reg[5]_6 ; wire \curr_state_reg[5]_7 ; wire \curr_state_reg[5]_i_23_n_0 ; wire \data_err_ctr_q[15]_i_3_n_0 ; wire data_halt_d1_out; wire [2:0]data_in_IBUF; wire destuff_enable; wire destuff_enable_i_10_n_0; wire destuff_enable_i_1_n_0; wire destuff_enable_i_2_n_0; wire destuff_enable_i_3_n_0; wire destuff_enable_i_8_n_0; wire destuff_enable_i_9_n_0; wire destuff_enable_reg_0; wire destuff_enable_reg_1; wire destuff_enable_reg_2; wire destuff_enable_reg_3; wire enable_prev; wire err_capt_err_erp_reg; wire \err_capt_err_pos_q[0]_i_2_n_0 ; wire \err_capt_err_pos_q[0]_i_4_n_0 ; wire \err_capt_err_pos_q[0]_i_5_n_0 ; wire \err_capt_err_pos_q[0]_i_6_n_0 ; wire \err_capt_err_pos_q[1]_i_2_n_0 ; wire \err_capt_err_pos_q[1]_i_3_n_0 ; wire \err_capt_err_pos_q[1]_i_4_n_0 ; wire \err_capt_err_pos_q[2]_i_2_n_0 ; wire \err_capt_err_pos_q[3]_i_2_n_0 ; wire \err_capt_err_pos_q_reg[0] ; wire \err_capt_err_type_q[2]_i_10_n_0 ; wire \err_capt_err_type_q[2]_i_12_n_0 ; wire \err_capt_err_type_q[2]_i_13_n_0 ; wire \err_capt_err_type_q[2]_i_14_n_0 ; wire \err_capt_err_type_q[2]_i_15_n_0 ; wire \err_capt_err_type_q[2]_i_17_n_0 ; wire \err_capt_err_type_q[2]_i_3_n_0 ; wire \err_capt_err_type_q[2]_i_4_n_0 ; wire \err_capt_err_type_q[2]_i_8_0 ; wire \err_capt_err_type_q[2]_i_8_n_0 ; wire \err_capt_err_type_q[2]_i_9_n_0 ; wire \err_capt_err_type_q_reg[1] ; wire err_frm_req_reg; wire err_frm_req_reg_0; wire [0:0]err_frm_req_reg_1; wire err_frm_req_reg_10; wire [3:0]err_frm_req_reg_2; wire err_frm_req_reg_3; wire err_frm_req_reg_4; wire err_frm_req_reg_5; wire [0:0]err_frm_req_reg_6; wire [0:0]err_frm_req_reg_7; wire err_frm_req_reg_8; wire err_frm_req_reg_9; wire \exp_seg_length_q[8]_i_13_n_0 ; wire \exp_seg_length_q[8]_i_14_n_0 ; wire \exp_seg_length_q_reg[0] ; wire \exp_seg_length_q_reg[0]_0 ; wire first_err_delim_q; wire first_err_delim_q_i_1_n_0; wire first_err_delim_q_i_2_n_0; wire first_err_delim_q_i_3_n_0; wire first_ssp_q0; wire fixed_prev_q; wire g0_b0_n_0; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[1].reg_value_r_reg[1] ; wire [1:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][0] ; wire ident_valid_q; wire [0:0]ident_valid_q_reg; wire int_status_i_10_n_0; wire int_status_i_2__1_0; wire int_status_i_2__1_1; wire int_status_i_2__1_n_0; wire int_status_i_3__1_n_0; wire [1:0]int_status_i_4_0; wire int_status_i_4_n_0; wire int_status_i_5_n_0; wire int_status_i_8_n_0; wire int_status_i_9_n_0; wire int_status_reg; wire int_status_reg_0; wire int_status_reg_1; wire [0:0]int_status_reg_2; wire is_tseg1; wire is_tseg2; wire mr_command_ercrst_q; wire mr_command_ercrst_q_i_1_n_0; wire mr_command_ercrst_q_reg_0; wire mr_ctr_pres_efd_q; wire [0:0]mr_ctr_pres_efd_q_reg; wire mr_ctr_pres_enorm_q; wire [0:0]mr_ctr_pres_enorm_q_reg; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_ctrl_out[settings_rtrle] ; wire [2:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; wire mr_int_stat_txbhci_o; wire mr_status_pexs_i_1_n_0; wire mr_status_pexs_i_3_n_0; wire mr_status_pexs_reg_0; wire mr_status_pexs_reg_1; wire \nom_err_ctr_q_reg[0] ; wire p_0_out; wire p_131_in; wire \pc_dbg[is_ack_delim] ; wire \pc_dbg[is_arbitration] ; wire \pc_dbg[is_eof] ; wire \pc_dbg[is_intermission] ; wire pexs_set107_out; wire prev_val_d; wire \r_data[10]_i_6_n_0 ; wire \r_data[11]_i_8_n_0 ; wire \r_data[12]_i_6_n_0 ; wire \r_data[13]_i_2_n_0 ; wire \r_data[13]_i_5_n_0 ; wire \r_data[15]_i_2_n_0 ; wire \r_data[15]_i_4__0_n_0 ; wire \r_data[16]_i_2__0_n_0 ; wire \r_data[16]_i_5_n_0 ; wire \r_data[17]_i_10_n_0 ; wire \r_data[17]_i_7_n_0 ; wire \r_data[18]_i_10_n_0 ; wire \r_data[18]_i_2_n_0 ; wire \r_data[18]_i_7_n_0 ; wire \r_data[3]_i_14_n_0 ; wire \r_data[3]_i_15_n_0 ; wire \r_data[7]_i_12_n_0 ; wire [0:0]\r_data[7]_i_3__0_0 ; wire \r_data[7]_i_7_n_0 ; wire \r_data[9]_i_6_n_0 ; wire \r_data_reg[12] ; wire \r_data_reg[12]_0 ; wire \r_data_reg[13] ; wire \r_data_reg[13]_0 ; wire [0:0]\r_data_reg[13]_1 ; wire \r_data_reg[13]_2 ; wire \r_data_reg[13]_3 ; wire \r_data_reg[13]_4 ; wire \r_data_reg[15] ; wire \r_data_reg[15]_0 ; wire \r_data_reg[15]_1 ; wire \r_data_reg[15]_2 ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[16]_1 ; wire \r_data_reg[18] ; wire \r_data_reg[18]_0 ; wire \r_data_reg[18]_1 ; wire \r_data_reg[18]_2 ; wire \r_data_reg[18]_3 ; wire \r_data_reg[18]_4 ; wire rec_abort_f; wire rec_abort_reg_0; wire rec_abort_reg_1; wire rec_abort_reg_2; wire \rec_dlc[3]_i_2_n_0 ; wire \rec_dlc_reg[0] ; wire \rec_ident[17]_i_2_n_0 ; wire \rec_ident[28]_i_2_n_0 ; wire rec_ivld; wire rec_ivld_i; wire rec_ivld_q_i_1_n_0; wire rec_ivld_q_i_3_n_0; wire rec_ivld_q_i_4_n_0; wire rec_ivld_q_i_5_n_0; wire rec_ivld_q_i_7_n_0; wire rec_ivld_q_reg_0; wire rec_lbpf; wire rec_lbpf_q_reg_0; wire rec_valid_i_1_n_0; wire rec_valid_i_4_n_0; wire rec_valid_i_5_n_0; wire rec_valid_reg_0; wire [2:0]rec_valid_reg_1; wire rec_valid_reg_2; wire rec_valid_reg_3; wire reg_q; wire reg_q_i_2__5_n_0; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire [0:0]reg_q_reg_10; wire [0:0]reg_q_reg_11; wire [0:0]reg_q_reg_12; wire [2:0]reg_q_reg_13; wire reg_q_reg_14; wire reg_q_reg_15; wire reg_q_reg_16; wire reg_q_reg_17; wire reg_q_reg_18; wire reg_q_reg_2; wire [0:0]reg_q_reg_3; wire [0:0]reg_q_reg_4; wire reg_q_reg_5; wire [0:0]reg_q_reg_6; wire reg_q_reg_7; wire reg_q_reg_8; wire [0:0]reg_q_reg_9; wire reinteg_ctr_ce; wire \reinteg_ctr_q[7]_i_5_n_0 ; wire retr_ctr_add; wire retr_ctr_add_block; wire retr_ctr_add_block_i_1_n_0; wire retr_ctr_add_block_i_2_n_0; wire [0:0]\retr_ctr_q_reg[0] ; wire [0:0]\retr_ctr_q_reg[0]_0 ; wire \retr_ctr_q_reg[3] ; wire rx_data_nbs_prev_reg_0; wire rx_data_nbs_prev_reg_1; wire rx_data_sync_prev_reg; wire rx_data_wbs; wire \rx_err_ctr_q[8]_i_10_n_0 ; wire \rx_err_ctr_q[8]_i_12_n_0 ; wire \rx_err_ctr_q[8]_i_13_n_0 ; wire \rx_err_ctr_q[8]_i_8_n_0 ; wire \rx_stuff_count[3]_i_2_n_0 ; wire \rx_stuff_count_reg[3] ; wire \same_bits_q_reg[2] ; wire [1:0]sbe_IBUF; wire \segm_counter_q_reg[0] ; wire \segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire \segm_counter_q_reg[0]_2 ; wire \shift_regs[21]_i_3_n_0 ; wire \shift_regs[22]_i_3_n_0 ; wire \shift_regs[23]_i_3_n_0 ; wire \shift_regs[24]_i_3_n_0 ; wire \shift_regs[25]_i_3_n_0 ; wire \shift_regs[26]_i_3_n_0 ; wire \shift_regs[27]_i_2 ; wire \shift_regs[27]_i_3_n_0 ; wire \shift_regs[27]_i_6_n_0 ; wire \shift_regs[27]_i_7_n_0 ; wire \shift_regs[28]_i_2_n_0 ; wire \shift_regs[28]_i_4_n_0 ; wire \shift_regs[29]_i_12_n_0 ; wire \shift_regs[29]_i_13_n_0 ; wire \shift_regs[29]_i_14_n_0 ; wire \shift_regs[29]_i_2_n_0 ; wire \shift_regs[29]_i_4_n_0 ; wire \shift_regs[29]_i_7_n_0 ; wire \shift_regs[30]_i_3_n_0 ; wire \shift_regs[30]_i_4_n_0 ; wire \shift_regs[30]_i_6_n_0 ; wire \shift_regs[31]_i_10_n_0 ; wire \shift_regs[31]_i_11_n_0 ; wire \shift_regs[31]_i_15_n_0 ; wire \shift_regs[31]_i_16_n_0 ; wire \shift_regs[31]_i_17_n_0 ; wire \shift_regs[31]_i_22_n_0 ; wire \shift_regs[31]_i_23_n_0 ; wire \shift_regs[31]_i_25_n_0 ; wire \shift_regs[31]_i_26_n_0 ; wire \shift_regs[31]_i_5_n_0 ; wire \shift_regs[31]_i_7_0 ; wire \shift_regs_reg[0] ; wire \shift_regs_reg[0]_0 ; wire \shift_regs_reg[11] ; wire \shift_regs_reg[11]_0 ; wire \shift_regs_reg[12] ; wire \shift_regs_reg[12]_0 ; wire \shift_regs_reg[13] ; wire \shift_regs_reg[14] ; wire \shift_regs_reg[14]_0 ; wire \shift_regs_reg[15] ; wire \shift_regs_reg[15]_0 ; wire \shift_regs_reg[16] ; wire \shift_regs_reg[16]_0 ; wire \shift_regs_reg[16]_1 ; wire \shift_regs_reg[17] ; wire \shift_regs_reg[17]_0 ; wire \shift_regs_reg[18] ; wire \shift_regs_reg[18]_0 ; wire \shift_regs_reg[19] ; wire \shift_regs_reg[19]_0 ; wire \shift_regs_reg[1] ; wire \shift_regs_reg[20] ; wire \shift_regs_reg[20]_0 ; wire \shift_regs_reg[21] ; wire \shift_regs_reg[21]_0 ; wire \shift_regs_reg[22] ; wire \shift_regs_reg[22]_0 ; wire \shift_regs_reg[23] ; wire \shift_regs_reg[24] ; wire \shift_regs_reg[25] ; wire \shift_regs_reg[25]_0 ; wire \shift_regs_reg[26] ; wire \shift_regs_reg[26]_0 ; wire \shift_regs_reg[27] ; wire [13:0]\shift_regs_reg[27]_0 ; wire \shift_regs_reg[28] ; wire \shift_regs_reg[28]_0 ; wire \shift_regs_reg[28]_1 ; wire \shift_regs_reg[28]_2 ; wire \shift_regs_reg[28]_3 ; wire \shift_regs_reg[29] ; wire \shift_regs_reg[29]_0 ; wire \shift_regs_reg[29]_1 ; wire \shift_regs_reg[29]_2 ; wire \shift_regs_reg[2] ; wire \shift_regs_reg[30] ; wire \shift_regs_reg[30]_0 ; wire \shift_regs_reg[30]_1 ; wire \shift_regs_reg[30]_2 ; wire \shift_regs_reg[31] ; wire \shift_regs_reg[31]_0 ; wire \shift_regs_reg[31]_1 ; wire \shift_regs_reg[31]_2 ; wire [0:0]sp_control; wire [1:0]sp_control_q; wire \sp_control_q_i[0]_i_1_n_0 ; wire \sp_control_q_i[1]_i_1_n_0 ; wire \sp_control_q_i[1]_i_2_n_0 ; wire \sp_control_q_i[1]_i_3_n_0 ; wire \sp_control_q_i[1]_i_4_n_0 ; wire \sp_control_q_i_reg[0]_0 ; wire \sp_control_q_i_reg[0]_1 ; wire \sp_control_q_i_reg[1]_0 ; wire \sp_control_q_i_reg[1]_1 ; wire \sp_control_q_i_reg[1]_2 ; wire sspc_ena_q; wire sspc_ena_q_reg; wire store_data; wire store_data_reg_0; wire [0:0]store_data_word; wire store_metadata_reg_0; wire store_metadata_reg_1; wire stuff_enable_i_1_n_0; wire stuff_enable_i_2_n_0; wire stuff_enable_i_4_n_0; wire stuff_enable_i_5_n_0; wire stuff_enable_reg_0; wire stuff_err; wire stuff_err_d; wire [1:0]sync_control_d; wire \sync_control_q[1]_i_2_n_0 ; wire \sync_control_q[1]_i_3_n_0 ; wire \sync_control_q[1]_i_4_n_0 ; wire \sync_control_q_reg[0]_0 ; wire \sync_control_q_reg[0]_1 ; wire [1:0]\sync_control_q_reg[1]_0 ; wire sync_edge; wire sync_edge3__0; wire sync_flag; wire \timestamp[14] ; wire \timestamp[17] ; wire \timestamp[41] ; wire \timestamp[42] ; wire \timestamp[43] ; wire \timestamp[7] ; wire \timestamp[8] ; wire [19:0]timestamp_IBUF; wire \timestamp_capture[63]_i_2_n_0 ; wire \timestamp_capture[63]_i_3_n_0 ; wire \timestamp_capture[63]_i_4_n_0 ; wire \timestamp_capture_reg[63] ; wire \tq_counter_q[7]_i_3_n_0 ; wire \tq_counter_q[7]_i_4_n_0 ; wire \tq_counter_q_reg[7] ; wire tq_edge; wire tran_brs; wire tran_delay_meas; wire \tran_frame_test[fcrc] ; wire tran_frame_valid; wire tran_ident_type; wire tran_is_rtr; wire [20:0]tran_word; wire tx_data_prev; wire tx_frame_no_sof_q_i_1_n_0; wire tx_frame_no_sof_q_i_2_n_0; wire tx_frame_no_sof_q_i_5_n_0; wire tx_frame_no_sof_q_reg_0; wire tx_frame_no_sof_q_reg_1; wire tx_frame_no_sof_q_reg_2; wire tx_frame_no_sof_q_reg_3; wire tx_frame_no_sof_q_reg_4; wire tx_frame_no_sof_q_reg_5; wire tx_trigger_q; wire [3:0]txtb_allow_bb; wire \txtb_hw_cmd[arbl] ; wire \txtb_hw_cmd[err] ; wire [1:0]txtb_hw_cmd_cs; wire \txtb_hw_cmd_q[arbl] ; wire \txtb_hw_cmd_q[arbl]_i_2_n_0 ; wire \txtb_hw_cmd_q[arbl]_i_3_n_0 ; wire \txtb_hw_cmd_q[err] ; wire \txtb_hw_cmd_q[err]_i_5_n_0 ; wire \txtb_hw_cmd_q[failed] ; wire \txtb_hw_cmd_q[lock] ; wire \txtb_hw_cmd_q[lock]_i_2_n_0 ; wire \txtb_hw_cmd_q[lock]_i_3_n_0 ; wire \txtb_hw_cmd_q[lock]_i_4_n_0 ; wire \txtb_hw_cmd_q[lock]_i_5_n_0 ; wire \txtb_hw_cmd_q[valid] ; wire \txtb_hw_cmd_q_reg[arbl]_0 ; wire \txtb_hw_cmd_q_reg[err]_0 ; wire \txtb_hw_cmd_q_reg[failed]_0 ; wire \txtb_hw_cmd_q_reg[failed]_1 ; wire \txtb_hw_cmd_q_reg[failed]_2 ; wire \txtb_hw_cmd_q_reg[failed]_3 ; wire \txtb_hw_cmd_q_reg[failed]_4 ; wire \txtb_hw_cmd_q_reg[failed]_5 ; wire \txtb_hw_cmd_q_reg[failed]_6 ; wire \txtb_hw_cmd_q_reg[failed]_7 ; wire \txtb_hw_cmd_q_reg[lock]_0 ; wire \txtb_hw_cmd_q_reg[lock]_1 ; wire \txtb_hw_cmd_q_reg[lock]_2 ; wire \txtb_hw_cmd_q_reg[lock]_3 ; wire \txtb_hw_cmd_q_reg[lock]_4 ; wire \txtb_hw_cmd_q_reg[lock]_5 ; wire \txtb_hw_cmd_q_reg[valid]_0 ; wire \txtb_hw_cmd_q_reg[valid]_1 ; wire \txtb_hw_cmd_q_reg[valid]_2 ; wire \txtb_hw_cmd_q_reg[valid]_3 ; wire [0:0]\txtb_hw_cmd_q_reg[valid]_4 ; wire \txtb_ptr_q[2]_i_3_n_0 ; wire \txtb_ptr_q[2]_i_4_n_0 ; wire \txtb_ptr_q_reg[2]_0 ; wire \txtb_ptr_q_reg[2]_1 ; wire [4:0]\txtb_ptr_q_reg[4]_0 ; wire \txtb_ptr_q_reg[4]_1 ; wire \txtb_ptr_q_reg[4]_2 ; wire [0:0]\txtb_ptr_q_reg[4]_3 ; wire [3:0]\txtb_ptr_q_reg[4]_4 ; assign \g_bit[0].reg_value_r_reg[0]_3 = \g_bit[0].reg_value_r_reg[0]_2 ; (* SOFT_HLUTNM = "soft_lutpair218" *) LUT2 #( .INIT(4'h8)) \FSM_onehot_curr_state[0]_i_3 (.I0(rec_abort_reg_0), .I1(ident_valid_q), .O(rec_abort_f)); (* SOFT_HLUTNM = "soft_lutpair223" *) LUT5 #( .INIT(32'h0000DDD5)) \FSM_onehot_curr_state[11]_i_6 (.I0(\FSM_onehot_curr_state_reg[6] [3]), .I1(ident_valid_q), .I2(rec_abort_reg_0), .I3(rec_valid_reg_0), .I4(\g_bit[0].reg_value_r_reg[0] ), .O(\FSM_onehot_curr_state_reg[5] )); LUT6 #( .INIT(64'hFF8F0F0F88880000)) \FSM_onehot_curr_state[1]_i_1 (.I0(store_metadata_reg_0), .I1(ident_valid_q), .I2(\FSM_onehot_curr_state[1]_i_2_n_0 ), .I3(\FSM_onehot_curr_state_reg[1] ), .I4(\FSM_onehot_curr_state_reg[6] [0]), .I5(\FSM_onehot_curr_state_reg[6] [1]), .O(rec_valid_reg_1[0])); (* SOFT_HLUTNM = "soft_lutpair223" *) LUT4 #( .INIT(16'hE0FF)) \FSM_onehot_curr_state[1]_i_2 (.I0(rec_valid_reg_0), .I1(rec_abort_reg_0), .I2(ident_valid_q), .I3(\FSM_onehot_curr_state_reg[6] [3]), .O(\FSM_onehot_curr_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h70FF7070)) \FSM_onehot_curr_state[2]_i_1 (.I0(rec_abort_reg_0), .I1(ident_valid_q), .I2(\FSM_onehot_curr_state_reg[6] [1]), .I3(\FSM_onehot_curr_state_reg[5] ), .I4(\FSM_onehot_curr_state_reg[6] [2]), .O(rec_valid_reg_1[1])); LUT6 #( .INIT(64'hFFFF3F0020002000)) \FSM_onehot_curr_state[6]_i_1 (.I0(rec_valid_reg_0), .I1(rec_abort_reg_0), .I2(ident_valid_q), .I3(\FSM_onehot_curr_state_reg[6] [3]), .I4(\g_bit[0].reg_value_r_reg[0] ), .I5(\FSM_onehot_curr_state_reg[6] [4]), .O(rec_valid_reg_1[2])); LUT5 #( .INIT(32'h0070F0F0)) \FSM_onehot_curr_state[6]_i_2 (.I0(\mr_ctrl_out[mode_erfm] ), .I1(rec_abort_reg_0), .I2(\FSM_onehot_curr_state_reg[6] [0]), .I3(store_metadata_reg_0), .I4(ident_valid_q), .O(\g_bit[0].reg_value_r_reg[0] )); LUT6 #( .INIT(64'h8A0000008A8A8A8A)) \FSM_onehot_curr_state[8]_i_2 (.I0(\FSM_onehot_curr_state[1]_i_2_n_0 ), .I1(\FSM_onehot_curr_state_reg[1] ), .I2(\FSM_onehot_curr_state_reg[6] [3]), .I3(ident_valid_q), .I4(store_metadata_reg_0), .I5(\FSM_onehot_curr_state_reg[6] [0]), .O(\FSM_onehot_curr_state_reg[5]_0 )); LUT6 #( .INIT(64'hFFFFFFFCAAAAAAAA)) \FSM_sequential_curr_state[0]_i_11 (.I0(\FSM_sequential_curr_state[0]_i_7 ), .I1(\txtb_hw_cmd_q_reg[valid]_0 ), .I2(\txtb_hw_cmd[err] ), .I3(\txtb_hw_cmd_q_reg[failed]_0 ), .I4(\txtb_hw_cmd[arbl] ), .I5(\FSM_sequential_curr_state[0]_i_7_0 ), .O(\txtb_hw_cmd_q_reg[valid]_2 )); LUT6 #( .INIT(64'h0D08FFFFFFFF0000)) \FSM_sequential_curr_state[0]_i_1__4 (.I0(\shift_regs_reg[0]_0 ), .I1(\FSM_sequential_curr_state[1]_i_2__4_n_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\txtb_hw_cmd_q[lock] ), .I4(\FSM_sequential_curr_state[1]_i_4__2_n_0 ), .I5(\shift_regs_reg[0] ), .O(\FSM_sequential_curr_state_reg[1]_1 )); LUT6 #( .INIT(64'h0101010001000100)) \FSM_sequential_curr_state[0]_i_2__5 (.I0(\rec_dlc_reg[0] ), .I1(rec_abort_reg_2), .I2(Q[5]), .I3(\FSM_sequential_curr_state[0]_i_3__1_n_0 ), .I4(\cc_stat[is_bus_off] ), .I5(\FSM_sequential_curr_state[0]_i_4__4_n_0 ), .O(err_frm_req_reg_8)); LUT6 #( .INIT(64'h0200000000000000)) \FSM_sequential_curr_state[0]_i_3__1 (.I0(\FSM_sequential_curr_state[1]_i_8_0 ), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(Q[3]), .O(\FSM_sequential_curr_state[0]_i_3__1_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \FSM_sequential_curr_state[0]_i_4__4 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[0]), .I2(Q[4]), .I3(Q[3]), .I4(Q[2]), .I5(Q[1]), .O(\FSM_sequential_curr_state[0]_i_4__4_n_0 )); LUT2 #( .INIT(4'h1)) \FSM_sequential_curr_state[0]_i_5__4 (.I0(\txtb_hw_cmd_q_reg[lock]_0 ), .I1(\FSM_sequential_curr_state[0]_i_7 ), .O(\txtb_hw_cmd_q_reg[lock]_3 )); LUT6 #( .INIT(64'hFFFFFFFF4F444F4F)) \FSM_sequential_curr_state[1]_i_10 (.I0(\rec_dlc_reg[0] ), .I1(\cc_stat[is_bus_off] ), .I2(rec_abort_reg_2), .I3(\FSM_sequential_curr_state[1]_i_14_n_0 ), .I4(\FSM_sequential_curr_state[1]_i_13_n_0 ), .I5(err_frm_req_reg_0), .O(\FSM_sequential_curr_state[1]_i_10_n_0 )); LUT6 #( .INIT(64'h00000000EAEEEAEA)) \FSM_sequential_curr_state[1]_i_11 (.I0(rec_abort_reg_2), .I1(\FSM_sequential_curr_state[1]_i_15_n_0 ), .I2(\rec_dlc_reg[0] ), .I3(\FSM_sequential_curr_state[1]_i_16_n_0 ), .I4(\FSM_sequential_curr_state[1]_i_17_n_0 ), .I5(\FSM_sequential_curr_state[1]_i_4__2_0 ), .O(\FSM_sequential_curr_state[1]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair212" *) LUT4 #( .INIT(16'hFEFF)) \FSM_sequential_curr_state[1]_i_12 (.I0(Q[0]), .I1(Q[2]), .I2(Q[3]), .I3(Q[1]), .O(\FSM_sequential_curr_state[1]_i_12_n_0 )); LUT6 #( .INIT(64'hFF0FFFBFFF0FFFFF)) \FSM_sequential_curr_state[1]_i_13 (.I0(\rx_stuff_count_reg[3] ), .I1(\curr_state[4]_i_8_n_0 ), .I2(\txtb_hw_cmd_q[lock]_i_3_n_0 ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[1]_0 ), .I5(tx_frame_no_sof_q_reg_3), .O(\FSM_sequential_curr_state[1]_i_13_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \FSM_sequential_curr_state[1]_i_14 (.I0(\FSM_sequential_curr_state[1]_i_12_n_0 ), .I1(Q[4]), .I2(Q[5]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\cc_stat[is_bus_off] ), .I5(tran_frame_valid), .O(\FSM_sequential_curr_state[1]_i_14_n_0 )); LUT6 #( .INIT(64'h00000000FFFF51FF)) \FSM_sequential_curr_state[1]_i_15 (.I0(tx_frame_no_sof_q_reg_3), .I1(\curr_state_reg[1]_0 ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(\txtb_hw_cmd_q[lock]_i_3_n_0 ), .I4(\timestamp_capture[63]_i_4_n_0 ), .I5(\FSM_sequential_curr_state[1]_i_14_n_0 ), .O(\FSM_sequential_curr_state[1]_i_15_n_0 )); LUT6 #( .INIT(64'h00000000CC080000)) \FSM_sequential_curr_state[1]_i_16 (.I0(\curr_state[4]_i_8_n_0 ), .I1(tran_frame_valid), .I2(\curr_state_reg[4]_2 ), .I3(\FSM_sequential_curr_state[1]_i_19_n_0 ), .I4(\txtb_hw_cmd_q[lock]_i_3_n_0 ), .I5(\rx_stuff_count_reg[3] ), .O(\FSM_sequential_curr_state[1]_i_16_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFEFFFF)) \FSM_sequential_curr_state[1]_i_17 (.I0(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .I4(Q[1]), .I5(\txtb_hw_cmd_q_reg[lock]_5 ), .O(\FSM_sequential_curr_state[1]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_curr_state[1]_i_19 (.I0(Q[1]), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(Q[0]), .O(\FSM_sequential_curr_state[1]_i_19_n_0 )); LUT5 #( .INIT(32'hF022AAAA)) \FSM_sequential_curr_state[1]_i_1__5 (.I0(\shift_regs_reg[0]_0 ), .I1(\FSM_sequential_curr_state[1]_i_2__4_n_0 ), .I2(\FSM_sequential_curr_state[1]_i_3__1_n_0 ), .I3(\shift_regs_reg[0] ), .I4(\FSM_sequential_curr_state[1]_i_4__2_n_0 ), .O(\FSM_sequential_curr_state_reg[1]_0 )); LUT6 #( .INIT(64'h2322232222222322)) \FSM_sequential_curr_state[1]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_2 ), .I1(\FSM_sequential_curr_state_reg[1]_3 ), .I2(\txtb_hw_cmd_q_reg[failed]_0 ), .I3(\FSM_sequential_curr_state_reg[2] ), .I4(\txtb_hw_cmd_q_reg[err]_0 ), .I5(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_3 )); LUT6 #( .INIT(64'h2322232222222322)) \FSM_sequential_curr_state[1]_i_2__1 (.I0(\FSM_sequential_curr_state_reg[1]_4 ), .I1(\FSM_sequential_curr_state_reg[1]_3 ), .I2(\txtb_hw_cmd_q_reg[failed]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_1 ), .I4(\txtb_hw_cmd_q_reg[err]_0 ), .I5(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_6 )); LUT6 #( .INIT(64'hFFFFAAFBAAAAAAAA)) \FSM_sequential_curr_state[1]_i_2__4 (.I0(\ctrl_ctr_q_reg[0] ), .I1(\FSM_sequential_curr_state[1]_i_5_n_0 ), .I2(\FSM_sequential_curr_state[1]_i_6_n_0 ), .I3(\FSM_sequential_curr_state[1]_i_7_n_0 ), .I4(\FSM_sequential_curr_state[1]_i_8_n_0 ), .I5(\timestamp_capture[63]_i_2_n_0 ), .O(\FSM_sequential_curr_state[1]_i_2__4_n_0 )); LUT6 #( .INIT(64'h0F0808080C0C0C0C)) \FSM_sequential_curr_state[1]_i_3 (.I0(\FSM_sequential_curr_state[1]_i_4__3_n_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_3 ), .I3(\FSM_sequential_curr_state[1]_i_2__0 ), .I4(\txtb_hw_cmd_q_reg[lock]_0 ), .I5(txtb_hw_cmd_cs[0]), .O(\txtb_hw_cmd_q_reg[lock]_1 )); LUT6 #( .INIT(64'h0F0808080C0C0C0C)) \FSM_sequential_curr_state[1]_i_3__0 (.I0(\FSM_sequential_curr_state[1]_i_4__3_n_0 ), .I1(\FSM_sequential_curr_state_reg[2]_2 ), .I2(\FSM_sequential_curr_state_reg[1]_3 ), .I3(\FSM_sequential_curr_state[1]_i_2__2 ), .I4(\txtb_hw_cmd_q_reg[lock]_0 ), .I5(txtb_hw_cmd_cs[1]), .O(\txtb_hw_cmd_q_reg[lock]_2 )); LUT6 #( .INIT(64'hF0FFB0BBF0FF8088)) \FSM_sequential_curr_state[1]_i_3__1 (.I0(err_frm_req_reg_0), .I1(\shift_regs_reg[0]_0 ), .I2(\rec_dlc_reg[0] ), .I3(\cc_stat[is_bus_off] ), .I4(\FSM_sequential_curr_state[1]_i_9_n_0 ), .I5(\txtb_hw_cmd_q[lock] ), .O(\FSM_sequential_curr_state[1]_i_3__1_n_0 )); LUT6 #( .INIT(64'hF0B0F080FFBCFF8C)) \FSM_sequential_curr_state[1]_i_4__2 (.I0(\FSM_sequential_curr_state[1]_i_10_n_0 ), .I1(\shift_regs_reg[0] ), .I2(\shift_regs_reg[0]_0 ), .I3(\FSM_sequential_curr_state[1]_i_2__4_n_0 ), .I4(\txtb_hw_cmd_q[lock] ), .I5(\FSM_sequential_curr_state[1]_i_11_n_0 ), .O(\FSM_sequential_curr_state[1]_i_4__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'h00F1)) \FSM_sequential_curr_state[1]_i_4__3 (.I0(\txtb_hw_cmd[err] ), .I1(\txtb_hw_cmd[arbl] ), .I2(\txtb_hw_cmd_q_reg[valid]_0 ), .I3(\txtb_hw_cmd_q_reg[failed]_0 ), .O(\FSM_sequential_curr_state[1]_i_4__3_n_0 )); LUT6 #( .INIT(64'hFFDF55DFFFDFFFDF)) \FSM_sequential_curr_state[1]_i_5 (.I0(\curr_state[4]_i_8_n_0 ), .I1(\curr_state_reg[4]_2 ), .I2(destuff_enable_reg_0), .I3(\rx_stuff_count_reg[3] ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\mr_ctrl_out[mode_rom] ), .O(\FSM_sequential_curr_state[1]_i_5_n_0 )); LUT6 #( .INIT(64'h0040004F00400040)) \FSM_sequential_curr_state[1]_i_6 (.I0(\rx_stuff_count_reg[3] ), .I1(destuff_enable_reg_0), .I2(Q[1]), .I3(Q[0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\FSM_sequential_curr_state[1]_i_2__4_0 ), .O(\FSM_sequential_curr_state[1]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT3 #( .INIT(8'hBF)) \FSM_sequential_curr_state[1]_i_7 (.I0(Q[2]), .I1(Q[3]), .I2(Q[4]), .O(\FSM_sequential_curr_state[1]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00001000)) \FSM_sequential_curr_state[1]_i_8 (.I0(Q[1]), .I1(Q[2]), .I2(\rec_ident[17]_i_2_n_0 ), .I3(Q[0]), .I4(\rx_stuff_count_reg[3] ), .I5(\FSM_sequential_curr_state[0]_i_3__1_n_0 ), .O(\FSM_sequential_curr_state[1]_i_8_n_0 )); LUT6 #( .INIT(64'h0000010055555555)) \FSM_sequential_curr_state[1]_i_9 (.I0(rec_abort_reg_2), .I1(\FSM_sequential_curr_state[1]_i_12_n_0 ), .I2(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .I3(rec_ivld_q_reg_0), .I4(tran_frame_valid), .I5(\FSM_sequential_curr_state[1]_i_13_n_0 ), .O(\FSM_sequential_curr_state[1]_i_9_n_0 )); LUT6 #( .INIT(64'hCFCC4744CFCC4747)) \FSM_sequential_curr_state[2]_i_11__3 (.I0(\txtb_hw_cmd_q_reg[valid]_1 ), .I1(curr_state_6), .I2(\txtb_hw_cmd_q_reg[lock]_0 ), .I3(\FSM_sequential_curr_state[0]_i_7 ), .I4(\FSM_sequential_curr_state[2]_i_3__3 ), .I5(\FSM_sequential_curr_state[2]_i_3__3_0 ), .O(\FSM_sequential_curr_state_reg[0] )); LUT2 #( .INIT(4'hE)) \FSM_sequential_curr_state[2]_i_13__1 (.I0(\txtb_hw_cmd_q_reg[failed]_0 ), .I1(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_1 )); LUT6 #( .INIT(64'hAAAA0000FBFF0000)) \FSM_sequential_curr_state[2]_i_2__0 (.I0(\txtb_hw_cmd_q_reg[failed]_0 ), .I1(curr_state_1), .I2(abort_applied), .I3(\txtb_hw_cmd_q_reg[err]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .I5(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_4 )); LUT6 #( .INIT(64'hAAAA0000FBFF0000)) \FSM_sequential_curr_state[2]_i_2__2 (.I0(\txtb_hw_cmd_q_reg[failed]_0 ), .I1(curr_state_4), .I2(abort_applied_5), .I3(\txtb_hw_cmd_q_reg[err]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_2 ), .I5(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_7 )); LUT6 #( .INIT(64'hAAAA0000FBFF0000)) \FSM_sequential_curr_state[2]_i_5 (.I0(\txtb_hw_cmd_q_reg[failed]_0 ), .I1(curr_state_0), .I2(abort_or_skipped), .I3(\txtb_hw_cmd_q_reg[err]_0 ), .I4(\FSM_sequential_curr_state_reg[2] ), .I5(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_2 )); LUT6 #( .INIT(64'hAAAA0000FBFF0000)) \FSM_sequential_curr_state[2]_i_5__1 (.I0(\txtb_hw_cmd_q_reg[failed]_0 ), .I1(curr_state_2), .I2(abort_or_skipped_3), .I3(\txtb_hw_cmd_q_reg[err]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_1 ), .I5(\txtb_hw_cmd_q_reg[valid]_0 ), .O(\txtb_hw_cmd_q_reg[failed]_5 )); LUT2 #( .INIT(4'hE)) \FSM_sequential_curr_state[2]_i_8__3 (.I0(\txtb_hw_cmd[err] ), .I1(\txtb_hw_cmd[arbl] ), .O(\txtb_hw_cmd_q_reg[err]_0 )); LUT6 #( .INIT(64'hFFFFABFFAAAAAAAA)) ack_err_flag_i_1 (.I0(ack_err_flag_reg_0), .I1(ack_err_flag_i_3_n_0), .I2(ack_err_flag_i_4_n_0), .I3(ack_err_flag_i_5_n_0), .I4(first_err_delim_q_i_2_n_0), .I5(ack_err_flag), .O(ack_err_flag_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair269" *) LUT2 #( .INIT(4'h8)) ack_err_flag_i_3 (.I0(Q[1]), .I1(Q[0]), .O(ack_err_flag_i_3_n_0)); LUT5 #( .INIT(32'h00000800)) ack_err_flag_i_4 (.I0(ack_err_flag), .I1(Q[1]), .I2(tx_frame_no_sof_q_reg_5), .I3(tx_frame_no_sof_q_reg_4), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .O(ack_err_flag_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT2 #( .INIT(4'h2)) ack_err_flag_i_5 (.I0(Q[2]), .I1(rec_abort_reg_2), .O(ack_err_flag_i_5_n_0)); LUT6 #( .INIT(64'hFFFFEEFFFFFFFEFF)) ack_err_flag_i_6 (.I0(ack_err_flag_i_7_n_0), .I1(\mr_ctrl_out[mode_stm] ), .I2(Q[1]), .I3(Q[4]), .I4(Q[0]), .I5(rx_data_nbs_prev_reg_0), .O(\g_bit[0].reg_value_r_reg[0]_4 )); (* SOFT_HLUTNM = "soft_lutpair215" *) LUT2 #( .INIT(4'hB)) ack_err_flag_i_7 (.I0(Q[3]), .I1(Q[2]), .O(ack_err_flag_i_7_n_0)); FDCE ack_err_flag_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(ack_err_flag_i_1_n_0), .Q(ack_err_flag)); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT4 #( .INIT(16'h0002)) \alc_alc_bit[4]_i_1 (.I0(\txtb_hw_cmd_q[arbl]_i_2_n_0 ), .I1(rec_abort_reg_2), .I2(Q[4]), .I3(\txtb_hw_cmd_q[arbl]_i_3_n_0 ), .O(err_frm_req_reg_0)); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT5 #( .INIT(32'h00050010)) \alc_alc_id_field[0]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[3]), .I3(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .I4(Q[2]), .O(\curr_state_reg[1]_6 [0])); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT5 #( .INIT(32'h00140000)) \alc_alc_id_field[1]_i_1 (.I0(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .O(\curr_state_reg[1]_6 [1])); (* SOFT_HLUTNM = "soft_lutpair220" *) LUT4 #( .INIT(16'h0810)) \alc_alc_id_field[2]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[3]), .I3(Q[2]), .O(\curr_state_reg[1]_6 [2])); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT4 #( .INIT(16'hABAA)) bit_err_q_i_2 (.I0(rec_abort_reg_2), .I1(bit_err_q_i_5_n_0), .I2(bit_err_q_i_6_n_0), .I3(bit_err_q_i_7_n_0), .O(bit_err_enable)); LUT6 #( .INIT(64'h000000FF00FF002E)) bit_err_q_i_5 (.I0(\mr_ctrl_out[settings_ena] ), .I1(Q[1]), .I2(\err_capt_err_pos_q_reg[0] ), .I3(bit_err_q_i_8_n_0), .I4(Q[3]), .I5(Q[0]), .O(bit_err_q_i_5_n_0)); LUT6 #( .INIT(64'hFFF0F0F1F4F4F0F4)) bit_err_q_i_6 (.I0(Q[2]), .I1(Q[3]), .I2(bit_err_q_i_9_n_0), .I3(Q[0]), .I4(Q[4]), .I5(Q[1]), .O(bit_err_q_i_6_n_0)); LUT6 #( .INIT(64'hFFFFFFFF0004FF00)) bit_err_q_i_7 (.I0(bit_err_q_i_2_0), .I1(crc_match), .I2(\mr_ctrl_out[mode_bmm] ), .I3(Q[1]), .I4(Q[4]), .I5(ack_err_flag_i_7_n_0), .O(bit_err_q_i_7_n_0)); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT3 #( .INIT(8'hBE)) bit_err_q_i_8 (.I0(Q[5]), .I1(Q[3]), .I2(Q[4]), .O(bit_err_q_i_8_n_0)); LUT6 #( .INIT(64'h7070FF7070707070)) bit_err_q_i_9 (.I0(Q[1]), .I1(Q[0]), .I2(Q[5]), .I3(\shift_regs_reg[0]_0 ), .I4(\shift_regs_reg[0] ), .I5(g0_b0_n_0), .O(bit_err_q_i_9_n_0)); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT2 #( .INIT(4'h2)) \compl_ctr_q[0]_i_1 (.I0(\curr_state_reg[3]_0 ), .I1(\compl_ctr_q_reg[0]_0 ), .O(\compl_ctr_q_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT4 #( .INIT(16'h40FF)) \compl_ctr_q[8]_i_1 (.I0(tx_frame_no_sof_q_reg_5), .I1(tx_frame_no_sof_q_reg_4), .I2(err_frm_req_reg), .I3(\curr_state_reg[3]_0 ), .O(reg_q_reg_3)); LUT2 #( .INIT(4'h1)) \crc_q[0]_i_1__0 (.I0(reg_q_reg_5), .I1(\crc_q_reg[0]_0 ), .O(reg_q_reg_12)); LUT5 #( .INIT(32'h0000596A)) \crc_q[0]_i_1__1 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(reg_q_reg_5), .O(\crc_q_reg[14] [0])); LUT6 #( .INIT(64'hA6950000596A0000)) \crc_q[10]_i_1__1 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[5]_7 ), .I5(\crc_q_reg[14]_0 [4]), .O(\crc_q_reg[14] [5])); LUT6 #( .INIT(64'h000000000000FBFF)) \crc_q[14]_i_10 (.I0(first_err_delim_q_i_2_n_0), .I1(\ctrl_ctr_q[8]_i_23_n_0 ), .I2(Q[1]), .I3(\rx_stuff_count_reg[3] ), .I4(\FSM_sequential_curr_state[0]_i_4__4_n_0 ), .I5(\FSM_sequential_curr_state[0]_i_3__1_n_0 ), .O(\crc_q[14]_i_10_n_0 )); LUT6 #( .INIT(64'h00000000D5D555D5)) \crc_q[14]_i_11 (.I0(Q[0]), .I1(\crc_q[14]_i_15_n_0 ), .I2(first_err_delim_q_i_2_n_0), .I3(\crc_q[14]_i_6_1 ), .I4(tran_brs), .I5(\crc_q[14]_i_17_n_0 ), .O(\crc_q[14]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF0002)) \crc_q[14]_i_12 (.I0(\sp_control_q_i_reg[1]_2 ), .I1(rec_abort_reg_2), .I2(\curr_state_reg[5]_0 ), .I3(\crc_q[14]_i_6_0 [31]), .I4(\crc_q[14]_i_18_n_0 ), .I5(\crc_q[14]_i_19_n_0 ), .O(\crc_q[14]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT5 #( .INIT(32'hFFFFFAEA)) \crc_q[14]_i_13 (.I0(rec_abort_reg_2), .I1(Q[2]), .I2(Q[4]), .I3(Q[1]), .I4(Q[5]), .O(\crc_q[14]_i_13_n_0 )); LUT6 #( .INIT(64'hFF9FFFFFFFFFFFBF)) \crc_q[14]_i_14 (.I0(Q[0]), .I1(Q[1]), .I2(mr_command_ercrst_q_reg_0), .I3(Q[5]), .I4(Q[3]), .I5(Q[4]), .O(\crc_q[14]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFEFEFEF)) \crc_q[14]_i_15 (.I0(tran_ident_type), .I1(Q[3]), .I2(\sp_control_q_i_reg[1]_2 ), .I3(tran_is_rtr), .I4(reg_q_reg_16), .I5(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .O(\crc_q[14]_i_15_n_0 )); LUT6 #( .INIT(64'h040400F004040000)) \crc_q[14]_i_17 (.I0(bit_err_q_i_2_0), .I1(crc_match), .I2(Q[3]), .I3(Q[0]), .I4(Q[4]), .I5(\crc_q[14]_i_11_0 ), .O(\crc_q[14]_i_17_n_0 )); LUT6 #( .INIT(64'h0000000000008AA0)) \crc_q[14]_i_18 (.I0(\crc_q[14]_i_21_n_0 ), .I1(\sp_control_q_i_reg[1]_2 ), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .I5(Q[2]), .O(\crc_q[14]_i_18_n_0 )); LUT6 #( .INIT(64'h000000008A020000)) \crc_q[14]_i_19 (.I0(\sp_control_q_i_reg[1]_2 ), .I1(Q[3]), .I2(tran_ident_type), .I3(\curr_state_reg[0]_9 ), .I4(Q[1]), .I5(\crc_q[14]_i_22_n_0 ), .O(\crc_q[14]_i_19_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF45440100)) \crc_q[14]_i_1__0 (.I0(\crc_q[14]_i_3_n_0 ), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(tx_frame_no_sof_q_reg_5), .I3(tx_frame_no_sof_q_reg_4), .I4(\crc_q_reg[0] ), .I5(reg_q_reg_5), .O(reg_q_reg_6)); LUT6 #( .INIT(64'hA6950000596A0000)) \crc_q[14]_i_2 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[5]_7 ), .I5(\crc_q_reg[14]_0 [5]), .O(\crc_q_reg[14] [6])); LUT6 #( .INIT(64'hEABAFABAC898D898)) \crc_q[14]_i_21 (.I0(Q[1]), .I1(Q[0]), .I2(\sp_control_q_i_reg[1]_2 ), .I3(reg_q_reg_16), .I4(tran_is_rtr), .I5(Q[3]), .O(\crc_q[14]_i_21_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT3 #( .INIT(8'hEF)) \crc_q[14]_i_22 (.I0(Q[4]), .I1(Q[0]), .I2(Q[2]), .O(\crc_q[14]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT3 #( .INIT(8'hA8)) \crc_q[14]_i_3 (.I0(\crc_q[14]_i_8_n_0 ), .I1(\crc_q[14]_i_9_n_0 ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\crc_q[14]_i_3_n_0 )); LUT4 #( .INIT(16'h2202)) \crc_q[14]_i_4 (.I0(\crc_q[14]_i_9_n_0 ), .I1(\pc_dbg[is_arbitration] ), .I2(\shift_regs_reg[0]_0 ), .I3(\shift_regs_reg[0] ), .O(\FSM_sequential_curr_state_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair217" *) LUT5 #( .INIT(32'h00000004)) \crc_q[14]_i_5 (.I0(tx_frame_no_sof_q_reg_5), .I1(tx_frame_no_sof_q_reg_4), .I2(rec_abort_reg_2), .I3(Q[5]), .I4(\crc_q[14]_i_10_n_0 ), .O(reg_q_reg_5)); LUT6 #( .INIT(64'h4444444477777747)) \crc_q[14]_i_6 (.I0(\curr_state_reg[0]_9 ), .I1(rec_abort_reg_2), .I2(Q[2]), .I3(Q[1]), .I4(\crc_q[14]_i_11_n_0 ), .I5(\crc_q[14]_i_12_n_0 ), .O(err_frm_req_reg_4)); (* SOFT_HLUTNM = "soft_lutpair217" *) LUT5 #( .INIT(32'hFFFFFEFF)) \crc_q[14]_i_7 (.I0(\crc_q[14]_i_10_n_0 ), .I1(Q[5]), .I2(tx_frame_no_sof_q_reg_5), .I3(tx_frame_no_sof_q_reg_4), .I4(rec_abort_reg_2), .O(\curr_state_reg[5]_7 )); LUT6 #( .INIT(64'hFF09FF09FF09FFFF)) \crc_q[14]_i_8 (.I0(Q[4]), .I1(Q[3]), .I2(\ctrl_ctr_q[0]_i_3_n_0 ), .I3(\crc_q[14]_i_13_n_0 ), .I4(rec_ivld_q_reg_0), .I5(\FSM_sequential_curr_state[1]_i_12_n_0 ), .O(\crc_q[14]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00000E00)) \crc_q[14]_i_9 (.I0(\rx_stuff_count_reg[3] ), .I1(\cc_stat[is_bus_off] ), .I2(Q[1]), .I3(\ctrl_ctr_q[8]_i_23_n_0 ), .I4(first_err_delim_q_i_2_n_0), .I5(\crc_q[14]_i_14_n_0 ), .O(\crc_q[14]_i_9_n_0 )); LUT6 #( .INIT(64'hABBBAAAABBBBBBBB)) \crc_q[16]_i_1 (.I0(reg_q_reg_5), .I1(\crc_q[16]_i_3_n_0 ), .I2(\curr_state_reg[1]_3 ), .I3(data_halt_d1_out), .I4(tx_trigger_q), .I5(\FSM_sequential_curr_state_reg[1] ), .O(reg_q_reg_4)); LUT6 #( .INIT(64'hFFFFE0FFE0E0E0E0)) \crc_q[16]_i_3 (.I0(crc_data_rx_wbs), .I1(\crc_q[14]_i_9_n_0 ), .I2(\crc_q[14]_i_8_n_0 ), .I3(tx_frame_no_sof_q_reg_4), .I4(\curr_state_reg[1]_3 ), .I5(\crc_q_reg[20] ), .O(\crc_q[16]_i_3_n_0 )); LUT6 #( .INIT(64'hA6950000596A0000)) \crc_q[3]_i_1__1 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[5]_7 ), .I5(\crc_q_reg[14]_0 [0]), .O(\crc_q_reg[14] [1])); LUT6 #( .INIT(64'hA6950000596A0000)) \crc_q[4]_i_1__1 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[5]_7 ), .I5(\crc_q_reg[14]_0 [1]), .O(\crc_q_reg[14] [2])); LUT6 #( .INIT(64'hA6950000596A0000)) \crc_q[7]_i_1__1 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[5]_7 ), .I5(\crc_q_reg[14]_0 [2]), .O(\crc_q_reg[14] [3])); LUT6 #( .INIT(64'hA6950000596A0000)) \crc_q[8]_i_1__1 (.I0(\crc_q_reg[14]_0 [6]), .I1(\FSM_sequential_curr_state_reg[1] ), .I2(err_frm_req_reg_4), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[5]_7 ), .I5(\crc_q_reg[14]_0 [3]), .O(\crc_q_reg[14] [4])); LUT6 #( .INIT(64'h4744474447444747)) \ctrl_ctr_q[0]_i_1 (.I0(\ctrl_ctr_q_reg[1] [0]), .I1(\curr_state_reg[3]_0 ), .I2(\ctrl_ctr_q_reg[0] ), .I3(\ctrl_ctr_q[0]_i_2_n_0 ), .I4(\ctrl_ctr_q[0]_i_3_n_0 ), .I5(\ctrl_ctr_q[0]_i_4_n_0 ), .O(err_frm_req_reg_2[0])); LUT6 #( .INIT(64'hFF00BB0FFFFFBB0F)) \ctrl_ctr_q[0]_i_10 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[5]), .I2(Q[3]), .I3(Q[0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(Q[1]), .O(\ctrl_ctr_q[0]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair276" *) LUT2 #( .INIT(4'h1)) \ctrl_ctr_q[0]_i_11 (.I0(Q[3]), .I1(Q[0]), .O(\ctrl_ctr_q[0]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFBABABAAA)) \ctrl_ctr_q[0]_i_2 (.I0(\ctrl_ctr_q[0]_i_5_n_0 ), .I1(Q[4]), .I2(\curr_state_reg[1]_0 ), .I3(\ctrl_ctr_q[0]_i_6_n_0 ), .I4(Q[3]), .I5(rec_abort_reg_2), .O(\ctrl_ctr_q[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair271" *) LUT2 #( .INIT(4'hE)) \ctrl_ctr_q[0]_i_3 (.I0(Q[2]), .I1(Q[1]), .O(\ctrl_ctr_q[0]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000011330333)) \ctrl_ctr_q[0]_i_4 (.I0(\ctrl_ctr_q[0]_i_7_n_0 ), .I1(\ctrl_ctr_q[0]_i_6_n_0 ), .I2(\ctrl_ctr_q_reg[0]_0 ), .I3(Q[4]), .I4(Q[0]), .I5(\ctrl_ctr_q[0]_i_9_n_0 ), .O(\ctrl_ctr_q[0]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000DDD50000)) \ctrl_ctr_q[0]_i_5 (.I0(\ctrl_ctr_q[0]_i_10_n_0 ), .I1(\rec_dlc[3]_i_2_n_0 ), .I2(\ctrl_ctr_q_reg[1]_0 ), .I3(\shift_regs[31]_i_7_0 ), .I4(Q[2]), .I5(Q[4]), .O(\ctrl_ctr_q[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair224" *) LUT3 #( .INIT(8'h04)) \ctrl_ctr_q[0]_i_6 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(Q[5]), .I2(\rx_stuff_count_reg[3] ), .O(\ctrl_ctr_q[0]_i_6_n_0 )); LUT6 #( .INIT(64'h0C400C400C400000)) \ctrl_ctr_q[0]_i_7 (.I0(\mr_ctrl_out[mode_rom] ), .I1(Q[3]), .I2(\rx_stuff_count_reg[3] ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[1]_7 [1]), .I5(\curr_state_reg[1]_7 [0]), .O(\ctrl_ctr_q[0]_i_7_n_0 )); LUT6 #( .INIT(64'h0222002000200020)) \ctrl_ctr_q[0]_i_9 (.I0(\ctrl_ctr_q[0]_i_11_n_0 ), .I1(Q[5]), .I2(Q[4]), .I3(\ctrl_ctr_q[0]_i_4_0 ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\mr_ctrl_out[settings_ena] ), .O(\ctrl_ctr_q[0]_i_9_n_0 )); LUT6 #( .INIT(64'hFFF100F100F1FFF1)) \ctrl_ctr_q[1]_i_1 (.I0(\ctrl_ctr_q[1]_i_2_n_0 ), .I1(rec_abort_reg_2), .I2(\ctrl_ctr_q[1]_i_3_n_0 ), .I3(\curr_state_reg[3]_0 ), .I4(\ctrl_ctr_q_reg[1] [1]), .I5(\ctrl_ctr_q_reg[1] [0]), .O(err_frm_req_reg_2[1])); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT4 #( .INIT(16'hEFFF)) \ctrl_ctr_q[1]_i_10 (.I0(Q[4]), .I1(\rx_stuff_count_reg[3] ), .I2(Q[3]), .I3(Q[1]), .O(\ctrl_ctr_q[1]_i_10_n_0 )); LUT6 #( .INIT(64'h000FFFFFDDDDDDDD)) \ctrl_ctr_q[1]_i_12 (.I0(\ctrl_ctr_q[1]_i_4_0 ), .I1(Q[5]), .I2(\curr_state_reg[4]_3 ), .I3(\FSM_sequential_curr_state[1]_i_2__4_0 ), .I4(Q[4]), .I5(Q[3]), .O(\ctrl_ctr_q[1]_i_12_n_0 )); LUT6 #( .INIT(64'hFF0FFFFFFF7FFF0F)) \ctrl_ctr_q[1]_i_13 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(\mr_ctrl_out[settings_pex] ), .I2(Q[1]), .I3(Q[5]), .I4(Q[3]), .I5(Q[4]), .O(\ctrl_ctr_q[1]_i_13_n_0 )); LUT6 #( .INIT(64'hFF00FFF1330033F1)) \ctrl_ctr_q[1]_i_14 (.I0(\cc_stat[is_bus_off] ), .I1(Q[4]), .I2(Q[3]), .I3(Q[0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(mr_command_ercrst_q), .O(\ctrl_ctr_q[1]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair278" *) LUT2 #( .INIT(4'h2)) \ctrl_ctr_q[1]_i_15 (.I0(Q[1]), .I1(Q[4]), .O(\ctrl_ctr_q[1]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF050F350F)) \ctrl_ctr_q[1]_i_17 (.I0(Q[5]), .I1(Q[4]), .I2(Q[3]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(destuff_enable_reg_2), .I5(Q[0]), .O(\ctrl_ctr_q[1]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair224" *) LUT5 #( .INIT(32'h2000AAAA)) \ctrl_ctr_q[1]_i_18 (.I0(Q[0]), .I1(\rx_stuff_count_reg[3] ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[5]), .I4(\ctrl_ctr_q[2]_i_13_n_0 ), .O(\ctrl_ctr_q[1]_i_18_n_0 )); LUT6 #( .INIT(64'h00000000AA8A8888)) \ctrl_ctr_q[1]_i_2 (.I0(\ctrl_ctr_q[1]_i_4_n_0 ), .I1(Q[2]), .I2(\ctrl_ctr_q[1]_i_5_n_0 ), .I3(\ctrl_ctr_q[1]_i_6_n_0 ), .I4(\ctrl_ctr_q[1]_i_7_n_0 ), .I5(\ctrl_ctr_q[1]_i_8_n_0 ), .O(\ctrl_ctr_q[1]_i_2_n_0 )); LUT6 #( .INIT(64'hBFBBBFBFAAAAAAAA)) \ctrl_ctr_q[1]_i_3 (.I0(\ctrl_ctr_q_reg[0] ), .I1(\ctrl_ctr_q[1]_i_9_n_0 ), .I2(\ctrl_ctr_q[1]_i_10_n_0 ), .I3(\ctrl_ctr_q_reg[1]_0 ), .I4(\ctrl_ctr_q_reg[1]_1 ), .I5(ack_err_flag_i_5_n_0), .O(\ctrl_ctr_q[1]_i_3_n_0 )); LUT6 #( .INIT(64'hABBBBBBBABBBAAAA)) \ctrl_ctr_q[1]_i_4 (.I0(\ctrl_ctr_q[0]_i_3_n_0 ), .I1(\ctrl_ctr_q_reg[2] ), .I2(reg_q_i_2__5_n_0), .I3(destuff_enable_reg_2), .I4(Q[0]), .I5(\ctrl_ctr_q[1]_i_12_n_0 ), .O(\ctrl_ctr_q[1]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT3 #( .INIT(8'h40)) \ctrl_ctr_q[1]_i_5 (.I0(Q[1]), .I1(Q[4]), .I2(Q[0]), .O(\ctrl_ctr_q[1]_i_5_n_0 )); LUT6 #( .INIT(64'hEFFFAA00EFFFAAFF)) \ctrl_ctr_q[1]_i_6 (.I0(\cc_stat[is_bus_off] ), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(\mr_ctrl_out[mode_rom] ), .I3(Q[3]), .I4(\rx_stuff_count_reg[3] ), .I5(\ctrl_ctr_q_reg[4]_0 ), .O(\ctrl_ctr_q[1]_i_6_n_0 )); LUT6 #( .INIT(64'hFBFF0000FBFFFBFF)) \ctrl_ctr_q[1]_i_7 (.I0(Q[4]), .I1(Q[0]), .I2(Q[5]), .I3(\ctrl_ctr_q[3]_i_3_0 ), .I4(\ctrl_ctr_q[1]_i_13_n_0 ), .I5(\ctrl_ctr_q[1]_i_14_n_0 ), .O(\ctrl_ctr_q[1]_i_7_n_0 )); LUT6 #( .INIT(64'h3000300030E03000)) \ctrl_ctr_q[1]_i_8 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(Q[0]), .I2(\ctrl_ctr_q[1]_i_15_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(\rx_stuff_count_reg[3] ), .O(\ctrl_ctr_q[1]_i_8_n_0 )); LUT6 #( .INIT(64'h00000000FF4CFF40)) \ctrl_ctr_q[1]_i_9 (.I0(\ctrl_ctr_q[1]_i_3_0 ), .I1(Q[4]), .I2(Q[1]), .I3(\ctrl_ctr_q[1]_i_17_n_0 ), .I4(\ctrl_ctr_q[1]_i_3_1 ), .I5(\ctrl_ctr_q[1]_i_18_n_0 ), .O(\ctrl_ctr_q[1]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT3 #( .INIT(8'h04)) \ctrl_ctr_q[2]_i_11 (.I0(Q[2]), .I1(Q[4]), .I2(Q[1]), .O(\ctrl_ctr_q[2]_i_11_n_0 )); LUT6 #( .INIT(64'hD0C000C000C000C0)) \ctrl_ctr_q[2]_i_12 (.I0(\ctrl_ctr_q[2]_i_6_0 ), .I1(\ctrl_ctr_q[0]_i_6_n_0 ), .I2(Q[1]), .I3(Q[4]), .I4(Q[2]), .I5(Q[3]), .O(\ctrl_ctr_q[2]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT5 #( .INIT(32'h0CFFBBFF)) \ctrl_ctr_q[2]_i_13 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[3]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[4]), .I4(Q[1]), .O(\ctrl_ctr_q[2]_i_13_n_0 )); LUT6 #( .INIT(64'h2022303320220000)) \ctrl_ctr_q[2]_i_3 (.I0(\ctrl_ctr_q[2]_i_4_n_0 ), .I1(rec_abort_reg_2), .I2(\ctrl_ctr_q[0]_i_3_n_0 ), .I3(\ctrl_ctr_q_reg[2] ), .I4(Q[0]), .I5(\ctrl_ctr_q[2]_i_6_n_0 ), .O(err_frm_req_reg_3)); LUT6 #( .INIT(64'hA2A2F3F3A2A2C0F3)) \ctrl_ctr_q[2]_i_4 (.I0(\ctrl_ctr_q[2]_i_7_n_0 ), .I1(Q[1]), .I2(\ctrl_ctr_q[2]_i_3_1 ), .I3(Q[4]), .I4(Q[2]), .I5(\ctrl_ctr_q[2]_i_3_2 ), .O(\ctrl_ctr_q[2]_i_4_n_0 )); LUT6 #( .INIT(64'h0007070707070707)) \ctrl_ctr_q[2]_i_6 (.I0(\ctrl_ctr_q[2]_i_3_0 ), .I1(\ctrl_ctr_q[2]_i_11_n_0 ), .I2(\ctrl_ctr_q[2]_i_12_n_0 ), .I3(Q[5]), .I4(Q[2]), .I5(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\ctrl_ctr_q[2]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000AAFB0000)) \ctrl_ctr_q[2]_i_7 (.I0(\ctrl_ctr_q[1]_i_10_n_0 ), .I1(\ctrl_ctr_q[2]_i_4_0 ), .I2(\shift_regs[31]_i_7_0 ), .I3(\ctrl_ctr_q_reg[1]_0 ), .I4(\ctrl_ctr_q[2]_i_13_n_0 ), .I5(\ctrl_ctr_q[0]_i_6_n_0 ), .O(\ctrl_ctr_q[2]_i_7_n_0 )); LUT6 #( .INIT(64'hB8BBB888B8BBB8BB)) \ctrl_ctr_q[3]_i_1 (.I0(\ctrl_ctr_q_reg[3] ), .I1(\curr_state_reg[3]_0 ), .I2(\mr_ctrl_out[mode_rom] ), .I3(rec_abort_reg_2), .I4(\ctrl_ctr_q[3]_i_3_n_0 ), .I5(\ctrl_ctr_q[3]_i_4_n_0 ), .O(err_frm_req_reg_2[2])); LUT6 #( .INIT(64'h000008000C000800)) \ctrl_ctr_q[3]_i_10 (.I0(\ctrl_ctr_q_reg[4]_0 ), .I1(\rec_dlc[3]_i_2_n_0 ), .I2(Q[4]), .I3(Q[0]), .I4(\ctrl_ctr_q_reg[1]_0 ), .I5(\ctrl_ctr_q[3]_i_4_0 ), .O(\ctrl_ctr_q[3]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT3 #( .INIT(8'h2A)) \ctrl_ctr_q[3]_i_12 (.I0(Q[3]), .I1(\mr_ctrl_out[settings_pex] ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\ctrl_ctr_q[3]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'h2)) \ctrl_ctr_q[3]_i_13 (.I0(Q[0]), .I1(Q[4]), .O(\ctrl_ctr_q[3]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT4 #( .INIT(16'hEFFF)) \ctrl_ctr_q[3]_i_15 (.I0(Q[4]), .I1(\mr_ctrl_out[mode_fde] ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(\mr_ctrl_out[settings_pex] ), .O(\ctrl_ctr_q[3]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair265" *) LUT2 #( .INIT(4'h8)) \ctrl_ctr_q[3]_i_16 (.I0(Q[3]), .I1(Q[0]), .O(\ctrl_ctr_q[3]_i_16_n_0 )); LUT6 #( .INIT(64'h7FFF7F3F0F0F0F0F)) \ctrl_ctr_q[3]_i_17 (.I0(mr_command_ercrst_q), .I1(Q[3]), .I2(Q[4]), .I3(Q[0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(Q[1]), .O(\ctrl_ctr_q[3]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT5 #( .INIT(32'h07000500)) \ctrl_ctr_q[3]_i_18 (.I0(Q[1]), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(Q[0]), .I3(Q[4]), .I4(Q[3]), .O(\ctrl_ctr_q[3]_i_18_n_0 )); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT5 #( .INIT(32'h2AFFFFFF)) \ctrl_ctr_q[3]_i_21 (.I0(Q[1]), .I1(mr_command_ercrst_q), .I2(Q[3]), .I3(Q[0]), .I4(Q[4]), .O(\ctrl_ctr_q[3]_i_21_n_0 )); LUT6 #( .INIT(64'hAAAA88A8AAAAAAAA)) \ctrl_ctr_q[3]_i_3 (.I0(\ctrl_ctr_q[3]_i_5_n_0 ), .I1(\ctrl_ctr_q[3]_i_6_n_0 ), .I2(\rec_ident[17]_i_2_n_0 ), .I3(\ctrl_ctr_q[3]_i_7_n_0 ), .I4(\ctrl_ctr_q[3]_i_8_n_0 ), .I5(\ctrl_ctr_q[3]_i_9_n_0 ), .O(\ctrl_ctr_q[3]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFF5551FFFFFFFF)) \ctrl_ctr_q[3]_i_4 (.I0(\ctrl_ctr_q[3]_i_10_n_0 ), .I1(Q[3]), .I2(rec_valid_i_4_n_0), .I3(\ctrl_ctr_q_reg[3]_0 ), .I4(Q[5]), .I5(Q[2]), .O(\ctrl_ctr_q[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair216" *) LUT2 #( .INIT(4'h1)) \ctrl_ctr_q[3]_i_5 (.I0(Q[2]), .I1(Q[5]), .O(\ctrl_ctr_q[3]_i_5_n_0 )); LUT6 #( .INIT(64'h4444444440FF4040)) \ctrl_ctr_q[3]_i_6 (.I0(\ctrl_ctr_q[3]_i_12_n_0 ), .I1(\ctrl_ctr_q[3]_i_13_n_0 ), .I2(\ctrl_ctr_q[3]_i_3_0 ), .I3(\ctrl_ctr_q[3]_i_15_n_0 ), .I4(\ctrl_ctr_q[3]_i_16_n_0 ), .I5(Q[1]), .O(\ctrl_ctr_q[3]_i_6_n_0 )); LUT6 #( .INIT(64'hFD0DFD0DFD0DFDFD)) \ctrl_ctr_q[3]_i_7 (.I0(\mr_ctrl_out[settings_ena] ), .I1(Q[0]), .I2(Q[1]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state_reg[1]_7 [0]), .I5(\curr_state_reg[1]_7 [1]), .O(\ctrl_ctr_q[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT5 #( .INIT(32'h0000FF02)) \ctrl_ctr_q[3]_i_8 (.I0(\ctrl_ctr_q_reg[4]_0 ), .I1(\rx_stuff_count_reg[3] ), .I2(Q[3]), .I3(Q[1]), .I4(\ctrl_ctr_q[3]_i_17_n_0 ), .O(\ctrl_ctr_q[3]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFF7770FFFFFFFF)) \ctrl_ctr_q[3]_i_9 (.I0(\ctrl_ctr_q[3]_i_18_n_0 ), .I1(\FSM_sequential_curr_state[1]_i_2__4_0 ), .I2(\ctrl_ctr_q[3]_i_3_1 ), .I3(\ctrl_ctr_q[3]_i_21_n_0 ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(Q[3]), .O(\ctrl_ctr_q[3]_i_9_n_0 )); LUT5 #( .INIT(32'h8888888B)) \ctrl_ctr_q[4]_i_1 (.I0(\ctrl_ctr_q_reg[4] ), .I1(\curr_state_reg[3]_0 ), .I2(rec_abort_reg_2), .I3(\ctrl_ctr_q[4]_i_3_n_0 ), .I4(\ctrl_ctr_q[4]_i_4_n_0 ), .O(err_frm_req_reg_2[3])); LUT6 #( .INIT(64'h0F0F0F0FF0FFF0CD)) \ctrl_ctr_q[4]_i_3 (.I0(\mr_ctrl_out[settings_nisofd] ), .I1(\rx_stuff_count_reg[3] ), .I2(Q[0]), .I3(Q[1]), .I4(\ctrl_ctr_q_reg[4]_0 ), .I5(Q[3]), .O(\ctrl_ctr_q[4]_i_3_n_0 )); LUT6 #( .INIT(64'hDFDBDFFBFFDBFFFB)) \ctrl_ctr_q[4]_i_4 (.I0(Q[1]), .I1(Q[4]), .I2(Q[2]), .I3(Q[3]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\ctrl_ctr_q_reg[4]_1 ), .O(\ctrl_ctr_q[4]_i_4_n_0 )); LUT6 #( .INIT(64'hDDDDDDDDD5D555D5)) \ctrl_ctr_q[8]_i_1 (.I0(\curr_state_reg[3]_0 ), .I1(\txtb_hw_cmd_q_reg[lock]_4 ), .I2(Q[5]), .I3(\curr_state_reg[2]_3 ), .I4(\rx_stuff_count_reg[3] ), .I5(\ctrl_ctr_q[8]_i_5_n_0 ), .O(\curr_state_reg[5]_1 )); LUT6 #( .INIT(64'h3230323332303230)) \ctrl_ctr_q[8]_i_11 (.I0(\ctrl_ctr_q[8]_i_19_n_0 ), .I1(\ctrl_ctr_q[8]_i_20_n_0 ), .I2(Q[5]), .I3(Q[4]), .I4(\ctrl_ctr_q[8]_i_21_n_0 ), .I5(\ctrl_ctr_q[8]_i_22_n_0 ), .O(\ctrl_ctr_q[8]_i_11_n_0 )); LUT6 #( .INIT(64'hDDDDDDDDDDDDDDDF)) \ctrl_ctr_q[8]_i_12 (.I0(\rec_dlc_reg[0] ), .I1(rec_abort_reg_2), .I2(\err_capt_err_pos_q[2]_i_2_n_0 ), .I3(Q[5]), .I4(Q[4]), .I5(rec_valid_i_4_n_0), .O(\ctrl_ctr_q[8]_i_12_n_0 )); LUT6 #( .INIT(64'h575757FFFFFFFFFF)) \ctrl_ctr_q[8]_i_13 (.I0(sync_edge), .I1(\mr_ctrl_out[mode_fde] ), .I2(\mr_ctrl_out[settings_pex] ), .I3(Q[3]), .I4(\ctrl_ctr_q[8]_i_23_n_0 ), .I5(\ctrl_ctr_q[8]_i_24_n_0 ), .O(\ctrl_ctr_q[8]_i_13_n_0 )); LUT6 #( .INIT(64'h00000000300089D8)) \ctrl_ctr_q[8]_i_14 (.I0(Q[3]), .I1(Q[4]), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(Q[5]), .O(\ctrl_ctr_q[8]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair215" *) LUT5 #( .INIT(32'hB8FFB800)) \ctrl_ctr_q[8]_i_19 (.I0(\ctrl_ctr_q[8]_i_28_n_0 ), .I1(Q[2]), .I2(\ctrl_ctr_q[8]_i_29_n_0 ), .I3(Q[3]), .I4(\ctrl_ctr_q[8]_i_30_n_0 ), .O(\ctrl_ctr_q[8]_i_19_n_0 )); (* SOFT_HLUTNM = "soft_lutpair216" *) LUT5 #( .INIT(32'hFFFFAABA)) \ctrl_ctr_q[8]_i_20 (.I0(\ctrl_ctr_q[8]_i_31_n_0 ), .I1(Q[2]), .I2(Q[5]), .I3(\rx_stuff_count_reg[3] ), .I4(rec_abort_reg_2), .O(\ctrl_ctr_q[8]_i_20_n_0 )); LUT6 #( .INIT(64'hCFCCCDCDCCCCCDCD)) \ctrl_ctr_q[8]_i_21 (.I0(\ctrl_ctr_q[8]_i_11_0 ), .I1(\ctrl_ctr_q[8]_i_33_n_0 ), .I2(Q[3]), .I3(\ctrl_ctr_q[8]_i_11_1 ), .I4(Q[2]), .I5(Q[1]), .O(\ctrl_ctr_q[8]_i_21_n_0 )); LUT6 #( .INIT(64'hB0FFB0FFB3FFB0FF)) \ctrl_ctr_q[8]_i_22 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[1]), .I2(Q[0]), .I3(\curr_state_reg[3]_5 ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(destuff_enable_reg_2), .O(\ctrl_ctr_q[8]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair272" *) LUT2 #( .INIT(4'h2)) \ctrl_ctr_q[8]_i_23 (.I0(Q[0]), .I1(Q[2]), .O(\ctrl_ctr_q[8]_i_23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair275" *) LUT2 #( .INIT(4'h1)) \ctrl_ctr_q[8]_i_24 (.I0(Q[1]), .I1(Q[5]), .O(\ctrl_ctr_q[8]_i_24_n_0 )); LUT6 #( .INIT(64'h3FCC0FFC01C001C0)) \ctrl_ctr_q[8]_i_28 (.I0(\curr_state[5]_i_4_0 ), .I1(Q[0]), .I2(Q[1]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(rx_data_nbs_prev_reg_0), .I5(\rx_stuff_count_reg[3] ), .O(\ctrl_ctr_q[8]_i_28_n_0 )); LUT6 #( .INIT(64'h0FFFEECC0F00AACC)) \ctrl_ctr_q[8]_i_29 (.I0(\cc_stat[is_bus_off] ), .I1(\rx_stuff_count_reg[3] ), .I2(mr_command_ercrst_q), .I3(Q[0]), .I4(Q[1]), .I5(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\ctrl_ctr_q[8]_i_29_n_0 )); LUT6 #( .INIT(64'hBBBBBBBB8BBBBB88)) \ctrl_ctr_q[8]_i_3 (.I0(\ctrl_ctr_q[8]_i_11_n_0 ), .I1(\ctrl_ctr_q[8]_i_12_n_0 ), .I2(\curr_state_reg[2]_3 ), .I3(Q[3]), .I4(Q[4]), .I5(\ctrl_ctr_q[8]_i_13_n_0 ), .O(\curr_state_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT4 #( .INIT(16'h5EFE)) \ctrl_ctr_q[8]_i_30 (.I0(Q[1]), .I1(\rx_stuff_count_reg[3] ), .I2(Q[2]), .I3(Q[0]), .O(\ctrl_ctr_q[8]_i_30_n_0 )); LUT6 #( .INIT(64'h57DF541000000000)) \ctrl_ctr_q[8]_i_31 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(Q[5]), .O(\ctrl_ctr_q[8]_i_31_n_0 )); LUT6 #( .INIT(64'h00000000F4303030)) \ctrl_ctr_q[8]_i_33 (.I0(\mr_ctrl_out[mode_fde] ), .I1(Q[0]), .I2(Q[1]), .I3(\mr_ctrl_out[settings_pex] ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(rec_valid_i_5_n_0), .O(\ctrl_ctr_q[8]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair272" *) LUT2 #( .INIT(4'h2)) \ctrl_ctr_q[8]_i_4 (.I0(Q[2]), .I1(Q[0]), .O(\curr_state_reg[2]_3 )); LUT6 #( .INIT(64'hFFFFFFFFC5004500)) \ctrl_ctr_q[8]_i_5 (.I0(Q[0]), .I1(Q[3]), .I2(Q[2]), .I3(Q[4]), .I4(\rx_stuff_count_reg[3] ), .I5(\ctrl_ctr_q[8]_i_14_n_0 ), .O(\ctrl_ctr_q[8]_i_5_n_0 )); LUT6 #( .INIT(64'h0020000000000000)) \ctrl_ctr_q[8]_i_9 (.I0(Q[0]), .I1(rec_abort_reg_2), .I2(Q[2]), .I3(Q[4]), .I4(\rec_dlc[3]_i_2_n_0 ), .I5(\ctrl_ctr_q_reg[1]_0 ), .O(\curr_state_reg[0]_7 )); LUT6 #( .INIT(64'hEEF0EE00EEF0EEF0)) \curr_state[0]_i_1 (.I0(\mr_ctrl_out[mode_rom] ), .I1(\curr_state_reg[0]_9 ), .I2(\curr_state[0]_i_3_n_0 ), .I3(rec_abort_reg_2), .I4(\curr_state[0]_i_4_n_0 ), .I5(\curr_state[0]_i_5_n_0 ), .O(\curr_state[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT4 #( .INIT(16'h4000)) \curr_state[0]_i_11 (.I0(Q[0]), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(Q[1]), .I3(tran_frame_valid), .O(\curr_state[0]_i_11_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF0004444)) \curr_state[0]_i_3 (.I0(\curr_state[0]_i_6_n_0 ), .I1(\curr_state[0]_i_7_n_0 ), .I2(\curr_state[0]_i_8_n_0 ), .I3(\curr_state[0]_i_9_n_0 ), .I4(\curr_state[4]_i_3_n_0 ), .I5(Q[5]), .O(\curr_state[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair279" *) LUT2 #( .INIT(4'h6)) \curr_state[0]_i_4 (.I0(Q[1]), .I1(Q[0]), .O(\curr_state[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair280" *) LUT2 #( .INIT(4'h2)) \curr_state[0]_i_5 (.I0(Q[5]), .I1(Q[2]), .O(\curr_state[0]_i_5_n_0 )); LUT6 #( .INIT(64'h4440444045454544)) \curr_state[0]_i_6 (.I0(Q[3]), .I1(Q[0]), .I2(Q[2]), .I3(\ctrl_ctr_q_reg[4]_0 ), .I4(\mr_ctrl_out[settings_nisofd] ), .I5(Q[1]), .O(\curr_state[0]_i_6_n_0 )); LUT6 #( .INIT(64'h7DFF7DFF7D557D5F)) \curr_state[0]_i_7 (.I0(Q[3]), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(\curr_state[0]_i_3_0 ), .I5(\curr_state[0]_i_11_n_0 ), .O(\curr_state[0]_i_7_n_0 )); LUT6 #( .INIT(64'h7F7FFFFF3F33FFFF)) \curr_state[0]_i_8 (.I0(\curr_state[0]_i_3_1 ), .I1(Q[3]), .I2(Q[2]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(Q[0]), .I5(Q[1]), .O(\curr_state[0]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00F200FF)) \curr_state[0]_i_9 (.I0(\cc_stat[is_bus_off] ), .I1(Q[2]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[0]), .I4(Q[1]), .I5(Q[3]), .O(\curr_state[0]_i_9_n_0 )); LUT6 #( .INIT(64'h45FF450045FF45FF)) \curr_state[1]_i_1 (.I0(\mr_ctrl_out[mode_rom] ), .I1(\curr_state_reg[1]_7 [1]), .I2(\curr_state_reg[1]_7 [0]), .I3(rec_abort_reg_2), .I4(\curr_state[1]_i_2_n_0 ), .I5(\curr_state[1]_i_3_n_0 ), .O(\curr_state[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT5 #( .INIT(32'h20102050)) \curr_state[1]_i_2 (.I0(Q[0]), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(Q[5]), .I3(Q[2]), .I4(Q[1]), .O(\curr_state[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFEFEFEAEAEAEFEAE)) \curr_state[1]_i_3 (.I0(Q[5]), .I1(\curr_state[1]_i_4_n_0 ), .I2(\curr_state[4]_i_3_n_0 ), .I3(\curr_state[1]_i_5_n_0 ), .I4(Q[3]), .I5(\curr_state[1]_i_6_n_0 ), .O(\curr_state[1]_i_3_n_0 )); LUT6 #( .INIT(64'hBB88888BBB888888)) \curr_state[1]_i_4 (.I0(\curr_state[1]_i_7_n_0 ), .I1(Q[3]), .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), .I5(\shift_regs[31]_i_7_0 ), .O(\curr_state[1]_i_4_n_0 )); LUT6 #( .INIT(64'h9999DDDD9999DDD9)) \curr_state[1]_i_5 (.I0(Q[0]), .I1(Q[1]), .I2(\curr_state_reg[1]_7 [1]), .I3(\curr_state_reg[1]_7 [0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(Q[2]), .O(\curr_state[1]_i_5_n_0 )); LUT6 #( .INIT(64'hEE0000F0FF00F0FF)) \curr_state[1]_i_6 (.I0(\ctrl_ctr_q_reg[1]_0 ), .I1(\shift_regs[31]_i_7_0 ), .I2(destuff_enable_reg_2), .I3(Q[0]), .I4(Q[1]), .I5(Q[2]), .O(\curr_state[1]_i_6_n_0 )); LUT6 #( .INIT(64'h55FF005544445550)) \curr_state[1]_i_7 (.I0(Q[2]), .I1(\curr_state[1]_i_4_0 ), .I2(\mr_ctrl_out[mode_rom] ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(Q[0]), .I5(Q[1]), .O(\curr_state[1]_i_7_n_0 )); LUT5 #( .INIT(32'h70707077)) \curr_state[2]_i_1 (.I0(\mr_ctrl_out[mode_rom] ), .I1(rec_abort_reg_2), .I2(\curr_state[2]_i_2_n_0 ), .I3(Q[5]), .I4(\curr_state_reg[2]_i_3_n_0 ), .O(\curr_state[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT5 #( .INIT(32'hAEEAAEAA)) \curr_state[2]_i_2 (.I0(rec_abort_reg_2), .I1(Q[5]), .I2(Q[2]), .I3(Q[0]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\curr_state[2]_i_2_n_0 )); LUT6 #( .INIT(64'hF00203F3F00F0F0F)) \curr_state[2]_i_4 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(\curr_state[2]_i_6_n_0 ), .I2(Q[2]), .I3(Q[0]), .I4(Q[1]), .I5(Q[3]), .O(\curr_state[2]_i_4_n_0 )); LUT6 #( .INIT(64'h00000000FFFFC037)) \curr_state[2]_i_5 (.I0(rec_ivld_q_reg_0), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .I4(Q[3]), .I5(\curr_state[2]_i_7_n_0 ), .O(\curr_state[2]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000011100000)) \curr_state[2]_i_6 (.I0(\rx_stuff_count_reg[3] ), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(\curr_state_reg[1]_7 [1]), .I3(\curr_state_reg[1]_7 [0]), .I4(Q[0]), .I5(Q[1]), .O(\curr_state[2]_i_6_n_0 )); LUT6 #( .INIT(64'hAFFBAAAAAAAAAAAA)) \curr_state[2]_i_7 (.I0(\curr_state[3]_i_7_n_0 ), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(Q[3]), .O(\curr_state[2]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair222" *) LUT5 #( .INIT(32'h44CC44CF)) \curr_state[3]_i_1 (.I0(\mr_ctrl_out[mode_rom] ), .I1(\curr_state[5]_i_9_n_0 ), .I2(\curr_state_reg[3]_i_2_n_0 ), .I3(rec_abort_reg_2), .I4(Q[5]), .O(\curr_state[3]_i_1_n_0 )); LUT5 #( .INIT(32'h43773777)) \curr_state[3]_i_3 (.I0(\curr_state[4]_i_4_n_0 ), .I1(Q[3]), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .O(\curr_state[3]_i_3_n_0 )); LUT6 #( .INIT(64'h5515155155111511)) \curr_state[3]_i_4 (.I0(\curr_state[3]_i_5_n_0 ), .I1(Q[3]), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(destuff_enable_reg_2), .O(\curr_state[3]_i_4_n_0 )); LUT6 #( .INIT(64'hFF40FF40FFFFFF40)) \curr_state[3]_i_5 (.I0(Q[3]), .I1(Q[2]), .I2(\curr_state[3]_i_6_n_0 ), .I3(\curr_state[3]_i_7_n_0 ), .I4(\cc_stat[is_bus_off] ), .I5(\FSM_sequential_curr_state[1]_i_12_n_0 ), .O(\curr_state[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT3 #( .INIT(8'h8A)) \curr_state[3]_i_6 (.I0(Q[1]), .I1(Q[0]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\curr_state[3]_i_6_n_0 )); LUT6 #( .INIT(64'h7FFF000000000000)) \curr_state[3]_i_7 (.I0(\mr_ctrl_out[mode_fde] ), .I1(\mr_ctrl_out[settings_pex] ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[0]), .I4(rec_ivld_q_i_7_n_0), .I5(Q[3]), .O(\curr_state[3]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF77740000)) \curr_state[4]_i_1 (.I0(\curr_state[4]_i_2_n_0 ), .I1(\curr_state[4]_i_3_n_0 ), .I2(\curr_state[4]_i_4_n_0 ), .I3(\curr_state[4]_i_5_n_0 ), .I4(\curr_state_reg[4]_4 ), .I5(\curr_state[4]_i_7_n_0 ), .O(\curr_state[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT3 #( .INIT(8'hFE)) \curr_state[4]_i_11 (.I0(Q[1]), .I1(Q[0]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\curr_state[4]_i_11_n_0 )); LUT6 #( .INIT(64'h7FFF7FFF7FFF7EFF)) \curr_state[4]_i_2 (.I0(Q[0]), .I1(Q[2]), .I2(Q[3]), .I3(Q[1]), .I4(\curr_state_reg[1]_7 [1]), .I5(\curr_state_reg[1]_7 [0]), .O(\curr_state[4]_i_2_n_0 )); LUT3 #( .INIT(8'h47)) \curr_state[4]_i_3 (.I0(Q[2]), .I1(Q[5]), .I2(Q[4]), .O(\curr_state[4]_i_3_n_0 )); LUT6 #( .INIT(64'h000000D500000000)) \curr_state[4]_i_4 (.I0(\curr_state[4]_i_8_n_0 ), .I1(\curr_state_reg[4]_2 ), .I2(\curr_state_reg[4]_3 ), .I3(Q[2]), .I4(\curr_state_reg[1]_0 ), .I5(\curr_state[4]_i_11_n_0 ), .O(\curr_state[4]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair219" *) LUT4 #( .INIT(16'h28FF)) \curr_state[4]_i_5 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(\curr_state[4]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair222" *) LUT3 #( .INIT(8'h2A)) \curr_state[4]_i_7 (.I0(\curr_state[5]_i_9_n_0 ), .I1(\mr_ctrl_out[mode_rom] ), .I2(rec_abort_reg_2), .O(\curr_state[4]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT4 #( .INIT(16'h4440)) \curr_state[4]_i_8 (.I0(Q[1]), .I1(Q[0]), .I2(\curr_state_reg[1]_7 [0]), .I3(\curr_state_reg[1]_7 [1]), .O(\curr_state[4]_i_8_n_0 )); LUT6 #( .INIT(64'hABABABABABABABAA)) \curr_state[5]_i_1 (.I0(rec_abort_reg_2), .I1(\rec_dlc_reg[0] ), .I2(\curr_state[5]_i_3_n_0 ), .I3(\curr_state[5]_i_4_n_0 ), .I4(\curr_state[5]_i_5_n_0 ), .I5(\curr_state[5]_i_6_n_0 ), .O(curr_state)); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT4 #( .INIT(16'hA888)) \curr_state[5]_i_10 (.I0(\curr_state[5]_i_20_n_0 ), .I1(\curr_state[5]_i_21_n_0 ), .I2(Q[4]), .I3(\rx_stuff_count_reg[3] ), .O(\curr_state[5]_i_10_n_0 )); LUT6 #( .INIT(64'h00000000FFFFFFB8)) \curr_state[5]_i_11 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[5]), .I2(\curr_state[5]_i_5_0 ), .I3(Q[4]), .I4(Q[2]), .I5(\curr_state_reg[5]_i_23_n_0 ), .O(\curr_state[5]_i_11_n_0 )); LUT6 #( .INIT(64'hCC000000FF7F3033)) \curr_state[5]_i_12 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(Q[2]), .I2(Q[5]), .I3(Q[0]), .I4(\rx_stuff_count_reg[3] ), .I5(Q[3]), .O(\curr_state[5]_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair214" *) LUT4 #( .INIT(16'h2022)) \curr_state[5]_i_13 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\rx_stuff_count_reg[3] ), .O(\curr_state[5]_i_13_n_0 )); LUT6 #( .INIT(64'hC000CF0FCF00CF0A)) \curr_state[5]_i_14 (.I0(\cc_stat[is_receiver] ), .I1(mr_command_ercrst_q), .I2(Q[0]), .I3(Q[1]), .I4(\rx_stuff_count_reg[3] ), .I5(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\curr_state[5]_i_14_n_0 )); LUT6 #( .INIT(64'hFFFFE000FFFFFFFF)) \curr_state[5]_i_15 (.I0(\curr_state_reg[1]_7 [1]), .I1(\curr_state_reg[1]_7 [0]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(\rx_stuff_count_reg[3] ), .I4(Q[1]), .I5(Q[0]), .O(\curr_state[5]_i_15_n_0 )); (* SOFT_HLUTNM = "soft_lutpair221" *) LUT5 #( .INIT(32'h7F037F00)) \curr_state[5]_i_16 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(Q[1]), .I2(Q[0]), .I3(\rx_stuff_count_reg[3] ), .I4(\curr_state[5]_i_4_0 ), .O(\curr_state[5]_i_16_n_0 )); LUT6 #( .INIT(64'hF000050004045000)) \curr_state[5]_i_18 (.I0(Q[3]), .I1(\curr_state[5]_i_5_0 ), .I2(Q[0]), .I3(\rx_stuff_count_reg[3] ), .I4(Q[1]), .I5(Q[2]), .O(\curr_state[5]_i_18_n_0 )); LUT6 #( .INIT(64'h00000000FFFF8880)) \curr_state[5]_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(\curr_state[5]_i_7_n_0 ), .I3(\curr_state_reg[1]_4 ), .I4(Q[5]), .I5(\curr_state[5]_i_9_n_0 ), .O(\curr_state[5]_i_2_n_0 )); LUT6 #( .INIT(64'hAAFFD8FFFFFFD8FF)) \curr_state[5]_i_20 (.I0(Q[0]), .I1(\curr_state[5]_i_10_0 ), .I2(\rx_stuff_count_reg[3] ), .I3(Q[3]), .I4(Q[2]), .I5(\FSM_sequential_curr_state[1]_i_8_0 ), .O(\curr_state[5]_i_20_n_0 )); LUT6 #( .INIT(64'hF0F04F4FFFFF404F)) \curr_state[5]_i_21 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(\rx_stuff_count_reg[3] ), .I2(Q[5]), .I3(\mr_ctrl_out[settings_ena] ), .I4(Q[2]), .I5(Q[0]), .O(\curr_state[5]_i_21_n_0 )); LUT5 #( .INIT(32'h0CBC3C7C)) \curr_state[5]_i_26 (.I0(rx_data_nbs_prev_reg_0), .I1(Q[2]), .I2(Q[3]), .I3(\rx_stuff_count_reg[3] ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\curr_state[5]_i_26_n_0 )); LUT6 #( .INIT(64'h00000000E4550055)) \curr_state[5]_i_27 (.I0(Q[2]), .I1(mr_command_ercrst_q), .I2(\err_capt_err_type_q_reg[1] ), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(\curr_state[5]_i_27_n_0 )); LUT6 #( .INIT(64'h00000000E2E2E200)) \curr_state[5]_i_3 (.I0(\curr_state[5]_i_10_n_0 ), .I1(Q[1]), .I2(\curr_state[5]_i_11_n_0 ), .I3(Q[4]), .I4(\curr_state[5]_i_12_n_0 ), .I5(\curr_state[5]_i_13_n_0 ), .O(\curr_state[5]_i_3_n_0 )); LUT6 #( .INIT(64'h0000101111111011)) \curr_state[5]_i_4 (.I0(first_err_delim_q_i_2_n_0), .I1(Q[5]), .I2(\curr_state[5]_i_14_n_0 ), .I3(\curr_state[5]_i_15_n_0 ), .I4(Q[2]), .I5(\curr_state[5]_i_16_n_0 ), .O(\curr_state[5]_i_4_n_0 )); LUT6 #( .INIT(64'h0045000000455555)) \curr_state[5]_i_5 (.I0(Q[5]), .I1(ack_err_flag_i_3_n_0), .I2(\curr_state_reg[0]_10 ), .I3(Q[3]), .I4(Q[4]), .I5(\curr_state[5]_i_18_n_0 ), .O(\curr_state[5]_i_5_n_0 )); LUT6 #( .INIT(64'h22FF00000AFA0000)) \curr_state[5]_i_6 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(Q[0]), .I2(Q[1]), .I3(\rx_stuff_count_reg[3] ), .I4(Q[5]), .I5(Q[2]), .O(\curr_state[5]_i_6_n_0 )); LUT6 #( .INIT(64'h0000000000002075)) \curr_state[5]_i_7 (.I0(Q[0]), .I1(\cc_stat[is_bus_off] ), .I2(\rx_stuff_count_reg[3] ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\ctrl_ctr_q[0]_i_3_n_0 ), .I5(\mr_ctrl_out[mode_rom] ), .O(\curr_state[5]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT3 #( .INIT(8'h80)) \curr_state[5]_i_8 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .O(\curr_state_reg[1]_4 )); LUT6 #( .INIT(64'hAAEEAAAAEAAAAAAA)) \curr_state[5]_i_9 (.I0(rec_abort_reg_2), .I1(Q[5]), .I2(Q[1]), .I3(\curr_state[4]_i_3_n_0 ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(Q[0]), .O(\curr_state[5]_i_9_n_0 )); FDCE #( .INIT(1'b0)) \curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(curr_state), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state[0]_i_1_n_0 ), .Q(Q[0])); FDCE #( .INIT(1'b0)) \curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(curr_state), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state[1]_i_1_n_0 ), .Q(Q[1])); FDCE #( .INIT(1'b0)) \curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(curr_state), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state[2]_i_1_n_0 ), .Q(Q[2])); MUXF7 \curr_state_reg[2]_i_3 (.I0(\curr_state[2]_i_4_n_0 ), .I1(\curr_state[2]_i_5_n_0 ), .O(\curr_state_reg[2]_i_3_n_0 ), .S(\curr_state[4]_i_3_n_0 )); FDCE #( .INIT(1'b0)) \curr_state_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(curr_state), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state[3]_i_1_n_0 ), .Q(Q[3])); MUXF7 \curr_state_reg[3]_i_2 (.I0(\curr_state[3]_i_3_n_0 ), .I1(\curr_state[3]_i_4_n_0 ), .O(\curr_state_reg[3]_i_2_n_0 ), .S(\curr_state[4]_i_3_n_0 )); FDCE #( .INIT(1'b0)) \curr_state_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(curr_state), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state[4]_i_1_n_0 ), .Q(Q[4])); FDCE #( .INIT(1'b0)) \curr_state_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(curr_state), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state[5]_i_2_n_0 ), .Q(Q[5])); MUXF7 \curr_state_reg[5]_i_23 (.I0(\curr_state[5]_i_26_n_0 ), .I1(\curr_state[5]_i_27_n_0 ), .O(\curr_state_reg[5]_i_23_n_0 ), .S(Q[0])); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT4 #( .INIT(16'hAAEB)) \data_err_ctr_q[15]_i_1 (.I0(mr_ctr_pres_efd_q), .I1(\data_err_ctr_q[15]_i_3_n_0 ), .I2(sp_control), .I3(\g_bit[0].reg_value_r_reg[0]_0 ), .O(mr_ctr_pres_efd_q_reg)); LUT6 #( .INIT(64'h4C447F77FFFFFFFF)) \data_err_ctr_q[15]_i_3 (.I0(\sp_control_q_i_reg[1]_2 ), .I1(\sp_control_q_i[1]_i_2_n_0 ), .I2(\mr_ctrl_out[ssp_cfg_ssp_src] [1]), .I3(\mr_ctrl_out[ssp_cfg_ssp_src] [0]), .I4(sp_control_q[1]), .I5(\sp_control_q_i[1]_i_3_n_0 ), .O(\data_err_ctr_q[15]_i_3_n_0 )); LUT6 #( .INIT(64'h08A8A8A808A808A8)) \data_err_ctr_q[15]_i_4 (.I0(\sp_control_q_i[1]_i_3_n_0 ), .I1(sp_control_q[0]), .I2(\sp_control_q_i[1]_i_2_n_0 ), .I3(\sp_control_q_i_reg[1]_2 ), .I4(\mr_ctrl_out[ssp_cfg_ssp_src] [1]), .I5(\mr_ctrl_out[ssp_cfg_ssp_src] [0]), .O(sp_control)); LUT6 #( .INIT(64'h00AB00FF00000055)) destuff_enable_i_1 (.I0(\rec_dlc_reg[0] ), .I1(destuff_enable_i_2_n_0), .I2(destuff_enable_i_3_n_0), .I3(rec_abort_reg_2), .I4(reg_q_reg), .I5(destuff_enable), .O(destuff_enable_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000010)) destuff_enable_i_10 (.I0(Q[5]), .I1(Q[4]), .I2(Q[1]), .I3(Q[3]), .I4(Q[2]), .I5(Q[0]), .O(destuff_enable_i_10_n_0)); LUT6 #( .INIT(64'h0000000000600000)) destuff_enable_i_2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[3]), .I3(Q[1]), .I4(destuff_enable_reg_2), .I5(Q[4]), .O(destuff_enable_i_2_n_0)); LUT6 #( .INIT(64'h0000480800000000)) destuff_enable_i_3 (.I0(Q[4]), .I1(Q[1]), .I2(Q[3]), .I3(destuff_enable_reg_3), .I4(Q[2]), .I5(Q[0]), .O(destuff_enable_i_3_n_0)); LUT6 #( .INIT(64'h00000BFFBBFFBBFF)) destuff_enable_i_4 (.I0(destuff_enable_reg_0), .I1(destuff_enable_i_8_n_0), .I2(destuff_enable_i_9_n_0), .I3(\txtb_hw_cmd_q[lock]_i_3_n_0 ), .I4(destuff_enable_i_10_n_0), .I5(destuff_enable_reg_1), .O(reg_q_reg)); (* SOFT_HLUTNM = "soft_lutpair221" *) LUT4 #( .INIT(16'h0444)) destuff_enable_i_8 (.I0(Q[0]), .I1(Q[1]), .I2(\rx_stuff_count_reg[3] ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .O(destuff_enable_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT3 #( .INIT(8'h04)) destuff_enable_i_9 (.I0(Q[1]), .I1(Q[0]), .I2(\rx_stuff_count_reg[3] ), .O(destuff_enable_i_9_n_0)); FDCE destuff_enable_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(destuff_enable_i_1_n_0), .Q(destuff_enable)); LUT6 #( .INIT(64'hFFFFFFFFC004CC04)) \err_capt_err_pos_q[0]_i_1 (.I0(Q[4]), .I1(\err_capt_err_pos_q[0]_i_2_n_0 ), .I2(Q[0]), .I3(Q[2]), .I4(\err_capt_err_pos_q_reg[0] ), .I5(\err_capt_err_pos_q[0]_i_4_n_0 ), .O(\curr_state_reg[0]_5 [0])); (* SOFT_HLUTNM = "soft_lutpair280" *) LUT2 #( .INIT(4'h1)) \err_capt_err_pos_q[0]_i_2 (.I0(Q[3]), .I1(Q[5]), .O(\err_capt_err_pos_q[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF0000C00B)) \err_capt_err_pos_q[0]_i_4 (.I0(Q[5]), .I1(Q[1]), .I2(Q[4]), .I3(Q[0]), .I4(Q[2]), .I5(\err_capt_err_pos_q[0]_i_5_n_0 ), .O(\err_capt_err_pos_q[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFAFAEAEAAAAAAABF)) \err_capt_err_pos_q[0]_i_5 (.I0(\err_capt_err_pos_q[0]_i_6_n_0 ), .I1(Q[0]), .I2(Q[4]), .I3(Q[5]), .I4(Q[1]), .I5(Q[3]), .O(\err_capt_err_pos_q[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT3 #( .INIT(8'hF8)) \err_capt_err_pos_q[0]_i_6 (.I0(Q[2]), .I1(Q[4]), .I2(rec_abort_reg_2), .O(\err_capt_err_pos_q[0]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFEBEEFFFFEBEF)) \err_capt_err_pos_q[1]_i_1 (.I0(rec_abort_reg_2), .I1(Q[3]), .I2(Q[2]), .I3(\err_capt_err_pos_q[1]_i_2_n_0 ), .I4(\err_capt_err_pos_q[1]_i_3_n_0 ), .I5(\err_capt_err_pos_q[1]_i_4_n_0 ), .O(\curr_state_reg[0]_5 [1])); (* SOFT_HLUTNM = "soft_lutpair279" *) LUT2 #( .INIT(4'h1)) \err_capt_err_pos_q[1]_i_2 (.I0(Q[4]), .I1(Q[0]), .O(\err_capt_err_pos_q[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFF00FF4500000000)) \err_capt_err_pos_q[1]_i_3 (.I0(tran_ident_type), .I1(\shift_regs_reg[0] ), .I2(\shift_regs_reg[0]_0 ), .I3(Q[3]), .I4(Q[4]), .I5(\curr_state_reg[1]_0 ), .O(\err_capt_err_pos_q[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT4 #( .INIT(16'hFFF8)) \err_capt_err_pos_q[1]_i_4 (.I0(Q[0]), .I1(Q[4]), .I2(Q[5]), .I3(Q[1]), .O(\err_capt_err_pos_q[1]_i_4_n_0 )); LUT6 #( .INIT(64'hFAFAFAFAFAEFFBEF)) \err_capt_err_pos_q[2]_i_1 (.I0(rec_abort_reg_2), .I1(Q[1]), .I2(Q[4]), .I3(Q[0]), .I4(Q[5]), .I5(\err_capt_err_pos_q[2]_i_2_n_0 ), .O(\curr_state_reg[0]_5 [2])); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT2 #( .INIT(4'hE)) \err_capt_err_pos_q[2]_i_2 (.I0(Q[3]), .I1(Q[2]), .O(\err_capt_err_pos_q[2]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAABFE)) \err_capt_err_pos_q[3]_i_1 (.I0(\err_capt_err_pos_q[3]_i_2_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(first_err_delim_q_i_2_n_0), .I5(rec_abort_reg_2), .O(\curr_state_reg[0]_5 [3])); LUT6 #( .INIT(64'h1010100110101101)) \err_capt_err_pos_q[3]_i_2 (.I0(Q[3]), .I1(Q[4]), .I2(Q[5]), .I3(Q[0]), .I4(Q[2]), .I5(Q[1]), .O(\err_capt_err_pos_q[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT5 #( .INIT(32'h00150005)) \err_capt_err_type_q[0]_i_1 (.I0(\err_capt_err_type_q[2]_i_3_n_0 ), .I1(\curr_state_reg[1]_3 ), .I2(stuff_err), .I3(\err_capt_err_type_q[2]_i_4_n_0 ), .I4(err_capt_err_erp_reg), .O(reg_q_reg_13[0])); LUT5 #( .INIT(32'hEAFFEAEA)) \err_capt_err_type_q[1]_i_1 (.I0(\err_capt_err_type_q[2]_i_3_n_0 ), .I1(\curr_state_reg[1]_3 ), .I2(stuff_err), .I3(\err_capt_err_type_q[2]_i_4_n_0 ), .I4(ack_err_flag_reg_0), .O(reg_q_reg_13[1])); LUT4 #( .INIT(16'hFFFE)) \err_capt_err_type_q[2]_i_1 (.I0(\err_capt_err_type_q[2]_i_3_n_0 ), .I1(stuff_err), .I2(\err_capt_err_type_q[2]_i_4_n_0 ), .I3(err_capt_err_erp_reg), .O(reg_q_reg_1)); LUT6 #( .INIT(64'hFFA8FFFFFFFFFFFF)) \err_capt_err_type_q[2]_i_10 (.I0(Q[3]), .I1(Q[2]), .I2(Q[0]), .I3(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\txtb_hw_cmd_q_reg[lock]_4 ), .O(\err_capt_err_type_q[2]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair267" *) LUT2 #( .INIT(4'hB)) \err_capt_err_type_q[2]_i_11 (.I0(Q[3]), .I1(Q[4]), .O(\curr_state_reg[3]_1 )); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT4 #( .INIT(16'h0010)) \err_capt_err_type_q[2]_i_12 (.I0(Q[2]), .I1(rec_abort_reg_2), .I2(Q[4]), .I3(Q[3]), .O(\err_capt_err_type_q[2]_i_12_n_0 )); LUT6 #( .INIT(64'h4444474444444444)) \err_capt_err_type_q[2]_i_13 (.I0(\err_capt_err_type_q[2]_i_15_n_0 ), .I1(Q[0]), .I2(Q[1]), .I3(Q[2]), .I4(Q[4]), .I5(\err_capt_err_type_q[2]_i_8_0 ), .O(\err_capt_err_type_q[2]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT2 #( .INIT(4'h8)) \err_capt_err_type_q[2]_i_14 (.I0(Q[4]), .I1(Q[1]), .O(\err_capt_err_type_q[2]_i_14_n_0 )); LUT6 #( .INIT(64'hFFBBFFABFEBBFEAB)) \err_capt_err_type_q[2]_i_15 (.I0(\err_capt_err_type_q[2]_i_17_n_0 ), .I1(Q[3]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[4]), .I4(Q[5]), .I5(\rec_dlc_reg[0] ), .O(\err_capt_err_type_q[2]_i_15_n_0 )); LUT6 #( .INIT(64'hFFFFCEFFCFCFCFCF)) \err_capt_err_type_q[2]_i_17 (.I0(\mr_ctrl_out[mode_fde] ), .I1(Q[2]), .I2(Q[1]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\mr_ctrl_out[settings_pex] ), .I5(Q[3]), .O(\err_capt_err_type_q[2]_i_17_n_0 )); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT5 #( .INIT(32'h00000015)) \err_capt_err_type_q[2]_i_2 (.I0(\err_capt_err_type_q[2]_i_3_n_0 ), .I1(\curr_state_reg[1]_3 ), .I2(stuff_err), .I3(\err_capt_err_type_q[2]_i_4_n_0 ), .I4(err_capt_err_erp_reg), .O(reg_q_reg_13[2])); LUT6 #( .INIT(64'hAAAA2000AAAAAAAA)) \err_capt_err_type_q[2]_i_3 (.I0(\txtb_hw_cmd_q_reg[lock]_4 ), .I1(\err_capt_err_type_q_reg[1] ), .I2(Q[5]), .I3(\curr_state_reg[1]_0 ), .I4(\err_capt_err_type_q[2]_i_8_n_0 ), .I5(\err_capt_err_type_q[2]_i_9_n_0 ), .O(\err_capt_err_type_q[2]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAABBBAABA)) \err_capt_err_type_q[2]_i_4 (.I0(bit_err), .I1(\err_capt_err_type_q[2]_i_10_n_0 ), .I2(Q[3]), .I3(Q[1]), .I4(Q[2]), .I5(can_tx_OBUF), .O(\err_capt_err_type_q[2]_i_4_n_0 )); LUT6 #( .INIT(64'h00405A5A00000000)) \err_capt_err_type_q[2]_i_6 (.I0(Q[1]), .I1(Q[4]), .I2(Q[0]), .I3(\err_capt_err_pos_q[2]_i_2_n_0 ), .I4(\ctrl_ctr_q_reg[4]_0 ), .I5(\err_capt_err_type_q[2]_i_12_n_0 ), .O(\curr_state_reg[1]_3 )); LUT6 #( .INIT(64'hFFFFFFFF01010100)) \err_capt_err_type_q[2]_i_8 (.I0(first_err_delim_q_i_2_n_0), .I1(Q[2]), .I2(\curr_state[4]_i_11_n_0 ), .I3(\sp_control_q_i_reg[1]_2 ), .I4(\rx_stuff_count_reg[3] ), .I5(\err_capt_err_type_q[2]_i_13_n_0 ), .O(\err_capt_err_type_q[2]_i_8_n_0 )); LUT6 #( .INIT(64'hFFDDFFDFFFDFFFDF)) \err_capt_err_type_q[2]_i_9 (.I0(Q[0]), .I1(ack_err_flag_i_7_n_0), .I2(\err_capt_err_type_q[2]_i_14_n_0 ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\rx_stuff_count_reg[3] ), .I5(Q[5]), .O(\err_capt_err_type_q[2]_i_9_n_0 )); LUT6 #( .INIT(64'h80000000FFFFFFFF)) \exp_seg_length_q[8]_i_13 (.I0(\curr_state_reg[3]_2 ), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(Q[0]), .I3(Q[2]), .I4(\curr_state_reg[4]_1 ), .I5(sp_control_q[1]), .O(\exp_seg_length_q[8]_i_13_n_0 )); LUT6 #( .INIT(64'h1555555555555555)) \exp_seg_length_q[8]_i_14 (.I0(sp_control_q[0]), .I1(\curr_state_reg[3]_2 ), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[0]), .I4(Q[2]), .I5(\curr_state_reg[4]_1 ), .O(\exp_seg_length_q[8]_i_14_n_0 )); LUT6 #( .INIT(64'hFEFFFFFFFFFFFFFF)) \exp_seg_length_q[8]_i_3 (.I0(\exp_seg_length_q_reg[0] ), .I1(\sync_control_q_reg[1]_0 [0]), .I2(\exp_seg_length_q_reg[0]_0 ), .I3(sync_edge3__0), .I4(tq_edge), .I5(\sync_control_q_reg[1]_0 [1]), .O(\sync_control_q_reg[0]_0 )); LUT6 #( .INIT(64'hF7FF555504005555)) \exp_seg_length_q[8]_i_9 (.I0(\segm_counter_q_reg[0]_1 ), .I1(\exp_seg_length_q[8]_i_13_n_0 ), .I2(rx_data_sync_prev_reg), .I3(\exp_seg_length_q[8]_i_14_n_0 ), .I4(\sp_control_q_i[1]_i_3_n_0 ), .I5(\segm_counter_q_reg[0] ), .O(tq_edge)); LUT6 #( .INIT(64'hFFFF000400000004)) first_err_delim_q_i_1 (.I0(first_err_delim_q_i_2_n_0), .I1(Q[2]), .I2(rec_abort_reg_2), .I3(first_err_delim_q_i_3_n_0), .I4(\rec_dlc_reg[0] ), .I5(first_err_delim_q), .O(first_err_delim_q_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair267" *) LUT2 #( .INIT(4'h7)) first_err_delim_q_i_2 (.I0(Q[4]), .I1(Q[3]), .O(first_err_delim_q_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT5 #( .INIT(32'hF9FBFBF9)) first_err_delim_q_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(\rx_stuff_count_reg[3] ), .I3(rx_data_nbs_prev_reg_0), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .O(first_err_delim_q_i_3_n_0)); FDCE first_err_delim_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(first_err_delim_q_i_1_n_0), .Q(first_err_delim_q)); LUT6 #( .INIT(64'h000000000007FE00)) g0_b0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .I5(Q[5]), .O(g0_b0_n_0)); (* SOFT_HLUTNM = "soft_lutpair264" *) LUT3 #( .INIT(8'hB8)) \g_byte_shift_reg[1].shift_reg_q[1][0]_i_1 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(err_frm_req_reg), .I2(\g_byte_shift_reg[1].shift_reg_q_reg[1][0] [1]), .O(reg_q_reg_9)); LUT6 #( .INIT(64'hFFFFFFFFDFDBFFE7)) \g_byte_shift_reg[1].shift_reg_q[1][7]_i_4 (.I0(Q[0]), .I1(Q[4]), .I2(Q[2]), .I3(Q[3]), .I4(Q[1]), .I5(Q[5]), .O(\curr_state_reg[0]_6 )); (* SOFT_HLUTNM = "soft_lutpair264" *) LUT3 #( .INIT(8'hB8)) \g_byte_shift_reg[2].shift_reg_q[2][0]_i_1 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(err_frm_req_reg), .I2(\g_byte_shift_reg[1].shift_reg_q_reg[1][0] [0]), .O(reg_q_reg_10)); LUT3 #( .INIT(8'hB8)) \g_byte_shift_reg[3].shift_reg_q[3][0]_i_1 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(err_frm_req_reg), .I2(store_data_word), .O(reg_q_reg_11)); LUT5 #( .INIT(32'hBFFFAAAA)) \g_int_module[11].i_im_channel/int_status_i_1 (.I0(int_status_i_2__1_n_0), .I1(int_status_reg_0), .I2(data_in_IBUF[2]), .I3(int_status_reg_1), .I4(mr_int_stat_txbhci_o), .O(int_status_reg)); (* SOFT_HLUTNM = "soft_lutpair218" *) LUT5 #( .INIT(32'hF4CC44CC)) \g_ram_rst_false.ram_memory_reg_i_129 (.I0(rec_abort_reg_0), .I1(\FSM_onehot_curr_state_reg[6] [1]), .I2(store_data), .I3(ident_valid_q), .I4(\FSM_onehot_curr_state_reg[6] [3]), .O(rec_abort_reg_1)); LUT4 #( .INIT(16'h5150)) \i_bm_ssp_generator/btmc_meas_running_q_i_1 (.I0(\curr_state_reg[3]_6 ), .I1(btmc_meas_running_q_reg_0), .I2(first_ssp_q0), .I3(btmc_meas_running_q), .O(btmc_meas_running_q_reg)); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT4 #( .INIT(16'hABAA)) \i_bm_ssp_generator/sspc_ena_q_i_1 (.I0(first_ssp_q0), .I1(\data_err_ctr_q[15]_i_3_n_0 ), .I2(sp_control), .I3(sspc_ena_q), .O(sspc_ena_q_reg)); LUT6 #( .INIT(64'h000000AE000000AA)) int_status_i_10 (.I0(\txtb_hw_cmd_q_reg[failed]_1 ), .I1(\txtb_hw_cmd_q_reg[err]_0 ), .I2(curr_state_0), .I3(int_status_i_4_0[0]), .I4(int_status_i_4_0[1]), .I5(\FSM_sequential_curr_state_reg[2] ), .O(int_status_i_10_n_0)); LUT3 #( .INIT(8'h0E)) int_status_i_2__1 (.I0(int_status_i_3__1_n_0), .I1(int_status_i_4_n_0), .I2(int_status_reg_2), .O(int_status_i_2__1_n_0)); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT2 #( .INIT(4'hB)) int_status_i_2__2 (.I0(\sp_control_q_i[1]_i_2_n_0 ), .I1(\sp_control_q_i[1]_i_3_n_0 ), .O(br_shifted)); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT3 #( .INIT(8'hA8)) int_status_i_2__3 (.I0(Q[5]), .I1(Q[0]), .I2(Q[2]), .O(\curr_state_reg[5]_5 )); LUT6 #( .INIT(64'hFFFFFFFFFEFECCFE)) int_status_i_3__1 (.I0(txtb_allow_bb[1]), .I1(int_status_i_5_n_0), .I2(txtb_allow_bb[2]), .I3(int_status_i_2__1_0), .I4(int_status_i_2__1_1), .I5(int_status_i_8_n_0), .O(int_status_i_3__1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFEFECCFE)) int_status_i_4 (.I0(txtb_allow_bb[3]), .I1(int_status_i_9_n_0), .I2(txtb_allow_bb[0]), .I3(int_status_i_2__1_0), .I4(int_status_i_2__1_1), .I5(int_status_i_10_n_0), .O(int_status_i_4_n_0)); LUT6 #( .INIT(64'h0000AE000000AA00)) int_status_i_5 (.I0(\txtb_hw_cmd_q_reg[failed]_1 ), .I1(\txtb_hw_cmd_q_reg[err]_0 ), .I2(curr_state_1), .I3(int_status_i_4_0[0]), .I4(int_status_i_4_0[1]), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(int_status_i_5_n_0)); LUT6 #( .INIT(64'h0000AE000000AA00)) int_status_i_8 (.I0(\txtb_hw_cmd_q_reg[failed]_1 ), .I1(\txtb_hw_cmd_q_reg[err]_0 ), .I2(curr_state_2), .I3(int_status_i_4_0[1]), .I4(int_status_i_4_0[0]), .I5(\FSM_sequential_curr_state_reg[2]_1 ), .O(int_status_i_8_n_0)); LUT6 #( .INIT(64'hAE000000AA000000)) int_status_i_9 (.I0(\txtb_hw_cmd_q_reg[failed]_1 ), .I1(\txtb_hw_cmd_q_reg[err]_0 ), .I2(curr_state_4), .I3(int_status_i_4_0[0]), .I4(int_status_i_4_0[1]), .I5(\FSM_sequential_curr_state_reg[2]_2 ), .O(int_status_i_9_n_0)); LUT6 #( .INIT(64'hFF20FFFF20202020)) mr_command_ercrst_q_i_1 (.I0(data_in_IBUF[0]), .I1(mr_status_pexs_reg_0), .I2(mr_status_pexs_reg_1), .I3(\rec_dlc_reg[0] ), .I4(\curr_state_reg[4]_0 ), .I5(mr_command_ercrst_q), .O(mr_command_ercrst_q_i_1_n_0)); LUT6 #( .INIT(64'h8000000000000000)) mr_command_ercrst_q_i_3 (.I0(Q[4]), .I1(mr_command_ercrst_q_reg_0), .I2(Q[0]), .I3(mr_command_ercrst_q), .I4(Q[3]), .I5(Q[1]), .O(\curr_state_reg[4]_0 )); FDCE mr_command_ercrst_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(mr_command_ercrst_q_i_1_n_0), .Q(mr_command_ercrst_q)); LUT5 #( .INIT(32'hFFDFFF00)) mr_status_pexs_i_1 (.I0(data_in_IBUF[1]), .I1(mr_status_pexs_reg_0), .I2(mr_status_pexs_reg_1), .I3(pexs_set107_out), .I4(\cc_stat[status_pexs] ), .O(mr_status_pexs_i_1_n_0)); LUT6 #( .INIT(64'h0000000047000000)) mr_status_pexs_i_2 (.I0(Q[2]), .I1(Q[1]), .I2(\mr_ctrl_out[mode_fde] ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\mr_ctrl_out[settings_pex] ), .I5(mr_status_pexs_i_3_n_0), .O(pexs_set107_out)); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT5 #( .INIT(32'hFFF9FFFF)) mr_status_pexs_i_3 (.I0(Q[0]), .I1(Q[2]), .I2(rec_abort_reg_2), .I3(Q[4]), .I4(Q[3]), .O(mr_status_pexs_i_3_n_0)); FDCE mr_status_pexs_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(mr_status_pexs_i_1_n_0), .Q(\cc_stat[status_pexs] )); LUT3 #( .INIT(8'hBA)) \nom_err_ctr_q[15]_i_1 (.I0(mr_ctr_pres_enorm_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(\sp_control_q_i_reg[1]_0 ), .O(mr_ctr_pres_enorm_q_reg)); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT4 #( .INIT(16'h01FF)) \nom_err_ctr_q[15]_i_3 (.I0(sp_control_q[1]), .I1(\sp_control_q_i[1]_i_2_n_0 ), .I2(sp_control_q[0]), .I3(\sp_control_q_i[1]_i_3_n_0 ), .O(\sp_control_q_i_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT2 #( .INIT(4'h1)) prev_sample_q_i_2 (.I0(\data_err_ctr_q[15]_i_3_n_0 ), .I1(sp_control), .O(\g_bit[1].reg_value_r_reg[1] )); LUT6 #( .INIT(64'hF03F5F0FFF3F5F0F)) \r_data[10]_i_3__0 (.I0(timestamp_IBUF[13]), .I1(timestamp_IBUF[3]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\r_data[10]_i_6_n_0 ), .O(\timestamp[42] )); LUT6 #( .INIT(64'h0000000400000000)) \r_data[10]_i_6 (.I0(Q[3]), .I1(Q[4]), .I2(rec_abort_reg_2), .I3(Q[2]), .I4(Q[0]), .I5(Q[1]), .O(\r_data[10]_i_6_n_0 )); LUT6 #( .INIT(64'hF03F5F0FFF3F5F0F)) \r_data[11]_i_4 (.I0(timestamp_IBUF[14]), .I1(timestamp_IBUF[4]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\r_data[11]_i_8_n_0 ), .O(\timestamp[43] )); LUT6 #( .INIT(64'h0000000000004000)) \r_data[11]_i_8 (.I0(Q[3]), .I1(Q[4]), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(rec_abort_reg_2), .O(\r_data[11]_i_8_n_0 )); LUT6 #( .INIT(64'hFFFFFFFBAAAAFFFB)) \r_data[12]_i_4 (.I0(\r_data_reg[16] ), .I1(ack_err_flag_i_5_n_0), .I2(\r_data[12]_i_6_n_0 ), .I3(\r_data_reg[12] ), .I4(\r_data_reg[18]_3 ), .I5(\r_data_reg[12]_0 ), .O(\curr_state_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT4 #( .INIT(16'hFF8F)) \r_data[12]_i_6 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[3]), .O(\r_data[12]_i_6_n_0 )); LUT6 #( .INIT(64'hA8AAA8A888888888)) \r_data[13]_i_1 (.I0(sbe_IBUF[0]), .I1(\r_data[13]_i_2_n_0 ), .I2(\r_data_reg[13] ), .I3(\r_data_reg[13]_0 ), .I4(\r_data_reg[13]_1 ), .I5(\r_data_reg[13]_2 ), .O(D[0])); LUT6 #( .INIT(64'h1F1F1F1F101F1010)) \r_data[13]_i_2 (.I0(\r_data_reg[16] ), .I1(\r_data[13]_i_5_n_0 ), .I2(adress_IBUF[3]), .I3(\r_data_reg[15]_0 ), .I4(\r_data_reg[13]_3 ), .I5(\r_data_reg[13]_4 ), .O(\r_data[13]_i_2_n_0 )); LUT6 #( .INIT(64'hF03F5F0FFF3F5F0F)) \r_data[13]_i_5 (.I0(timestamp_IBUF[15]), .I1(timestamp_IBUF[5]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\pc_dbg[is_ack_delim] ), .O(\r_data[13]_i_5_n_0 )); LUT6 #( .INIT(64'h0000400000000000)) \r_data[13]_i_7 (.I0(Q[3]), .I1(Q[4]), .I2(Q[1]), .I3(Q[0]), .I4(rec_abort_reg_2), .I5(Q[2]), .O(\pc_dbg[is_ack_delim] )); LUT6 #( .INIT(64'hF05F3FFFFF5F3FFF)) \r_data[14]_i_3 (.I0(timestamp_IBUF[6]), .I1(timestamp_IBUF[16]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\pc_dbg[is_eof] ), .O(\timestamp[14] )); LUT6 #( .INIT(64'h0001000000000000)) \r_data[14]_i_6 (.I0(Q[0]), .I1(Q[1]), .I2(rec_abort_reg_2), .I3(Q[2]), .I4(Q[4]), .I5(Q[3]), .O(\pc_dbg[is_eof] )); LUT5 #( .INIT(32'h8888888A)) \r_data[15]_i_1 (.I0(sbe_IBUF[0]), .I1(\r_data[15]_i_2_n_0 ), .I2(adress_IBUF[2]), .I3(adress_IBUF[3]), .I4(\r_data_reg[15] ), .O(D[1])); LUT6 #( .INIT(64'h101F10101F1F1F1F)) \r_data[15]_i_2 (.I0(\r_data_reg[16] ), .I1(\r_data[15]_i_4__0_n_0 ), .I2(adress_IBUF[3]), .I3(\r_data_reg[15]_0 ), .I4(\r_data_reg[15]_1 ), .I5(\r_data_reg[15]_2 ), .O(\r_data[15]_i_2_n_0 )); LUT6 #( .INIT(64'hF03F5F0FFF3F5F0F)) \r_data[15]_i_4__0 (.I0(timestamp_IBUF[17]), .I1(timestamp_IBUF[7]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\pc_dbg[is_intermission] ), .O(\r_data[15]_i_4__0_n_0 )); LUT6 #( .INIT(64'h0002000000000000)) \r_data[15]_i_8 (.I0(Q[4]), .I1(rec_abort_reg_2), .I2(Q[2]), .I3(Q[1]), .I4(Q[3]), .I5(Q[0]), .O(\pc_dbg[is_intermission] )); LUT6 #( .INIT(64'h02AA0200AAAAAAAA)) \r_data[16]_i_1 (.I0(sbe_IBUF[1]), .I1(\r_data_reg[16] ), .I2(\r_data[16]_i_2__0_n_0 ), .I3(adress_IBUF[3]), .I4(\r_data_reg[16]_0 ), .I5(\r_data_reg[16]_1 ), .O(D[2])); LUT6 #( .INIT(64'hC4F4FFFFC4F40000)) \r_data[16]_i_2__0 (.I0(timestamp_IBUF[18]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[8]), .I4(\r_data_reg[18]_3 ), .I5(\r_data[16]_i_5_n_0 ), .O(\r_data[16]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFDFDFDFD3DFDFDFD)) \r_data[16]_i_5 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [0]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\curr_state_reg[1]_0 ), .I4(mr_command_ercrst_q_reg_0), .I5(first_err_delim_q_i_2_n_0), .O(\r_data[16]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair277" *) LUT2 #( .INIT(4'h1)) \r_data[17]_i_10 (.I0(Q[2]), .I1(Q[0]), .O(\r_data[17]_i_10_n_0 )); LUT6 #( .INIT(64'hC7F7FFFFC7F70000)) \r_data[17]_i_3 (.I0(timestamp_IBUF[9]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(timestamp_IBUF[19]), .I4(\r_data_reg[18]_3 ), .I5(\r_data[17]_i_7_n_0 ), .O(\timestamp[17] )); LUT6 #( .INIT(64'hFDFDFDFDFD3DFDFD)) \r_data[17]_i_7 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\r_data[17]_i_10_n_0 ), .I4(Q[5]), .I5(rec_abort_reg_2), .O(\r_data[17]_i_7_n_0 )); LUT6 #( .INIT(64'h8A8A8A888A888A88)) \r_data[18]_i_1 (.I0(sbe_IBUF[1]), .I1(\r_data[18]_i_2_n_0 ), .I2(adress_IBUF[3]), .I3(\r_data_reg[18] ), .I4(\r_data_reg[18]_0 ), .I5(\r_data_reg[18]_1 ), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT3 #( .INIT(8'h01)) \r_data[18]_i_10 (.I0(rec_abort_reg_2), .I1(Q[5]), .I2(Q[4]), .O(\r_data[18]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF20222000)) \r_data[18]_i_2 (.I0(adress_IBUF[3]), .I1(\r_data_reg[16] ), .I2(\r_data_reg[18]_2 ), .I3(\r_data_reg[18]_3 ), .I4(\r_data[18]_i_7_n_0 ), .I5(\r_data_reg[18]_4 ), .O(\r_data[18]_i_2_n_0 )); LUT6 #( .INIT(64'h02C2020202020202)) \r_data[18]_i_7 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [2]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\err_capt_err_pos_q[2]_i_2_n_0 ), .I4(ack_err_flag_i_3_n_0), .I5(\r_data[18]_i_10_n_0 ), .O(\r_data[18]_i_7_n_0 )); LUT6 #( .INIT(64'h4404440444040000)) \r_data[3]_i_12 (.I0(rec_abort_reg_2), .I1(\r_data[3]_i_14_n_0 ), .I2(first_err_delim_q_i_2_n_0), .I3(Q[5]), .I4(\curr_state_reg[1]_0 ), .I5(\r_data[3]_i_15_n_0 ), .O(err_frm_req_reg_10)); (* SOFT_HLUTNM = "soft_lutpair276" *) LUT2 #( .INIT(4'h9)) \r_data[3]_i_14 (.I0(Q[3]), .I1(Q[2]), .O(\r_data[3]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair274" *) LUT2 #( .INIT(4'h9)) \r_data[3]_i_15 (.I0(Q[2]), .I1(Q[0]), .O(\r_data[3]_i_15_n_0 )); LUT6 #( .INIT(64'h00BF000005000000)) \r_data[6]_i_9 (.I0(Q[0]), .I1(\err_capt_err_pos_q_reg[0] ), .I2(Q[1]), .I3(Q[3]), .I4(\r_data[18]_i_10_n_0 ), .I5(Q[2]), .O(\pc_dbg[is_arbitration] )); LUT6 #( .INIT(64'hFFFFFFFFFFFF3137)) \r_data[7]_i_12 (.I0(Q[2]), .I1(Q[3]), .I2(Q[0]), .I3(Q[1]), .I4(Q[4]), .I5(rec_abort_reg_2), .O(\r_data[7]_i_12_n_0 )); LUT6 #( .INIT(64'h2F23FFFF2F230000)) \r_data[7]_i_3__0 (.I0(timestamp_IBUF[0]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(timestamp_IBUF[10]), .I4(\r_data_reg[18]_3 ), .I5(\r_data[7]_i_7_n_0 ), .O(\timestamp[7] )); LUT6 #( .INIT(64'h0E0000FF0E000000)) \r_data[7]_i_7 (.I0(\err_capt_err_pos_q_reg[0] ), .I1(Q[3]), .I2(\r_data[7]_i_12_n_0 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\r_data[7]_i_3__0_0 ), .O(\r_data[7]_i_7_n_0 )); LUT6 #( .INIT(64'hF05F3FFFFF5F3FFF)) \r_data[8]_i_3 (.I0(timestamp_IBUF[1]), .I1(timestamp_IBUF[11]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(err_frm_req_reg), .O(\timestamp[8] )); LUT6 #( .INIT(64'hF03F5F0FFF3F5F0F)) \r_data[9]_i_3__0 (.I0(timestamp_IBUF[12]), .I1(timestamp_IBUF[2]), .I2(\r_data_reg[18]_3 ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\r_data[9]_i_6_n_0 ), .O(\timestamp[41] )); LUT6 #( .INIT(64'h0000000000001000)) \r_data[9]_i_6 (.I0(rec_abort_reg_2), .I1(Q[1]), .I2(Q[4]), .I3(Q[0]), .I4(Q[3]), .I5(Q[2]), .O(\r_data[9]_i_6_n_0 )); FDCE rec_abort_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(rec_abort_reg_2), .Q(rec_abort_reg_0)); LUT6 #( .INIT(64'h0002000000000000)) rec_brs_i_2 (.I0(Q[3]), .I1(Q[1]), .I2(rec_abort_reg_2), .I3(Q[4]), .I4(Q[0]), .I5(Q[2]), .O(\curr_state_reg[3]_6 )); LUT6 #( .INIT(64'h0000000000200000)) \rec_dlc[3]_i_1 (.I0(Q[0]), .I1(rec_abort_reg_2), .I2(Q[2]), .I3(Q[4]), .I4(\rec_dlc[3]_i_2_n_0 ), .I5(\rec_dlc_reg[0] ), .O(\curr_state_reg[0]_4 )); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT3 #( .INIT(8'h08)) \rec_dlc[3]_i_2 (.I0(Q[1]), .I1(Q[3]), .I2(\rx_stuff_count_reg[3] ), .O(\rec_dlc[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT2 #( .INIT(4'h2)) rec_esi_i_2 (.I0(Q[1]), .I1(Q[0]), .O(\curr_state_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair273" *) LUT2 #( .INIT(4'h8)) rec_esi_i_3 (.I0(Q[3]), .I1(Q[2]), .O(\curr_state_reg[3]_5 )); (* SOFT_HLUTNM = "soft_lutpair266" *) LUT2 #( .INIT(4'h2)) rec_frame_type_i_i_2 (.I0(Q[3]), .I1(Q[1]), .O(\curr_state_reg[3]_2 )); LUT6 #( .INIT(64'h4000000000000000)) \rec_ident[17]_i_1 (.I0(\rx_stuff_count_reg[3] ), .I1(\txtb_hw_cmd_q_reg[lock]_4 ), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(\rec_ident[17]_i_2_n_0 ), .O(\curr_state_reg[5]_2 [0])); (* SOFT_HLUTNM = "soft_lutpair270" *) LUT2 #( .INIT(4'h1)) \rec_ident[17]_i_2 (.I0(Q[4]), .I1(Q[3]), .O(\rec_ident[17]_i_2_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \rec_ident[28]_i_1 (.I0(\rec_ident[28]_i_2_n_0 ), .I1(Q[5]), .I2(Q[1]), .I3(\curr_state_reg[4]_1 ), .I4(Q[3]), .I5(Q[0]), .O(\curr_state_reg[5]_2 [1])); (* SOFT_HLUTNM = "soft_lutpair274" *) LUT2 #( .INIT(4'h2)) \rec_ident[28]_i_2 (.I0(Q[2]), .I1(\rx_stuff_count_reg[3] ), .O(\rec_ident[28]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT4 #( .INIT(16'h0010)) \rec_ident[28]_i_3 (.I0(Q[4]), .I1(rec_abort_reg_2), .I2(tx_frame_no_sof_q_reg_4), .I3(tx_frame_no_sof_q_reg_5), .O(\curr_state_reg[4]_1 )); (* SOFT_HLUTNM = "soft_lutpair278" *) LUT2 #( .INIT(4'h2)) rec_ident_type_i_2 (.I0(Q[1]), .I1(Q[3]), .O(\curr_state_reg[1]_5 )); LUT6 #( .INIT(64'h0000000000000100)) rec_is_rtr_i_i_2 (.I0(Q[5]), .I1(Q[1]), .I2(tx_frame_no_sof_q_reg_5), .I3(tx_frame_no_sof_q_reg_4), .I4(rec_abort_reg_2), .I5(Q[4]), .O(\curr_state_reg[5]_3 )); LUT6 #( .INIT(64'hFFFFFBFF00000800)) rec_ivld_q_i_1 (.I0(rec_ivld_i), .I1(rec_ivld_q_i_3_n_0), .I2(rec_ivld_q_i_4_n_0), .I3(\timestamp_capture[63]_i_2_n_0 ), .I4(rec_ivld_q_i_5_n_0), .I5(rec_ivld), .O(rec_ivld_q_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT5 #( .INIT(32'hFFEF00EE)) rec_ivld_q_i_2 (.I0(Q[2]), .I1(Q[3]), .I2(Q[0]), .I3(Q[4]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .O(rec_ivld_i)); LUT6 #( .INIT(64'hAAAAAAAAABABEBAB)) rec_ivld_q_i_3 (.I0(Q[1]), .I1(Q[4]), .I2(Q[0]), .I3(rec_ivld_q_reg_0), .I4(\rx_stuff_count_reg[3] ), .I5(rec_valid_i_5_n_0), .O(rec_ivld_q_i_3_n_0)); LUT6 #( .INIT(64'h8888888888888880)) rec_ivld_q_i_4 (.I0(Q[1]), .I1(Q[2]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[4]), .I4(Q[3]), .I5(Q[0]), .O(rec_ivld_q_i_4_n_0)); LUT6 #( .INIT(64'hCCC0CCCCCCC00CC8)) rec_ivld_q_i_5 (.I0(\cc_stat[is_bus_off] ), .I1(rec_ivld_q_i_7_n_0), .I2(Q[3]), .I3(Q[4]), .I4(Q[0]), .I5(\txtb_hw_cmd_q_reg[valid]_4 ), .O(rec_ivld_q_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair271" *) LUT2 #( .INIT(4'h2)) rec_ivld_q_i_7 (.I0(Q[1]), .I1(Q[2]), .O(rec_ivld_q_i_7_n_0)); FDCE rec_ivld_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(rec_ivld_q_i_1_n_0), .Q(rec_ivld)); LUT6 #( .INIT(64'h0000004000000000)) rec_lbpf_q_i_2 (.I0(\rx_stuff_count_reg[3] ), .I1(Q[3]), .I2(Q[1]), .I3(\txtb_ptr_q[2]_i_3_n_0 ), .I4(rec_abort_reg_2), .I5(Q[0]), .O(p_131_in)); FDCE rec_lbpf_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(rec_lbpf_q_reg_0), .Q(rec_lbpf)); LUT6 #( .INIT(64'h0000020000000000)) rec_valid_i_1 (.I0(rec_valid_reg_2), .I1(rec_valid_reg_3), .I2(rec_valid_i_4_n_0), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(rec_valid_i_5_n_0), .I5(\txtb_hw_cmd_q_reg[lock]_4 ), .O(rec_valid_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair269" *) LUT2 #( .INIT(4'hE)) rec_valid_i_4 (.I0(Q[1]), .I1(Q[0]), .O(rec_valid_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair273" *) LUT2 #( .INIT(4'hB)) rec_valid_i_5 (.I0(Q[2]), .I1(Q[3]), .O(rec_valid_i_5_n_0)); FDCE rec_valid_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(rec_valid_i_1_n_0), .Q(rec_valid_reg_0)); LUT6 #( .INIT(64'hF8DFFFFFFFFFFFFF)) reg_q_i_1__10 (.I0(\sp_control_q_i_reg[1]_2 ), .I1(reg_q_reg_16), .I2(Q[0]), .I3(Q[2]), .I4(\curr_state_reg[3]_2 ), .I5(reg_q_reg_18), .O(\curr_state_reg[0]_8 )); LUT6 #( .INIT(64'hBA00000000000000)) reg_q_i_1__6 (.I0(reg_q_reg_14), .I1(fixed_prev_q), .I2(\curr_state_reg[1]_3 ), .I3(reg_q_reg_15), .I4(reg_q_reg_8), .I5(destuff_enable), .O(stuff_err_d)); LUT5 #( .INIT(32'hAEAEFF00)) reg_q_i_1__8 (.I0(bds_data_in), .I1(\curr_state_reg[1]_3 ), .I2(fixed_prev_q), .I3(reg_q), .I4(reg_q_reg_15), .O(prev_val_d)); LUT6 #( .INIT(64'hFFFFFFBFFFFFFFFF)) reg_q_i_1__9 (.I0(can_tx_OBUF), .I1(tx_data_prev), .I2(reg_q_i_2__5_n_0), .I3(rec_abort_reg_2), .I4(Q[2]), .I5(Q[1]), .O(p_0_out)); (* SOFT_HLUTNM = "soft_lutpair270" *) LUT2 #( .INIT(4'h2)) reg_q_i_2__5 (.I0(Q[3]), .I1(Q[4]), .O(reg_q_i_2__5_n_0)); LUT5 #( .INIT(32'hDDCD00C0)) reg_q_i_2__6 (.I0(\mr_ctrl_out[mode_bmm] ), .I1(reg_q_reg_17), .I2(sp_control_q[1]), .I3(sp_control_q[0]), .I4(rx_data_wbs), .O(bds_data_in)); LUT6 #( .INIT(64'h9A9955559A999599)) reg_q_i_2__9 (.I0(reg_q), .I1(rx_data_wbs), .I2(sp_control_q[0]), .I3(sp_control_q[1]), .I4(reg_q_reg_17), .I5(\mr_ctrl_out[mode_bmm] ), .O(reg_q_reg_8)); LUT6 #( .INIT(64'hAAAAAAAAAAAEAAAA)) \reinteg_ctr_q[7]_i_1 (.I0(\curr_state_reg[4]_0 ), .I1(\txtb_hw_cmd_q_reg[lock]_4 ), .I2(first_err_delim_q_i_2_n_0), .I3(rec_valid_i_4_n_0), .I4(Q[2]), .I5(\rx_stuff_count_reg[3] ), .O(reinteg_ctr_ce)); LUT6 #( .INIT(64'hFBFFFFFFFFFFFFFF)) \reinteg_ctr_q[7]_i_3 (.I0(rec_abort_reg_2), .I1(Q[4]), .I2(Q[2]), .I3(\reinteg_ctr_q[7]_i_5_n_0 ), .I4(mr_command_ercrst_q), .I5(Q[0]), .O(err_frm_req_reg_5)); (* SOFT_HLUTNM = "soft_lutpair266" *) LUT2 #( .INIT(4'h8)) \reinteg_ctr_q[7]_i_5 (.I0(Q[3]), .I1(Q[1]), .O(\reinteg_ctr_q[7]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFDFFFFFF0000)) retr_ctr_add_block_i_1 (.I0(retr_ctr_add_block_i_2_n_0), .I1(Q[2]), .I2(rec_abort_reg_2), .I3(Q[4]), .I4(retr_ctr_add), .I5(retr_ctr_add_block), .O(retr_ctr_add_block_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair265" *) LUT3 #( .INIT(8'h08)) retr_ctr_add_block_i_2 (.I0(Q[0]), .I1(Q[3]), .I2(Q[1]), .O(retr_ctr_add_block_i_2_n_0)); LUT6 #( .INIT(64'h0000000E00000000)) retr_ctr_add_block_i_3 (.I0(err_frm_req_reg_0), .I1(rec_abort_reg_2), .I2(retr_ctr_add_block), .I3(reg_q_reg_2), .I4(\cc_stat[is_receiver] ), .I5(\mr_ctrl_out[settings_rtrle] ), .O(retr_ctr_add)); LUT6 #( .INIT(64'hFFFFFFFF00200000)) retr_ctr_add_block_i_4 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(\rec_dlc_reg[0] ), .I2(\sp_control_q_i_reg[1]_2 ), .I3(rec_abort_reg_2), .I4(\curr_state_reg[0]_2 ), .I5(\txtb_hw_cmd_q[failed] ), .O(reg_q_reg_2)); FDCE retr_ctr_add_block_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(retr_ctr_add_block_i_1_n_0), .Q(retr_ctr_add_block)); (* SOFT_HLUTNM = "soft_lutpair268" *) LUT2 #( .INIT(4'h2)) \retr_ctr_q[0]_i_1 (.I0(retr_ctr_add), .I1(\retr_ctr_q_reg[0]_0 ), .O(\retr_ctr_q_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair268" *) LUT2 #( .INIT(4'hE)) \retr_ctr_q[3]_i_1 (.I0(retr_ctr_add), .I1(\retr_ctr_q_reg[3] ), .O(err_frm_req_reg_1)); FDPE rx_data_nbs_prev_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(rx_data_nbs_prev_reg_1), .PRE(\sp_control_q_i_reg[1]_1 ), .Q(rx_data_nbs_prev_reg_0)); LUT6 #( .INIT(64'h0000000055555557)) rx_data_sync_prev_i_2 (.I0(\sp_control_q_i[1]_i_3_n_0 ), .I1(sp_control_q[0]), .I2(\sp_control_q_i[1]_i_2_n_0 ), .I3(rx_data_sync_prev_reg), .I4(sp_control_q[1]), .I5(\segm_counter_q_reg[0]_1 ), .O(\sp_control_q_i_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair212" *) LUT5 #( .INIT(32'hDFFFFFFF)) rx_data_sync_prev_i_4 (.I0(Q[3]), .I1(Q[1]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(Q[0]), .I4(Q[2]), .O(\curr_state_reg[3]_7 )); LUT6 #( .INIT(64'h00004040000040FF)) \rx_err_ctr_q[8]_i_10 (.I0(first_err_delim_q_i_2_n_0), .I1(\curr_state_reg[2]_3 ), .I2(ack_err_flag_i_4_n_0), .I3(\rx_err_ctr_q[8]_i_12_n_0 ), .I4(rec_abort_reg_2), .I5(\rec_dlc_reg[0] ), .O(\rx_err_ctr_q[8]_i_10_n_0 )); LUT6 #( .INIT(64'h0000002040000000)) \rx_err_ctr_q[8]_i_11 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(Q[4]), .I4(Q[3]), .I5(Q[5]), .O(\curr_state_reg[1]_2 )); LUT6 #( .INIT(64'hCFFFFF55FFFFFF55)) \rx_err_ctr_q[8]_i_12 (.I0(\ctrl_ctr_q[0]_i_6_n_0 ), .I1(\rx_err_ctr_q[8]_i_13_n_0 ), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(Q[3]), .O(\rx_err_ctr_q[8]_i_12_n_0 )); LUT5 #( .INIT(32'hFFDFFFFF)) \rx_err_ctr_q[8]_i_13 (.I0(Q[4]), .I1(\txtb_hw_cmd_q_reg[valid]_4 ), .I2(first_err_delim_q), .I3(\shift_regs_reg[0] ), .I4(\shift_regs_reg[0]_0 ), .O(\rx_err_ctr_q[8]_i_13_n_0 )); LUT6 #( .INIT(64'hABAAAAAAAAAAAAAA)) \rx_err_ctr_q[8]_i_4 (.I0(\txtb_hw_cmd_q_reg[valid]_0 ), .I1(Q[3]), .I2(\txtb_hw_cmd_q_reg[valid]_4 ), .I3(ack_err_flag_i_5_n_0), .I4(\cc_stat[is_receiver] ), .I5(\rx_err_ctr_q[8]_i_8_n_0 ), .O(\txtb_hw_cmd_q_reg[valid]_3 )); LUT6 #( .INIT(64'hFFFF0002FFFF3333)) \rx_err_ctr_q[8]_i_5 (.I0(\nom_err_ctr_q_reg[0] ), .I1(\rx_err_ctr_q[8]_i_10_n_0 ), .I2(\curr_state_reg[1]_2 ), .I3(\cc_stat[is_receiver] ), .I4(\mr_ctrl_out[mode_rom] ), .I5(reg_q_reg_1), .O(\g_bit[0].reg_value_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT3 #( .INIT(8'h40)) \rx_err_ctr_q[8]_i_8 (.I0(Q[1]), .I1(Q[4]), .I2(crc_match), .O(\rx_err_ctr_q[8]_i_8_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hFFFFFDFF)) rx_err_ctr_sat1_carry_i_10 (.I0(reg_q_reg_1), .I1(\mr_ctrl_out[mode_rom] ), .I2(\shift_regs_reg[0] ), .I3(\shift_regs_reg[0]_0 ), .I4(\curr_state_reg[1]_2 ), .O(\g_bit[0].reg_value_r_reg[0]_2 )); LUT6 #( .INIT(64'h0000000000000040)) \rx_stuff_count[3]_i_1 (.I0(\err_capt_err_pos_q[2]_i_2_n_0 ), .I1(Q[0]), .I2(\rx_stuff_count[3]_i_2_n_0 ), .I3(rec_abort_reg_2), .I4(\rx_stuff_count_reg[3] ), .I5(\rec_dlc_reg[0] ), .O(\curr_state_reg[0]_3 )); (* SOFT_HLUTNM = "soft_lutpair275" *) LUT2 #( .INIT(4'h2)) \rx_stuff_count[3]_i_2 (.I0(Q[4]), .I1(Q[1]), .O(\rx_stuff_count[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT3 #( .INIT(8'h8F)) \same_bits_q[1]_i_2 (.I0(tx_frame_no_sof_q_reg_0), .I1(err_frm_req_reg_4), .I2(stuff_enable_reg_0), .O(tx_frame_no_sof_q_reg_1)); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT4 #( .INIT(16'hFFDF)) \same_bits_q[2]_i_4 (.I0(enable_prev), .I1(btmc_meas_running_q_reg_0), .I2(stuff_enable_reg_0), .I3(tx_frame_no_sof_q_reg_0), .O(reg_q_reg_7)); LUT6 #( .INIT(64'h0000000000450000)) \same_bits_q[2]_i_5 (.I0(\curr_state_reg[1]_3 ), .I1(is_tseg2), .I2(\sp_control_q_i_reg[0]_0 ), .I3(\same_bits_q_reg[2] ), .I4(is_tseg1), .I5(reg_q_reg_8), .O(\FSM_onehot_current_state_reg[2] )); LUT4 #( .INIT(16'hFFF8)) \segm_counter_q[6]_i_1__0 (.I0(err_frm_req_reg_6), .I1(\segm_counter_q_reg[0] ), .I2(\sp_control_q_i_reg[0]_0 ), .I3(\segm_counter_q_reg[0]_0 ), .O(err_frm_req_reg_7)); LUT4 #( .INIT(16'hFCFE)) \segm_counter_q[7]_i_1 (.I0(\curr_state_reg[5]_4 ), .I1(\sp_control_q_i_reg[0]_0 ), .I2(\segm_counter_q_reg[0]_0 ), .I3(\segm_counter_q_reg[0]_1 ), .O(\curr_state_reg[5]_6 )); LUT2 #( .INIT(4'h2)) \segm_counter_q[7]_i_3 (.I0(\sp_control_q_i_reg[0]_1 ), .I1(\segm_counter_q_reg[0]_2 ), .O(\sp_control_q_i_reg[0]_0 )); LUT4 #( .INIT(16'hF444)) \shift_regs[10]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [9]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[12]), .O(\bst_ctr_q_reg[2] [9])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hFFF4F4F4)) \shift_regs[11]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [10]), .I2(\shift_regs_reg[11] ), .I3(\curr_state_reg[2]_1 ), .I4(\shift_regs_reg[11]_0 ), .O(\bst_ctr_q_reg[2] [10])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hFFF4F4F4)) \shift_regs[12]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [11]), .I2(\shift_regs_reg[12] ), .I3(\curr_state_reg[2]_1 ), .I4(\shift_regs_reg[12]_0 ), .O(\bst_ctr_q_reg[2] [11])); LUT5 #( .INIT(32'hFFF4F4F4)) \shift_regs[13]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [12]), .I2(\shift_regs_reg[13] ), .I3(tran_word[13]), .I4(\curr_state_reg[2]_1 ), .O(\bst_ctr_q_reg[2] [12])); LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[14]_i_1 (.I0(\crc_q[14]_i_6_0 [13]), .I1(\curr_state_reg[2]_1 ), .I2(tran_word[14]), .I3(\shift_regs_reg[14] ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[14]_0 ), .O(\bst_ctr_q_reg[2] [13])); LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[15]_i_1 (.I0(\crc_q[14]_i_6_0 [14]), .I1(\curr_state_reg[2]_1 ), .I2(tran_word[15]), .I3(\shift_regs_reg[15] ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[15]_0 ), .O(\bst_ctr_q_reg[2] [14])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[16]_i_1 (.I0(\crc_q[14]_i_6_0 [15]), .I1(\shift_regs_reg[16] ), .I2(\curr_state_reg[2]_1 ), .I3(\shift_regs_reg[16]_0 ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[16]_1 ), .O(\bst_ctr_q_reg[2] [15])); LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[17]_i_1 (.I0(\crc_q[14]_i_6_0 [16]), .I1(\curr_state_reg[2]_1 ), .I2(tran_word[5]), .I3(\shift_regs_reg[17] ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[17]_0 ), .O(\bst_ctr_q_reg[2] [16])); LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[18]_i_1 (.I0(\crc_q[14]_i_6_0 [17]), .I1(\curr_state_reg[2]_1 ), .I2(tran_word[6]), .I3(\shift_regs_reg[18] ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[18]_0 ), .O(\bst_ctr_q_reg[2] [17])); LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[19]_i_1 (.I0(\crc_q[14]_i_6_0 [18]), .I1(\curr_state_reg[2]_1 ), .I2(tran_word[7]), .I3(\shift_regs_reg[19] ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[19]_0 ), .O(\bst_ctr_q_reg[2] [18])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'hF444)) \shift_regs[1]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [0]), .I2(\shift_regs_reg[1] ), .I3(\curr_state_reg[2]_1 ), .O(\bst_ctr_q_reg[2] [0])); LUT6 #( .INIT(64'hFFFFAAAAFFC0AAAA)) \shift_regs[20]_i_1 (.I0(\crc_q[14]_i_6_0 [19]), .I1(\curr_state_reg[2]_1 ), .I2(tran_word[8]), .I3(\shift_regs_reg[20] ), .I4(\shift_regs[31]_i_5_n_0 ), .I5(\shift_regs_reg[20]_0 ), .O(\bst_ctr_q_reg[2] [19])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[21]_i_1 (.I0(\shift_regs_reg[21] ), .I1(\curr_state_reg[2]_1 ), .I2(\shift_regs_reg[21]_0 ), .I3(\shift_regs[21]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [20]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [20])); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT4 #( .INIT(16'hF808)) \shift_regs[21]_i_3 (.I0(\curr_state_reg[1]_1 ), .I1(\shift_regs_reg[27]_0 [0]), .I2(\curr_state_reg[2]_2 ), .I3(\shift_regs_reg[27]_0 [7]), .O(\shift_regs[21]_i_3_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[22]_i_1 (.I0(\shift_regs_reg[22] ), .I1(\curr_state_reg[2]_1 ), .I2(\shift_regs_reg[22]_0 ), .I3(\shift_regs[22]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [21]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [21])); LUT4 #( .INIT(16'h8F88)) \shift_regs[22]_i_3 (.I0(\curr_state_reg[2]_2 ), .I1(\shift_regs_reg[27]_0 [8]), .I2(\shift_regs[27]_i_6_n_0 ), .I3(\shift_regs_reg[27]_0 [1]), .O(\shift_regs[22]_i_3_n_0 )); LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[23]_i_1 (.I0(\shift_regs_reg[23] ), .I1(tran_word[9]), .I2(\curr_state_reg[2]_1 ), .I3(\shift_regs[23]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [22]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [22])); LUT4 #( .INIT(16'h8F88)) \shift_regs[23]_i_3 (.I0(\curr_state_reg[2]_2 ), .I1(\shift_regs_reg[27]_0 [9]), .I2(\shift_regs[27]_i_6_n_0 ), .I3(\shift_regs_reg[27]_0 [2]), .O(\shift_regs[23]_i_3_n_0 )); LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[24]_i_1 (.I0(\shift_regs_reg[24] ), .I1(tran_word[0]), .I2(\curr_state_reg[2]_1 ), .I3(\shift_regs[24]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [23]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [23])); LUT4 #( .INIT(16'hF808)) \shift_regs[24]_i_3 (.I0(\curr_state_reg[1]_1 ), .I1(\shift_regs_reg[27]_0 [3]), .I2(\curr_state_reg[2]_2 ), .I3(\shift_regs_reg[27]_0 [10]), .O(\shift_regs[24]_i_3_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[25]_i_1 (.I0(\shift_regs_reg[25] ), .I1(\curr_state_reg[2]_1 ), .I2(\shift_regs_reg[25]_0 ), .I3(\shift_regs[25]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [24]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [24])); LUT4 #( .INIT(16'hF808)) \shift_regs[25]_i_3 (.I0(\curr_state_reg[1]_1 ), .I1(\shift_regs_reg[27]_0 [4]), .I2(\curr_state_reg[2]_2 ), .I3(\shift_regs_reg[27]_0 [11]), .O(\shift_regs[25]_i_3_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[26]_i_1 (.I0(\shift_regs_reg[26] ), .I1(\curr_state_reg[2]_1 ), .I2(\shift_regs_reg[26]_0 ), .I3(\shift_regs[26]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [25]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [25])); LUT4 #( .INIT(16'h8F88)) \shift_regs[26]_i_3 (.I0(\curr_state_reg[2]_2 ), .I1(\shift_regs_reg[27]_0 [12]), .I2(\shift_regs[27]_i_6_n_0 ), .I3(\shift_regs_reg[27]_0 [5]), .O(\shift_regs[26]_i_3_n_0 )); LUT6 #( .INIT(64'hFFEAFFEAFFFFFFEA)) \shift_regs[27]_i_1 (.I0(\shift_regs_reg[27] ), .I1(tran_word[1]), .I2(\curr_state_reg[2]_1 ), .I3(\shift_regs[27]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [26]), .I5(\shift_regs[31]_i_5_n_0 ), .O(\bst_ctr_q_reg[2] [26])); LUT4 #( .INIT(16'h8F88)) \shift_regs[27]_i_3 (.I0(\curr_state_reg[2]_2 ), .I1(\shift_regs_reg[27]_0 [13]), .I2(\shift_regs[27]_i_6_n_0 ), .I3(\shift_regs_reg[27]_0 [6]), .O(\shift_regs[27]_i_3_n_0 )); LUT6 #( .INIT(64'hFFEFFFFFFFFFFFFF)) \shift_regs[27]_i_6 (.I0(Q[4]), .I1(Q[0]), .I2(\shift_regs[27]_i_7_n_0 ), .I3(Q[3]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\txtb_hw_cmd_q_reg[lock]_4 ), .O(\shift_regs[27]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair277" *) LUT2 #( .INIT(4'h8)) \shift_regs[27]_i_7 (.I0(Q[2]), .I1(Q[1]), .O(\shift_regs[27]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFAE)) \shift_regs[28]_i_1 (.I0(\shift_regs[28]_i_2_n_0 ), .I1(tran_word[2]), .I2(\shift_regs[30]_i_4_n_0 ), .I3(\shift_regs_reg[28] ), .I4(\shift_regs[28]_i_4_n_0 ), .I5(\shift_regs_reg[28]_0 ), .O(\bst_ctr_q_reg[2] [27])); LUT6 #( .INIT(64'h0000000000000200)) \shift_regs[28]_i_2 (.I0(\crc_q[14]_i_6_0 [27]), .I1(\curr_state_reg[2]_1 ), .I2(\curr_state_reg[0]_0 ), .I3(\curr_state_reg[0]_1 ), .I4(reg_q_reg_0), .I5(\shift_regs[31]_i_11_n_0 ), .O(\shift_regs[28]_i_2_n_0 )); LUT4 #( .INIT(16'h802A)) \shift_regs[28]_i_4 (.I0(\shift_regs[29]_i_7_n_0 ), .I1(\shift_regs_reg[28]_1 ), .I2(\shift_regs_reg[28]_2 ), .I3(\shift_regs_reg[28]_3 ), .O(\shift_regs[28]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFAE)) \shift_regs[29]_i_1 (.I0(\shift_regs[29]_i_2_n_0 ), .I1(tran_word[3]), .I2(\shift_regs[30]_i_4_n_0 ), .I3(\shift_regs_reg[29] ), .I4(\shift_regs[29]_i_4_n_0 ), .I5(\shift_regs_reg[29]_0 ), .O(\bst_ctr_q_reg[2] [28])); LUT6 #( .INIT(64'h0000080000000000)) \shift_regs[29]_i_11 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(Q[3]), .I5(\curr_state_reg[4]_1 ), .O(\curr_state_reg[1]_1 )); LUT6 #( .INIT(64'hDDD5DDD5DDD5DDD0)) \shift_regs[29]_i_12 (.I0(\shift_regs[31]_i_25_n_0 ), .I1(\shift_regs[31]_i_23_n_0 ), .I2(\shift_regs[31]_i_7_0 ), .I3(\rx_stuff_count_reg[3] ), .I4(\shift_regs[31]_i_26_n_0 ), .I5(\ctrl_ctr_q_reg[1]_0 ), .O(\shift_regs[29]_i_12_n_0 )); LUT6 #( .INIT(64'h0011001100010000)) \shift_regs[29]_i_13 (.I0(first_err_delim_q_i_2_n_0), .I1(Q[2]), .I2(\rx_stuff_count_reg[3] ), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(\curr_state[4]_i_8_n_0 ), .I5(\curr_state_reg[1]_0 ), .O(\shift_regs[29]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT4 #( .INIT(16'h0004)) \shift_regs[29]_i_14 (.I0(Q[4]), .I1(Q[1]), .I2(Q[2]), .I3(Q[3]), .O(\shift_regs[29]_i_14_n_0 )); LUT6 #( .INIT(64'h0000000000000200)) \shift_regs[29]_i_2 (.I0(\crc_q[14]_i_6_0 [28]), .I1(\curr_state_reg[2]_1 ), .I2(\curr_state_reg[0]_0 ), .I3(\curr_state_reg[0]_1 ), .I4(reg_q_reg_0), .I5(\shift_regs[31]_i_11_n_0 ), .O(\shift_regs[29]_i_2_n_0 )); LUT4 #( .INIT(16'h08A2)) \shift_regs[29]_i_4 (.I0(\shift_regs[29]_i_7_n_0 ), .I1(\tran_frame_test[fcrc] ), .I2(\shift_regs_reg[29]_1 ), .I3(\shift_regs_reg[29]_2 ), .O(\shift_regs[29]_i_4_n_0 )); LUT6 #( .INIT(64'h0000000000000004)) \shift_regs[29]_i_7 (.I0(\curr_state_reg[0]_0 ), .I1(\shift_regs[30]_i_4_n_0 ), .I2(Q[5]), .I3(rec_abort_reg_2), .I4(\rec_dlc_reg[0] ), .I5(\shift_regs[29]_i_12_n_0 ), .O(\shift_regs[29]_i_7_n_0 )); LUT6 #( .INIT(64'hAAA8AAAA88888888)) \shift_regs[29]_i_9 (.I0(\timestamp_capture[63]_i_2_n_0 ), .I1(\shift_regs[29]_i_13_n_0 ), .I2(Q[2]), .I3(ack_err_flag_i_3_n_0), .I4(\txtb_hw_cmd_q_reg[lock]_5 ), .I5(\shift_regs[29]_i_14_n_0 ), .O(\curr_state_reg[2]_2 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'hF444)) \shift_regs[2]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [1]), .I2(\shift_regs_reg[2] ), .I3(\curr_state_reg[2]_1 ), .O(\bst_ctr_q_reg[2] [1])); LUT6 #( .INIT(64'hFFFFFFFFAAEAEEEE)) \shift_regs[30]_i_1 (.I0(\shift_regs_reg[30] ), .I1(\shift_regs[30]_i_3_n_0 ), .I2(tran_word[4]), .I3(\shift_regs[30]_i_4_n_0 ), .I4(\shift_regs_reg[30]_0 ), .I5(\shift_regs[30]_i_6_n_0 ), .O(\bst_ctr_q_reg[2] [29])); (* SOFT_HLUTNM = "soft_lutpair213" *) LUT2 #( .INIT(4'hE)) \shift_regs[30]_i_3 (.I0(\curr_state_reg[0]_0 ), .I1(\curr_state_reg[2]_1 ), .O(\shift_regs[30]_i_3_n_0 )); LUT6 #( .INIT(64'hDDDDDD5DDDDDDDDD)) \shift_regs[30]_i_4 (.I0(\shift_regs[31]_i_16_n_0 ), .I1(\shift_regs[31]_i_17_n_0 ), .I2(\rx_stuff_count_reg[3] ), .I3(\shift_regs_reg[30]_2 ), .I4(\err_capt_err_pos_q[2]_i_2_n_0 ), .I5(Q[4]), .O(\shift_regs[30]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00100000)) \shift_regs[30]_i_6 (.I0(\shift_regs[31]_i_11_n_0 ), .I1(reg_q_reg_0), .I2(\curr_state_reg[0]_1 ), .I3(\shift_regs[30]_i_3_n_0 ), .I4(\crc_q[14]_i_6_0 [29]), .I5(\shift_regs_reg[30]_1 ), .O(\shift_regs[30]_i_6_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00080000)) \shift_regs[31]_i_1 (.I0(\shift_regs_reg[0]_0 ), .I1(\shift_regs_reg[0] ), .I2(rec_abort_reg_2), .I3(\curr_state_reg[5]_0 ), .I4(\crc_q_reg[0] ), .I5(\shift_regs[31]_i_5_n_0 ), .O(E)); LUT6 #( .INIT(64'hAAAAABAAAAAAAAAA)) \shift_regs[31]_i_10 (.I0(\shift_regs_reg[31]_2 ), .I1(\shift_regs[31]_i_11_n_0 ), .I2(reg_q_reg_0), .I3(\curr_state_reg[0]_1 ), .I4(\shift_regs[30]_i_3_n_0 ), .I5(\crc_q[14]_i_6_0 [30]), .O(\shift_regs[31]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT2 #( .INIT(4'hE)) \shift_regs[31]_i_11 (.I0(\curr_state_reg[2]_2 ), .I1(\curr_state_reg[1]_1 ), .O(\shift_regs[31]_i_11_n_0 )); LUT6 #( .INIT(64'h0000D50000000000)) \shift_regs[31]_i_12 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(\curr_state_reg[1]_0 ), .I2(reg_q_i_2__5_n_0), .I3(\txtb_hw_cmd_q_reg[lock]_4 ), .I4(\shift_regs[31]_i_22_n_0 ), .I5(\ctrl_ctr_q[0]_i_3_n_0 ), .O(reg_q_reg_0)); LUT6 #( .INIT(64'h8FFF8FFF8FFF8FCF)) \shift_regs[31]_i_13 (.I0(\shift_regs[31]_i_23_n_0 ), .I1(\shift_regs[27]_i_2 ), .I2(\timestamp_capture[63]_i_2_n_0 ), .I3(\shift_regs[31]_i_25_n_0 ), .I4(\shift_regs[31]_i_26_n_0 ), .I5(\ctrl_ctr_q_reg[1]_0 ), .O(\curr_state_reg[0]_1 )); LUT6 #( .INIT(64'hFFFFFBFFFFF3FFFF)) \shift_regs[31]_i_15 (.I0(\ctrl_ctr_q_reg[1]_0 ), .I1(\shift_regs[31]_i_7_0 ), .I2(\rx_stuff_count_reg[3] ), .I3(Q[2]), .I4(Q[4]), .I5(Q[3]), .O(\shift_regs[31]_i_15_n_0 )); LUT6 #( .INIT(64'h0400000000000004)) \shift_regs[31]_i_16 (.I0(tx_frame_no_sof_q_reg_5), .I1(tx_frame_no_sof_q_reg_4), .I2(rec_abort_reg_2), .I3(Q[1]), .I4(Q[2]), .I5(Q[0]), .O(\shift_regs[31]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair214" *) LUT5 #( .INIT(32'hFFDFFFFF)) \shift_regs[31]_i_17 (.I0(Q[3]), .I1(Q[4]), .I2(Q[2]), .I3(\rx_stuff_count_reg[3] ), .I4(\ctrl_ctr_q_reg[1]_0 ), .O(\shift_regs[31]_i_17_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFFFFFFFFFFFF444)) \shift_regs[31]_i_2 (.I0(\shift_regs_reg[31] ), .I1(\curr_state_reg[0]_0 ), .I2(\shift_regs_reg[31]_0 ), .I3(\curr_state_reg[2]_1 ), .I4(\shift_regs_reg[31]_1 ), .I5(\shift_regs[31]_i_10_n_0 ), .O(\bst_ctr_q_reg[2] [30])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT3 #( .INIT(8'hFD)) \shift_regs[31]_i_22 (.I0(Q[3]), .I1(Q[0]), .I2(Q[4]), .O(\shift_regs[31]_i_22_n_0 )); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT4 #( .INIT(16'hF0FD)) \shift_regs[31]_i_23 (.I0(Q[0]), .I1(Q[1]), .I2(\rx_stuff_count_reg[3] ), .I3(Q[2]), .O(\shift_regs[31]_i_23_n_0 )); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT4 #( .INIT(16'h0004)) \shift_regs[31]_i_25 (.I0(Q[1]), .I1(Q[4]), .I2(Q[2]), .I3(Q[3]), .O(\shift_regs[31]_i_25_n_0 )); (* SOFT_HLUTNM = "soft_lutpair211" *) LUT5 #( .INIT(32'hDFFFFFFF)) \shift_regs[31]_i_26 (.I0(Q[1]), .I1(Q[4]), .I2(Q[2]), .I3(Q[0]), .I4(Q[3]), .O(\shift_regs[31]_i_26_n_0 )); LUT6 #( .INIT(64'hEFEFFFF3FFFEFF33)) \shift_regs[31]_i_3 (.I0(Q[5]), .I1(Q[4]), .I2(Q[1]), .I3(Q[3]), .I4(Q[2]), .I5(Q[0]), .O(\curr_state_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair213" *) LUT5 #( .INIT(32'hFFFFFFEF)) \shift_regs[31]_i_5 (.I0(\shift_regs[31]_i_11_n_0 ), .I1(reg_q_reg_0), .I2(\curr_state_reg[0]_1 ), .I3(\curr_state_reg[0]_0 ), .I4(\curr_state_reg[2]_1 ), .O(\shift_regs[31]_i_5_n_0 )); LUT6 #( .INIT(64'h0000000000000081)) \shift_regs[31]_i_7 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .I3(rec_abort_reg_2), .I4(\rec_dlc_reg[0] ), .I5(\shift_regs[31]_i_15_n_0 ), .O(\curr_state_reg[0]_0 )); LUT6 #( .INIT(64'h00000020AAAAAAAA)) \shift_regs[31]_i_8 (.I0(\shift_regs[31]_i_16_n_0 ), .I1(Q[2]), .I2(\rx_stuff_count_reg[3] ), .I3(\shift_regs_reg[30]_2 ), .I4(\curr_state_reg[3]_1 ), .I5(\shift_regs[31]_i_17_n_0 ), .O(\curr_state_reg[2]_1 )); LUT4 #( .INIT(16'hF444)) \shift_regs[3]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [2]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[16]), .O(\bst_ctr_q_reg[2] [2])); LUT4 #( .INIT(16'hF444)) \shift_regs[4]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [3]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[17]), .O(\bst_ctr_q_reg[2] [3])); LUT4 #( .INIT(16'hF444)) \shift_regs[5]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [4]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[18]), .O(\bst_ctr_q_reg[2] [4])); LUT4 #( .INIT(16'hF444)) \shift_regs[6]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [5]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[19]), .O(\bst_ctr_q_reg[2] [5])); LUT4 #( .INIT(16'hF444)) \shift_regs[7]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [6]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[20]), .O(\bst_ctr_q_reg[2] [6])); LUT4 #( .INIT(16'hF444)) \shift_regs[8]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [7]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[10]), .O(\bst_ctr_q_reg[2] [7])); LUT4 #( .INIT(16'hF444)) \shift_regs[9]_i_1 (.I0(\shift_regs[31]_i_5_n_0 ), .I1(\crc_q[14]_i_6_0 [8]), .I2(\curr_state_reg[2]_1 ), .I3(tran_word[11]), .O(\bst_ctr_q_reg[2] [8])); LUT6 #( .INIT(64'h75FF000075000000)) \sp_control_q_i[0]_i_1 (.I0(\sp_control_q_i_reg[1]_2 ), .I1(\mr_ctrl_out[ssp_cfg_ssp_src] [1]), .I2(\mr_ctrl_out[ssp_cfg_ssp_src] [0]), .I3(\sp_control_q_i[1]_i_2_n_0 ), .I4(\sp_control_q_i[1]_i_3_n_0 ), .I5(sp_control_q[0]), .O(\sp_control_q_i[0]_i_1_n_0 )); LUT6 #( .INIT(64'hD0FF0000D0000000)) \sp_control_q_i[1]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_src] [0]), .I1(\mr_ctrl_out[ssp_cfg_ssp_src] [1]), .I2(\sp_control_q_i_reg[1]_2 ), .I3(\sp_control_q_i[1]_i_2_n_0 ), .I4(\sp_control_q_i[1]_i_3_n_0 ), .I5(sp_control_q[1]), .O(\sp_control_q_i[1]_i_1_n_0 )); LUT6 #( .INIT(64'h0000800000000000)) \sp_control_q_i[1]_i_2 (.I0(\curr_state_reg[4]_1 ), .I1(Q[2]), .I2(Q[0]), .I3(\txtb_hw_cmd_q_reg[valid]_4 ), .I4(Q[1]), .I5(Q[3]), .O(\sp_control_q_i[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFF5151FFFF5555FF)) \sp_control_q_i[1]_i_3 (.I0(rec_abort_reg_2), .I1(tx_frame_no_sof_q_reg_4), .I2(tx_frame_no_sof_q_reg_5), .I3(sp_control_q[1]), .I4(sp_control_q[0]), .I5(\sp_control_q_i[1]_i_4_n_0 ), .O(\sp_control_q_i[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair211" *) LUT5 #( .INIT(32'h10000000)) \sp_control_q_i[1]_i_4 (.I0(Q[3]), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(Q[4]), .O(\sp_control_q_i[1]_i_4_n_0 )); FDCE \sp_control_q_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\sp_control_q_i[0]_i_1_n_0 ), .Q(sp_control_q[0])); FDCE \sp_control_q_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\sp_control_q_i[1]_i_1_n_0 ), .Q(sp_control_q[1])); LUT6 #( .INIT(64'h2000000000000000)) sspc_ena_q_i_2 (.I0(ack_err_flag_i_5_n_0), .I1(sp_control_q[0]), .I2(sp_control_q[1]), .I3(\curr_state_reg[1]_0 ), .I4(reg_q_i_2__5_n_0), .I5(btmc_meas_running_q_reg_0), .O(first_ssp_q0)); LUT6 #( .INIT(64'h0000000000000010)) store_data_i_4 (.I0(rec_abort_reg_2), .I1(Q[1]), .I2(Q[4]), .I3(Q[0]), .I4(Q[3]), .I5(Q[2]), .O(err_frm_req_reg)); FDCE store_data_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(store_data_reg_0), .Q(store_data)); FDCE store_metadata_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(store_metadata_reg_1), .Q(store_metadata_reg_0)); LUT6 #( .INIT(64'hF323232301010101)) stuff_enable_i_1 (.I0(\rec_dlc_reg[0] ), .I1(rec_abort_reg_2), .I2(stuff_enable_i_2_n_0), .I3(err_frm_req_reg_9), .I4(stuff_enable_i_4_n_0), .I5(stuff_enable_reg_0), .O(stuff_enable_i_1_n_0)); LUT6 #( .INIT(64'hFE00FEFEFEFEFEFE)) stuff_enable_i_2 (.I0(\txtb_hw_cmd_q[lock]_i_5_n_0 ), .I1(Q[4]), .I2(Q[5]), .I3(\rx_stuff_count_reg[3] ), .I4(\txtb_hw_cmd_q[lock]_i_3_n_0 ), .I5(\txtb_hw_cmd_q[lock]_i_2_n_0 ), .O(stuff_enable_i_2_n_0)); LUT6 #( .INIT(64'h5555555555551555)) stuff_enable_i_3 (.I0(rec_abort_reg_2), .I1(Q[4]), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .I5(Q[3]), .O(err_frm_req_reg_9)); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT4 #( .INIT(16'hFFFE)) stuff_enable_i_4 (.I0(stuff_enable_i_5_n_0), .I1(\txtb_hw_cmd_q[arbl]_i_3_n_0 ), .I2(Q[4]), .I3(Q[5]), .O(stuff_enable_i_4_n_0)); LUT6 #( .INIT(64'h888888A8AAAAAAAA)) stuff_enable_i_5 (.I0(Q[2]), .I1(Q[3]), .I2(\curr_state_reg[1]_0 ), .I3(tran_ident_type), .I4(\cc_stat[is_receiver] ), .I5(\alc_alc_bit_reg[0] ), .O(stuff_enable_i_5_n_0)); FDCE stuff_enable_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(stuff_enable_i_1_n_0), .Q(stuff_enable_reg_0)); LUT6 #( .INIT(64'h00A2A2A282A2A2A2)) \sync_control_q[0]_i_1 (.I0(\sync_control_q[1]_i_2_n_0 ), .I1(sp_control_q[1]), .I2(sp_control_q[0]), .I3(\shift_regs_reg[0]_0 ), .I4(\shift_regs_reg[0] ), .I5(\sp_control_q_i[1]_i_2_n_0 ), .O(sync_control_d[0])); LUT6 #( .INIT(64'h0051515141515151)) \sync_control_q[1]_i_1 (.I0(\sync_control_q[1]_i_2_n_0 ), .I1(sp_control_q[1]), .I2(sp_control_q[0]), .I3(\shift_regs_reg[0]_0 ), .I4(\shift_regs_reg[0] ), .I5(\sp_control_q_i[1]_i_2_n_0 ), .O(sync_control_d[1])); LUT6 #( .INIT(64'h003CAAAA00000000)) \sync_control_q[1]_i_2 (.I0(\sync_control_q[1]_i_3_n_0 ), .I1(Q[2]), .I2(Q[1]), .I3(first_err_delim_q_i_2_n_0), .I4(\sync_control_q[1]_i_4_n_0 ), .I5(\curr_state_reg[4]_4 ), .O(\sync_control_q[1]_i_2_n_0 )); LUT6 #( .INIT(64'h000000FF0000B0AF)) \sync_control_q[1]_i_3 (.I0(rec_valid_reg_2), .I1(\rx_stuff_count_reg[3] ), .I2(Q[3]), .I3(Q[4]), .I4(Q[2]), .I5(Q[1]), .O(\sync_control_q[1]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT3 #( .INIT(8'h45)) \sync_control_q[1]_i_4 (.I0(Q[0]), .I1(Q[3]), .I2(Q[1]), .O(\sync_control_q[1]_i_4_n_0 )); FDPE \sync_control_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(sync_control_d[0]), .PRE(\sp_control_q_i_reg[1]_1 ), .Q(\sync_control_q_reg[1]_0 [0])); FDCE \sync_control_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(sync_control_d[1]), .Q(\sync_control_q_reg[1]_0 [1])); LUT5 #( .INIT(32'h48FF4848)) sync_flag_i_1 (.I0(\sync_control_q_reg[1]_0 [0]), .I1(sync_edge), .I2(\sync_control_q_reg[1]_0 [1]), .I3(reg_q_reg_15), .I4(sync_flag), .O(\sync_control_q_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT3 #( .INIT(8'h82)) \test_probe[tx_trigger]_INST_0_i_8 (.I0(\segm_counter_q_reg[0] ), .I1(sp_control), .I2(\data_err_ctr_q[15]_i_3_n_0 ), .O(\tq_counter_q_reg[7] )); LUT6 #( .INIT(64'hF8080808FFFFFFFF)) \timestamp_capture[63]_i_1 (.I0(ident_valid_q), .I1(rec_valid_reg_0), .I2(\mr_ctrl_out[rx_settings_rtsop] ), .I3(\timestamp_capture[63]_i_2_n_0 ), .I4(\timestamp_capture[63]_i_3_n_0 ), .I5(\FSM_onehot_curr_state_reg[1] ), .O(ident_valid_q_reg)); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT4 #( .INIT(16'h0010)) \timestamp_capture[63]_i_2 (.I0(Q[5]), .I1(rec_abort_reg_2), .I2(tx_frame_no_sof_q_reg_4), .I3(tx_frame_no_sof_q_reg_5), .O(\timestamp_capture[63]_i_2_n_0 )); LUT6 #( .INIT(64'h0000505000000300)) \timestamp_capture[63]_i_3 (.I0(\timestamp_capture[63]_i_4_n_0 ), .I1(\timestamp_capture_reg[63] ), .I2(Q[4]), .I3(Q[1]), .I4(Q[2]), .I5(Q[3]), .O(\timestamp_capture[63]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFDDDDFFFF999D)) \timestamp_capture[63]_i_4 (.I0(Q[1]), .I1(Q[0]), .I2(\curr_state_reg[1]_7 [0]), .I3(\curr_state_reg[1]_7 [1]), .I4(\txtb_hw_cmd_q_reg[valid]_4 ), .I5(\rx_stuff_count_reg[3] ), .O(\timestamp_capture[63]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \tq_counter_q[7]_i_1 (.I0(\err_capt_err_pos_q[2]_i_2_n_0 ), .I1(Q[5]), .I2(Q[4]), .I3(rec_valid_i_4_n_0), .I4(\mr_ctrl_out[settings_ena] ), .I5(rec_abort_reg_2), .O(\curr_state_reg[5]_4 )); LUT5 #( .INIT(32'hBBBBBBBA)) \tq_counter_q[7]_i_1__0 (.I0(rec_abort_reg_2), .I1(\tq_counter_q[7]_i_3_n_0 ), .I2(\tq_counter_q[7]_i_4_n_0 ), .I3(sp_control_q[1]), .I4(sp_control_q[0]), .O(err_frm_req_reg_6)); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT5 #( .INIT(32'hF18FFF0F)) \tq_counter_q[7]_i_3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[4]), .I3(Q[3]), .I4(Q[2]), .O(\tq_counter_q[7]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT5 #( .INIT(32'h06644000)) \tq_counter_q[7]_i_4 (.I0(Q[3]), .I1(Q[4]), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .O(\tq_counter_q[7]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'h0001)) tran_frame_valid_com_i_3 (.I0(\txtb_hw_cmd_q_reg[valid]_0 ), .I1(\txtb_hw_cmd[err] ), .I2(\txtb_hw_cmd_q_reg[failed]_0 ), .I3(\txtb_hw_cmd[arbl] ), .O(\txtb_hw_cmd_q_reg[valid]_1 )); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT5 #( .INIT(32'h00040000)) trv_meas_progress_q_i_2 (.I0(Q[4]), .I1(Q[3]), .I2(rec_abort_reg_2), .I3(Q[2]), .I4(Q[1]), .O(tran_delay_meas)); LUT5 #( .INIT(32'hABAABBBB)) \tx_err_ctr_q[8]_i_3 (.I0(\mr_ctrl_out[mode_rom] ), .I1(\rx_err_ctr_q[8]_i_10_n_0 ), .I2(\curr_state_reg[1]_2 ), .I3(\nom_err_ctr_q_reg[0] ), .I4(reg_q_reg_1), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'hFFFF01FF00000100)) tx_frame_no_sof_q_i_1 (.I0(Q[5]), .I1(rec_abort_reg_2), .I2(tx_frame_no_sof_q_i_2_n_0), .I3(tx_frame_no_sof_q_reg_4), .I4(tx_frame_no_sof_q_reg_5), .I5(tx_frame_no_sof_q_reg_0), .O(tx_frame_no_sof_q_i_1_n_0)); LUT6 #( .INIT(64'hEEEEEEEEE0EEEEEE)) tx_frame_no_sof_q_i_2 (.I0(tx_frame_no_sof_q_reg_2), .I1(\txtb_hw_cmd_q[lock]_i_5_n_0 ), .I2(tx_frame_no_sof_q_reg_3), .I3(tx_frame_no_sof_q_i_5_n_0), .I4(rec_ivld_q_reg_0), .I5(\rx_stuff_count_reg[3] ), .O(tx_frame_no_sof_q_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT5 #( .INIT(32'h04000000)) tx_frame_no_sof_q_i_5 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[4]), .I4(Q[3]), .O(tx_frame_no_sof_q_i_5_n_0)); FDCE tx_frame_no_sof_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(tx_frame_no_sof_q_i_1_n_0), .Q(tx_frame_no_sof_q_reg_0)); LUT6 #( .INIT(64'h0000000000000002)) \txtb_hw_cmd_q[arbl]_i_1 (.I0(\txtb_hw_cmd_q[arbl]_i_2_n_0 ), .I1(\txtb_hw_cmd_q_reg[arbl]_0 ), .I2(\rec_dlc_reg[0] ), .I3(rec_abort_reg_2), .I4(Q[4]), .I5(\txtb_hw_cmd_q[arbl]_i_3_n_0 ), .O(\txtb_hw_cmd_q[arbl] )); LUT6 #( .INIT(64'h0040FFFF0444FFFF)) \txtb_hw_cmd_q[arbl]_i_2 (.I0(Q[3]), .I1(\alc_alc_bit_reg[0] ), .I2(\curr_state_reg[1]_0 ), .I3(\err_capt_err_pos_q_reg[0] ), .I4(Q[2]), .I5(Q[5]), .O(\txtb_hw_cmd_q[arbl]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair219" *) LUT5 #( .INIT(32'h54555555)) \txtb_hw_cmd_q[arbl]_i_3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(\alc_alc_bit_reg[0] ), .O(\txtb_hw_cmd_q[arbl]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00002220)) \txtb_hw_cmd_q[err]_i_3 (.I0(Q[2]), .I1(Q[5]), .I2(Q[0]), .I3(Q[1]), .I4(first_err_delim_q_i_2_n_0), .I5(\txtb_hw_cmd_q[err]_i_5_n_0 ), .O(\curr_state_reg[2]_4 )); LUT6 #( .INIT(64'h6000FFFFFFFFFFFF)) \txtb_hw_cmd_q[err]_i_5 (.I0(Q[2]), .I1(Q[1]), .I2(\rec_ident[17]_i_2_n_0 ), .I3(Q[5]), .I4(\sp_control_q_i_reg[1]_2 ), .I5(rec_abort_reg_2), .O(\txtb_hw_cmd_q[err]_i_5_n_0 )); LUT3 #( .INIT(8'h8A)) \txtb_hw_cmd_q[failed]_i_1 (.I0(\txtb_hw_cmd_q_reg[arbl]_0 ), .I1(err_frm_req_reg_0), .I2(\curr_state_reg[2]_4 ), .O(\txtb_hw_cmd_q[failed] )); LUT6 #( .INIT(64'h008000800080AAAA)) \txtb_hw_cmd_q[lock]_i_1 (.I0(\txtb_hw_cmd_q_reg[lock]_4 ), .I1(\txtb_hw_cmd_q[lock]_i_2_n_0 ), .I2(\txtb_hw_cmd_q[lock]_i_3_n_0 ), .I3(\rx_stuff_count_reg[3] ), .I4(\txtb_hw_cmd_q[lock]_i_4_n_0 ), .I5(\txtb_hw_cmd_q[lock]_i_5_n_0 ), .O(\txtb_hw_cmd_q[lock] )); LUT6 #( .INIT(64'h0000A0000030A000)) \txtb_hw_cmd_q[lock]_i_2 (.I0(\txtb_hw_cmd_q_reg[valid]_4 ), .I1(\curr_state_reg[4]_2 ), .I2(tran_frame_valid), .I3(Q[1]), .I4(Q[0]), .I5(\cc_stat[is_bus_off] ), .O(\txtb_hw_cmd_q[lock]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT4 #( .INIT(16'h1000)) \txtb_hw_cmd_q[lock]_i_3 (.I0(Q[5]), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .O(\txtb_hw_cmd_q[lock]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT2 #( .INIT(4'hE)) \txtb_hw_cmd_q[lock]_i_4 (.I0(Q[4]), .I1(Q[5]), .O(\txtb_hw_cmd_q[lock]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair220" *) LUT5 #( .INIT(32'hFFFFFFFB)) \txtb_hw_cmd_q[lock]_i_5 (.I0(\txtb_hw_cmd_q_reg[lock]_5 ), .I1(Q[1]), .I2(Q[3]), .I3(Q[2]), .I4(Q[0]), .O(\txtb_hw_cmd_q[lock]_i_5_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \txtb_hw_cmd_q[valid]_i_1 (.I0(\curr_state_reg[0]_2 ), .I1(rec_abort_reg_2), .I2(\sp_control_q_i_reg[1]_2 ), .I3(tx_frame_no_sof_q_reg_4), .I4(tx_frame_no_sof_q_reg_5), .I5(\txtb_hw_cmd_q_reg[valid]_4 ), .O(\txtb_hw_cmd_q[valid] )); LUT6 #( .INIT(64'h0001000000000000)) \txtb_hw_cmd_q[valid]_i_2 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .I3(\rx_stuff_count_reg[3] ), .I4(Q[4]), .I5(Q[3]), .O(\curr_state_reg[0]_2 )); FDCE \txtb_hw_cmd_q_reg[arbl] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_hw_cmd_q[arbl] ), .Q(\txtb_hw_cmd[arbl] )); FDCE \txtb_hw_cmd_q_reg[err] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_hw_cmd_q[err] ), .Q(\txtb_hw_cmd[err] )); FDCE \txtb_hw_cmd_q_reg[failed] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_hw_cmd_q[failed] ), .Q(\txtb_hw_cmd_q_reg[failed]_0 )); FDCE \txtb_hw_cmd_q_reg[lock] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_hw_cmd_q[lock] ), .Q(\txtb_hw_cmd_q_reg[lock]_0 )); FDCE \txtb_hw_cmd_q_reg[valid] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_hw_cmd_q[valid] ), .Q(\txtb_hw_cmd_q_reg[valid]_0 )); LUT6 #( .INIT(64'h000000000000AAEA)) \txtb_ptr_q[2]_i_1 (.I0(\txtb_ptr_q_reg[2]_1 ), .I1(Q[3]), .I2(\sp_control_q_i_reg[1]_2 ), .I3(\txtb_ptr_q[2]_i_3_n_0 ), .I4(\txtb_ptr_q[2]_i_4_n_0 ), .I5(rec_abort_reg_2), .O(\curr_state_reg[3]_3 )); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT2 #( .INIT(4'hB)) \txtb_ptr_q[2]_i_3 (.I0(Q[4]), .I1(Q[2]), .O(\txtb_ptr_q[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT3 #( .INIT(8'h7E)) \txtb_ptr_q[2]_i_4 (.I0(Q[0]), .I1(Q[2]), .I2(Q[1]), .O(\txtb_ptr_q[2]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT3 #( .INIT(8'hEF)) \txtb_ptr_q[2]_i_5 (.I0(Q[2]), .I1(Q[3]), .I2(Q[4]), .O(\curr_state_reg[2]_5 )); LUT4 #( .INIT(16'hFFF6)) \txtb_ptr_q[4]_i_3 (.I0(\curr_state_reg[3]_3 ), .I1(\txtb_ptr_q_reg[4]_0 [2]), .I2(\txtb_ptr_q_reg[4]_1 ), .I3(\txtb_ptr_q_reg[4]_2 ), .O(\txtb_ptr_q_reg[2]_0 )); LUT6 #( .INIT(64'h0000000400000000)) \txtb_ptr_q[4]_i_7 (.I0(Q[3]), .I1(Q[4]), .I2(rec_abort_reg_2), .I3(Q[2]), .I4(rec_valid_i_4_n_0), .I5(\sp_control_q_i_reg[1]_2 ), .O(\curr_state_reg[3]_4 )); FDCE #( .INIT(1'b0)) \txtb_ptr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\txtb_ptr_q_reg[4]_3 ), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_ptr_q_reg[4]_4 [0]), .Q(\txtb_ptr_q_reg[4]_0 [0])); FDCE #( .INIT(1'b0)) \txtb_ptr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\txtb_ptr_q_reg[4]_3 ), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_ptr_q_reg[4]_4 [1]), .Q(\txtb_ptr_q_reg[4]_0 [1])); FDCE #( .INIT(1'b0)) \txtb_ptr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\txtb_ptr_q_reg[4]_3 ), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\curr_state_reg[3]_3 ), .Q(\txtb_ptr_q_reg[4]_0 [2])); FDCE #( .INIT(1'b0)) \txtb_ptr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\txtb_ptr_q_reg[4]_3 ), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_ptr_q_reg[4]_4 [2]), .Q(\txtb_ptr_q_reg[4]_0 [3])); FDCE #( .INIT(1'b0)) \txtb_ptr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\txtb_ptr_q_reg[4]_3 ), .CLR(\sp_control_q_i_reg[1]_1 ), .D(\txtb_ptr_q_reg[4]_4 [3]), .Q(\txtb_ptr_q_reg[4]_0 [4])); endmodule module mac_pc_reintegration_counter (\reinteg_ctr_q_reg[2]_0 , reinteg_ctr_ce, clk_sys_IBUF_BUFG, \reinteg_ctr_q_reg[7]_0 , \reinteg_ctr_q_reg[3]_0 , \reinteg_ctr_q_reg[0]_0 ); output \reinteg_ctr_q_reg[2]_0 ; input reinteg_ctr_ce; input clk_sys_IBUF_BUFG; input \reinteg_ctr_q_reg[7]_0 ; input \reinteg_ctr_q_reg[3]_0 ; input \reinteg_ctr_q_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire \curr_state[5]_i_28_n_0 ; wire reinteg_ctr_ce; wire [7:0]reinteg_ctr_d; wire \reinteg_ctr_q[5]_i_2_n_0 ; wire \reinteg_ctr_q[7]_i_4_n_0 ; wire [7:0]reinteg_ctr_q_reg; wire \reinteg_ctr_q_reg[0]_0 ; wire \reinteg_ctr_q_reg[2]_0 ; wire \reinteg_ctr_q_reg[3]_0 ; wire \reinteg_ctr_q_reg[7]_0 ; LUT5 #( .INIT(32'hFFFFFFFE)) \curr_state[5]_i_24 (.I0(reinteg_ctr_q_reg[2]), .I1(reinteg_ctr_q_reg[5]), .I2(reinteg_ctr_q_reg[4]), .I3(reinteg_ctr_q_reg[6]), .I4(\curr_state[5]_i_28_n_0 ), .O(\reinteg_ctr_q_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair281" *) LUT4 #( .INIT(16'hFFFD)) \curr_state[5]_i_28 (.I0(reinteg_ctr_q_reg[7]), .I1(reinteg_ctr_q_reg[0]), .I2(reinteg_ctr_q_reg[3]), .I3(reinteg_ctr_q_reg[1]), .O(\curr_state[5]_i_28_n_0 )); (* SOFT_HLUTNM = "soft_lutpair283" *) LUT2 #( .INIT(4'h1)) \reinteg_ctr_q[0]_i_1 (.I0(reinteg_ctr_q_reg[0]), .I1(\reinteg_ctr_q_reg[0]_0 ), .O(reinteg_ctr_d[0])); (* SOFT_HLUTNM = "soft_lutpair281" *) LUT3 #( .INIT(8'h06)) \reinteg_ctr_q[1]_i_1 (.I0(reinteg_ctr_q_reg[1]), .I1(reinteg_ctr_q_reg[0]), .I2(\reinteg_ctr_q_reg[0]_0 ), .O(reinteg_ctr_d[1])); (* SOFT_HLUTNM = "soft_lutpair283" *) LUT4 #( .INIT(16'h0078)) \reinteg_ctr_q[2]_i_1 (.I0(reinteg_ctr_q_reg[0]), .I1(reinteg_ctr_q_reg[1]), .I2(reinteg_ctr_q_reg[2]), .I3(\reinteg_ctr_q_reg[0]_0 ), .O(reinteg_ctr_d[2])); LUT5 #( .INIT(32'h2AAA8000)) \reinteg_ctr_q[3]_i_1 (.I0(\reinteg_ctr_q_reg[3]_0 ), .I1(reinteg_ctr_q_reg[2]), .I2(reinteg_ctr_q_reg[1]), .I3(reinteg_ctr_q_reg[0]), .I4(reinteg_ctr_q_reg[3]), .O(reinteg_ctr_d[3])); LUT6 #( .INIT(64'h2AAAAAAA80000000)) \reinteg_ctr_q[4]_i_1 (.I0(\reinteg_ctr_q_reg[3]_0 ), .I1(reinteg_ctr_q_reg[0]), .I2(reinteg_ctr_q_reg[1]), .I3(reinteg_ctr_q_reg[2]), .I4(reinteg_ctr_q_reg[3]), .I5(reinteg_ctr_q_reg[4]), .O(reinteg_ctr_d[4])); LUT3 #( .INIT(8'h28)) \reinteg_ctr_q[5]_i_1 (.I0(\reinteg_ctr_q_reg[3]_0 ), .I1(\reinteg_ctr_q[5]_i_2_n_0 ), .I2(reinteg_ctr_q_reg[5]), .O(reinteg_ctr_d[5])); LUT5 #( .INIT(32'h80000000)) \reinteg_ctr_q[5]_i_2 (.I0(reinteg_ctr_q_reg[3]), .I1(reinteg_ctr_q_reg[2]), .I2(reinteg_ctr_q_reg[1]), .I3(reinteg_ctr_q_reg[0]), .I4(reinteg_ctr_q_reg[4]), .O(\reinteg_ctr_q[5]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair282" *) LUT3 #( .INIT(8'h28)) \reinteg_ctr_q[6]_i_1 (.I0(\reinteg_ctr_q_reg[3]_0 ), .I1(\reinteg_ctr_q[7]_i_4_n_0 ), .I2(reinteg_ctr_q_reg[6]), .O(reinteg_ctr_d[6])); (* SOFT_HLUTNM = "soft_lutpair282" *) LUT4 #( .INIT(16'h2A80)) \reinteg_ctr_q[7]_i_2 (.I0(\reinteg_ctr_q_reg[3]_0 ), .I1(reinteg_ctr_q_reg[6]), .I2(\reinteg_ctr_q[7]_i_4_n_0 ), .I3(reinteg_ctr_q_reg[7]), .O(reinteg_ctr_d[7])); LUT6 #( .INIT(64'h8000000000000000)) \reinteg_ctr_q[7]_i_4 (.I0(reinteg_ctr_q_reg[4]), .I1(reinteg_ctr_q_reg[0]), .I2(reinteg_ctr_q_reg[1]), .I3(reinteg_ctr_q_reg[2]), .I4(reinteg_ctr_q_reg[3]), .I5(reinteg_ctr_q_reg[5]), .O(\reinteg_ctr_q[7]_i_4_n_0 )); FDCE \reinteg_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[0]), .Q(reinteg_ctr_q_reg[0])); FDCE \reinteg_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[1]), .Q(reinteg_ctr_q_reg[1])); FDCE \reinteg_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[2]), .Q(reinteg_ctr_q_reg[2])); FDCE \reinteg_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[3]), .Q(reinteg_ctr_q_reg[3])); FDCE \reinteg_ctr_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[4]), .Q(reinteg_ctr_q_reg[4])); FDCE \reinteg_ctr_q_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[5]), .Q(reinteg_ctr_q_reg[5])); FDCE \reinteg_ctr_q_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[6]), .Q(reinteg_ctr_q_reg[6])); FDCE \reinteg_ctr_q_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(reinteg_ctr_ce), .CLR(\reinteg_ctr_q_reg[7]_0 ), .D(reinteg_ctr_d[7]), .Q(reinteg_ctr_q_reg[7])); endmodule module mac_pc_retransmitt_counter (\retr_ctr_q_reg[3]_0 , D, retr_ctr_add, E, clk_sys_IBUF_BUFG, \retr_ctr_q_reg[3]_1 ); output [3:0]\retr_ctr_q_reg[3]_0 ; input [0:0]D; input retr_ctr_add; input [0:0]E; input clk_sys_IBUF_BUFG; input \retr_ctr_q_reg[3]_1 ; wire [0:0]D; wire [0:0]E; wire clk_sys_IBUF_BUFG; wire retr_ctr_add; wire [3:1]retr_ctr_d; wire [3:0]\retr_ctr_q_reg[3]_0 ; wire \retr_ctr_q_reg[3]_1 ; LUT3 #( .INIT(8'h28)) \retr_ctr_q[1]_i_1 (.I0(retr_ctr_add), .I1(\retr_ctr_q_reg[3]_0 [1]), .I2(\retr_ctr_q_reg[3]_0 [0]), .O(retr_ctr_d[1])); (* SOFT_HLUTNM = "soft_lutpair284" *) LUT4 #( .INIT(16'h2A80)) \retr_ctr_q[2]_i_1 (.I0(retr_ctr_add), .I1(\retr_ctr_q_reg[3]_0 [0]), .I2(\retr_ctr_q_reg[3]_0 [1]), .I3(\retr_ctr_q_reg[3]_0 [2]), .O(retr_ctr_d[2])); (* SOFT_HLUTNM = "soft_lutpair284" *) LUT5 #( .INIT(32'h2AAA8000)) \retr_ctr_q[3]_i_2 (.I0(retr_ctr_add), .I1(\retr_ctr_q_reg[3]_0 [2]), .I2(\retr_ctr_q_reg[3]_0 [1]), .I3(\retr_ctr_q_reg[3]_0 [0]), .I4(\retr_ctr_q_reg[3]_0 [3]), .O(retr_ctr_d[3])); FDCE \retr_ctr_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\retr_ctr_q_reg[3]_1 ), .D(D), .Q(\retr_ctr_q_reg[3]_0 [0])); FDCE \retr_ctr_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\retr_ctr_q_reg[3]_1 ), .D(retr_ctr_d[1]), .Q(\retr_ctr_q_reg[3]_0 [1])); FDCE \retr_ctr_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\retr_ctr_q_reg[3]_1 ), .D(retr_ctr_d[2]), .Q(\retr_ctr_q_reg[3]_0 [2])); FDCE \retr_ctr_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\retr_ctr_q_reg[3]_1 ), .D(retr_ctr_d[3]), .Q(\retr_ctr_q_reg[3]_0 [3])); endmodule module mac_pc_rx_shift_reg (rec_brs, \rec_dlc_reg[2]_0 , Q, \rec_dlc_reg[2]_1 , rec_frame_type_i_reg_0, \rec_dlc_reg[1]_0 , \rec_dlc_reg[3]_0 , rec_is_rtr_i_reg_0, \g_bit[0].reg_value_r_reg[0] , \rec_dlc_reg[1]_1 , \g_byte_shift_reg[0].shift_reg_q_reg[0][1] , \g_byte_shift_reg[0].shift_reg_q_reg[0][7] , rec_is_rtr, reg_q_reg, \FSM_sequential_curr_state_reg[1] , \g_byte_shift_reg[0].shift_reg_q_reg[0][2] , \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 , \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 , S, \g_byte_shift_reg[1].shift_reg_q_reg[1][6] , D, \g_byte_shift_reg[2].shift_reg_q_reg[2][0] , store_data_word, \g_byte_shift_reg[0].shift_reg_q_reg[0][5] , \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 , reg_q_reg_0, \rec_ident_reg[28]_0 , rec_ident_type, rec_esi, reg_q_reg_1, clk_sys_IBUF_BUFG, reg_q_reg_2, rec_brs_reg_0, \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_i_55_0 , crc_match_q_i_3, \mr_ctrl_out[settings_nisofd] , \cc_stat[dst_ctr] , \cc_stat[is_receiver] , \g_byte_shift_reg[0].shift_reg_q_reg[0][0] , \ctrl_ctr_q_reg[8] , \ctrl_ctr_q_reg[5] , \ctrl_ctr_q_reg[8]_0 , \ctrl_ctr_q_reg[8]_1 , \ctrl_ctr_q_reg[5]_0 , \ctrl_ctr_q_reg[5]_1 , \ctrl_ctr_q_reg[5]_2 , crc_match_c6_carry__0, crc_match_c5_carry__0, \crc_match_c6_inferred__0/i__carry , scan_mode_IBUF, rst_n_out_OBUF, \ctrl_ctr_q_reg[8]_2 , \ctrl_ctr_q_reg[8]_3 , \ctrl_ctr_q_reg[8]_4 , rx_shift_cmd, \g_byte_shift_reg[1].shift_reg_q_reg[1][0] , \g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 , \g_byte_shift_reg[3].shift_reg_q_reg[3][0] , E, \rec_dlc_reg[0]_0 , rec_esi_reg_0, rec_frame_type_i_reg_1, rec_frame_type_i_reg_2, rec_is_rtr_i_reg_1, rec_ident_type_reg_0, rec_ident_type_reg_1, rec_ident_type_reg_2, rec_esi_reg_1, rec_esi_reg_2, \rx_stuff_count_reg[3]_0 ); output rec_brs; output \rec_dlc_reg[2]_0 ; output [3:0]Q; output \rec_dlc_reg[2]_1 ; output rec_frame_type_i_reg_0; output \rec_dlc_reg[1]_0 ; output \rec_dlc_reg[3]_0 ; output rec_is_rtr_i_reg_0; output \g_bit[0].reg_value_r_reg[0] ; output \rec_dlc_reg[1]_1 ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][1] ; output [7:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][7] ; output rec_is_rtr; output reg_q_reg; output \FSM_sequential_curr_state_reg[1] ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2] ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 ; output [0:0]S; output [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][6] ; output [8:0]D; output [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0] ; output [14:0]store_data_word; output [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][5] ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 ; output [0:0]reg_q_reg_0; output [28:0]\rec_ident_reg[28]_0 ; output rec_ident_type; output rec_esi; input reg_q_reg_1; input clk_sys_IBUF_BUFG; input reg_q_reg_2; input rec_brs_reg_0; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \g_ram_rst_false.ram_memory_reg_2 ; input [0:0]\g_ram_rst_false.ram_memory_reg_i_55_0 ; input crc_match_q_i_3; input \mr_ctrl_out[settings_nisofd] ; input [2:0]\cc_stat[dst_ctr] ; input \cc_stat[is_receiver] ; input [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; input \ctrl_ctr_q_reg[8] ; input \ctrl_ctr_q_reg[5] ; input \ctrl_ctr_q_reg[8]_0 ; input \ctrl_ctr_q_reg[8]_1 ; input \ctrl_ctr_q_reg[5]_0 ; input [1:0]\ctrl_ctr_q_reg[5]_1 ; input \ctrl_ctr_q_reg[5]_2 ; input [5:0]crc_match_c6_carry__0; input [2:0]crc_match_c5_carry__0; input [2:0]\crc_match_c6_inferred__0/i__carry ; input scan_mode_IBUF; input rst_n_out_OBUF; input \ctrl_ctr_q_reg[8]_2 ; input \ctrl_ctr_q_reg[8]_3 ; input \ctrl_ctr_q_reg[8]_4 ; input [3:0]rx_shift_cmd; input [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][0] ; input [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 ; input [0:0]\g_byte_shift_reg[3].shift_reg_q_reg[3][0] ; input [1:0]E; input [0:0]\rec_dlc_reg[0]_0 ; input [3:0]rec_esi_reg_0; input rec_frame_type_i_reg_1; input rec_frame_type_i_reg_2; input rec_is_rtr_i_reg_1; input rec_ident_type_reg_0; input rec_ident_type_reg_1; input rec_ident_type_reg_2; input rec_esi_reg_1; input rec_esi_reg_2; input [0:0]\rx_stuff_count_reg[3]_0 ; wire [8:0]D; wire [1:0]E; wire \FSM_sequential_curr_state_reg[1] ; wire [3:0]Q; wire [0:0]S; wire [2:0]\cc_stat[dst_ctr] ; wire \cc_stat[is_receiver] ; wire clk_sys_IBUF_BUFG; wire [2:0]crc_match_c5_carry__0; wire [5:0]crc_match_c6_carry__0; wire [2:0]\crc_match_c6_inferred__0/i__carry ; wire crc_match_q_i_3; wire crc_match_q_i_6_n_0; wire \ctrl_ctr_q_reg[5] ; wire \ctrl_ctr_q_reg[5]_0 ; wire [1:0]\ctrl_ctr_q_reg[5]_1 ; wire \ctrl_ctr_q_reg[5]_2 ; wire \ctrl_ctr_q_reg[8] ; wire \ctrl_ctr_q_reg[8]_0 ; wire \ctrl_ctr_q_reg[8]_1 ; wire \ctrl_ctr_q_reg[8]_2 ; wire \ctrl_ctr_q_reg[8]_3 ; wire \ctrl_ctr_q_reg[8]_4 ; wire \g_bit[0].reg_value_r_reg[0] ; wire [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][1] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 ; wire [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][5] ; wire [7:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][7] ; wire [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][0] ; wire [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][6] ; wire [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0] ; wire [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 ; wire [0:0]\g_byte_shift_reg[3].shift_reg_q_reg[3][0] ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_i_121_n_0 ; wire [0:0]\g_ram_rst_false.ram_memory_reg_i_55_0 ; wire i_rx_shift_res_reg_n_0; wire \mr_ctrl_out[settings_nisofd] ; wire rec_brs; wire rec_brs_reg_0; wire [0:0]\rec_dlc_reg[0]_0 ; wire \rec_dlc_reg[1]_0 ; wire \rec_dlc_reg[1]_1 ; wire \rec_dlc_reg[2]_0 ; wire \rec_dlc_reg[2]_1 ; wire \rec_dlc_reg[3]_0 ; wire rec_esi; wire rec_esi_i_1_n_0; wire [3:0]rec_esi_reg_0; wire rec_esi_reg_1; wire rec_esi_reg_2; wire rec_frame_type_i_i_1_n_0; wire rec_frame_type_i_reg_0; wire rec_frame_type_i_reg_1; wire rec_frame_type_i_reg_2; wire [28:0]\rec_ident_reg[28]_0 ; wire rec_ident_type; wire rec_ident_type_i_1_n_0; wire rec_ident_type_reg_0; wire rec_ident_type_reg_1; wire rec_ident_type_reg_2; wire rec_is_rtr; wire rec_is_rtr_i_i_1_n_0; wire rec_is_rtr_i_reg_0; wire rec_is_rtr_i_reg_1; wire reg_q_reg; wire [0:0]reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire rst_n_out_OBUF; wire [3:0]rx_shift_cmd; wire [3:0]rx_stuff_count; wire [0:0]\rx_stuff_count_reg[3]_0 ; wire scan_mode_IBUF; wire [14:0]store_data_word; LUT6 #( .INIT(64'h1110101110111110)) crc_match_q_i_5 (.I0(crc_match_q_i_3), .I1(\mr_ctrl_out[settings_nisofd] ), .I2(crc_match_q_i_6_n_0), .I3(\cc_stat[dst_ctr] [1]), .I4(rx_stuff_count[2]), .I5(\cc_stat[dst_ctr] [2]), .O(\g_bit[0].reg_value_r_reg[0] )); LUT6 #( .INIT(64'hFF7DBEFF7DFFFFBE)) crc_match_q_i_6 (.I0(rx_stuff_count[0]), .I1(\cc_stat[dst_ctr] [2]), .I2(rx_stuff_count[3]), .I3(\cc_stat[dst_ctr] [1]), .I4(\cc_stat[dst_ctr] [0]), .I5(rx_stuff_count[1]), .O(crc_match_q_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair286" *) LUT3 #( .INIT(8'h45)) \g_ram_rst_false.ram_memory_reg_i_121 (.I0(\g_ram_rst_false.ram_memory_reg_i_55_0 ), .I1(rec_frame_type_i_reg_0), .I2(rec_is_rtr_i_reg_0), .O(\g_ram_rst_false.ram_memory_reg_i_121_n_0 )); (* SOFT_HLUTNM = "soft_lutpair286" *) LUT2 #( .INIT(4'h2)) \g_ram_rst_false.ram_memory_reg_i_124 (.I0(rec_is_rtr_i_reg_0), .I1(rec_frame_type_i_reg_0), .O(rec_is_rtr)); LUT6 #( .INIT(64'h000000000000FF95)) \g_ram_rst_false.ram_memory_reg_i_49__2 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 ), .I5(\g_ram_rst_false.ram_memory_reg_1 ), .O(\rec_dlc_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFFFE2010001)) \g_ram_rst_false.ram_memory_reg_i_50__0 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .I4(rec_frame_type_i_reg_0), .I5(\g_ram_rst_false.ram_memory_reg_2 ), .O(\rec_dlc_reg[2]_1 )); LUT6 #( .INIT(64'h2AAA2A2A2A2AAA88)) \g_ram_rst_false.ram_memory_reg_i_52 (.I0(\g_ram_rst_false.ram_memory_reg_i_121_n_0 ), .I1(Q[3]), .I2(rec_frame_type_i_reg_0), .I3(Q[2]), .I4(Q[1]), .I5(Q[0]), .O(\rec_dlc_reg[3]_0 )); LUT6 #( .INIT(64'h3000336600000000)) \g_ram_rst_false.ram_memory_reg_i_55 (.I0(Q[1]), .I1(Q[2]), .I2(rec_frame_type_i_reg_0), .I3(Q[0]), .I4(Q[3]), .I5(\g_ram_rst_false.ram_memory_reg_i_121_n_0 ), .O(\rec_dlc_reg[1]_0 )); rst_reg_58 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg(i_rx_shift_res_reg_n_0), .reg_q_reg_0(reg_q_reg_1), .reg_q_reg_1(reg_q_reg_2), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); shift_reg_byte i_shift_reg_byte (.D({D[8:7],\g_byte_shift_reg[0].shift_reg_q_reg[0][7] ,D[6:0]}), .\FSM_sequential_curr_state_reg[1] (\FSM_sequential_curr_state_reg[1] ), .S(S), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_match_c5_carry__0(crc_match_c5_carry__0), .crc_match_c6_carry__0(crc_match_c6_carry__0), .\crc_match_c6_inferred__0/i__carry (\crc_match_c6_inferred__0/i__carry ), .\ctrl_ctr_q_reg[5] (\ctrl_ctr_q_reg[5] ), .\ctrl_ctr_q_reg[5]_0 (\ctrl_ctr_q_reg[5]_0 ), .\ctrl_ctr_q_reg[5]_1 (rec_frame_type_i_reg_0), .\ctrl_ctr_q_reg[5]_2 (\ctrl_ctr_q_reg[5]_1 ), .\ctrl_ctr_q_reg[5]_3 (\ctrl_ctr_q_reg[5]_2 ), .\ctrl_ctr_q_reg[8] (\ctrl_ctr_q_reg[8] ), .\ctrl_ctr_q_reg[8]_0 (\ctrl_ctr_q_reg[8]_0 ), .\ctrl_ctr_q_reg[8]_1 (\ctrl_ctr_q_reg[8]_1 ), .\ctrl_ctr_q_reg[8]_2 (\ctrl_ctr_q_reg[8]_2 ), .\ctrl_ctr_q_reg[8]_3 (\ctrl_ctr_q_reg[8]_3 ), .\ctrl_ctr_q_reg[8]_4 (\ctrl_ctr_q_reg[8]_4 ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 (\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 (\g_byte_shift_reg[0].shift_reg_q_reg[0][1] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_1 (\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 (\g_byte_shift_reg[0].shift_reg_q_reg[0][2] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 (\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_2 (\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][5]_0 (\g_byte_shift_reg[0].shift_reg_q_reg[0][5] ), .\g_byte_shift_reg[1].shift_reg_q_reg[1][0]_0 (\g_byte_shift_reg[1].shift_reg_q_reg[1][0] ), .\g_byte_shift_reg[1].shift_reg_q_reg[1][6]_0 (\g_byte_shift_reg[1].shift_reg_q_reg[1][6] ), .\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 (\g_byte_shift_reg[2].shift_reg_q_reg[2][0] ), .\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_1 (\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 ), .\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 (i_rx_shift_res_reg_n_0), .\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_1 (\g_byte_shift_reg[3].shift_reg_q_reg[3][0] ), .rec_is_rtr(rec_is_rtr), .reg_q_reg(reg_q_reg), .reg_q_reg_0(reg_q_reg_0), .rx_shift_cmd(rx_shift_cmd), .store_data_word(store_data_word)); FDCE rec_brs_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rx_shift_res_reg_n_0), .D(rec_brs_reg_0), .Q(rec_brs)); FDCE \rec_dlc_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\rec_dlc_reg[0]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .Q(Q[0])); FDCE \rec_dlc_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\rec_dlc_reg[0]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [0]), .Q(Q[1])); FDCE \rec_dlc_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\rec_dlc_reg[0]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [1]), .Q(Q[2])); FDCE \rec_dlc_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\rec_dlc_reg[0]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [2]), .Q(Q[3])); LUT6 #( .INIT(64'hFFBFFFFF00800000)) rec_esi_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(rec_ident_type_reg_1), .I2(rec_esi_reg_1), .I3(rec_esi_reg_0[3]), .I4(rec_esi_reg_2), .I5(rec_esi), .O(rec_esi_i_1_n_0)); FDCE rec_esi_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rx_shift_res_reg_n_0), .D(rec_esi_i_1_n_0), .Q(rec_esi)); LUT6 #( .INIT(64'hEBFFFFFF28000000)) rec_frame_type_i_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(rec_esi_reg_0[1]), .I2(rec_esi_reg_0[0]), .I3(rec_frame_type_i_reg_1), .I4(rec_frame_type_i_reg_2), .I5(rec_frame_type_i_reg_0), .O(rec_frame_type_i_i_1_n_0)); FDCE rec_frame_type_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rx_shift_res_reg_n_0), .D(rec_frame_type_i_i_1_n_0), .Q(rec_frame_type_i_reg_0)); FDCE \rec_ident_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .Q(\rec_ident_reg[28]_0 [0])); FDCE \rec_ident_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[8]), .Q(\rec_ident_reg[28]_0 [10])); FDCE \rec_ident_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[0]), .Q(\rec_ident_reg[28]_0 [11])); FDCE \rec_ident_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[1]), .Q(\rec_ident_reg[28]_0 [12])); FDCE \rec_ident_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[2]), .Q(\rec_ident_reg[28]_0 [13])); FDCE \rec_ident_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[3]), .Q(\rec_ident_reg[28]_0 [14])); FDCE \rec_ident_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[4]), .Q(\rec_ident_reg[28]_0 [15])); FDCE \rec_ident_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[5]), .Q(\rec_ident_reg[28]_0 [16])); FDCE \rec_ident_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[6]), .Q(\rec_ident_reg[28]_0 [17])); FDCE \rec_ident_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .Q(\rec_ident_reg[28]_0 [18])); FDCE \rec_ident_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [0]), .Q(\rec_ident_reg[28]_0 [19])); FDCE \rec_ident_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [0]), .Q(\rec_ident_reg[28]_0 [1])); FDCE \rec_ident_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [1]), .Q(\rec_ident_reg[28]_0 [20])); FDCE \rec_ident_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [2]), .Q(\rec_ident_reg[28]_0 [21])); FDCE \rec_ident_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [3]), .Q(\rec_ident_reg[28]_0 [22])); FDCE \rec_ident_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [4]), .Q(\rec_ident_reg[28]_0 [23])); FDCE \rec_ident_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [5]), .Q(\rec_ident_reg[28]_0 [24])); FDCE \rec_ident_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [6]), .Q(\rec_ident_reg[28]_0 [25])); FDCE \rec_ident_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [7]), .Q(\rec_ident_reg[28]_0 [26])); FDCE \rec_ident_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(D[7]), .Q(\rec_ident_reg[28]_0 [27])); FDCE \rec_ident_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(E[1]), .CLR(i_rx_shift_res_reg_n_0), .D(D[8]), .Q(\rec_ident_reg[28]_0 [28])); FDCE \rec_ident_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [1]), .Q(\rec_ident_reg[28]_0 [2])); FDCE \rec_ident_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [2]), .Q(\rec_ident_reg[28]_0 [3])); FDCE \rec_ident_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [3]), .Q(\rec_ident_reg[28]_0 [4])); FDCE \rec_ident_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [4]), .Q(\rec_ident_reg[28]_0 [5])); FDCE \rec_ident_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [5]), .Q(\rec_ident_reg[28]_0 [6])); FDCE \rec_ident_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [6]), .Q(\rec_ident_reg[28]_0 [7])); FDCE \rec_ident_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [7]), .Q(\rec_ident_reg[28]_0 [8])); FDCE \rec_ident_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(E[0]), .CLR(i_rx_shift_res_reg_n_0), .D(D[7]), .Q(\rec_ident_reg[28]_0 [9])); LUT6 #( .INIT(64'hFFBFFFFF00800000)) rec_ident_type_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(rec_ident_type_reg_0), .I2(rec_ident_type_reg_1), .I3(rec_esi_reg_0[3]), .I4(rec_ident_type_reg_2), .I5(rec_ident_type), .O(rec_ident_type_i_1_n_0)); FDCE rec_ident_type_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rx_shift_res_reg_n_0), .D(rec_ident_type_i_1_n_0), .Q(rec_ident_type)); LUT6 #( .INIT(64'hFBFFFFBF08000080)) rec_is_rtr_i_i_1 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .I1(rec_is_rtr_i_reg_1), .I2(rec_esi_reg_0[2]), .I3(rec_esi_reg_0[1]), .I4(rec_esi_reg_0[0]), .I5(rec_is_rtr_i_reg_0), .O(rec_is_rtr_i_i_1_n_0)); FDCE rec_is_rtr_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rx_shift_res_reg_n_0), .D(rec_is_rtr_i_i_1_n_0), .Q(rec_is_rtr_i_reg_0)); FDCE \rx_stuff_count_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\rx_stuff_count_reg[3]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .Q(rx_stuff_count[0])); FDCE \rx_stuff_count_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\rx_stuff_count_reg[3]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [0]), .Q(rx_stuff_count[1])); FDCE \rx_stuff_count_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\rx_stuff_count_reg[3]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [1]), .Q(rx_stuff_count[2])); FDCE \rx_stuff_count_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\rx_stuff_count_reg[3]_0 ), .CLR(i_rx_shift_res_reg_n_0), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][7] [2]), .Q(rx_stuff_count[3])); LUT6 #( .INIT(64'hF800000000000000)) \shift_regs[16]_i_7 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(\cc_stat[is_receiver] ), .I4(rec_frame_type_i_reg_0), .I5(Q[3]), .O(\rec_dlc_reg[1]_1 )); endmodule module mac_pc_top (store_metadata_reg, rec_valid_reg, rec_abort_reg, err_frm_req_reg, \txtb_hw_cmd_q_reg[lock] , \txtb_hw_cmd_q_reg[valid] , \txtb_hw_cmd_q_reg[failed] , \cc_stat[err_erp] , E, rx_data_nbs_prev, rec_lbpf, rec_brs, D, \curr_state_reg[2] , \timestamp[8] , \timestamp[14] , \timestamp[17] , \timestamp[7] , Q, \timestamp[41] , \timestamp[42] , \timestamp[43] , \err_capt_err_type_q_reg[0] , \err_capt_err_type_q_reg[2] , err_capt_err_erp_reg, \err_capt_err_pos_q_reg[0] , \err_capt_err_pos_q_reg[3] , rec_abort_reg_0, rec_valid_reg_0, \FSM_onehot_curr_state_reg[5] , \rec_dlc_reg[2] , \rec_dlc_reg[3] , \FSM_onehot_curr_state_reg[5]_0 , \g_bit[0].reg_value_r_reg[0] , ident_valid_q_reg, \rec_dlc_reg[2]_0 , rec_frame_type_i_reg, \rec_dlc_reg[1] , \rec_dlc_reg[3]_0 , rec_is_rtr_i_reg, \txtb_hw_cmd_q_reg[failed]_0 , \txtb_hw_cmd_q_reg[err] , \txtb_hw_cmd_q_reg[failed]_1 , \txtb_hw_cmd_q_reg[failed]_2 , \txtb_hw_cmd_q_reg[failed]_3 , \txtb_hw_cmd_q_reg[lock]_0 , \txtb_hw_cmd_q_reg[failed]_4 , \txtb_hw_cmd_q_reg[failed]_5 , \txtb_hw_cmd_q_reg[failed]_6 , \txtb_hw_cmd_q_reg[lock]_1 , \FSM_sequential_curr_state_reg[0] , \txtb_hw_cmd_q_reg[valid]_0 , \txtb_hw_cmd_q_reg[valid]_1 , rec_abort_f, \curr_state_reg[2]_0 , \curr_state_reg[0] , err_frm_req_reg_0, \ctrl_ctr_q_reg[7] , \curr_state_reg[1] , \curr_state_reg[2]_1 , reg_q_reg, \curr_state_reg[0]_0 , mr_ctr_pres_efd_q_reg, \g_bit[0].reg_value_r_reg[0]_0 , mr_ctr_pres_enorm_q_reg, \sp_control_q_i_reg[1] , \curr_state_reg[1]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , \pc_dbg[is_arbitration] , \retr_ctr_q_reg[3] , reg_q_reg_0, reg_q_reg_1, reg_q_reg_2, \curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1] , reg_q_reg_3, reg_q_reg_4, stuff_enable, tx_frame_no_sof, \FSM_onehot_current_state_reg[2] , \sp_control_q_i_reg[0] , reg_q_reg_5, stuff_err_d, destuff_enable, prev_val_d, bds_data_in, br_shifted, \curr_state_reg[4] , \curr_state_reg[2]_2 , \curr_state_reg[0]_1 , \rec_dlc_reg[1]_0 , bit_err_enable, \g_byte_shift_reg[0].shift_reg_q_reg[0][1] , \g_byte_shift_reg[1].shift_reg_q_reg[1][1] , rec_is_rtr, \txtb_hw_cmd_q_reg[valid]_2 , tx_frame_no_sof_q_reg, err_frm_req_reg_1, p_131_in, tran_delay_meas, \compl_ctr_q_reg[7] , \txtb_ptr_q_reg[4] , \curr_state_reg[5] , store_data_word, err_frm_req_reg_2, \curr_state_reg[5]_0 , \g_byte_shift_reg[0].shift_reg_q_reg[0][2] , err_frm_req_reg_3, \curr_state_reg[5]_1 , \tq_counter_q_reg[7] , \sync_control_q_reg[0] , \sync_control_q_reg[1] , \sp_control_q_i_reg[0]_0 , first_ssp_q0, p_0_out, \txtb_hw_cmd_q_reg[lock]_2 , err_frm_req_reg_4, \curr_state_reg[5]_2 , \g_bit[1].reg_value_r_reg[1] , reg_q_reg_6, err_frm_req_reg_5, \curr_state_reg[0]_2 , \curr_state_reg[3] , err_frm_req_reg_6, \curr_state_reg[3]_0 , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , \crc_q_reg[14] , \sync_control_q_reg[0]_0 , int_status_reg, sspc_ena_q_reg, btmc_meas_running_q_reg, \cc_stat[status_pexs] , rec_ivld, \alc_alc_bit_reg[4] , \alc_alc_id_field_reg[2] , \rec_ident_reg[28] , rec_ident_type, rec_esi, store_metadata_reg_0, clk_sys_IBUF_BUFG, \shift_regs_reg[0] , \txtb_hw_cmd_q[err] , \cc_stat[is_err_passive] , reg_q_reg_7, S, crc_match_q_i_2, crc_match_c5_carry__0, crc_match_q_i_3, \crc_match_c6_inferred__0/i__carry__0 , crc_match_q_i_2_0, rx_data_nbs_prev_reg, rec_lbpf_q_reg, rec_brs_reg, sbe_IBUF, adress_IBUF, \r_data_reg[19] , \r_data_reg[16] , \r_data_reg[16]_0 , \r_data_reg[16]_1 , \r_data_reg[15] , \r_data_reg[15]_0 , \r_data_reg[15]_1 , \r_data_reg[15]_2 , \r_data_reg[13] , \r_data_reg[13]_0 , \r_data_reg[13]_1 , \r_data_reg[13]_2 , \r_data_reg[13]_3 , \r_data_reg[13]_4 , \r_data_reg[18] , \r_data_reg[18]_0 , \r_data_reg[18]_1 , \r_data_reg[18]_2 , \r_data_reg[18]_3 , \r_data_reg[12] , \r_data_reg[12]_0 , timestamp_IBUF, \r_data_reg[19]_0 , \r_data_reg[19]_1 , \mr_ctrl_out[settings_rtrth] , \err_capt_err_pos_q_reg[0]_0 , \r_data[7]_i_3__0 , \mr_ctrl_out[ssp_cfg_ssp_offset] , \r_data[19]_i_2 , \r_data_reg[18]_4 , \r_data_reg[18]_5 , \mr_tx_priority[1] , \r_data_reg[5]_i_5 , \mr_tx_priority[0] , \r_data[0]_i_5 , \g_ram_rst_false.ram_memory_reg_i_55 , ident_valid_q, \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \FSM_onehot_curr_state_reg[1] , \mr_ctrl_out[mode_erfm] , \mr_ctrl_out[rx_settings_rtsop] , \g_ram_rst_false.ram_memory_reg_2 , curr_state_0, int_status_i_4, \FSM_sequential_curr_state_reg[2] , abort_or_skipped, \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , curr_state_1, abort_applied, \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state[1]_i_2__0 , txtb_hw_cmd_cs, curr_state_2, \FSM_sequential_curr_state_reg[2]_1 , abort_or_skipped_3, \FSM_sequential_curr_state_reg[1]_4 , curr_state_4, abort_applied_5, \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state[1]_i_2__2 , curr_state_6, \FSM_sequential_curr_state[0]_i_7 , \FSM_sequential_curr_state[2]_i_3__3 , \FSM_sequential_curr_state[2]_i_3__3_0 , \FSM_sequential_curr_state[0]_i_7_0 , \shift_regs_reg[24] , tran_word, \shift_regs_reg[25] , \shift_regs_reg[25]_0 , \shift_regs_reg[26] , \shift_regs_reg[26]_0 , \shift_regs_reg[27] , \shift_regs_reg[28] , \shift_regs_reg[28]_0 , \shift_regs_reg[29] , \shift_regs_reg[29]_0 , \shift_regs_reg[30] , \shift_regs_reg[30]_0 , \shift_regs_reg[31] , \shift_regs_reg[31]_0 , \shift_regs_reg[31]_1 , \shift_regs_reg[16] , \shift_regs_reg[16]_0 , \shift_regs_reg[16]_1 , \shift_regs_reg[17] , \shift_regs_reg[17]_0 , \shift_regs_reg[18] , \shift_regs_reg[18]_0 , \shift_regs_reg[19] , \shift_regs_reg[19]_0 , \shift_regs_reg[20] , \shift_regs_reg[20]_0 , \shift_regs_reg[21] , \shift_regs_reg[21]_0 , \shift_regs_reg[22] , \shift_regs_reg[22]_0 , \shift_regs_reg[23] , \shift_regs_reg[11] , \shift_regs_reg[11]_0 , \shift_regs_reg[12] , \shift_regs_reg[12]_0 , \shift_regs_reg[13] , \shift_regs_reg[14] , \shift_regs_reg[14]_0 , \shift_regs_reg[15] , \shift_regs_reg[15]_0 , \shift_regs_reg[1] , \shift_regs_reg[2] , \shift_regs_reg[0]_0 , \shift_regs_reg[0]_1 , \rec_dlc_reg[0] , \cc_stat[is_bus_off] , \FSM_sequential_curr_state[1]_i_4__2 , tran_frame_valid, \curr_state_reg[4]_0 , \g_byte_shift_reg[0].shift_reg_q_reg[0][0] , tx_frame_no_sof_q_reg_0, tx_frame_no_sof_q_reg_1, rec_ivld_q_reg, \mr_ctrl_out[mode_rom] , \curr_state_reg[0]_3 , \curr_state[0]_i_3 , \txtb_hw_cmd_q_reg[lock]_3 , destuff_enable_reg, destuff_enable_reg_0, \shift_regs_reg[27]_0 , \shift_regs_reg[30]_1 , \shift_regs_reg[31]_2 , \crc_q_reg[0] , \FSM_sequential_curr_state[1]_i_2__4 , \curr_state[5]_i_5 , \retr_ctr_q_reg[3]_0 , mr_ctr_pres_efd_q, mr_ctr_pres_enorm_q, \cc_stat[is_receiver] , stuff_err, \sp_control_q_i_reg[1]_0 , tx_frame_no_sof_q_reg_2, tx_frame_no_sof_q_reg_3, \mr_ctrl_out[settings_rtrle] , rec_valid_reg_1, bit_err, can_tx_OBUF, \err_capt_err_type_q_reg[1] , \shift_regs_reg[28]_1 , \shift_regs_reg[28]_2 , \shift_regs_reg[28]_3 , \tran_frame_test[fcrc] , \shift_regs_reg[29]_1 , \shift_regs_reg[29]_2 , \ctrl_ctr_q_reg[6] , data_halt_d1_out, tx_trigger_q, crc_data_rx_wbs, \crc_q_reg[20] , \mr_ctrl_out[settings_ilbp] , enable_prev, btmc_meas_running_q_reg_0, is_tseg2, \same_bits_q_reg[2] , is_tseg1, reg_q_reg_8, fixed_prev_q, reg_q_reg_9, reg_q, sync_edge, \mr_ctrl_out[mode_fde] , \mr_ctrl_out[settings_pex] , \ctrl_ctr_q[3]_i_3 , \ctrl_ctr_q_reg[1] , \ctrl_ctr_q_reg[1]_0 , \mr_ctrl_out[ssp_cfg_ssp_src] , \curr_state[5]_i_10 , \txtb_hw_cmd_q_reg[arbl] , \alc_alc_bit_reg[0] , tran_ident_type, \err_capt_err_type_q[2]_i_8 , \ctrl_ctr_q[2]_i_3 , \shift_regs[31]_i_7 , \mr_ctrl_out[settings_ena] , \curr_state_reg[1]_2 , \ctrl_ctr_q_reg[4] , \mr_ctrl_out[settings_nisofd] , \curr_state[0]_i_3_0 , destuff_enable_reg_1, crc_match_q_reg, crc_match_q_i_2_1, \cc_stat[dst_ctr] , \ctrl_ctr_q_reg[5] , \curr_state_reg[4]_1 , \crc_q[14]_i_6 , tran_brs, bit_err_q_i_2, \crc_q[14]_i_11 , \mr_ctrl_out[mode_bmm] , reg_q_reg_10, tran_is_rtr, \txtb_ptr_q_reg[4]_0 , \txtb_ptr_q_reg[4]_1 , \txtb_ptr_q_reg[4]_2 , \ctrl_ctr_q_reg[8] , \ctrl_ctr_q_reg[8]_0 , \ctrl_ctr_q_reg[5]_0 , \ctrl_ctr_q_reg[5]_1 , \ctrl_ctr_q[8]_i_11 , \ctrl_ctr_q[8]_i_11_0 , destuff_enable_reg_2, \timestamp_capture_reg[63] , \mr_ctrl_out[mode_stm] , \curr_state[1]_i_4 , reg_q_reg_11, rx_data_wbs, crc_match_c6_carry__0, crc_match_c5_carry__0_0, \crc_q_reg[14]_0 , scan_mode_IBUF, rst_n_out_OBUF, \segm_counter_q_reg[0] , \segm_counter_q_reg[0]_0 , \segm_counter_q_reg[0]_1 , \exp_seg_length_q_reg[0] , \exp_seg_length_q_reg[0]_0 , sync_edge3__0, \segm_counter_q_reg[0]_2 , rx_data_sync_prev_reg, tx_data_prev, \crc_q_reg[0]_0 , \ctrl_ctr_q_reg[4]_0 , \ctrl_ctr_q[3]_i_3_0 , \FSM_sequential_curr_state_reg[0]_0 , sync_flag, int_status_reg_0, data_in_IBUF, int_status_reg_1, mr_int_stat_txbhci_o, sspc_ena_q, btmc_meas_running_q, mr_status_pexs_reg, mr_status_pexs_reg_0, \shift_regs_reg[0]_2 , txtb_allow_bb, int_status_i_2__1, int_status_i_2__1_0, int_status_reg_2); output store_metadata_reg; output rec_valid_reg; output rec_abort_reg; output err_frm_req_reg; output \txtb_hw_cmd_q_reg[lock] ; output \txtb_hw_cmd_q_reg[valid] ; output \txtb_hw_cmd_q_reg[failed] ; output \cc_stat[err_erp] ; output [0:0]E; output rx_data_nbs_prev; output rec_lbpf; output rec_brs; output [4:0]D; output \curr_state_reg[2] ; output \timestamp[8] ; output \timestamp[14] ; output \timestamp[17] ; output \timestamp[7] ; output [3:0]Q; output \timestamp[41] ; output \timestamp[42] ; output \timestamp[43] ; output \err_capt_err_type_q_reg[0] ; output [2:0]\err_capt_err_type_q_reg[2] ; output err_capt_err_erp_reg; output \err_capt_err_pos_q_reg[0] ; output [3:0]\err_capt_err_pos_q_reg[3] ; output rec_abort_reg_0; output [2:0]rec_valid_reg_0; output \FSM_onehot_curr_state_reg[5] ; output \rec_dlc_reg[2] ; output [3:0]\rec_dlc_reg[3] ; output \FSM_onehot_curr_state_reg[5]_0 ; output \g_bit[0].reg_value_r_reg[0] ; output [0:0]ident_valid_q_reg; output \rec_dlc_reg[2]_0 ; output rec_frame_type_i_reg; output \rec_dlc_reg[1] ; output \rec_dlc_reg[3]_0 ; output rec_is_rtr_i_reg; output \txtb_hw_cmd_q_reg[failed]_0 ; output \txtb_hw_cmd_q_reg[err] ; output \txtb_hw_cmd_q_reg[failed]_1 ; output \txtb_hw_cmd_q_reg[failed]_2 ; output \txtb_hw_cmd_q_reg[failed]_3 ; output \txtb_hw_cmd_q_reg[lock]_0 ; output \txtb_hw_cmd_q_reg[failed]_4 ; output \txtb_hw_cmd_q_reg[failed]_5 ; output \txtb_hw_cmd_q_reg[failed]_6 ; output \txtb_hw_cmd_q_reg[lock]_1 ; output \FSM_sequential_curr_state_reg[0] ; output \txtb_hw_cmd_q_reg[valid]_0 ; output \txtb_hw_cmd_q_reg[valid]_1 ; output rec_abort_f; output \curr_state_reg[2]_0 ; output \curr_state_reg[0] ; output [0:0]err_frm_req_reg_0; output \ctrl_ctr_q_reg[7] ; output \curr_state_reg[1] ; output \curr_state_reg[2]_1 ; output reg_q_reg; output \curr_state_reg[0]_0 ; output [0:0]mr_ctr_pres_efd_q_reg; output \g_bit[0].reg_value_r_reg[0]_0 ; output [0:0]mr_ctr_pres_enorm_q_reg; output \sp_control_q_i_reg[1] ; output \curr_state_reg[1]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output [0:0]\g_bit[0].reg_value_r_reg[0]_2 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \pc_dbg[is_arbitration] ; output [3:0]\retr_ctr_q_reg[3] ; output reg_q_reg_0; output [0:0]reg_q_reg_1; output reg_q_reg_2; output \curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1] ; output [0:0]reg_q_reg_3; output reg_q_reg_4; output stuff_enable; output tx_frame_no_sof; output \FSM_onehot_current_state_reg[2] ; output \sp_control_q_i_reg[0] ; output reg_q_reg_5; output stuff_err_d; output destuff_enable; output prev_val_d; output bds_data_in; output br_shifted; output \curr_state_reg[4] ; output \curr_state_reg[2]_2 ; output [0:0]\curr_state_reg[0]_1 ; output \rec_dlc_reg[1]_0 ; output bit_err_enable; output \g_byte_shift_reg[0].shift_reg_q_reg[0][1] ; output [16:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][1] ; output rec_is_rtr; output \txtb_hw_cmd_q_reg[valid]_2 ; output tx_frame_no_sof_q_reg; output err_frm_req_reg_1; output p_131_in; output tran_delay_meas; output [3:0]\compl_ctr_q_reg[7] ; output [4:0]\txtb_ptr_q_reg[4] ; output [0:0]\curr_state_reg[5] ; output [14:0]store_data_word; output [0:0]err_frm_req_reg_2; output \curr_state_reg[5]_0 ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2] ; output [0:0]err_frm_req_reg_3; output [0:0]\curr_state_reg[5]_1 ; output \tq_counter_q_reg[7] ; output \sync_control_q_reg[0] ; output [1:0]\sync_control_q_reg[1] ; output \sp_control_q_i_reg[0]_0 ; output first_ssp_q0; output p_0_out; output \txtb_hw_cmd_q_reg[lock]_2 ; output err_frm_req_reg_4; output \curr_state_reg[5]_2 ; output \g_bit[1].reg_value_r_reg[1] ; output [0:0]reg_q_reg_6; output err_frm_req_reg_5; output \curr_state_reg[0]_2 ; output \curr_state_reg[3] ; output err_frm_req_reg_6; output \curr_state_reg[3]_0 ; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output [6:0]\crc_q_reg[14] ; output \sync_control_q_reg[0]_0 ; output int_status_reg; output sspc_ena_q_reg; output btmc_meas_running_q_reg; output \cc_stat[status_pexs] ; output rec_ivld; output [2:0]\alc_alc_bit_reg[4] ; output [2:0]\alc_alc_id_field_reg[2] ; output [28:0]\rec_ident_reg[28] ; output rec_ident_type; output rec_esi; input store_metadata_reg_0; input clk_sys_IBUF_BUFG; input \shift_regs_reg[0] ; input \txtb_hw_cmd_q[err] ; input \cc_stat[is_err_passive] ; input reg_q_reg_7; input [2:0]S; input [0:0]crc_match_q_i_2; input [3:0]crc_match_c5_carry__0; input [1:0]crc_match_q_i_3; input [2:0]\crc_match_c6_inferred__0/i__carry__0 ; input [0:0]crc_match_q_i_2_0; input rx_data_nbs_prev_reg; input rec_lbpf_q_reg; input rec_brs_reg; input [1:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[19] ; input \r_data_reg[16] ; input \r_data_reg[16]_0 ; input \r_data_reg[16]_1 ; input \r_data_reg[15] ; input \r_data_reg[15]_0 ; input \r_data_reg[15]_1 ; input \r_data_reg[15]_2 ; input \r_data_reg[13] ; input \r_data_reg[13]_0 ; input [0:0]\r_data_reg[13]_1 ; input \r_data_reg[13]_2 ; input \r_data_reg[13]_3 ; input \r_data_reg[13]_4 ; input \r_data_reg[18] ; input \r_data_reg[18]_0 ; input \r_data_reg[18]_1 ; input \r_data_reg[18]_2 ; input \r_data_reg[18]_3 ; input \r_data_reg[12] ; input \r_data_reg[12]_0 ; input [19:0]timestamp_IBUF; input \r_data_reg[19]_0 ; input \r_data_reg[19]_1 ; input [0:0]\mr_ctrl_out[settings_rtrth] ; input \err_capt_err_pos_q_reg[0]_0 ; input [0:0]\r_data[7]_i_3__0 ; input [2:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; input \r_data[19]_i_2 ; input \r_data_reg[18]_4 ; input \r_data_reg[18]_5 ; input [1:0]\mr_tx_priority[1] ; input [1:0]\r_data_reg[5]_i_5 ; input [0:0]\mr_tx_priority[0] ; input [0:0]\r_data[0]_i_5 ; input [5:0]\g_ram_rst_false.ram_memory_reg_i_55 ; input ident_valid_q; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \FSM_onehot_curr_state_reg[1] ; input \mr_ctrl_out[mode_erfm] ; input \mr_ctrl_out[rx_settings_rtsop] ; input \g_ram_rst_false.ram_memory_reg_2 ; input [0:0]curr_state_0; input [1:0]int_status_i_4; input \FSM_sequential_curr_state_reg[2] ; input abort_or_skipped; input \FSM_sequential_curr_state_reg[1]_2 ; input \FSM_sequential_curr_state_reg[1]_3 ; input [0:0]curr_state_1; input abort_applied; input \FSM_sequential_curr_state_reg[2]_0 ; input \FSM_sequential_curr_state[1]_i_2__0 ; input [1:0]txtb_hw_cmd_cs; input [0:0]curr_state_2; input \FSM_sequential_curr_state_reg[2]_1 ; input abort_or_skipped_3; input \FSM_sequential_curr_state_reg[1]_4 ; input [0:0]curr_state_4; input abort_applied_5; input \FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state[1]_i_2__2 ; input [0:0]curr_state_6; input \FSM_sequential_curr_state[0]_i_7 ; input \FSM_sequential_curr_state[2]_i_3__3 ; input \FSM_sequential_curr_state[2]_i_3__3_0 ; input \FSM_sequential_curr_state[0]_i_7_0 ; input \shift_regs_reg[24] ; input [20:0]tran_word; input \shift_regs_reg[25] ; input \shift_regs_reg[25]_0 ; input \shift_regs_reg[26] ; input \shift_regs_reg[26]_0 ; input \shift_regs_reg[27] ; input \shift_regs_reg[28] ; input \shift_regs_reg[28]_0 ; input \shift_regs_reg[29] ; input \shift_regs_reg[29]_0 ; input \shift_regs_reg[30] ; input \shift_regs_reg[30]_0 ; input \shift_regs_reg[31] ; input \shift_regs_reg[31]_0 ; input \shift_regs_reg[31]_1 ; input \shift_regs_reg[16] ; input \shift_regs_reg[16]_0 ; input \shift_regs_reg[16]_1 ; input \shift_regs_reg[17] ; input \shift_regs_reg[17]_0 ; input \shift_regs_reg[18] ; input \shift_regs_reg[18]_0 ; input \shift_regs_reg[19] ; input \shift_regs_reg[19]_0 ; input \shift_regs_reg[20] ; input \shift_regs_reg[20]_0 ; input \shift_regs_reg[21] ; input \shift_regs_reg[21]_0 ; input \shift_regs_reg[22] ; input \shift_regs_reg[22]_0 ; input \shift_regs_reg[23] ; input \shift_regs_reg[11] ; input \shift_regs_reg[11]_0 ; input \shift_regs_reg[12] ; input \shift_regs_reg[12]_0 ; input \shift_regs_reg[13] ; input \shift_regs_reg[14] ; input \shift_regs_reg[14]_0 ; input \shift_regs_reg[15] ; input \shift_regs_reg[15]_0 ; input \shift_regs_reg[1] ; input \shift_regs_reg[2] ; input \shift_regs_reg[0]_0 ; input \shift_regs_reg[0]_1 ; input \rec_dlc_reg[0] ; input \cc_stat[is_bus_off] ; input \FSM_sequential_curr_state[1]_i_4__2 ; input tran_frame_valid; input \curr_state_reg[4]_0 ; input [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; input tx_frame_no_sof_q_reg_0; input tx_frame_no_sof_q_reg_1; input rec_ivld_q_reg; input \mr_ctrl_out[mode_rom] ; input \curr_state_reg[0]_3 ; input \curr_state[0]_i_3 ; input \txtb_hw_cmd_q_reg[lock]_3 ; input destuff_enable_reg; input destuff_enable_reg_0; input [13:0]\shift_regs_reg[27]_0 ; input \shift_regs_reg[30]_1 ; input \shift_regs_reg[31]_2 ; input \crc_q_reg[0] ; input \FSM_sequential_curr_state[1]_i_2__4 ; input \curr_state[5]_i_5 ; input \retr_ctr_q_reg[3]_0 ; input mr_ctr_pres_efd_q; input mr_ctr_pres_enorm_q; input \cc_stat[is_receiver] ; input stuff_err; input \sp_control_q_i_reg[1]_0 ; input tx_frame_no_sof_q_reg_2; input tx_frame_no_sof_q_reg_3; input \mr_ctrl_out[settings_rtrle] ; input rec_valid_reg_1; input bit_err; input can_tx_OBUF; input \err_capt_err_type_q_reg[1] ; input \shift_regs_reg[28]_1 ; input \shift_regs_reg[28]_2 ; input \shift_regs_reg[28]_3 ; input \tran_frame_test[fcrc] ; input \shift_regs_reg[29]_1 ; input \shift_regs_reg[29]_2 ; input \ctrl_ctr_q_reg[6] ; input data_halt_d1_out; input tx_trigger_q; input crc_data_rx_wbs; input \crc_q_reg[20] ; input \mr_ctrl_out[settings_ilbp] ; input enable_prev; input btmc_meas_running_q_reg_0; input is_tseg2; input \same_bits_q_reg[2] ; input is_tseg1; input reg_q_reg_8; input fixed_prev_q; input reg_q_reg_9; input reg_q; input sync_edge; input \mr_ctrl_out[mode_fde] ; input \mr_ctrl_out[settings_pex] ; input \ctrl_ctr_q[3]_i_3 ; input \ctrl_ctr_q_reg[1] ; input \ctrl_ctr_q_reg[1]_0 ; input [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; input \curr_state[5]_i_10 ; input \txtb_hw_cmd_q_reg[arbl] ; input \alc_alc_bit_reg[0] ; input tran_ident_type; input \err_capt_err_type_q[2]_i_8 ; input \ctrl_ctr_q[2]_i_3 ; input \shift_regs[31]_i_7 ; input \mr_ctrl_out[settings_ena] ; input [1:0]\curr_state_reg[1]_2 ; input \ctrl_ctr_q_reg[4] ; input \mr_ctrl_out[settings_nisofd] ; input \curr_state[0]_i_3_0 ; input destuff_enable_reg_1; input crc_match_q_reg; input crc_match_q_i_2_1; input [2:0]\cc_stat[dst_ctr] ; input \ctrl_ctr_q_reg[5] ; input \curr_state_reg[4]_1 ; input \crc_q[14]_i_6 ; input tran_brs; input bit_err_q_i_2; input \crc_q[14]_i_11 ; input \mr_ctrl_out[mode_bmm] ; input reg_q_reg_10; input tran_is_rtr; input \txtb_ptr_q_reg[4]_0 ; input \txtb_ptr_q_reg[4]_1 ; input \txtb_ptr_q_reg[4]_2 ; input \ctrl_ctr_q_reg[8] ; input \ctrl_ctr_q_reg[8]_0 ; input \ctrl_ctr_q_reg[5]_0 ; input [1:0]\ctrl_ctr_q_reg[5]_1 ; input \ctrl_ctr_q[8]_i_11 ; input \ctrl_ctr_q[8]_i_11_0 ; input destuff_enable_reg_2; input \timestamp_capture_reg[63] ; input \mr_ctrl_out[mode_stm] ; input \curr_state[1]_i_4 ; input reg_q_reg_11; input rx_data_wbs; input [5:0]crc_match_c6_carry__0; input [2:0]crc_match_c5_carry__0_0; input [8:0]\crc_q_reg[14]_0 ; input scan_mode_IBUF; input rst_n_out_OBUF; input \segm_counter_q_reg[0] ; input \segm_counter_q_reg[0]_0 ; input \segm_counter_q_reg[0]_1 ; input \exp_seg_length_q_reg[0] ; input \exp_seg_length_q_reg[0]_0 ; input sync_edge3__0; input \segm_counter_q_reg[0]_2 ; input rx_data_sync_prev_reg; input tx_data_prev; input \crc_q_reg[0]_0 ; input \ctrl_ctr_q_reg[4]_0 ; input \ctrl_ctr_q[3]_i_3_0 ; input \FSM_sequential_curr_state_reg[0]_0 ; input sync_flag; input int_status_reg_0; input [2:0]data_in_IBUF; input int_status_reg_1; input mr_int_stat_txbhci_o; input sspc_ena_q; input btmc_meas_running_q; input mr_status_pexs_reg; input mr_status_pexs_reg_0; input [0:0]\shift_regs_reg[0]_2 ; input [3:0]txtb_allow_bb; input int_status_i_2__1; input int_status_i_2__1_0; input [0:0]int_status_reg_2; wire [4:0]D; wire [0:0]E; wire \FSM_onehot_curr_state_reg[1] ; wire \FSM_onehot_curr_state_reg[5] ; wire \FSM_onehot_curr_state_reg[5]_0 ; wire \FSM_onehot_current_state_reg[2] ; wire \FSM_sequential_curr_state[0]_i_7 ; wire \FSM_sequential_curr_state[0]_i_7_0 ; wire \FSM_sequential_curr_state[1]_i_2__0 ; wire \FSM_sequential_curr_state[1]_i_2__2 ; wire \FSM_sequential_curr_state[1]_i_2__4 ; wire \FSM_sequential_curr_state[1]_i_4__2 ; wire \FSM_sequential_curr_state[2]_i_3__3 ; wire \FSM_sequential_curr_state[2]_i_3__3_0 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire [3:0]Q; wire [2:0]S; wire abort_applied; wire abort_applied_5; wire abort_or_skipped; wire abort_or_skipped_3; wire [5:0]adress_IBUF; wire \alc_alc_bit_reg[0] ; wire [2:0]\alc_alc_bit_reg[4] ; wire [2:0]\alc_alc_id_field_reg[2] ; wire [2:1]arbitration_part; wire bds_data_in; wire bit_err; wire bit_err_enable; wire bit_err_q_i_2; wire br_shifted; wire btmc_meas_running_q; wire btmc_meas_running_q_reg; wire btmc_meas_running_q_reg_0; wire can_tx_OBUF; wire [2:0]\cc_stat[dst_ctr] ; wire \cc_stat[err_erp] ; wire \cc_stat[is_bus_off] ; wire \cc_stat[is_err_passive] ; wire \cc_stat[is_receiver] ; wire \cc_stat[status_pexs] ; wire clk_sys_IBUF_BUFG; wire compl_ctr_ce; wire [0:0]compl_ctr_d; wire [3:0]\compl_ctr_q_reg[7] ; wire crc_data_rx_wbs; wire crc_match; wire [3:0]crc_match_c5_carry__0; wire [2:0]crc_match_c5_carry__0_0; wire [5:0]crc_match_c6_carry__0; wire [2:0]\crc_match_c6_inferred__0/i__carry__0 ; wire [0:0]crc_match_q_i_2; wire [0:0]crc_match_q_i_2_0; wire crc_match_q_i_2_1; wire [1:0]crc_match_q_i_3; wire crc_match_q_reg; wire \crc_q[14]_i_11 ; wire \crc_q[14]_i_6 ; wire \crc_q_reg[0] ; wire \crc_q_reg[0]_0 ; wire [6:0]\crc_q_reg[14] ; wire [8:0]\crc_q_reg[14]_0 ; wire \crc_q_reg[20] ; wire [8:0]ctrl_ctr_d; wire [0:0]ctrl_ctr_q; wire \ctrl_ctr_q[2]_i_3 ; wire \ctrl_ctr_q[3]_i_3 ; wire \ctrl_ctr_q[3]_i_3_0 ; wire \ctrl_ctr_q[8]_i_11 ; wire \ctrl_ctr_q[8]_i_11_0 ; wire \ctrl_ctr_q_reg[1] ; wire \ctrl_ctr_q_reg[1]_0 ; wire \ctrl_ctr_q_reg[4] ; wire \ctrl_ctr_q_reg[4]_0 ; wire \ctrl_ctr_q_reg[5] ; wire \ctrl_ctr_q_reg[5]_0 ; wire [1:0]\ctrl_ctr_q_reg[5]_1 ; wire \ctrl_ctr_q_reg[6] ; wire \ctrl_ctr_q_reg[7] ; wire \ctrl_ctr_q_reg[8] ; wire \ctrl_ctr_q_reg[8]_0 ; wire \curr_state[0]_i_3 ; wire \curr_state[0]_i_3_0 ; wire \curr_state[1]_i_4 ; wire \curr_state[5]_i_10 ; wire \curr_state[5]_i_5 ; wire [0:0]curr_state_0; wire [0:0]curr_state_1; wire [0:0]curr_state_2; wire [0:0]curr_state_4; wire [0:0]curr_state_6; wire \curr_state_reg[0] ; wire \curr_state_reg[0]_0 ; wire [0:0]\curr_state_reg[0]_1 ; wire \curr_state_reg[0]_2 ; wire \curr_state_reg[0]_3 ; wire \curr_state_reg[1] ; wire \curr_state_reg[1]_0 ; wire \curr_state_reg[1]_1 ; wire [1:0]\curr_state_reg[1]_2 ; wire \curr_state_reg[2] ; wire \curr_state_reg[2]_0 ; wire \curr_state_reg[2]_1 ; wire \curr_state_reg[2]_2 ; wire \curr_state_reg[3] ; wire \curr_state_reg[3]_0 ; wire \curr_state_reg[4] ; wire \curr_state_reg[4]_0 ; wire \curr_state_reg[4]_1 ; wire [0:0]\curr_state_reg[5] ; wire \curr_state_reg[5]_0 ; wire [0:0]\curr_state_reg[5]_1 ; wire \curr_state_reg[5]_2 ; wire data_halt_d1_out; wire [2:0]data_in_IBUF; wire destuff_enable; wire destuff_enable_reg; wire destuff_enable_reg_0; wire destuff_enable_reg_1; wire destuff_enable_reg_2; wire enable_prev; wire err_capt_err_erp_reg; wire \err_capt_err_pos_q_reg[0] ; wire \err_capt_err_pos_q_reg[0]_0 ; wire [3:0]\err_capt_err_pos_q_reg[3] ; wire [2:0]err_capt_err_type_d; wire \err_capt_err_type_q[2]_i_8 ; wire \err_capt_err_type_q_reg[0] ; wire \err_capt_err_type_q_reg[1] ; wire [2:0]\err_capt_err_type_q_reg[2] ; wire err_frm_req_reg; wire [0:0]err_frm_req_reg_0; wire err_frm_req_reg_1; wire [0:0]err_frm_req_reg_2; wire [0:0]err_frm_req_reg_3; wire err_frm_req_reg_4; wire err_frm_req_reg_5; wire err_frm_req_reg_6; wire [3:0]err_pos; wire \exp_seg_length_q_reg[0] ; wire \exp_seg_length_q_reg[0]_0 ; wire first_ssp_q0; wire fixed_prev_q; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[1].reg_value_r_reg[1] ; wire [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][1] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2] ; wire [16:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][1] ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire [5:0]\g_ram_rst_false.ram_memory_reg_i_55 ; wire i_mac_pc_control_counter_n_1; wire i_mac_pc_control_counter_n_10; wire i_mac_pc_control_counter_n_12; wire i_mac_pc_control_counter_n_13; wire i_mac_pc_control_counter_n_14; wire i_mac_pc_control_counter_n_15; wire i_mac_pc_control_counter_n_16; wire i_mac_pc_control_counter_n_17; wire i_mac_pc_control_counter_n_19; wire i_mac_pc_control_counter_n_23; wire i_mac_pc_control_counter_n_24; wire i_mac_pc_control_counter_n_25; wire i_mac_pc_control_counter_n_26; wire i_mac_pc_control_counter_n_27; wire i_mac_pc_control_counter_n_28; wire i_mac_pc_control_counter_n_29; wire i_mac_pc_control_counter_n_30; wire i_mac_pc_control_counter_n_31; wire i_mac_pc_control_counter_n_32; wire i_mac_pc_control_counter_n_33; wire i_mac_pc_control_counter_n_34; wire i_mac_pc_control_counter_n_35; wire i_mac_pc_control_counter_n_36; wire i_mac_pc_control_counter_n_6; wire i_mac_pc_control_counter_n_7; wire i_mac_pc_control_counter_n_8; wire i_mac_pc_control_counter_n_9; wire i_mac_pc_err_detector_n_12; wire i_mac_pc_err_detector_n_13; wire i_mac_pc_err_detector_n_15; wire i_mac_pc_err_detector_n_16; wire i_mac_pc_err_detector_n_17; wire i_mac_pc_err_detector_n_18; wire i_mac_pc_err_detector_n_19; wire i_mac_pc_err_detector_n_20; wire i_mac_pc_err_detector_n_21; wire i_mac_pc_fsm_n_104; wire i_mac_pc_fsm_n_106; wire i_mac_pc_fsm_n_107; wire i_mac_pc_fsm_n_108; wire i_mac_pc_fsm_n_110; wire i_mac_pc_fsm_n_134; wire i_mac_pc_fsm_n_137; wire i_mac_pc_fsm_n_138; wire i_mac_pc_fsm_n_14; wire i_mac_pc_fsm_n_141; wire i_mac_pc_fsm_n_151; wire i_mac_pc_fsm_n_154; wire i_mac_pc_fsm_n_161; wire i_mac_pc_fsm_n_162; wire i_mac_pc_fsm_n_165; wire i_mac_pc_fsm_n_166; wire i_mac_pc_fsm_n_167; wire i_mac_pc_fsm_n_170; wire i_mac_pc_fsm_n_171; wire i_mac_pc_fsm_n_172; wire i_mac_pc_fsm_n_175; wire i_mac_pc_fsm_n_18; wire i_mac_pc_fsm_n_190; wire i_mac_pc_fsm_n_193; wire i_mac_pc_fsm_n_194; wire i_mac_pc_fsm_n_21; wire i_mac_pc_fsm_n_27; wire i_mac_pc_fsm_n_84; wire i_mac_pc_fsm_n_89; wire i_mac_pc_fsm_n_90; wire i_mac_pc_reintegration_counter_n_0; wire i_mac_pc_rx_shift_reg_n_11; wire i_mac_pc_rx_shift_reg_n_23; wire i_mac_pc_rx_shift_reg_n_24; wire i_mac_pc_rx_shift_reg_n_25; wire i_mac_pc_rx_shift_reg_n_26; wire i_mac_pc_rx_shift_reg_n_27; wire i_mac_pc_rx_shift_reg_n_28; wire i_mac_pc_rx_shift_reg_n_29; wire i_mac_pc_rx_shift_reg_n_39; wire i_mac_pc_rx_shift_reg_n_55; wire i_mac_pc_tx_shift_reg_n_1; wire i_mac_pc_tx_shift_reg_n_10; wire i_mac_pc_tx_shift_reg_n_11; wire i_mac_pc_tx_shift_reg_n_12; wire i_mac_pc_tx_shift_reg_n_13; wire i_mac_pc_tx_shift_reg_n_14; wire i_mac_pc_tx_shift_reg_n_15; wire i_mac_pc_tx_shift_reg_n_16; wire i_mac_pc_tx_shift_reg_n_17; wire i_mac_pc_tx_shift_reg_n_18; wire i_mac_pc_tx_shift_reg_n_19; wire i_mac_pc_tx_shift_reg_n_2; wire i_mac_pc_tx_shift_reg_n_20; wire i_mac_pc_tx_shift_reg_n_21; wire i_mac_pc_tx_shift_reg_n_22; wire i_mac_pc_tx_shift_reg_n_23; wire i_mac_pc_tx_shift_reg_n_24; wire i_mac_pc_tx_shift_reg_n_25; wire i_mac_pc_tx_shift_reg_n_26; wire i_mac_pc_tx_shift_reg_n_27; wire i_mac_pc_tx_shift_reg_n_28; wire i_mac_pc_tx_shift_reg_n_29; wire i_mac_pc_tx_shift_reg_n_3; wire i_mac_pc_tx_shift_reg_n_30; wire i_mac_pc_tx_shift_reg_n_31; wire i_mac_pc_tx_shift_reg_n_4; wire i_mac_pc_tx_shift_reg_n_5; wire i_mac_pc_tx_shift_reg_n_6; wire i_mac_pc_tx_shift_reg_n_7; wire i_mac_pc_tx_shift_reg_n_8; wire i_mac_pc_tx_shift_reg_n_9; wire [1:1]\i_shift_reg_byte/shift_reg_in ; wire ident_valid_q; wire [0:0]ident_valid_q_reg; wire int_status_i_2__1; wire int_status_i_2__1_0; wire [1:0]int_status_i_4; wire int_status_reg; wire int_status_reg_0; wire int_status_reg_1; wire [0:0]int_status_reg_2; wire is_tseg1; wire is_tseg2; wire mr_ctr_pres_efd_q; wire [0:0]mr_ctr_pres_efd_q_reg; wire mr_ctr_pres_enorm_q; wire [0:0]mr_ctr_pres_enorm_q_reg; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_ctrl_out[settings_rtrle] ; wire [0:0]\mr_ctrl_out[settings_rtrth] ; wire [2:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; wire mr_int_stat_txbhci_o; wire mr_status_pexs_reg; wire mr_status_pexs_reg_0; wire [0:0]\mr_tx_priority[0] ; wire [1:0]\mr_tx_priority[1] ; wire p_0_out; wire p_131_in; wire [31:1]p_1_in; wire \pc_dbg[is_arbitration] ; wire prev_val_d; wire [0:0]\r_data[0]_i_5 ; wire \r_data[19]_i_2 ; wire [0:0]\r_data[7]_i_3__0 ; wire \r_data_reg[12] ; wire \r_data_reg[12]_0 ; wire \r_data_reg[13] ; wire \r_data_reg[13]_0 ; wire [0:0]\r_data_reg[13]_1 ; wire \r_data_reg[13]_2 ; wire \r_data_reg[13]_3 ; wire \r_data_reg[13]_4 ; wire \r_data_reg[15] ; wire \r_data_reg[15]_0 ; wire \r_data_reg[15]_1 ; wire \r_data_reg[15]_2 ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[16]_1 ; wire \r_data_reg[18] ; wire \r_data_reg[18]_0 ; wire \r_data_reg[18]_1 ; wire \r_data_reg[18]_2 ; wire \r_data_reg[18]_3 ; wire \r_data_reg[18]_4 ; wire \r_data_reg[18]_5 ; wire \r_data_reg[19] ; wire \r_data_reg[19]_0 ; wire \r_data_reg[19]_1 ; wire [1:0]\r_data_reg[5]_i_5 ; wire rec_abort_f; wire rec_abort_reg; wire rec_abort_reg_0; wire rec_brs; wire rec_brs_reg; wire \rec_dlc_reg[0] ; wire \rec_dlc_reg[1] ; wire \rec_dlc_reg[1]_0 ; wire \rec_dlc_reg[2] ; wire \rec_dlc_reg[2]_0 ; wire [3:0]\rec_dlc_reg[3] ; wire \rec_dlc_reg[3]_0 ; wire rec_esi; wire rec_frame_type_i_reg; wire [28:0]\rec_ident_reg[28] ; wire rec_ident_type; wire rec_is_rtr; wire rec_is_rtr_i_reg; wire rec_ivld; wire rec_ivld_q_reg; wire rec_lbpf; wire rec_lbpf_q_reg; wire rec_valid_reg; wire [2:0]rec_valid_reg_0; wire rec_valid_reg_1; wire reg_q; wire reg_q_reg; wire reg_q_reg_0; wire [0:0]reg_q_reg_1; wire reg_q_reg_10; wire reg_q_reg_11; wire reg_q_reg_2; wire [0:0]reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire [0:0]reg_q_reg_6; wire reg_q_reg_7; wire reg_q_reg_8; wire reg_q_reg_9; wire reinteg_ctr_ce; wire retr_ctr_add; wire [0:0]retr_ctr_d; wire [0:0]retr_ctr_q; wire [3:0]\retr_ctr_q_reg[3] ; wire \retr_ctr_q_reg[3]_0 ; wire rst_n_out_OBUF; wire rx_data_nbs_prev; wire rx_data_nbs_prev_reg; wire rx_data_sync_prev_reg; wire rx_data_wbs; wire [3:0]rx_shift_cmd; wire rx_store_base_id; wire rx_store_stuff_count; wire \same_bits_q_reg[2] ; wire [1:0]sbe_IBUF; wire scan_mode_IBUF; wire \segm_counter_q_reg[0] ; wire \segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire \segm_counter_q_reg[0]_2 ; wire \shift_regs[31]_i_7 ; wire \shift_regs_reg[0] ; wire \shift_regs_reg[0]_0 ; wire \shift_regs_reg[0]_1 ; wire [0:0]\shift_regs_reg[0]_2 ; wire \shift_regs_reg[11] ; wire \shift_regs_reg[11]_0 ; wire \shift_regs_reg[12] ; wire \shift_regs_reg[12]_0 ; wire \shift_regs_reg[13] ; wire \shift_regs_reg[14] ; wire \shift_regs_reg[14]_0 ; wire \shift_regs_reg[15] ; wire \shift_regs_reg[15]_0 ; wire \shift_regs_reg[16] ; wire \shift_regs_reg[16]_0 ; wire \shift_regs_reg[16]_1 ; wire \shift_regs_reg[17] ; wire \shift_regs_reg[17]_0 ; wire \shift_regs_reg[18] ; wire \shift_regs_reg[18]_0 ; wire \shift_regs_reg[19] ; wire \shift_regs_reg[19]_0 ; wire \shift_regs_reg[1] ; wire \shift_regs_reg[20] ; wire \shift_regs_reg[20]_0 ; wire \shift_regs_reg[21] ; wire \shift_regs_reg[21]_0 ; wire \shift_regs_reg[22] ; wire \shift_regs_reg[22]_0 ; wire \shift_regs_reg[23] ; wire \shift_regs_reg[24] ; wire \shift_regs_reg[25] ; wire \shift_regs_reg[25]_0 ; wire \shift_regs_reg[26] ; wire \shift_regs_reg[26]_0 ; wire \shift_regs_reg[27] ; wire [13:0]\shift_regs_reg[27]_0 ; wire \shift_regs_reg[28] ; wire \shift_regs_reg[28]_0 ; wire \shift_regs_reg[28]_1 ; wire \shift_regs_reg[28]_2 ; wire \shift_regs_reg[28]_3 ; wire \shift_regs_reg[29] ; wire \shift_regs_reg[29]_0 ; wire \shift_regs_reg[29]_1 ; wire \shift_regs_reg[29]_2 ; wire \shift_regs_reg[2] ; wire \shift_regs_reg[30] ; wire \shift_regs_reg[30]_0 ; wire \shift_regs_reg[30]_1 ; wire \shift_regs_reg[31] ; wire \shift_regs_reg[31]_0 ; wire \shift_regs_reg[31]_1 ; wire \shift_regs_reg[31]_2 ; wire \sp_control_q_i_reg[0] ; wire \sp_control_q_i_reg[0]_0 ; wire \sp_control_q_i_reg[1] ; wire \sp_control_q_i_reg[1]_0 ; wire sspc_ena_q; wire sspc_ena_q_reg; wire [14:0]store_data_word; wire store_metadata_reg; wire store_metadata_reg_0; wire stuff_enable; wire stuff_err; wire stuff_err_d; wire \sync_control_q_reg[0] ; wire \sync_control_q_reg[0]_0 ; wire [1:0]\sync_control_q_reg[1] ; wire sync_edge; wire sync_edge3__0; wire sync_flag; wire \timestamp[14] ; wire \timestamp[17] ; wire \timestamp[41] ; wire \timestamp[42] ; wire \timestamp[43] ; wire \timestamp[7] ; wire \timestamp[8] ; wire [19:0]timestamp_IBUF; wire \timestamp_capture_reg[63] ; wire \tq_counter_q_reg[7] ; wire tran_brs; wire tran_delay_meas; wire \tran_frame_test[fcrc] ; wire tran_frame_valid; wire tran_ident_type; wire tran_is_rtr; wire [20:0]tran_word; wire tx_data_prev; wire tx_frame_no_sof; wire tx_frame_no_sof_q_reg; wire tx_frame_no_sof_q_reg_0; wire tx_frame_no_sof_q_reg_1; wire tx_frame_no_sof_q_reg_2; wire tx_frame_no_sof_q_reg_3; wire tx_sr_output; wire tx_trigger_q; wire [3:0]txtb_allow_bb; wire txtb_clk_en_d; wire [1:0]txtb_hw_cmd_cs; wire \txtb_hw_cmd_q[err] ; wire \txtb_hw_cmd_q_reg[arbl] ; wire \txtb_hw_cmd_q_reg[err] ; wire \txtb_hw_cmd_q_reg[failed] ; wire \txtb_hw_cmd_q_reg[failed]_0 ; wire \txtb_hw_cmd_q_reg[failed]_1 ; wire \txtb_hw_cmd_q_reg[failed]_2 ; wire \txtb_hw_cmd_q_reg[failed]_3 ; wire \txtb_hw_cmd_q_reg[failed]_4 ; wire \txtb_hw_cmd_q_reg[failed]_5 ; wire \txtb_hw_cmd_q_reg[failed]_6 ; wire \txtb_hw_cmd_q_reg[lock] ; wire \txtb_hw_cmd_q_reg[lock]_0 ; wire \txtb_hw_cmd_q_reg[lock]_1 ; wire \txtb_hw_cmd_q_reg[lock]_2 ; wire \txtb_hw_cmd_q_reg[lock]_3 ; wire \txtb_hw_cmd_q_reg[valid] ; wire \txtb_hw_cmd_q_reg[valid]_0 ; wire \txtb_hw_cmd_q_reg[valid]_1 ; wire \txtb_hw_cmd_q_reg[valid]_2 ; wire [4:0]\txtb_ptr_q_reg[4] ; wire \txtb_ptr_q_reg[4]_0 ; wire \txtb_ptr_q_reg[4]_1 ; wire \txtb_ptr_q_reg[4]_2 ; mac_pc_control_counter i_mac_pc_control_counter (.D(D[4]), .E(txtb_clk_en_d), .\FSM_sequential_curr_state[0]_i_3__1 (tx_frame_no_sof_q_reg_3), .\FSM_sequential_curr_state[0]_i_3__1_0 (tx_frame_no_sof_q_reg_2), .Q(i_mac_pc_control_counter_n_6), .adress_IBUF(adress_IBUF), .\alc_alc_bit_reg[0]_0 (err_frm_req_reg_0), .\alc_alc_bit_reg[2]_0 (i_mac_pc_control_counter_n_1), .\alc_alc_bit_reg[4]_0 (\alc_alc_bit_reg[4] ), .\alc_alc_bit_reg[4]_1 (\shift_regs_reg[0] ), .\alc_alc_id_field_reg[2]_0 (\alc_alc_id_field_reg[2] ), .\alc_alc_id_field_reg[2]_1 ({arbitration_part,i_mac_pc_fsm_n_175}), .\cc_stat[is_bus_off] (\cc_stat[is_bus_off] ), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\compl_ctr_q_reg[0]_0 (compl_ctr_d), .\compl_ctr_q_reg[1]_0 (i_mac_pc_fsm_n_106), .\compl_ctr_q_reg[3]_0 (i_mac_pc_control_counter_n_7), .\compl_ctr_q_reg[5]_0 (i_mac_pc_control_counter_n_25), .\compl_ctr_q_reg[7]_0 ({i_mac_pc_control_counter_n_19,\compl_ctr_q_reg[7] [3],\compl_ctr_q_reg[7] [1:0]}), .\compl_ctr_q_reg[8]_0 (compl_ctr_ce), .\ctrl_ctr_q[0]_i_4 (\shift_regs_reg[0]_0 ), .\ctrl_ctr_q[0]_i_4_0 (\shift_regs_reg[0]_1 ), .\ctrl_ctr_q[1]_i_12 (\ctrl_ctr_q_reg[4] ), .\ctrl_ctr_q[1]_i_9 (\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .\ctrl_ctr_q[1]_i_9_0 (i_mac_pc_reintegration_counter_n_0), .\ctrl_ctr_q[1]_i_9_1 (rx_data_nbs_prev), .\ctrl_ctr_q[2]_i_4 ({i_mac_pc_fsm_n_18,Q[3:2],i_mac_pc_fsm_n_21}), .\ctrl_ctr_q[2]_i_4_0 (crc_match_q_reg), .\ctrl_ctr_q_reg[1]_0 ({i_mac_pc_control_counter_n_8,i_mac_pc_control_counter_n_9}), .\ctrl_ctr_q_reg[1]_1 (i_mac_pc_control_counter_n_26), .\ctrl_ctr_q_reg[2]_0 (i_mac_pc_err_detector_n_21), .\ctrl_ctr_q_reg[2]_1 (i_mac_pc_fsm_n_141), .\ctrl_ctr_q_reg[3]_0 (i_mac_pc_control_counter_n_30), .\ctrl_ctr_q_reg[4]_0 (i_mac_pc_control_counter_n_29), .\ctrl_ctr_q_reg[5]_0 (i_mac_pc_fsm_n_190), .\ctrl_ctr_q_reg[5]_1 (i_mac_pc_rx_shift_reg_n_27), .\ctrl_ctr_q_reg[5]_2 (i_mac_pc_rx_shift_reg_n_26), .\ctrl_ctr_q_reg[6]_0 (\ctrl_ctr_q_reg[6] ), .\ctrl_ctr_q_reg[6]_1 (i_mac_pc_rx_shift_reg_n_25), .\ctrl_ctr_q_reg[7]_0 (\ctrl_ctr_q_reg[7] ), .\ctrl_ctr_q_reg[7]_1 (i_mac_pc_rx_shift_reg_n_23), .\ctrl_ctr_q_reg[7]_2 (i_mac_pc_rx_shift_reg_n_24), .\ctrl_ctr_q_reg[8]_0 (i_mac_pc_control_counter_n_27), .\ctrl_ctr_q_reg[8]_1 ({ctrl_ctr_d[8],ctrl_ctr_d[4:3],ctrl_ctr_d[1:0]}), .\ctrl_ctr_q_reg[8]_2 (ctrl_ctr_q), .\curr_state_reg[2] (i_mac_pc_control_counter_n_35), .\curr_state_reg[3] (i_mac_pc_control_counter_n_31), .\curr_state_reg[5] (i_mac_pc_control_counter_n_36), .\g_bit[0].reg_value_r_reg[0] (i_mac_pc_control_counter_n_10), .\g_bit[0].reg_value_r_reg[0]_0 (i_mac_pc_control_counter_n_12), .\g_bit[0].reg_value_r_reg[0]_1 (i_mac_pc_control_counter_n_15), .\g_bit[0].reg_value_r_reg[0]_2 (i_mac_pc_control_counter_n_16), .\g_bit[0].reg_value_r_reg[0]_3 (i_mac_pc_control_counter_n_32), .\g_byte_shift_reg[0].shift_reg_q_reg[0][0] (i_mac_pc_err_detector_n_17), .\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 (i_mac_pc_fsm_n_167), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_ctrl_out[settings_rtrth] (\mr_ctrl_out[settings_rtrth] ), .\r_data[19]_i_2_0 (\r_data_reg[12] ), .\r_data[19]_i_2_1 (\r_data[19]_i_2 ), .\r_data_reg[18] (\r_data_reg[18]_4 ), .\r_data_reg[18]_0 (\r_data_reg[18]_5 ), .\r_data_reg[19] (\r_data_reg[19] ), .\r_data_reg[19]_0 (\r_data_reg[19]_0 ), .\r_data_reg[19]_1 (\r_data_reg[19]_1 ), .reg_q_reg(i_mac_pc_control_counter_n_13), .reg_q_reg_0(i_mac_pc_control_counter_n_14), .reg_q_reg_1(i_mac_pc_control_counter_n_17), .reg_q_reg_2(i_mac_pc_control_counter_n_34), .rx_data_nbs_prev_reg(i_mac_pc_control_counter_n_28), .rx_data_nbs_prev_reg_0(i_mac_pc_control_counter_n_33), .rx_shift_cmd(rx_shift_cmd), .sbe_IBUF(sbe_IBUF[1]), .store_data_reg(i_mac_pc_fsm_n_14), .store_data_reg_0(\rec_dlc_reg[0] ), .sync_edge(sync_edge), .\txtb_ptr_q[4]_i_3 ({\txtb_ptr_q_reg[4] [4:3],\txtb_ptr_q_reg[4] [1:0]}), .\txtb_ptr_q_reg[0] (i_mac_pc_control_counter_n_24), .\txtb_ptr_q_reg[2] (i_mac_pc_fsm_n_193), .\txtb_ptr_q_reg[2]_0 (\sp_control_q_i_reg[1]_0 ), .\txtb_ptr_q_reg[4] (i_mac_pc_control_counter_n_23), .\txtb_ptr_q_reg[4]_0 (i_mac_pc_fsm_n_154), .\txtb_ptr_q_reg[4]_1 (\txtb_ptr_q_reg[4]_0 ), .\txtb_ptr_q_reg[4]_2 (\txtb_ptr_q_reg[4]_1 ), .\txtb_ptr_q_reg[4]_3 (\txtb_ptr_q_reg[4]_2 ), .\txtb_ptr_q_reg[4]_4 (i_mac_pc_fsm_n_161)); mac_pc_err_detector i_mac_pc_err_detector (.D(err_capt_err_type_d), .Q({i_mac_pc_fsm_n_18,Q[3],i_mac_pc_fsm_n_21}), .S({S,i_mac_pc_rx_shift_reg_n_28}), .ack_err_flag_reg(\sp_control_q_i_reg[1]_0 ), .ack_err_flag_reg_0(\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .ack_err_flag_reg_1(tx_frame_no_sof_q_reg_2), .ack_err_flag_reg_2(tx_frame_no_sof_q_reg_3), .ack_err_flag_reg_3(i_mac_pc_fsm_n_170), .adress_IBUF(adress_IBUF[1:0]), .\cc_stat[err_erp] (\cc_stat[err_erp] ), .\cc_stat[is_err_passive] (\cc_stat[is_err_passive] ), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_match(crc_match), .crc_match_c5_carry__0_0(crc_match_c5_carry__0), .\crc_match_c6_inferred__0/i__carry__0_0 ({\crc_match_c6_inferred__0/i__carry__0 [2:1],i_mac_pc_rx_shift_reg_n_55,\crc_match_c6_inferred__0/i__carry__0 [0]}), .crc_match_q_i_2_0({crc_match_q_i_2,i_mac_pc_rx_shift_reg_n_29}), .crc_match_q_i_2_1(crc_match_q_i_2_0), .crc_match_q_i_2_2(crc_match_q_i_2_1), .crc_match_q_i_2_3(i_mac_pc_rx_shift_reg_n_11), .crc_match_q_i_3_0({crc_match_q_i_3[1],i_mac_pc_rx_shift_reg_n_39,crc_match_q_i_3[0]}), .crc_match_q_reg_0(i_mac_pc_err_detector_n_12), .crc_match_q_reg_1(\shift_regs_reg[0] ), .crc_match_q_reg_2(\ctrl_ctr_q_reg[4] ), .crc_match_q_reg_3(crc_match_q_reg), .crc_match_q_reg_4(i_mac_pc_fsm_n_104), .crc_match_q_reg_5(i_mac_pc_fsm_n_194), .crc_match_q_reg_6(\rec_dlc_reg[0] ), .err_capt_err_erp_reg_0(err_capt_err_erp_reg), .err_capt_err_erp_reg_1(E), .err_capt_err_erp_reg_2(i_mac_pc_fsm_n_108), .err_capt_err_erp_reg_3(i_mac_pc_fsm_n_162), .\err_capt_err_pos_q_reg[0]_0 (\err_capt_err_pos_q_reg[0] ), .\err_capt_err_pos_q_reg[3]_0 (\err_capt_err_pos_q_reg[3] ), .\err_capt_err_pos_q_reg[3]_1 (err_pos), .\err_capt_err_type_q_reg[0]_0 (\err_capt_err_type_q_reg[0] ), .\err_capt_err_type_q_reg[2]_0 (\err_capt_err_type_q_reg[2] ), .err_frm_req_reg_0(err_frm_req_reg), .err_frm_req_reg_1(i_mac_pc_err_detector_n_13), .err_frm_req_reg_2(i_mac_pc_err_detector_n_15), .err_frm_req_reg_3(i_mac_pc_err_detector_n_18), .err_frm_req_reg_4(i_mac_pc_err_detector_n_19), .err_frm_req_reg_5(i_mac_pc_err_detector_n_20), .err_frm_req_reg_6(i_mac_pc_err_detector_n_21), .err_frm_req_reg_7(err_frm_req_reg_4), .\g_byte_shift_reg[0].shift_reg_q_reg[0][0] (i_mac_pc_fsm_n_90), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_tx_priority[0] (\mr_tx_priority[0] ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .\pc_dbg[is_arbitration] (\pc_dbg[is_arbitration] ), .\r_data[0]_i_5 (\r_data[0]_i_5 ), .\r_data_reg[5]_i_5 (\r_data_reg[5]_i_5 ), .reg_q_reg(i_mac_pc_err_detector_n_16), .reg_q_reg_0(i_mac_pc_err_detector_n_17), .reg_q_reg_1(i_mac_pc_fsm_n_84), .stuff_err(stuff_err)); mac_pc_fsm i_mac_pc_fsm (.D(D[3:0]), .E(i_mac_pc_fsm_n_89), .\FSM_onehot_curr_state_reg[1] (\FSM_onehot_curr_state_reg[1] ), .\FSM_onehot_curr_state_reg[5] (\FSM_onehot_curr_state_reg[5] ), .\FSM_onehot_curr_state_reg[5]_0 (\FSM_onehot_curr_state_reg[5]_0 ), .\FSM_onehot_curr_state_reg[6] (\g_ram_rst_false.ram_memory_reg_i_55 [4:0]), .\FSM_onehot_current_state_reg[2] (\FSM_onehot_current_state_reg[2] ), .\FSM_sequential_curr_state[0]_i_7 (\FSM_sequential_curr_state[0]_i_7 ), .\FSM_sequential_curr_state[0]_i_7_0 (\FSM_sequential_curr_state[0]_i_7_0 ), .\FSM_sequential_curr_state[1]_i_2__0 (\FSM_sequential_curr_state[1]_i_2__0 ), .\FSM_sequential_curr_state[1]_i_2__2 (\FSM_sequential_curr_state[1]_i_2__2 ), .\FSM_sequential_curr_state[1]_i_2__4_0 (\FSM_sequential_curr_state[1]_i_2__4 ), .\FSM_sequential_curr_state[1]_i_4__2_0 (\FSM_sequential_curr_state[1]_i_4__2 ), .\FSM_sequential_curr_state[1]_i_8_0 (i_mac_pc_control_counter_n_14), .\FSM_sequential_curr_state[2]_i_3__3 (\FSM_sequential_curr_state[2]_i_3__3 ), .\FSM_sequential_curr_state[2]_i_3__3_0 (\FSM_sequential_curr_state[2]_i_3__3_0 ), .\FSM_sequential_curr_state_reg[0] (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[1] (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_0 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_1 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_4 ), .\FSM_sequential_curr_state_reg[2] (\FSM_sequential_curr_state_reg[2] ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_1 (\FSM_sequential_curr_state_reg[2]_1 ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_2 ), .Q({i_mac_pc_fsm_n_18,Q[3:2],i_mac_pc_fsm_n_21,Q[1:0]}), .abort_applied(abort_applied), .abort_applied_5(abort_applied_5), .abort_or_skipped(abort_or_skipped), .abort_or_skipped_3(abort_or_skipped_3), .ack_err_flag_reg_0(i_mac_pc_err_detector_n_13), .adress_IBUF({adress_IBUF[5:4],adress_IBUF[1:0]}), .\alc_alc_bit_reg[0] (\alc_alc_bit_reg[0] ), .bds_data_in(bds_data_in), .bit_err(bit_err), .bit_err_enable(bit_err_enable), .bit_err_q_i_2_0(bit_err_q_i_2), .br_shifted(br_shifted), .\bst_ctr_q_reg[2] (p_1_in), .btmc_meas_running_q(btmc_meas_running_q), .btmc_meas_running_q_reg(btmc_meas_running_q_reg), .btmc_meas_running_q_reg_0(btmc_meas_running_q_reg_0), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[is_bus_off] (\cc_stat[is_bus_off] ), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .\cc_stat[status_pexs] (\cc_stat[status_pexs] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\compl_ctr_q_reg[0] (compl_ctr_d), .\compl_ctr_q_reg[0]_0 (i_mac_pc_control_counter_n_6), .crc_data_rx_wbs(crc_data_rx_wbs), .crc_match(crc_match), .\crc_q[14]_i_11_0 (\crc_q[14]_i_11 ), .\crc_q[14]_i_6_0 ({tx_sr_output,i_mac_pc_tx_shift_reg_n_1,i_mac_pc_tx_shift_reg_n_2,i_mac_pc_tx_shift_reg_n_3,i_mac_pc_tx_shift_reg_n_4,i_mac_pc_tx_shift_reg_n_5,i_mac_pc_tx_shift_reg_n_6,i_mac_pc_tx_shift_reg_n_7,i_mac_pc_tx_shift_reg_n_8,i_mac_pc_tx_shift_reg_n_9,i_mac_pc_tx_shift_reg_n_10,i_mac_pc_tx_shift_reg_n_11,i_mac_pc_tx_shift_reg_n_12,i_mac_pc_tx_shift_reg_n_13,i_mac_pc_tx_shift_reg_n_14,i_mac_pc_tx_shift_reg_n_15,i_mac_pc_tx_shift_reg_n_16,i_mac_pc_tx_shift_reg_n_17,i_mac_pc_tx_shift_reg_n_18,i_mac_pc_tx_shift_reg_n_19,i_mac_pc_tx_shift_reg_n_20,i_mac_pc_tx_shift_reg_n_21,i_mac_pc_tx_shift_reg_n_22,i_mac_pc_tx_shift_reg_n_23,i_mac_pc_tx_shift_reg_n_24,i_mac_pc_tx_shift_reg_n_25,i_mac_pc_tx_shift_reg_n_26,i_mac_pc_tx_shift_reg_n_27,i_mac_pc_tx_shift_reg_n_28,i_mac_pc_tx_shift_reg_n_29,i_mac_pc_tx_shift_reg_n_30,i_mac_pc_tx_shift_reg_n_31}), .\crc_q[14]_i_6_1 (\crc_q[14]_i_6 ), .\crc_q_reg[0] (\crc_q_reg[0] ), .\crc_q_reg[0]_0 (\crc_q_reg[0]_0 ), .\crc_q_reg[14] (\crc_q_reg[14] ), .\crc_q_reg[14]_0 ({\crc_q_reg[14]_0 [8:4],\crc_q_reg[14]_0 [1:0]}), .\crc_q_reg[20] (\crc_q_reg[20] ), .\ctrl_ctr_q[0]_i_4_0 (i_mac_pc_control_counter_n_32), .\ctrl_ctr_q[1]_i_3_0 (i_mac_pc_control_counter_n_33), .\ctrl_ctr_q[1]_i_3_1 (i_mac_pc_control_counter_n_13), .\ctrl_ctr_q[1]_i_4_0 (i_mac_pc_control_counter_n_16), .\ctrl_ctr_q[2]_i_3_0 (\ctrl_ctr_q[2]_i_3 ), .\ctrl_ctr_q[2]_i_3_1 (i_mac_pc_control_counter_n_36), .\ctrl_ctr_q[2]_i_3_2 (i_mac_pc_control_counter_n_17), .\ctrl_ctr_q[2]_i_4_0 (crc_match_q_reg), .\ctrl_ctr_q[2]_i_6_0 (i_mac_pc_control_counter_n_28), .\ctrl_ctr_q[3]_i_3_0 (\ctrl_ctr_q[3]_i_3 ), .\ctrl_ctr_q[3]_i_3_1 (\ctrl_ctr_q[3]_i_3_0 ), .\ctrl_ctr_q[3]_i_4_0 (\ctrl_ctr_q_reg[5] ), .\ctrl_ctr_q[8]_i_11_0 (\ctrl_ctr_q[8]_i_11 ), .\ctrl_ctr_q[8]_i_11_1 (\ctrl_ctr_q[8]_i_11_0 ), .\ctrl_ctr_q_reg[0] (i_mac_pc_err_detector_n_21), .\ctrl_ctr_q_reg[0]_0 (i_mac_pc_control_counter_n_31), .\ctrl_ctr_q_reg[1] ({i_mac_pc_control_counter_n_8,i_mac_pc_control_counter_n_9}), .\ctrl_ctr_q_reg[1]_0 (\ctrl_ctr_q_reg[1] ), .\ctrl_ctr_q_reg[1]_1 (\ctrl_ctr_q_reg[1]_0 ), .\ctrl_ctr_q_reg[2] (i_mac_pc_control_counter_n_34), .\ctrl_ctr_q_reg[3] (i_mac_pc_control_counter_n_30), .\ctrl_ctr_q_reg[3]_0 (i_mac_pc_control_counter_n_12), .\ctrl_ctr_q_reg[4] (i_mac_pc_control_counter_n_29), .\ctrl_ctr_q_reg[4]_0 (\ctrl_ctr_q_reg[4] ), .\ctrl_ctr_q_reg[4]_1 (\ctrl_ctr_q_reg[4]_0 ), .\curr_state[0]_i_3_0 (\curr_state[0]_i_3 ), .\curr_state[0]_i_3_1 (\curr_state[0]_i_3_0 ), .\curr_state[1]_i_4_0 (\curr_state[1]_i_4 ), .\curr_state[5]_i_10_0 (\curr_state[5]_i_10 ), .\curr_state[5]_i_4_0 (i_mac_pc_reintegration_counter_n_0), .\curr_state[5]_i_5_0 (\curr_state[5]_i_5 ), .curr_state_0(curr_state_0), .curr_state_1(curr_state_1), .curr_state_2(curr_state_2), .curr_state_4(curr_state_4), .curr_state_6(curr_state_6), .\curr_state_reg[0]_0 (\curr_state_reg[0] ), .\curr_state_reg[0]_1 (\curr_state_reg[0]_0 ), .\curr_state_reg[0]_10 (i_mac_pc_control_counter_n_35), .\curr_state_reg[0]_2 (i_mac_pc_fsm_n_104), .\curr_state_reg[0]_3 (rx_store_stuff_count), .\curr_state_reg[0]_4 (\curr_state_reg[0]_1 ), .\curr_state_reg[0]_5 (err_pos), .\curr_state_reg[0]_6 (i_mac_pc_fsm_n_167), .\curr_state_reg[0]_7 (i_mac_pc_fsm_n_190), .\curr_state_reg[0]_8 (\curr_state_reg[0]_2 ), .\curr_state_reg[0]_9 (\curr_state_reg[0]_3 ), .\curr_state_reg[1]_0 (i_mac_pc_fsm_n_27), .\curr_state_reg[1]_1 (\curr_state_reg[1] ), .\curr_state_reg[1]_2 (\curr_state_reg[1]_0 ), .\curr_state_reg[1]_3 (\curr_state_reg[1]_1 ), .\curr_state_reg[1]_4 (i_mac_pc_fsm_n_162), .\curr_state_reg[1]_5 (i_mac_pc_fsm_n_172), .\curr_state_reg[1]_6 ({arbitration_part,i_mac_pc_fsm_n_175}), .\curr_state_reg[1]_7 (\curr_state_reg[1]_2 ), .\curr_state_reg[2]_0 (\curr_state_reg[2] ), .\curr_state_reg[2]_1 (\curr_state_reg[2]_0 ), .\curr_state_reg[2]_2 (\curr_state_reg[2]_1 ), .\curr_state_reg[2]_3 (i_mac_pc_fsm_n_107), .\curr_state_reg[2]_4 (\curr_state_reg[2]_2 ), .\curr_state_reg[2]_5 (i_mac_pc_fsm_n_193), .\curr_state_reg[3]_0 (i_mac_pc_fsm_n_106), .\curr_state_reg[3]_1 (i_mac_pc_fsm_n_108), .\curr_state_reg[3]_2 (i_mac_pc_fsm_n_134), .\curr_state_reg[3]_3 (\compl_ctr_q_reg[7] [2]), .\curr_state_reg[3]_4 (i_mac_pc_fsm_n_161), .\curr_state_reg[3]_5 (i_mac_pc_fsm_n_171), .\curr_state_reg[3]_6 (\curr_state_reg[3] ), .\curr_state_reg[3]_7 (\curr_state_reg[3]_0 ), .\curr_state_reg[4]_0 (i_mac_pc_fsm_n_110), .\curr_state_reg[4]_1 (\curr_state_reg[4] ), .\curr_state_reg[4]_2 (\curr_state_reg[4]_0 ), .\curr_state_reg[4]_3 (\curr_state_reg[4]_1 ), .\curr_state_reg[4]_4 (i_mac_pc_err_detector_n_20), .\curr_state_reg[5]_0 (i_mac_pc_fsm_n_90), .\curr_state_reg[5]_1 (ctrl_ctr_q), .\curr_state_reg[5]_2 ({rx_store_base_id,i_mac_pc_fsm_n_137}), .\curr_state_reg[5]_3 (i_mac_pc_fsm_n_138), .\curr_state_reg[5]_4 (\curr_state_reg[5] ), .\curr_state_reg[5]_5 (\curr_state_reg[5]_0 ), .\curr_state_reg[5]_6 (\curr_state_reg[5]_1 ), .\curr_state_reg[5]_7 (\curr_state_reg[5]_2 ), .data_halt_d1_out(data_halt_d1_out), .data_in_IBUF(data_in_IBUF), .destuff_enable(destuff_enable), .destuff_enable_reg_0(destuff_enable_reg), .destuff_enable_reg_1(destuff_enable_reg_0), .destuff_enable_reg_2(destuff_enable_reg_1), .destuff_enable_reg_3(destuff_enable_reg_2), .enable_prev(enable_prev), .err_capt_err_erp_reg(i_mac_pc_err_detector_n_12), .\err_capt_err_pos_q_reg[0] (\err_capt_err_pos_q_reg[0]_0 ), .\err_capt_err_type_q[2]_i_8_0 (\err_capt_err_type_q[2]_i_8 ), .\err_capt_err_type_q_reg[1] (\err_capt_err_type_q_reg[1] ), .err_frm_req_reg(i_mac_pc_fsm_n_14), .err_frm_req_reg_0(err_frm_req_reg_0), .err_frm_req_reg_1(retr_ctr_q), .err_frm_req_reg_10(err_frm_req_reg_6), .err_frm_req_reg_2({ctrl_ctr_d[4:3],ctrl_ctr_d[1:0]}), .err_frm_req_reg_3(i_mac_pc_fsm_n_141), .err_frm_req_reg_4(err_frm_req_reg_1), .err_frm_req_reg_5(i_mac_pc_fsm_n_151), .err_frm_req_reg_6(err_frm_req_reg_2), .err_frm_req_reg_7(err_frm_req_reg_3), .err_frm_req_reg_8(err_frm_req_reg_5), .err_frm_req_reg_9(i_mac_pc_fsm_n_194), .\exp_seg_length_q_reg[0] (\exp_seg_length_q_reg[0] ), .\exp_seg_length_q_reg[0]_0 (\exp_seg_length_q_reg[0]_0 ), .first_ssp_q0(first_ssp_q0), .fixed_prev_q(fixed_prev_q), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_1 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[0].reg_value_r_reg[0]_2 ), .\g_bit[0].reg_value_r_reg[0]_3 (\g_bit[0].reg_value_r_reg[0]_3 ), .\g_bit[0].reg_value_r_reg[0]_4 (i_mac_pc_fsm_n_170), .\g_bit[1].reg_value_r_reg[1] (\g_bit[1].reg_value_r_reg[1] ), .\g_byte_shift_reg[1].shift_reg_q_reg[1][0] ({\g_byte_shift_reg[1].shift_reg_q_reg[1][1] [14],\g_byte_shift_reg[1].shift_reg_q_reg[1][1] [5]}), .ident_valid_q(ident_valid_q), .ident_valid_q_reg(ident_valid_q_reg), .int_status_i_2__1_0(int_status_i_2__1), .int_status_i_2__1_1(int_status_i_2__1_0), .int_status_i_4_0(int_status_i_4), .int_status_reg(int_status_reg), .int_status_reg_0(int_status_reg_0), .int_status_reg_1(int_status_reg_1), .int_status_reg_2(int_status_reg_2), .is_tseg1(is_tseg1), .is_tseg2(is_tseg2), .mr_command_ercrst_q_reg_0(i_mac_pc_err_detector_n_18), .mr_ctr_pres_efd_q(mr_ctr_pres_efd_q), .mr_ctr_pres_efd_q_reg(mr_ctr_pres_efd_q_reg), .mr_ctr_pres_enorm_q(mr_ctr_pres_enorm_q), .mr_ctr_pres_enorm_q_reg(mr_ctr_pres_enorm_q_reg), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .\mr_ctrl_out[ssp_cfg_ssp_src] (\mr_ctrl_out[ssp_cfg_ssp_src] ), .mr_int_stat_txbhci_o(mr_int_stat_txbhci_o), .mr_status_pexs_reg_0(mr_status_pexs_reg), .mr_status_pexs_reg_1(mr_status_pexs_reg_0), .\nom_err_ctr_q_reg[0] (i_mac_pc_err_detector_n_16), .p_0_out(p_0_out), .p_131_in(p_131_in), .\pc_dbg[is_arbitration] (\pc_dbg[is_arbitration] ), .prev_val_d(prev_val_d), .\r_data[7]_i_3__0_0 (\r_data[7]_i_3__0 ), .\r_data_reg[12] (\r_data_reg[12] ), .\r_data_reg[12]_0 (\r_data_reg[12]_0 ), .\r_data_reg[13] (\r_data_reg[13] ), .\r_data_reg[13]_0 (\r_data_reg[13]_0 ), .\r_data_reg[13]_1 (\r_data_reg[13]_1 ), .\r_data_reg[13]_2 (\r_data_reg[13]_2 ), .\r_data_reg[13]_3 (\r_data_reg[13]_3 ), .\r_data_reg[13]_4 (\r_data_reg[13]_4 ), .\r_data_reg[15] (\r_data_reg[15] ), .\r_data_reg[15]_0 (\r_data_reg[15]_0 ), .\r_data_reg[15]_1 (\r_data_reg[15]_1 ), .\r_data_reg[15]_2 (\r_data_reg[15]_2 ), .\r_data_reg[16] (\r_data_reg[16] ), .\r_data_reg[16]_0 (\r_data_reg[16]_0 ), .\r_data_reg[16]_1 (\r_data_reg[16]_1 ), .\r_data_reg[18] (i_mac_pc_control_counter_n_1), .\r_data_reg[18]_0 (\r_data_reg[18] ), .\r_data_reg[18]_1 (\r_data_reg[18]_0 ), .\r_data_reg[18]_2 (\r_data_reg[18]_1 ), .\r_data_reg[18]_3 (\r_data_reg[18]_2 ), .\r_data_reg[18]_4 (\r_data_reg[18]_3 ), .rec_abort_f(rec_abort_f), .rec_abort_reg_0(rec_abort_reg), .rec_abort_reg_1(rec_abort_reg_0), .rec_abort_reg_2(err_frm_req_reg), .\rec_dlc_reg[0] (\rec_dlc_reg[0] ), .rec_ivld(rec_ivld), .rec_ivld_q_reg_0(rec_ivld_q_reg), .rec_lbpf(rec_lbpf), .rec_lbpf_q_reg_0(rec_lbpf_q_reg), .rec_valid_reg_0(rec_valid_reg), .rec_valid_reg_1(rec_valid_reg_0), .rec_valid_reg_2(i_mac_pc_control_counter_n_26), .rec_valid_reg_3(rec_valid_reg_1), .reg_q(reg_q), .reg_q_reg(i_mac_pc_fsm_n_84), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(E), .reg_q_reg_10(i_mac_pc_fsm_n_165), .reg_q_reg_11(i_mac_pc_fsm_n_166), .reg_q_reg_12(reg_q_reg_6), .reg_q_reg_13(err_capt_err_type_d), .reg_q_reg_14(reg_q_reg_8), .reg_q_reg_15(reg_q_reg_9), .reg_q_reg_16(reg_q_reg_10), .reg_q_reg_17(reg_q_reg_11), .reg_q_reg_18(i_mac_pc_err_detector_n_19), .reg_q_reg_2(reg_q_reg_0), .reg_q_reg_3(compl_ctr_ce), .reg_q_reg_4(reg_q_reg_1), .reg_q_reg_5(reg_q_reg_2), .reg_q_reg_6(reg_q_reg_3), .reg_q_reg_7(reg_q_reg_4), .reg_q_reg_8(reg_q_reg_5), .reg_q_reg_9(\i_shift_reg_byte/shift_reg_in ), .reinteg_ctr_ce(reinteg_ctr_ce), .retr_ctr_add(retr_ctr_add), .\retr_ctr_q_reg[0] (retr_ctr_d), .\retr_ctr_q_reg[0]_0 (\retr_ctr_q_reg[3] [0]), .\retr_ctr_q_reg[3] (\retr_ctr_q_reg[3]_0 ), .rx_data_nbs_prev_reg_0(rx_data_nbs_prev), .rx_data_nbs_prev_reg_1(rx_data_nbs_prev_reg), .rx_data_sync_prev_reg(rx_data_sync_prev_reg), .rx_data_wbs(rx_data_wbs), .\rx_stuff_count_reg[3] (\ctrl_ctr_q_reg[7] ), .\same_bits_q_reg[2] (\same_bits_q_reg[2] ), .sbe_IBUF(sbe_IBUF), .\segm_counter_q_reg[0] (\segm_counter_q_reg[0] ), .\segm_counter_q_reg[0]_0 (\segm_counter_q_reg[0]_0 ), .\segm_counter_q_reg[0]_1 (\segm_counter_q_reg[0]_1 ), .\segm_counter_q_reg[0]_2 (\segm_counter_q_reg[0]_2 ), .\shift_regs[27]_i_2 (i_mac_pc_control_counter_n_15), .\shift_regs[31]_i_7_0 (\shift_regs[31]_i_7 ), .\shift_regs_reg[0] (\shift_regs_reg[0]_0 ), .\shift_regs_reg[0]_0 (\shift_regs_reg[0]_1 ), .\shift_regs_reg[11] (\shift_regs_reg[11] ), .\shift_regs_reg[11]_0 (\shift_regs_reg[11]_0 ), .\shift_regs_reg[12] (\shift_regs_reg[12] ), .\shift_regs_reg[12]_0 (\shift_regs_reg[12]_0 ), .\shift_regs_reg[13] (\shift_regs_reg[13] ), .\shift_regs_reg[14] (\shift_regs_reg[14] ), .\shift_regs_reg[14]_0 (\shift_regs_reg[14]_0 ), .\shift_regs_reg[15] (\shift_regs_reg[15] ), .\shift_regs_reg[15]_0 (\shift_regs_reg[15]_0 ), .\shift_regs_reg[16] (\shift_regs_reg[16] ), .\shift_regs_reg[16]_0 (\shift_regs_reg[16]_0 ), .\shift_regs_reg[16]_1 (\shift_regs_reg[16]_1 ), .\shift_regs_reg[17] (\shift_regs_reg[17] ), .\shift_regs_reg[17]_0 (\shift_regs_reg[17]_0 ), .\shift_regs_reg[18] (\shift_regs_reg[18] ), .\shift_regs_reg[18]_0 (\shift_regs_reg[18]_0 ), .\shift_regs_reg[19] (\shift_regs_reg[19] ), .\shift_regs_reg[19]_0 (\shift_regs_reg[19]_0 ), .\shift_regs_reg[1] (\shift_regs_reg[1] ), .\shift_regs_reg[20] (\shift_regs_reg[20] ), .\shift_regs_reg[20]_0 (\shift_regs_reg[20]_0 ), .\shift_regs_reg[21] (\shift_regs_reg[21] ), .\shift_regs_reg[21]_0 (\shift_regs_reg[21]_0 ), .\shift_regs_reg[22] (\shift_regs_reg[22] ), .\shift_regs_reg[22]_0 (\shift_regs_reg[22]_0 ), .\shift_regs_reg[23] (\shift_regs_reg[23] ), .\shift_regs_reg[24] (\shift_regs_reg[24] ), .\shift_regs_reg[25] (\shift_regs_reg[25] ), .\shift_regs_reg[25]_0 (\shift_regs_reg[25]_0 ), .\shift_regs_reg[26] (\shift_regs_reg[26] ), .\shift_regs_reg[26]_0 (\shift_regs_reg[26]_0 ), .\shift_regs_reg[27] (\shift_regs_reg[27] ), .\shift_regs_reg[27]_0 (\shift_regs_reg[27]_0 ), .\shift_regs_reg[28] (\shift_regs_reg[28] ), .\shift_regs_reg[28]_0 (\shift_regs_reg[28]_0 ), .\shift_regs_reg[28]_1 (\shift_regs_reg[28]_1 ), .\shift_regs_reg[28]_2 (\shift_regs_reg[28]_2 ), .\shift_regs_reg[28]_3 (\shift_regs_reg[28]_3 ), .\shift_regs_reg[29] (\shift_regs_reg[29] ), .\shift_regs_reg[29]_0 (\shift_regs_reg[29]_0 ), .\shift_regs_reg[29]_1 (\shift_regs_reg[29]_1 ), .\shift_regs_reg[29]_2 (\shift_regs_reg[29]_2 ), .\shift_regs_reg[2] (\shift_regs_reg[2] ), .\shift_regs_reg[30] (\shift_regs_reg[30] ), .\shift_regs_reg[30]_0 (\shift_regs_reg[30]_0 ), .\shift_regs_reg[30]_1 (\shift_regs_reg[30]_1 ), .\shift_regs_reg[30]_2 (i_mac_pc_control_counter_n_7), .\shift_regs_reg[31] (\shift_regs_reg[31] ), .\shift_regs_reg[31]_0 (\shift_regs_reg[31]_0 ), .\shift_regs_reg[31]_1 (\shift_regs_reg[31]_1 ), .\shift_regs_reg[31]_2 (\shift_regs_reg[31]_2 ), .\sp_control_q_i_reg[0]_0 (\sp_control_q_i_reg[0] ), .\sp_control_q_i_reg[0]_1 (\sp_control_q_i_reg[0]_0 ), .\sp_control_q_i_reg[1]_0 (\sp_control_q_i_reg[1] ), .\sp_control_q_i_reg[1]_1 (\shift_regs_reg[0] ), .\sp_control_q_i_reg[1]_2 (\sp_control_q_i_reg[1]_0 ), .sspc_ena_q(sspc_ena_q), .sspc_ena_q_reg(sspc_ena_q_reg), .store_data_reg_0(i_mac_pc_control_counter_n_10), .store_data_word(store_data_word[6]), .store_metadata_reg_0(store_metadata_reg), .store_metadata_reg_1(store_metadata_reg_0), .stuff_enable_reg_0(stuff_enable), .stuff_err(stuff_err), .stuff_err_d(stuff_err_d), .\sync_control_q_reg[0]_0 (\sync_control_q_reg[0] ), .\sync_control_q_reg[0]_1 (\sync_control_q_reg[0]_0 ), .\sync_control_q_reg[1]_0 (\sync_control_q_reg[1] ), .sync_edge(sync_edge), .sync_edge3__0(sync_edge3__0), .sync_flag(sync_flag), .\timestamp[14] (\timestamp[14] ), .\timestamp[17] (\timestamp[17] ), .\timestamp[41] (\timestamp[41] ), .\timestamp[42] (\timestamp[42] ), .\timestamp[43] (\timestamp[43] ), .\timestamp[7] (\timestamp[7] ), .\timestamp[8] (\timestamp[8] ), .timestamp_IBUF(timestamp_IBUF), .\timestamp_capture_reg[63] (\timestamp_capture_reg[63] ), .\tq_counter_q_reg[7] (\tq_counter_q_reg[7] ), .tran_brs(tran_brs), .tran_delay_meas(tran_delay_meas), .\tran_frame_test[fcrc] (\tran_frame_test[fcrc] ), .tran_frame_valid(tran_frame_valid), .tran_ident_type(tran_ident_type), .tran_is_rtr(tran_is_rtr), .tran_word(tran_word), .tx_data_prev(tx_data_prev), .tx_frame_no_sof_q_reg_0(tx_frame_no_sof), .tx_frame_no_sof_q_reg_1(tx_frame_no_sof_q_reg), .tx_frame_no_sof_q_reg_2(tx_frame_no_sof_q_reg_0), .tx_frame_no_sof_q_reg_3(tx_frame_no_sof_q_reg_1), .tx_frame_no_sof_q_reg_4(tx_frame_no_sof_q_reg_2), .tx_frame_no_sof_q_reg_5(tx_frame_no_sof_q_reg_3), .tx_trigger_q(tx_trigger_q), .txtb_allow_bb(txtb_allow_bb), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .\txtb_hw_cmd_q[err] (\txtb_hw_cmd_q[err] ), .\txtb_hw_cmd_q_reg[arbl]_0 (\txtb_hw_cmd_q_reg[arbl] ), .\txtb_hw_cmd_q_reg[err]_0 (\txtb_hw_cmd_q_reg[err] ), .\txtb_hw_cmd_q_reg[failed]_0 (\txtb_hw_cmd_q_reg[failed] ), .\txtb_hw_cmd_q_reg[failed]_1 (\txtb_hw_cmd_q_reg[failed]_0 ), .\txtb_hw_cmd_q_reg[failed]_2 (\txtb_hw_cmd_q_reg[failed]_1 ), .\txtb_hw_cmd_q_reg[failed]_3 (\txtb_hw_cmd_q_reg[failed]_2 ), .\txtb_hw_cmd_q_reg[failed]_4 (\txtb_hw_cmd_q_reg[failed]_3 ), .\txtb_hw_cmd_q_reg[failed]_5 (\txtb_hw_cmd_q_reg[failed]_4 ), .\txtb_hw_cmd_q_reg[failed]_6 (\txtb_hw_cmd_q_reg[failed]_5 ), .\txtb_hw_cmd_q_reg[failed]_7 (\txtb_hw_cmd_q_reg[failed]_6 ), .\txtb_hw_cmd_q_reg[lock]_0 (\txtb_hw_cmd_q_reg[lock] ), .\txtb_hw_cmd_q_reg[lock]_1 (\txtb_hw_cmd_q_reg[lock]_0 ), .\txtb_hw_cmd_q_reg[lock]_2 (\txtb_hw_cmd_q_reg[lock]_1 ), .\txtb_hw_cmd_q_reg[lock]_3 (\txtb_hw_cmd_q_reg[lock]_2 ), .\txtb_hw_cmd_q_reg[lock]_4 (i_mac_pc_err_detector_n_15), .\txtb_hw_cmd_q_reg[lock]_5 (\txtb_hw_cmd_q_reg[lock]_3 ), .\txtb_hw_cmd_q_reg[valid]_0 (\txtb_hw_cmd_q_reg[valid] ), .\txtb_hw_cmd_q_reg[valid]_1 (\txtb_hw_cmd_q_reg[valid]_0 ), .\txtb_hw_cmd_q_reg[valid]_2 (\txtb_hw_cmd_q_reg[valid]_1 ), .\txtb_hw_cmd_q_reg[valid]_3 (\txtb_hw_cmd_q_reg[valid]_2 ), .\txtb_hw_cmd_q_reg[valid]_4 (\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .\txtb_ptr_q_reg[2]_0 (i_mac_pc_fsm_n_154), .\txtb_ptr_q_reg[2]_1 (i_mac_pc_control_counter_n_25), .\txtb_ptr_q_reg[4]_0 (\txtb_ptr_q_reg[4] ), .\txtb_ptr_q_reg[4]_1 (i_mac_pc_control_counter_n_24), .\txtb_ptr_q_reg[4]_2 (i_mac_pc_control_counter_n_23), .\txtb_ptr_q_reg[4]_3 (txtb_clk_en_d), .\txtb_ptr_q_reg[4]_4 ({i_mac_pc_control_counter_n_19,\compl_ctr_q_reg[7] [3],\compl_ctr_q_reg[7] [1:0]})); mac_pc_reintegration_counter i_mac_pc_reintegration_counter (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reinteg_ctr_ce(reinteg_ctr_ce), .\reinteg_ctr_q_reg[0]_0 (i_mac_pc_fsm_n_110), .\reinteg_ctr_q_reg[2]_0 (i_mac_pc_reintegration_counter_n_0), .\reinteg_ctr_q_reg[3]_0 (i_mac_pc_fsm_n_151), .\reinteg_ctr_q_reg[7]_0 (\shift_regs_reg[0] )); mac_pc_retransmitt_counter i_mac_pc_retransmitt_counter (.D(retr_ctr_d), .E(retr_ctr_q), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .retr_ctr_add(retr_ctr_add), .\retr_ctr_q_reg[3]_0 (\retr_ctr_q_reg[3] ), .\retr_ctr_q_reg[3]_1 (\shift_regs_reg[0] )); mac_pc_rx_shift_reg i_mac_pc_rx_shift_reg (.D({\g_byte_shift_reg[1].shift_reg_q_reg[1][1] [16:15],\g_byte_shift_reg[1].shift_reg_q_reg[1][1] [6:0]}), .E({rx_store_base_id,i_mac_pc_fsm_n_137}), .\FSM_sequential_curr_state_reg[1] (i_mac_pc_rx_shift_reg_n_24), .Q(\rec_dlc_reg[3] ), .S(i_mac_pc_rx_shift_reg_n_28), .\cc_stat[dst_ctr] (\cc_stat[dst_ctr] ), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_match_c5_carry__0(crc_match_c5_carry__0_0), .crc_match_c6_carry__0(crc_match_c6_carry__0), .\crc_match_c6_inferred__0/i__carry (\crc_q_reg[14]_0 [3:1]), .crc_match_q_i_3(\ctrl_ctr_q_reg[4] ), .\ctrl_ctr_q_reg[5] (\sp_control_q_i_reg[1]_0 ), .\ctrl_ctr_q_reg[5]_0 (\ctrl_ctr_q_reg[5]_0 ), .\ctrl_ctr_q_reg[5]_1 (\ctrl_ctr_q_reg[5]_1 ), .\ctrl_ctr_q_reg[5]_2 (\ctrl_ctr_q_reg[5] ), .\ctrl_ctr_q_reg[8] (\ctrl_ctr_q_reg[8] ), .\ctrl_ctr_q_reg[8]_0 (\ctrl_ctr_q_reg[8]_0 ), .\ctrl_ctr_q_reg[8]_1 (\ctrl_ctr_q_reg[6] ), .\ctrl_ctr_q_reg[8]_2 (i_mac_pc_control_counter_n_27), .\ctrl_ctr_q_reg[8]_3 (i_mac_pc_fsm_n_106), .\ctrl_ctr_q_reg[8]_4 (i_mac_pc_fsm_n_190), .\g_bit[0].reg_value_r_reg[0] (i_mac_pc_rx_shift_reg_n_11), .\g_byte_shift_reg[0].shift_reg_q_reg[0][0] (\g_byte_shift_reg[0].shift_reg_q_reg[0][0] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][1] (\g_byte_shift_reg[0].shift_reg_q_reg[0][1] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 (i_mac_pc_rx_shift_reg_n_27), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2] (i_mac_pc_rx_shift_reg_n_25), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 (i_mac_pc_rx_shift_reg_n_26), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 (\g_byte_shift_reg[0].shift_reg_q_reg[0][2] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][5] (i_mac_pc_rx_shift_reg_n_55), .\g_byte_shift_reg[0].shift_reg_q_reg[0][7] (\g_byte_shift_reg[1].shift_reg_q_reg[1][1] [14:7]), .\g_byte_shift_reg[1].shift_reg_q_reg[1][0] (\i_shift_reg_byte/shift_reg_in ), .\g_byte_shift_reg[1].shift_reg_q_reg[1][6] (i_mac_pc_rx_shift_reg_n_29), .\g_byte_shift_reg[2].shift_reg_q_reg[2][0] (i_mac_pc_rx_shift_reg_n_39), .\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 (i_mac_pc_fsm_n_165), .\g_byte_shift_reg[3].shift_reg_q_reg[3][0] (i_mac_pc_fsm_n_166), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg_0 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_1 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_2 ), .\g_ram_rst_false.ram_memory_reg_i_55_0 (\g_ram_rst_false.ram_memory_reg_i_55 [5]), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .rec_brs(rec_brs), .rec_brs_reg_0(rec_brs_reg), .\rec_dlc_reg[0]_0 (\curr_state_reg[0]_1 ), .\rec_dlc_reg[1]_0 (\rec_dlc_reg[1] ), .\rec_dlc_reg[1]_1 (\rec_dlc_reg[1]_0 ), .\rec_dlc_reg[2]_0 (\rec_dlc_reg[2] ), .\rec_dlc_reg[2]_1 (\rec_dlc_reg[2]_0 ), .\rec_dlc_reg[3]_0 (\rec_dlc_reg[3]_0 ), .rec_esi(rec_esi), .rec_esi_reg_0({Q[3:2],i_mac_pc_fsm_n_21,Q[0]}), .rec_esi_reg_1(i_mac_pc_fsm_n_27), .rec_esi_reg_2(i_mac_pc_fsm_n_171), .rec_frame_type_i_reg_0(rec_frame_type_i_reg), .rec_frame_type_i_reg_1(i_mac_pc_fsm_n_134), .rec_frame_type_i_reg_2(\curr_state_reg[4] ), .\rec_ident_reg[28]_0 (\rec_ident_reg[28] ), .rec_ident_type(rec_ident_type), .rec_ident_type_reg_0(i_mac_pc_fsm_n_172), .rec_ident_type_reg_1(i_mac_pc_err_detector_n_15), .rec_ident_type_reg_2(i_mac_pc_fsm_n_107), .rec_is_rtr(rec_is_rtr), .rec_is_rtr_i_reg_0(rec_is_rtr_i_reg), .rec_is_rtr_i_reg_1(i_mac_pc_fsm_n_138), .reg_q_reg(i_mac_pc_rx_shift_reg_n_23), .reg_q_reg_0(ctrl_ctr_d[8]), .reg_q_reg_1(reg_q_reg_7), .reg_q_reg_2(\shift_regs_reg[0] ), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_shift_cmd(rx_shift_cmd), .\rx_stuff_count_reg[3]_0 (rx_store_stuff_count), .scan_mode_IBUF(scan_mode_IBUF), .store_data_word(store_data_word)); mac_pc_tx_shift_reg i_mac_pc_tx_shift_reg (.D({p_1_in,\shift_regs_reg[0]_2 }), .E(i_mac_pc_fsm_n_89), .Q({tx_sr_output,i_mac_pc_tx_shift_reg_n_1,i_mac_pc_tx_shift_reg_n_2,i_mac_pc_tx_shift_reg_n_3,i_mac_pc_tx_shift_reg_n_4,i_mac_pc_tx_shift_reg_n_5,i_mac_pc_tx_shift_reg_n_6,i_mac_pc_tx_shift_reg_n_7,i_mac_pc_tx_shift_reg_n_8,i_mac_pc_tx_shift_reg_n_9,i_mac_pc_tx_shift_reg_n_10,i_mac_pc_tx_shift_reg_n_11,i_mac_pc_tx_shift_reg_n_12,i_mac_pc_tx_shift_reg_n_13,i_mac_pc_tx_shift_reg_n_14,i_mac_pc_tx_shift_reg_n_15,i_mac_pc_tx_shift_reg_n_16,i_mac_pc_tx_shift_reg_n_17,i_mac_pc_tx_shift_reg_n_18,i_mac_pc_tx_shift_reg_n_19,i_mac_pc_tx_shift_reg_n_20,i_mac_pc_tx_shift_reg_n_21,i_mac_pc_tx_shift_reg_n_22,i_mac_pc_tx_shift_reg_n_23,i_mac_pc_tx_shift_reg_n_24,i_mac_pc_tx_shift_reg_n_25,i_mac_pc_tx_shift_reg_n_26,i_mac_pc_tx_shift_reg_n_27,i_mac_pc_tx_shift_reg_n_28,i_mac_pc_tx_shift_reg_n_29,i_mac_pc_tx_shift_reg_n_30,i_mac_pc_tx_shift_reg_n_31}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\shift_regs_reg[0] (\shift_regs_reg[0] )); endmodule module mac_pc_tx_shift_reg (Q, E, D, clk_sys_IBUF_BUFG, \shift_regs_reg[0] ); output [31:0]Q; input [0:0]E; input [31:0]D; input clk_sys_IBUF_BUFG; input \shift_regs_reg[0] ; wire [31:0]D; wire [0:0]E; wire [31:0]Q; wire clk_sys_IBUF_BUFG; wire \shift_regs_reg[0] ; shift_reg_preload i_tx_shift_reg (.D(D), .E(E), .Q(Q), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\shift_regs_reg[0]_0 (\shift_regs_reg[0] )); endmodule module mac_top (store_metadata, rec_valid, rec_abort, err_frm_req, \txtb_hw_cmd[lock] , \txtb_hw_cmd[valid] , \txtb_hw_cmd[failed] , \cc_stat[err_erp] , err_detected, err_warning_limit_q, destuffed, \tx_err_ctr_q_reg[7] , Q, D, \nom_err_ctr_q_reg[12] , \curr_state_reg[2] , \timestamp[8] , \data_err_ctr_q_reg[15] , \FSM_sequential_curr_state_reg[1] , \tx_err_ctr_q_reg[6] , \tx_err_ctr_q_reg[7]_0 , \nom_err_ctr_q_reg[0] , \rx_err_ctr_q_reg[1] , \rx_err_ctr_q_reg[3] , \rx_err_ctr_q_reg[5] , \rx_err_ctr_q_reg[7] , \rx_err_ctr_q_reg[8] , \timestamp[7] , \curr_state_reg[3] , \timestamp[41] , \timestamp[42] , \timestamp[43] , \alc_alc_bit_reg[4] , \nom_err_ctr_q_reg[11] , \FSM_sequential_curr_state_reg[1]_0 , curr_state, \err_capt_err_type_q_reg[0] , \err_capt_err_type_q_reg[2] , err_capt_err_erp_reg, \err_capt_err_pos_q_reg[0] , \err_capt_err_pos_q_reg[3] , rec_abort_reg, rec_valid_reg, \FSM_onehot_curr_state_reg[5] , \rec_dlc_reg[2] , \rec_dlc_reg[3] , \FSM_onehot_curr_state_reg[5]_0 , \g_bit[0].reg_value_r_reg[0] , E, \rec_dlc_reg[2]_0 , rec_frame_type, \rec_dlc_reg[1] , \rec_dlc_reg[3]_0 , rec_is_rtr_i, \txtb_hw_cmd_q_reg[failed] , \txtb_hw_cmd_q_reg[err] , \txtb_hw_cmd_q_reg[failed]_0 , \txtb_hw_cmd_q_reg[failed]_1 , \txtb_hw_cmd_q_reg[failed]_2 , \txtb_hw_cmd_q_reg[lock] , \txtb_hw_cmd_q_reg[failed]_3 , \txtb_hw_cmd_q_reg[failed]_4 , \txtb_hw_cmd_q_reg[failed]_5 , \txtb_hw_cmd_q_reg[lock]_0 , \FSM_sequential_curr_state_reg[0] , \txtb_hw_cmd_q_reg[valid] , \txtb_hw_cmd_q_reg[valid]_0 , rec_abort_f, \curr_state_reg[2]_0 , \curr_state_reg[0] , arbitration_lost, pc_rx_data_nbs, \cc_stat[is_err_active] , \curr_state_reg[1] , \curr_state_reg[2]_1 , reg_q_reg, \curr_state_reg[0]_0 , \sp_control_q_i_reg[1] , \cc_stat[is_transmitter] , \pc_dbg[is_arbitration] , \retr_ctr_q_reg[3] , reg_q_reg_0, \crc_q_reg[1] , \cc_stat[bst_ctr] , \curr_state_reg[1]_0 , crc_data_tx_wbs, \sp_control_q_i_reg[0] , br_shifted, \curr_state_reg[2]_2 , \g_bit[0].reg_value_r_reg[0]_0 , \cc_stat[dst_ctr] , \crc_q_reg[10] , \crc_q_reg[9] , \crc_q_reg[8] , \crc_q_reg[7] , \crc_q_reg[2] , \crc_q_reg[1]_0 , \crc_q_reg[0] , \rec_dlc_reg[1]_0 , bit_err_enable, \g_byte_shift_reg[0].shift_reg_q_reg[0][1] , store_data_word, rec_is_rtr, tran_delay_meas, \compl_ctr_q_reg[7] , \curr_state_reg[3]_0 , \txtb_ptr_q_reg[4] , \curr_state_reg[5] , err_frm_req_reg, \curr_state_reg[5]_0 , \rx_err_ctr_q_reg[8]_0 , err_frm_req_reg_0, \curr_state_reg[5]_1 , \tq_counter_q_reg[7] , \sync_control_q_reg[0] , \sync_control_q_reg[1] , \sp_control_q_i_reg[0]_0 , first_ssp_q0, tx_trigger_ssp, \g_bit[1].reg_value_r_reg[1] , p_0_out, \data_err_ctr_q_reg[4] , \data_err_ctr_q_reg[5] , \data_err_ctr_q_reg[8] , \nom_err_ctr_q_reg[2] , \txtb_hw_cmd_q_reg[lock]_1 , err_frm_req_reg_1, \curr_state_reg[0]_1 , \curr_state_reg[3]_1 , err_frm_req_reg_2, \sync_control_q_reg[0]_0 , int_status_reg, int_status_reg_0, sspc_ena_q_reg, btmc_meas_running_q_reg, \write_pointer_q_reg[0] , \cc_stat[status_pexs] , rec_lbpf, rec_ivld, \alc_alc_id_field_reg[2] , \rec_ident_reg[28] , rec_ident_type, rec_brs, rec_esi, clk_sys_IBUF_BUFG, reg_q_reg_1, \txtb_hw_cmd_q[err] , \mr_ctrl_out[ctr_pres_prx] , \mr_ctrl_out[ctr_pres_ptx] , reg_q_reg_2, \mr_ctrl_out[ctr_pres_enorm] , \mr_ctrl_out[ctr_pres_efd] , S, DI, next_state2_carry__0, \next_state2_inferred__0/i__carry__0 , reg_q_reg_3, sbe_IBUF, adress_IBUF, \r_data_reg[19] , \r_data_reg[16] , \r_data_reg[16]_0 , \r_data_reg[15] , \r_data_reg[15]_0 , \r_data_reg[15]_1 , \r_data_reg[13] , \r_data_reg[13]_0 , \r_data_reg[13]_1 , \r_data_reg[13]_2 , \r_data_reg[13]_3 , \r_data_reg[18] , \r_data_reg[18]_0 , \r_data_reg[18]_1 , \r_data_reg[18]_2 , \r_data_reg[4] , \r_data_reg[4]_0 , \r_data_reg[6] , \r_data_reg[12] , \r_data_reg[12]_0 , \r_data_reg[6]_0 , \r_data_reg[6]_1 , \r_data[6]_i_2 , timestamp_IBUF, \r_data_reg[20] , \r_data_reg[20]_0 , \mr_ctrl_out[btr_ph2] , \r_data_reg[19]_0 , \mr_ctrl_out[settings_rtrth] , \r_data[19]_i_2 , \r_data_reg[22] , \r_data_reg[23] , \r_data_reg[20]_1 , \r_data[0]_i_2 , \r_data[1]_i_2__0 , \r_data_reg[3]_i_5 , \r_data[4]_i_2 , \r_data[5]_i_2 , \r_data_reg[7]_i_6 , \r_data_reg[8]_i_4 , \r_data_reg[17] , \r_data_reg[17]_0 , \r_data[7]_i_3__0 , \r_data_reg[14] , \mr_ctrl_out[ssp_cfg_ssp_offset] , \r_data[19]_i_2_0 , \r_data_reg[18]_3 , \r_data_reg[18]_4 , \r_data[11]_i_2__0 , \mr_ctrl_out[btr_fd_ph2_fd] , \mr_ctrl_out[mode_rom] , \mr_tx_priority[1] , \r_data_reg[5]_i_5 , \r_data[4]_i_2_0 , \mr_ctrl_out[mode_fde] , \mr_tx_priority[0] , \r_data[0]_i_5 , \g_ram_rst_false.ram_memory_reg_i_55 , ident_valid_q, \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \FSM_onehot_curr_state_reg[1] , \mr_ctrl_out[mode_erfm] , \mr_ctrl_out[rx_settings_rtsop] , \g_ram_rst_false.ram_memory_reg_2 , curr_state_0, int_status_i_4, \FSM_sequential_curr_state_reg[2] , abort_or_skipped, \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , curr_state_1, abort_applied, \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state[1]_i_2__0 , txtb_hw_cmd_cs, curr_state_2, \FSM_sequential_curr_state_reg[2]_1 , abort_or_skipped_3, \FSM_sequential_curr_state_reg[1]_3 , curr_state_4, abort_applied_5, \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state[1]_i_2__2 , curr_state_6, \FSM_sequential_curr_state[0]_i_7 , \FSM_sequential_curr_state[2]_i_3__3 , \FSM_sequential_curr_state[2]_i_3__3_0 , \FSM_sequential_curr_state[0]_i_7_0 , \shift_regs_reg[0] , \shift_regs_reg[24] , tran_word, \shift_regs_reg[25] , \shift_regs_reg[25]_0 , \shift_regs_reg[26] , \shift_regs_reg[26]_0 , \shift_regs_reg[27] , \shift_regs_reg[28] , \shift_regs_reg[28]_0 , \shift_regs_reg[29] , \shift_regs_reg[31] , \shift_regs_reg[31]_0 , \shift_regs_reg[16] , \shift_regs_reg[16]_0 , \shift_regs_reg[17] , \shift_regs_reg[17]_0 , \shift_regs_reg[18] , \shift_regs_reg[18]_0 , \shift_regs_reg[19] , \shift_regs_reg[19]_0 , \shift_regs_reg[20] , \shift_regs_reg[21] , \shift_regs_reg[22] , \shift_regs_reg[11] , \shift_regs_reg[11]_0 , \shift_regs_reg[12] , \shift_regs_reg[12]_0 , \shift_regs_reg[14] , \shift_regs_reg[15] , \shift_regs_reg[1] , \shift_regs_reg[2] , tran_frame_valid, q_i, scan_mode_IBUF, rst_n_out_OBUF, tx_frame_no_sof_q_reg, \shift_regs_reg[27]_0 , \shift_regs_reg[30] , \shift_regs_reg[31]_1 , \retr_ctr_q_reg[3]_0 , \mr_ctrl_out[ctr_pres_ctpv] , \mr_ctrl_out[settings_rtrle] , \mr_ctrl_out[settings_nisofd] , bit_err, can_tx_OBUF, \shift_regs_reg[28]_1 , \shift_regs_reg[28]_2 , \tran_frame_test[fcrc] , \shift_regs_reg[29]_0 , \tran_frame_test[fstc] , \shift_regs_reg[30]_0 , \mr_ctrl_out[settings_ilbp] , is_tseg2, \same_bits_q_reg[2] , is_tseg1, reg_q_reg_4, sync_edge, \mr_ctrl_out[settings_pex] , \ctrl_ctr_q_reg[1] , \mr_ctrl_out[ssp_cfg_ssp_src] , \txtb_hw_cmd_q_reg[arbl] , tran_ident_type, \err_capt_err_type_q[2]_i_8 , \shift_regs_reg[13] , \shift_regs_reg[13]_0 , \shift_regs_reg[14]_0 , \shift_regs_reg[15]_0 , \shift_regs_reg[16]_1 , \shift_regs_reg[20]_0 , \shift_regs_reg[21]_0 , \shift_regs_reg[22]_0 , \shift_regs_reg[23] , \mr_ctrl_out[settings_ena] , \curr_state[0]_i_3 , destuff_enable_reg, tran_frame_type, tran_brs, bit_err_q_i_2, \mr_ctrl_out[mode_bmm] , reg_q_reg_5, tran_is_rtr, \txtb_ptr_q_reg[4]_0 , \txtb_ptr_q_reg[4]_1 , \txtb_ptr_q_reg[4]_2 , \ctrl_ctr_q_reg[8] , \ctrl_ctr_q_reg[8]_0 , \ctrl_ctr_q_reg[6] , \ctrl_ctr_q_reg[5] , \ctrl_ctr_q_reg[5]_0 , \mr_ctrl_out[mode_stm] , rx_data_wbs, \mr_ctrl_out[ewl_ew_limit] , \mr_ctrl_out[erp_erp_limit] , \segm_counter_q_reg[0] , \segm_counter_q_reg[0]_0 , \segm_counter_q_reg[0]_1 , \exp_seg_length_q_reg[0] , \exp_seg_length_q_reg[0]_0 , sync_edge3__0, \segm_counter_q_reg[0]_2 , tx_data_prev, \r_data_reg[20]_2 , \r_data_reg[21] , \r_data_reg[24] , \r_data_reg[2] , \r_data_reg[16]_1 , \r_data_reg[14]_i_2 , \r_data_reg[15]_2 , \mr_ctrl_out[settings_tbfbo] , sync_flag, int_status_reg_1, int_status_reg_2, data_in_IBUF, int_status_reg_3, mr_int_stat_txbhci_o, mr_status_pexs_reg, mr_int_stat_fcsi_o, sspc_ena_q, btmc_meas_running_q, \write_pointer_q_reg[0]_0 , mr_status_pexs_reg_0, \bst_ctr_q_reg[0] , \dst_ctr_q_reg[1] , txtb_allow_bb, int_status_i_2__1); output store_metadata; output rec_valid; output rec_abort; output err_frm_req; output \txtb_hw_cmd[lock] ; output \txtb_hw_cmd[valid] ; output \txtb_hw_cmd[failed] ; output \cc_stat[err_erp] ; output err_detected; output err_warning_limit_q; output destuffed; output [7:0]\tx_err_ctr_q_reg[7] ; output [7:0]Q; output [8:0]D; output [2:0]\nom_err_ctr_q_reg[12] ; output \curr_state_reg[2] ; output \timestamp[8] ; output [6:0]\data_err_ctr_q_reg[15] ; output [1:0]\FSM_sequential_curr_state_reg[1] ; output \tx_err_ctr_q_reg[6] ; output \tx_err_ctr_q_reg[7]_0 ; output \nom_err_ctr_q_reg[0] ; output \rx_err_ctr_q_reg[1] ; output \rx_err_ctr_q_reg[3] ; output \rx_err_ctr_q_reg[5] ; output \rx_err_ctr_q_reg[7] ; output \rx_err_ctr_q_reg[8] ; output \timestamp[7] ; output [0:0]\curr_state_reg[3] ; output \timestamp[41] ; output \timestamp[42] ; output \timestamp[43] ; output [2:0]\alc_alc_bit_reg[4] ; output \nom_err_ctr_q_reg[11] ; output \FSM_sequential_curr_state_reg[1]_0 ; output [1:0]curr_state; output \err_capt_err_type_q_reg[0] ; output [2:0]\err_capt_err_type_q_reg[2] ; output err_capt_err_erp_reg; output \err_capt_err_pos_q_reg[0] ; output [3:0]\err_capt_err_pos_q_reg[3] ; output rec_abort_reg; output [2:0]rec_valid_reg; output \FSM_onehot_curr_state_reg[5] ; output \rec_dlc_reg[2] ; output [3:0]\rec_dlc_reg[3] ; output \FSM_onehot_curr_state_reg[5]_0 ; output \g_bit[0].reg_value_r_reg[0] ; output [0:0]E; output \rec_dlc_reg[2]_0 ; output rec_frame_type; output \rec_dlc_reg[1] ; output \rec_dlc_reg[3]_0 ; output rec_is_rtr_i; output \txtb_hw_cmd_q_reg[failed] ; output \txtb_hw_cmd_q_reg[err] ; output \txtb_hw_cmd_q_reg[failed]_0 ; output \txtb_hw_cmd_q_reg[failed]_1 ; output \txtb_hw_cmd_q_reg[failed]_2 ; output \txtb_hw_cmd_q_reg[lock] ; output \txtb_hw_cmd_q_reg[failed]_3 ; output \txtb_hw_cmd_q_reg[failed]_4 ; output \txtb_hw_cmd_q_reg[failed]_5 ; output \txtb_hw_cmd_q_reg[lock]_0 ; output \FSM_sequential_curr_state_reg[0] ; output \txtb_hw_cmd_q_reg[valid] ; output \txtb_hw_cmd_q_reg[valid]_0 ; output rec_abort_f; output \curr_state_reg[2]_0 ; output \curr_state_reg[0] ; output arbitration_lost; output pc_rx_data_nbs; output \cc_stat[is_err_active] ; output \curr_state_reg[1] ; output \curr_state_reg[2]_1 ; output reg_q_reg; output \curr_state_reg[0]_0 ; output \sp_control_q_i_reg[1] ; output \cc_stat[is_transmitter] ; output \pc_dbg[is_arbitration] ; output [3:0]\retr_ctr_q_reg[3] ; output reg_q_reg_0; output [1:0]\crc_q_reg[1] ; output [2:0]\cc_stat[bst_ctr] ; output \curr_state_reg[1]_0 ; output crc_data_tx_wbs; output \sp_control_q_i_reg[0] ; output br_shifted; output \curr_state_reg[2]_2 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output [2:0]\cc_stat[dst_ctr] ; output \crc_q_reg[10] ; output \crc_q_reg[9] ; output \crc_q_reg[8] ; output \crc_q_reg[7] ; output \crc_q_reg[2] ; output \crc_q_reg[1]_0 ; output \crc_q_reg[0] ; output \rec_dlc_reg[1]_0 ; output bit_err_enable; output \g_byte_shift_reg[0].shift_reg_q_reg[0][1] ; output [31:0]store_data_word; output rec_is_rtr; output tran_delay_meas; output \compl_ctr_q_reg[7] ; output [2:0]\curr_state_reg[3]_0 ; output [4:0]\txtb_ptr_q_reg[4] ; output [0:0]\curr_state_reg[5] ; output [0:0]err_frm_req_reg; output \curr_state_reg[5]_0 ; output \rx_err_ctr_q_reg[8]_0 ; output [0:0]err_frm_req_reg_0; output [0:0]\curr_state_reg[5]_1 ; output \tq_counter_q_reg[7] ; output \sync_control_q_reg[0] ; output [1:0]\sync_control_q_reg[1] ; output \sp_control_q_i_reg[0]_0 ; output first_ssp_q0; output tx_trigger_ssp; output \g_bit[1].reg_value_r_reg[1] ; output p_0_out; output \data_err_ctr_q_reg[4] ; output \data_err_ctr_q_reg[5] ; output \data_err_ctr_q_reg[8] ; output \nom_err_ctr_q_reg[2] ; output \txtb_hw_cmd_q_reg[lock]_1 ; output err_frm_req_reg_1; output \curr_state_reg[0]_1 ; output \curr_state_reg[3]_1 ; output err_frm_req_reg_2; output \sync_control_q_reg[0]_0 ; output int_status_reg; output int_status_reg_0; output sspc_ena_q_reg; output btmc_meas_running_q_reg; output \write_pointer_q_reg[0] ; output \cc_stat[status_pexs] ; output rec_lbpf; output rec_ivld; output [2:0]\alc_alc_id_field_reg[2] ; output [28:0]\rec_ident_reg[28] ; output rec_ident_type; output rec_brs; output rec_esi; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input \txtb_hw_cmd_q[err] ; input \mr_ctrl_out[ctr_pres_prx] ; input \mr_ctrl_out[ctr_pres_ptx] ; input reg_q_reg_2; input \mr_ctrl_out[ctr_pres_enorm] ; input \mr_ctrl_out[ctr_pres_efd] ; input [3:0]S; input [3:0]DI; input [3:0]next_state2_carry__0; input [3:0]\next_state2_inferred__0/i__carry__0 ; input reg_q_reg_3; input [2:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[19] ; input \r_data_reg[16] ; input \r_data_reg[16]_0 ; input \r_data_reg[15] ; input \r_data_reg[15]_0 ; input \r_data_reg[15]_1 ; input \r_data_reg[13] ; input \r_data_reg[13]_0 ; input \r_data_reg[13]_1 ; input \r_data_reg[13]_2 ; input \r_data_reg[13]_3 ; input \r_data_reg[18] ; input \r_data_reg[18]_0 ; input \r_data_reg[18]_1 ; input \r_data_reg[18]_2 ; input \r_data_reg[4] ; input \r_data_reg[4]_0 ; input \r_data_reg[6] ; input \r_data_reg[12] ; input \r_data_reg[12]_0 ; input \r_data_reg[6]_0 ; input \r_data_reg[6]_1 ; input \r_data[6]_i_2 ; input [19:0]timestamp_IBUF; input \r_data_reg[20] ; input \r_data_reg[20]_0 ; input [1:0]\mr_ctrl_out[btr_ph2] ; input \r_data_reg[19]_0 ; input [0:0]\mr_ctrl_out[settings_rtrth] ; input \r_data[19]_i_2 ; input \r_data_reg[22] ; input \r_data_reg[23] ; input \r_data_reg[20]_1 ; input \r_data[0]_i_2 ; input \r_data[1]_i_2__0 ; input \r_data_reg[3]_i_5 ; input \r_data[4]_i_2 ; input \r_data[5]_i_2 ; input \r_data_reg[7]_i_6 ; input \r_data_reg[8]_i_4 ; input \r_data_reg[17] ; input \r_data_reg[17]_0 ; input [0:0]\r_data[7]_i_3__0 ; input \r_data_reg[14] ; input [2:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; input \r_data[19]_i_2_0 ; input \r_data_reg[18]_3 ; input \r_data_reg[18]_4 ; input \r_data[11]_i_2__0 ; input [0:0]\mr_ctrl_out[btr_fd_ph2_fd] ; input \mr_ctrl_out[mode_rom] ; input [1:0]\mr_tx_priority[1] ; input [1:0]\r_data_reg[5]_i_5 ; input \r_data[4]_i_2_0 ; input \mr_ctrl_out[mode_fde] ; input [0:0]\mr_tx_priority[0] ; input [0:0]\r_data[0]_i_5 ; input [5:0]\g_ram_rst_false.ram_memory_reg_i_55 ; input ident_valid_q; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \FSM_onehot_curr_state_reg[1] ; input \mr_ctrl_out[mode_erfm] ; input \mr_ctrl_out[rx_settings_rtsop] ; input \g_ram_rst_false.ram_memory_reg_2 ; input [0:0]curr_state_0; input [1:0]int_status_i_4; input \FSM_sequential_curr_state_reg[2] ; input abort_or_skipped; input \FSM_sequential_curr_state_reg[1]_1 ; input \FSM_sequential_curr_state_reg[1]_2 ; input [0:0]curr_state_1; input abort_applied; input \FSM_sequential_curr_state_reg[2]_0 ; input \FSM_sequential_curr_state[1]_i_2__0 ; input [1:0]txtb_hw_cmd_cs; input [0:0]curr_state_2; input \FSM_sequential_curr_state_reg[2]_1 ; input abort_or_skipped_3; input \FSM_sequential_curr_state_reg[1]_3 ; input [0:0]curr_state_4; input abort_applied_5; input \FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state[1]_i_2__2 ; input [0:0]curr_state_6; input \FSM_sequential_curr_state[0]_i_7 ; input \FSM_sequential_curr_state[2]_i_3__3 ; input \FSM_sequential_curr_state[2]_i_3__3_0 ; input \FSM_sequential_curr_state[0]_i_7_0 ; input [0:0]\shift_regs_reg[0] ; input \shift_regs_reg[24] ; input [20:0]tran_word; input \shift_regs_reg[25] ; input \shift_regs_reg[25]_0 ; input \shift_regs_reg[26] ; input \shift_regs_reg[26]_0 ; input \shift_regs_reg[27] ; input \shift_regs_reg[28] ; input \shift_regs_reg[28]_0 ; input \shift_regs_reg[29] ; input \shift_regs_reg[31] ; input \shift_regs_reg[31]_0 ; input \shift_regs_reg[16] ; input \shift_regs_reg[16]_0 ; input \shift_regs_reg[17] ; input \shift_regs_reg[17]_0 ; input \shift_regs_reg[18] ; input \shift_regs_reg[18]_0 ; input \shift_regs_reg[19] ; input \shift_regs_reg[19]_0 ; input \shift_regs_reg[20] ; input \shift_regs_reg[21] ; input \shift_regs_reg[22] ; input \shift_regs_reg[11] ; input \shift_regs_reg[11]_0 ; input \shift_regs_reg[12] ; input \shift_regs_reg[12]_0 ; input \shift_regs_reg[14] ; input \shift_regs_reg[15] ; input \shift_regs_reg[1] ; input \shift_regs_reg[2] ; input tran_frame_valid; input q_i; input scan_mode_IBUF; input rst_n_out_OBUF; input tx_frame_no_sof_q_reg; input [13:0]\shift_regs_reg[27]_0 ; input \shift_regs_reg[30] ; input \shift_regs_reg[31]_1 ; input \retr_ctr_q_reg[3]_0 ; input [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; input \mr_ctrl_out[settings_rtrle] ; input \mr_ctrl_out[settings_nisofd] ; input bit_err; input can_tx_OBUF; input \shift_regs_reg[28]_1 ; input \shift_regs_reg[28]_2 ; input \tran_frame_test[fcrc] ; input \shift_regs_reg[29]_0 ; input \tran_frame_test[fstc] ; input \shift_regs_reg[30]_0 ; input \mr_ctrl_out[settings_ilbp] ; input is_tseg2; input \same_bits_q_reg[2] ; input is_tseg1; input reg_q_reg_4; input sync_edge; input \mr_ctrl_out[settings_pex] ; input \ctrl_ctr_q_reg[1] ; input [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; input \txtb_hw_cmd_q_reg[arbl] ; input tran_ident_type; input \err_capt_err_type_q[2]_i_8 ; input \shift_regs_reg[13] ; input \shift_regs_reg[13]_0 ; input \shift_regs_reg[14]_0 ; input \shift_regs_reg[15]_0 ; input \shift_regs_reg[16]_1 ; input \shift_regs_reg[20]_0 ; input \shift_regs_reg[21]_0 ; input \shift_regs_reg[22]_0 ; input \shift_regs_reg[23] ; input \mr_ctrl_out[settings_ena] ; input \curr_state[0]_i_3 ; input destuff_enable_reg; input tran_frame_type; input tran_brs; input bit_err_q_i_2; input \mr_ctrl_out[mode_bmm] ; input reg_q_reg_5; input tran_is_rtr; input \txtb_ptr_q_reg[4]_0 ; input \txtb_ptr_q_reg[4]_1 ; input \txtb_ptr_q_reg[4]_2 ; input \ctrl_ctr_q_reg[8] ; input \ctrl_ctr_q_reg[8]_0 ; input \ctrl_ctr_q_reg[6] ; input \ctrl_ctr_q_reg[5] ; input [2:0]\ctrl_ctr_q_reg[5]_0 ; input \mr_ctrl_out[mode_stm] ; input rx_data_wbs; input [7:0]\mr_ctrl_out[ewl_ew_limit] ; input [7:0]\mr_ctrl_out[erp_erp_limit] ; input \segm_counter_q_reg[0] ; input \segm_counter_q_reg[0]_0 ; input \segm_counter_q_reg[0]_1 ; input \exp_seg_length_q_reg[0] ; input \exp_seg_length_q_reg[0]_0 ; input sync_edge3__0; input \segm_counter_q_reg[0]_2 ; input tx_data_prev; input \r_data_reg[20]_2 ; input \r_data_reg[21] ; input \r_data_reg[24] ; input \r_data_reg[2] ; input \r_data_reg[16]_1 ; input \r_data_reg[14]_i_2 ; input \r_data_reg[15]_2 ; input \mr_ctrl_out[settings_tbfbo] ; input sync_flag; input [1:0]int_status_reg_1; input int_status_reg_2; input [2:0]data_in_IBUF; input int_status_reg_3; input mr_int_stat_txbhci_o; input mr_status_pexs_reg; input mr_int_stat_fcsi_o; input sspc_ena_q; input btmc_meas_running_q; input [0:0]\write_pointer_q_reg[0]_0 ; input mr_status_pexs_reg_0; input \bst_ctr_q_reg[0] ; input \dst_ctr_q_reg[1] ; input [3:0]txtb_allow_bb; input int_status_i_2__1; wire [8:0]D; wire [3:0]DI; wire [0:0]E; wire \FSM_onehot_curr_state_reg[1] ; wire \FSM_onehot_curr_state_reg[5] ; wire \FSM_onehot_curr_state_reg[5]_0 ; wire \FSM_sequential_curr_state[0]_i_7 ; wire \FSM_sequential_curr_state[0]_i_7_0 ; wire \FSM_sequential_curr_state[1]_i_2__0 ; wire \FSM_sequential_curr_state[1]_i_2__2 ; wire \FSM_sequential_curr_state[2]_i_3__3 ; wire \FSM_sequential_curr_state[2]_i_3__3_0 ; wire \FSM_sequential_curr_state_reg[0] ; wire [1:0]\FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire [7:0]Q; wire [3:0]S; wire abort_applied; wire abort_applied_5; wire abort_or_skipped; wire abort_or_skipped_3; wire [5:0]adress_IBUF; wire [2:0]\alc_alc_bit_reg[4] ; wire [2:0]\alc_alc_id_field_reg[2] ; wire arbitration_lost; wire bds_data_in; wire bit_err; wire bit_err_enable; wire bit_err_q_i_2; wire br_shifted; wire \bst_ctr_q_reg[0] ; wire btmc_meas_running_q; wire btmc_meas_running_q_reg; wire can_tx_OBUF; wire [2:0]\cc_stat[bst_ctr] ; wire [2:0]\cc_stat[dst_ctr] ; wire \cc_stat[err_erp] ; wire \cc_stat[is_bus_off] ; wire \cc_stat[is_err_active] ; wire \cc_stat[is_err_passive] ; wire \cc_stat[is_receiver] ; wire \cc_stat[is_transmitter] ; wire [13:13]\cc_stat[norm_err_ctr] ; wire \cc_stat[status_pexs] ; wire clk_sys_IBUF_BUFG; wire \compl_ctr_q_reg[7] ; wire [14:2]crc_15; wire [14:0]crc_17; wire [17:15]crc_21; wire [14:3]crc_d; wire crc_data_rx_wbs; wire crc_data_tx_wbs; wire \crc_q_reg[0] ; wire \crc_q_reg[10] ; wire [1:0]\crc_q_reg[1] ; wire \crc_q_reg[1]_0 ; wire \crc_q_reg[2] ; wire \crc_q_reg[7] ; wire \crc_q_reg[8] ; wire \crc_q_reg[9] ; wire \ctrl_ctr_q_reg[1] ; wire \ctrl_ctr_q_reg[5] ; wire [2:0]\ctrl_ctr_q_reg[5]_0 ; wire \ctrl_ctr_q_reg[6] ; wire \ctrl_ctr_q_reg[8] ; wire \ctrl_ctr_q_reg[8]_0 ; wire [1:0]curr_state; wire \curr_state[0]_i_3 ; wire [0:0]curr_state_0; wire [0:0]curr_state_1; wire [0:0]curr_state_2; wire [0:0]curr_state_4; wire [0:0]curr_state_6; wire \curr_state_reg[0] ; wire \curr_state_reg[0]_0 ; wire \curr_state_reg[0]_1 ; wire \curr_state_reg[1] ; wire \curr_state_reg[1]_0 ; wire \curr_state_reg[2] ; wire \curr_state_reg[2]_0 ; wire \curr_state_reg[2]_1 ; wire \curr_state_reg[2]_2 ; wire [0:0]\curr_state_reg[3] ; wire [2:0]\curr_state_reg[3]_0 ; wire \curr_state_reg[3]_1 ; wire [0:0]\curr_state_reg[5] ; wire \curr_state_reg[5]_0 ; wire [0:0]\curr_state_reg[5]_1 ; wire [6:0]\data_err_ctr_q_reg[15] ; wire \data_err_ctr_q_reg[4] ; wire \data_err_ctr_q_reg[5] ; wire \data_err_ctr_q_reg[8] ; wire data_halt_d1_out; wire [2:0]data_in_IBUF; wire destuff_enable; wire destuff_enable_reg; wire destuffed; wire \dst_ctr_q_reg[1] ; wire enable_prev; wire err_capt_err_erp_reg; wire \err_capt_err_pos_q_reg[0] ; wire [3:0]\err_capt_err_pos_q_reg[3] ; wire \err_capt_err_type_q[2]_i_8 ; wire \err_capt_err_type_q_reg[0] ; wire [2:0]\err_capt_err_type_q_reg[2] ; wire err_detected; wire err_frm_req; wire [0:0]err_frm_req_reg; wire [0:0]err_frm_req_reg_0; wire err_frm_req_reg_1; wire err_frm_req_reg_2; wire err_warning_limit_q; wire \exp_seg_length_q_reg[0] ; wire \exp_seg_length_q_reg[0]_0 ; wire first_ssp_q0; wire fixed_prev_q; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1] ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][1] ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire [5:0]\g_ram_rst_false.ram_memory_reg_i_55 ; wire i_mac_bit_destuffing_n_10; wire i_mac_bit_destuffing_n_11; wire i_mac_bit_destuffing_n_12; wire i_mac_bit_destuffing_n_13; wire i_mac_bit_destuffing_n_17; wire i_mac_bit_destuffing_n_18; wire i_mac_bit_destuffing_n_19; wire i_mac_bit_destuffing_n_20; wire i_mac_bit_destuffing_n_3; wire i_mac_bit_destuffing_n_4; wire i_mac_bit_destuffing_n_6; wire i_mac_bit_destuffing_n_8; wire i_mac_bit_destuffing_n_9; wire i_mac_bit_stuffing_n_2; wire i_mac_bit_stuffing_n_5; wire i_mac_bit_stuffing_n_8; wire \i_mac_crc_calc_15/crc_ce ; wire \i_mac_crc_calc_17_rx/crc_ce ; wire i_mac_crc_top_n_11; wire i_mac_crc_top_n_21; wire i_mac_crc_top_n_22; wire i_mac_crc_top_n_23; wire i_mac_crc_top_n_24; wire i_mac_crc_top_n_25; wire i_mac_crc_top_n_26; wire i_mac_crc_top_n_27; wire i_mac_crc_top_n_28; wire i_mac_crc_top_n_29; wire i_mac_crc_top_n_30; wire i_mac_crc_top_n_31; wire i_mac_crc_top_n_32; wire i_mac_crc_top_n_40; wire i_mac_crc_top_n_41; wire i_mac_crc_top_n_42; wire i_mac_crc_top_n_43; wire i_mac_crc_top_n_44; wire i_mac_crc_top_n_45; wire i_mac_crc_top_n_46; wire i_mac_crc_top_n_47; wire i_mac_crc_top_n_48; wire i_mac_crc_top_n_49; wire i_mac_crc_top_n_50; wire i_mac_crc_top_n_51; wire i_mac_crc_top_n_52; wire i_mac_crc_top_n_53; wire \i_mac_fc_err_counters/data_err_ctr_ce ; wire \i_mac_fc_err_counters/mr_ctr_pres_efd_q ; wire \i_mac_fc_err_counters/mr_ctr_pres_enorm_q ; wire \i_mac_fc_err_counters/mr_ctr_pres_ptx_q ; wire \i_mac_fc_err_counters/nom_err_ctr_ce ; wire [0:0]\i_mac_fc_err_counters/tx_err_ctr_q ; wire i_mac_fc_top_n_28; wire i_mac_fc_top_n_31; wire i_mac_fc_top_n_42; wire i_mac_fc_top_n_43; wire i_mac_fc_top_n_44; wire i_mac_fc_top_n_45; wire i_mac_fc_top_n_53; wire i_mac_fc_top_n_55; wire i_mac_fc_top_n_56; wire i_mac_fc_top_n_57; wire i_mac_fc_top_n_65; wire i_mac_fc_top_n_66; wire i_mac_fc_top_n_67; wire i_mac_fc_top_n_68; wire i_mac_fc_top_n_69; wire i_mac_fc_top_n_70; wire i_mac_fc_top_n_71; wire i_mac_fc_top_n_72; wire i_mac_fc_top_n_73; wire i_mac_operation_control_n_0; wire i_mac_operation_control_n_10; wire i_mac_operation_control_n_12; wire i_mac_operation_control_n_13; wire i_mac_operation_control_n_14; wire i_mac_operation_control_n_15; wire i_mac_operation_control_n_16; wire i_mac_operation_control_n_17; wire i_mac_operation_control_n_18; wire i_mac_operation_control_n_20; wire i_mac_operation_control_n_21; wire i_mac_operation_control_n_22; wire i_mac_operation_control_n_23; wire i_mac_operation_control_n_24; wire i_mac_operation_control_n_4; wire i_mac_operation_control_n_5; wire i_mac_operation_control_n_6; wire i_mac_operation_control_n_7; wire i_mac_operation_control_n_9; wire \i_mac_pc_fsm/p_131_in ; wire \i_mac_pc_fsm/rx_data_nbs_prev ; wire i_mac_pc_top_n_101; wire i_mac_pc_top_n_103; wire i_mac_pc_top_n_109; wire i_mac_pc_top_n_133; wire i_mac_pc_top_n_134; wire i_mac_pc_top_n_135; wire i_mac_pc_top_n_165; wire i_mac_pc_top_n_176; wire i_mac_pc_top_n_177; wire i_mac_pc_top_n_179; wire i_mac_pc_top_n_184; wire i_mac_pc_top_n_185; wire i_mac_pc_top_n_186; wire i_mac_pc_top_n_19; wire i_mac_pc_top_n_193; wire i_mac_pc_top_n_20; wire i_mac_pc_top_n_22; wire i_mac_pc_top_n_24; wire i_mac_pc_top_n_25; wire i_mac_pc_top_n_74; wire i_mac_pc_top_n_80; wire i_mac_pc_top_n_83; wire i_mac_pc_top_n_84; wire i_mac_pc_top_n_85; wire i_mac_pc_top_n_86; wire i_mac_pc_top_n_94; wire i_mac_pc_top_n_96; wire i_mac_pc_top_n_98; wire ident_valid_q; wire int_status_i_2__1; wire [1:0]int_status_i_4; wire int_status_reg; wire int_status_reg_0; wire [1:0]int_status_reg_1; wire int_status_reg_2; wire int_status_reg_3; wire is_tseg1; wire is_tseg2; wire [0:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [1:0]\mr_ctrl_out[btr_ph2] ; wire [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire [7:0]\mr_ctrl_out[erp_erp_limit] ; wire [7:0]\mr_ctrl_out[ewl_ew_limit] ; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_ctrl_out[settings_rtrle] ; wire [0:0]\mr_ctrl_out[settings_rtrth] ; wire \mr_ctrl_out[settings_tbfbo] ; wire [2:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; wire mr_int_stat_fcsi_o; wire mr_int_stat_txbhci_o; wire mr_status_pexs_reg; wire mr_status_pexs_reg_0; wire [0:0]\mr_tx_priority[0] ; wire [1:0]\mr_tx_priority[1] ; wire [3:0]next_state2_carry__0; wire [3:0]\next_state2_inferred__0/i__carry__0 ; wire \nom_err_ctr_q_reg[0] ; wire \nom_err_ctr_q_reg[11] ; wire [2:0]\nom_err_ctr_q_reg[12] ; wire \nom_err_ctr_q_reg[2] ; wire p_0_out; wire \pc_dbg[is_arbitration] ; wire pc_rx_data_nbs; wire prev_val_d; wire q_i; wire \r_data[0]_i_2 ; wire [0:0]\r_data[0]_i_5 ; wire \r_data[11]_i_2__0 ; wire \r_data[19]_i_2 ; wire \r_data[19]_i_2_0 ; wire \r_data[1]_i_2__0 ; wire \r_data[4]_i_2 ; wire \r_data[4]_i_2_0 ; wire \r_data[5]_i_2 ; wire \r_data[6]_i_2 ; wire [0:0]\r_data[7]_i_3__0 ; wire \r_data_reg[12] ; wire \r_data_reg[12]_0 ; wire \r_data_reg[13] ; wire \r_data_reg[13]_0 ; wire \r_data_reg[13]_1 ; wire \r_data_reg[13]_2 ; wire \r_data_reg[13]_3 ; wire \r_data_reg[14] ; wire \r_data_reg[14]_i_2 ; wire \r_data_reg[15] ; wire \r_data_reg[15]_0 ; wire \r_data_reg[15]_1 ; wire \r_data_reg[15]_2 ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[16]_1 ; wire \r_data_reg[17] ; wire \r_data_reg[17]_0 ; wire \r_data_reg[18] ; wire \r_data_reg[18]_0 ; wire \r_data_reg[18]_1 ; wire \r_data_reg[18]_2 ; wire \r_data_reg[18]_3 ; wire \r_data_reg[18]_4 ; wire \r_data_reg[19] ; wire \r_data_reg[19]_0 ; wire \r_data_reg[20] ; wire \r_data_reg[20]_0 ; wire \r_data_reg[20]_1 ; wire \r_data_reg[20]_2 ; wire \r_data_reg[21] ; wire \r_data_reg[22] ; wire \r_data_reg[23] ; wire \r_data_reg[24] ; wire \r_data_reg[2] ; wire \r_data_reg[3]_i_5 ; wire \r_data_reg[4] ; wire \r_data_reg[4]_0 ; wire [1:0]\r_data_reg[5]_i_5 ; wire \r_data_reg[6] ; wire \r_data_reg[6]_0 ; wire \r_data_reg[6]_1 ; wire \r_data_reg[7]_i_6 ; wire \r_data_reg[8]_i_4 ; wire rec_abort; wire rec_abort_f; wire rec_abort_reg; wire rec_brs; wire \rec_dlc_reg[1] ; wire \rec_dlc_reg[1]_0 ; wire \rec_dlc_reg[2] ; wire \rec_dlc_reg[2]_0 ; wire [3:0]\rec_dlc_reg[3] ; wire \rec_dlc_reg[3]_0 ; wire rec_esi; wire rec_frame_type; wire [28:0]\rec_ident_reg[28] ; wire rec_ident_type; wire rec_is_rtr; wire rec_is_rtr_i; wire rec_ivld; wire rec_lbpf; wire rec_valid; wire [2:0]rec_valid_reg; wire reg_q; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire [3:0]\retr_ctr_q_reg[3] ; wire \retr_ctr_q_reg[3]_0 ; wire rst_n_out_OBUF; wire rx_data_wbs; wire \rx_err_ctr_q_reg[1] ; wire \rx_err_ctr_q_reg[3] ; wire \rx_err_ctr_q_reg[5] ; wire \rx_err_ctr_q_reg[7] ; wire \rx_err_ctr_q_reg[8] ; wire \rx_err_ctr_q_reg[8]_0 ; wire rx_store_dlc; wire \same_bits_q_reg[2] ; wire [2:0]sbe_IBUF; wire scan_mode_IBUF; wire \segm_counter_q_reg[0] ; wire \segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire \segm_counter_q_reg[0]_2 ; wire [0:0]\shift_regs_reg[0] ; wire \shift_regs_reg[11] ; wire \shift_regs_reg[11]_0 ; wire \shift_regs_reg[12] ; wire \shift_regs_reg[12]_0 ; wire \shift_regs_reg[13] ; wire \shift_regs_reg[13]_0 ; wire \shift_regs_reg[14] ; wire \shift_regs_reg[14]_0 ; wire \shift_regs_reg[15] ; wire \shift_regs_reg[15]_0 ; wire \shift_regs_reg[16] ; wire \shift_regs_reg[16]_0 ; wire \shift_regs_reg[16]_1 ; wire \shift_regs_reg[17] ; wire \shift_regs_reg[17]_0 ; wire \shift_regs_reg[18] ; wire \shift_regs_reg[18]_0 ; wire \shift_regs_reg[19] ; wire \shift_regs_reg[19]_0 ; wire \shift_regs_reg[1] ; wire \shift_regs_reg[20] ; wire \shift_regs_reg[20]_0 ; wire \shift_regs_reg[21] ; wire \shift_regs_reg[21]_0 ; wire \shift_regs_reg[22] ; wire \shift_regs_reg[22]_0 ; wire \shift_regs_reg[23] ; wire \shift_regs_reg[24] ; wire \shift_regs_reg[25] ; wire \shift_regs_reg[25]_0 ; wire \shift_regs_reg[26] ; wire \shift_regs_reg[26]_0 ; wire \shift_regs_reg[27] ; wire [13:0]\shift_regs_reg[27]_0 ; wire \shift_regs_reg[28] ; wire \shift_regs_reg[28]_0 ; wire \shift_regs_reg[28]_1 ; wire \shift_regs_reg[28]_2 ; wire \shift_regs_reg[29] ; wire \shift_regs_reg[29]_0 ; wire \shift_regs_reg[2] ; wire \shift_regs_reg[30] ; wire \shift_regs_reg[30]_0 ; wire \shift_regs_reg[31] ; wire \shift_regs_reg[31]_0 ; wire \shift_regs_reg[31]_1 ; wire \sp_control_q_i_reg[0] ; wire \sp_control_q_i_reg[0]_0 ; wire \sp_control_q_i_reg[1] ; wire sspc_ena_q; wire sspc_ena_q_reg; wire [31:0]store_data_word; wire store_metadata; wire stuff_enable; wire stuff_err; wire stuff_err_d; wire \sync_control_q_reg[0] ; wire \sync_control_q_reg[0]_0 ; wire [1:0]\sync_control_q_reg[1] ; wire sync_edge; wire sync_edge3__0; wire sync_flag; wire \timestamp[41] ; wire \timestamp[42] ; wire \timestamp[43] ; wire \timestamp[7] ; wire \timestamp[8] ; wire [19:0]timestamp_IBUF; wire \tq_counter_q_reg[7] ; wire tran_brs; wire tran_delay_meas; wire \tran_frame_test[fcrc] ; wire \tran_frame_test[fstc] ; wire tran_frame_type; wire tran_frame_valid; wire tran_ident_type; wire tran_is_rtr; wire [20:0]tran_word; wire tx_data_prev; wire \tx_err_ctr_q_reg[6] ; wire [7:0]\tx_err_ctr_q_reg[7] ; wire \tx_err_ctr_q_reg[7]_0 ; wire tx_frame_no_sof; wire tx_frame_no_sof_q_reg; wire tx_trigger_q; wire tx_trigger_ssp; wire [3:0]txtb_allow_bb; wire \txtb_hw_cmd[failed] ; wire \txtb_hw_cmd[lock] ; wire \txtb_hw_cmd[valid] ; wire [1:0]txtb_hw_cmd_cs; wire \txtb_hw_cmd_q[err] ; wire \txtb_hw_cmd_q_reg[arbl] ; wire \txtb_hw_cmd_q_reg[err] ; wire \txtb_hw_cmd_q_reg[failed] ; wire \txtb_hw_cmd_q_reg[failed]_0 ; wire \txtb_hw_cmd_q_reg[failed]_1 ; wire \txtb_hw_cmd_q_reg[failed]_2 ; wire \txtb_hw_cmd_q_reg[failed]_3 ; wire \txtb_hw_cmd_q_reg[failed]_4 ; wire \txtb_hw_cmd_q_reg[failed]_5 ; wire \txtb_hw_cmd_q_reg[lock] ; wire \txtb_hw_cmd_q_reg[lock]_0 ; wire \txtb_hw_cmd_q_reg[lock]_1 ; wire \txtb_hw_cmd_q_reg[valid] ; wire \txtb_hw_cmd_q_reg[valid]_0 ; wire [4:0]\txtb_ptr_q_reg[4] ; wire \txtb_ptr_q_reg[4]_0 ; wire \txtb_ptr_q_reg[4]_1 ; wire \txtb_ptr_q_reg[4]_2 ; wire \write_pointer_q_reg[0] ; wire [0:0]\write_pointer_q_reg[0]_0 ; mac_bit_destuffing i_mac_bit_destuffing (.D(pc_rx_data_nbs), .Q({i_mac_pc_top_n_22,\curr_state_reg[3] ,i_mac_pc_top_n_25}), .bds_data_in(bds_data_in), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\crc_q[16]_i_3 (i_mac_pc_top_n_96), .destuff_enable(destuff_enable), .\dst_ctr_q_reg[0]_0 (\cc_stat[dst_ctr] [0]), .\dst_ctr_q_reg[1]_0 (\cc_stat[dst_ctr] [1]), .\dst_ctr_q_reg[1]_1 (\dst_ctr_q_reg[1] ), .\dst_ctr_q_reg[2]_0 (\cc_stat[dst_ctr] [2]), .\err_capt_err_type_q[2]_i_3 (i_mac_pc_top_n_74), .fixed_prev_q(fixed_prev_q), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .prev_val_d(prev_val_d), .q_i(q_i), .rec_brs(rec_brs), .rec_brs_reg(\curr_state_reg[3]_1 ), .reg_q(reg_q), .reg_q_reg(destuffed), .reg_q_reg_0(i_mac_bit_destuffing_n_3), .reg_q_reg_1(i_mac_bit_destuffing_n_4), .reg_q_reg_10(i_mac_bit_destuffing_n_20), .reg_q_reg_11(reg_q_reg_1), .reg_q_reg_12(tx_frame_no_sof_q_reg), .reg_q_reg_13(i_mac_pc_top_n_176), .reg_q_reg_14(reg_q_reg_4), .reg_q_reg_15(\curr_state_reg[1]_0 ), .reg_q_reg_2(i_mac_bit_destuffing_n_9), .reg_q_reg_3(i_mac_bit_destuffing_n_10), .reg_q_reg_4(i_mac_bit_destuffing_n_11), .reg_q_reg_5(i_mac_bit_destuffing_n_12), .reg_q_reg_6(i_mac_bit_destuffing_n_13), .reg_q_reg_7(i_mac_bit_destuffing_n_17), .reg_q_reg_8(i_mac_bit_destuffing_n_18), .reg_q_reg_9(i_mac_bit_destuffing_n_19), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_nbs_prev(\i_mac_pc_fsm/rx_data_nbs_prev ), .rx_trig_req_q_reg(i_mac_bit_destuffing_n_6), .\same_bits_q_reg[0]_0 (i_mac_pc_top_n_103), .\same_bits_q_reg[2]_0 (i_mac_bit_destuffing_n_8), .\same_bits_q_reg[2]_1 (i_mac_pc_top_n_101), .scan_mode_IBUF(scan_mode_IBUF), .stuff_err(stuff_err), .stuff_err_d(stuff_err_d), .sync_edge(sync_edge), .tran_frame_valid(tran_frame_valid)); mac_bit_stuffing i_mac_bit_stuffing (.\bst_ctr_q_reg[0]_0 (\cc_stat[bst_ctr] [0]), .\bst_ctr_q_reg[0]_1 (\bst_ctr_q_reg[0] ), .\bst_ctr_q_reg[1]_0 (\cc_stat[bst_ctr] [1]), .\bst_ctr_q_reg[1]_1 (i_mac_bit_stuffing_n_5), .\cc_stat[bst_ctr] (\cc_stat[bst_ctr] [2]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_halt_d1_out(data_halt_d1_out), .enable_prev(enable_prev), .reg_q_reg(crc_data_tx_wbs), .reg_q_reg_0(reg_q_reg_1), .reg_q_reg_1(i_mac_pc_top_n_135), .reg_q_reg_2(\curr_state_reg[1]_0 ), .reg_q_reg_3(reg_q_reg_3), .\same_bits_q_reg[1]_0 (i_mac_pc_top_n_134), .\same_bits_q_reg[2]_0 (i_mac_pc_top_n_98), .\shift_regs_reg[29] (\curr_state_reg[0] ), .\shift_regs_reg[29]_0 (\shift_regs_reg[29]_0 ), .\shift_regs_reg[30] (\curr_state_reg[2]_0 ), .\shift_regs_reg[30]_0 (\shift_regs_reg[30]_0 ), .stuff_enable(stuff_enable), .stuff_enable_reg(i_mac_bit_stuffing_n_8), .\tran_frame_test[fstc] (\tran_frame_test[fstc] ), .\tran_frame_test_reg[fstc] (i_mac_bit_stuffing_n_2), .tx_frame_no_sof(tx_frame_no_sof)); mac_crc_top i_mac_crc_top (.D({crc_d[14],crc_d[10],crc_d[8:7],crc_d[4:3],i_mac_pc_top_n_193}), .E(\i_mac_crc_calc_15/crc_ce ), .Q({crc_17[14:12],crc_17[2:0]}), .S({i_mac_crc_top_n_40,i_mac_crc_top_n_41,i_mac_crc_top_n_42}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_rx_wbs(crc_data_rx_wbs), .\crc_match_c6_inferred__0/i__carry ({store_data_word[9:0],store_data_word[16:10]}), .\crc_q_reg[0] (\crc_q_reg[0] ), .\crc_q_reg[0]_0 (i_mac_pc_top_n_179), .\crc_q_reg[10] (\crc_q_reg[10] ), .\crc_q_reg[11] (i_mac_crc_top_n_31), .\crc_q_reg[11]_0 ({i_mac_crc_top_n_44,i_mac_crc_top_n_45,i_mac_crc_top_n_46,i_mac_crc_top_n_47}), .\crc_q_reg[11]_1 ({i_mac_crc_top_n_50,i_mac_crc_top_n_51,i_mac_crc_top_n_52}), .\crc_q_reg[14] ({crc_15[14:13],crc_15[9],crc_15[7:2]}), .\crc_q_reg[14]_0 (i_mac_crc_top_n_30), .\crc_q_reg[14]_1 (i_mac_crc_top_n_32), .\crc_q_reg[14]_2 (i_mac_crc_top_n_53), .\crc_q_reg[16] (i_mac_crc_top_n_43), .\crc_q_reg[17] ({crc_21,\crc_q_reg[1] }), .\crc_q_reg[1] (\crc_q_reg[1]_0 ), .\crc_q_reg[1]_0 (i_mac_pc_top_n_94), .\crc_q_reg[20] (i_mac_crc_top_n_11), .\crc_q_reg[20]_0 ({i_mac_crc_top_n_48,i_mac_crc_top_n_49}), .\crc_q_reg[20]_1 (reg_q_reg_1), .\crc_q_reg[20]_2 (\i_mac_crc_calc_17_rx/crc_ce ), .\crc_q_reg[2] (i_mac_crc_top_n_21), .\crc_q_reg[2]_0 (\crc_q_reg[2] ), .\crc_q_reg[3] (i_mac_crc_top_n_22), .\crc_q_reg[3]_0 (i_mac_crc_top_n_25), .\crc_q_reg[3]_1 (i_mac_pc_top_n_177), .\crc_q_reg[3]_2 (i_mac_pc_top_n_96), .\crc_q_reg[3]_3 (crc_data_tx_wbs), .\crc_q_reg[4] (i_mac_crc_top_n_23), .\crc_q_reg[4]_0 (i_mac_crc_top_n_26), .\crc_q_reg[5] (i_mac_crc_top_n_24), .\crc_q_reg[5]_0 (i_mac_crc_top_n_27), .\crc_q_reg[6] (i_mac_crc_top_n_28), .\crc_q_reg[7] (\crc_q_reg[7] ), .\crc_q_reg[8] (\crc_q_reg[8] ), .\crc_q_reg[9] (\crc_q_reg[9] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\shift_regs[30]_i_2 (\g_bit[0].reg_value_r_reg[0]_0 ), .\shift_regs_reg[13] (\shift_regs_reg[13] ), .\shift_regs_reg[13]_0 (\shift_regs_reg[13]_0 ), .\shift_regs_reg[13]_1 (\curr_state_reg[0]_0 ), .\shift_regs_reg[14] (\shift_regs_reg[14]_0 ), .\shift_regs_reg[15] (\shift_regs_reg[15]_0 ), .\shift_regs_reg[16] (i_mac_operation_control_n_12), .\shift_regs_reg[16]_0 (\shift_regs_reg[16]_1 ), .\shift_regs_reg[20] (\shift_regs_reg[20]_0 ), .\shift_regs_reg[20]_0 (\shift_regs_reg[28]_2 ), .\shift_regs_reg[21] (\shift_regs_reg[21]_0 ), .\shift_regs_reg[22] (\shift_regs_reg[22]_0 ), .\shift_regs_reg[23] (\shift_regs_reg[23] ), .\shift_regs_reg[30] (\shift_regs_reg[30]_0 ), .\shift_regs_reg[31] (\shift_regs_reg[28]_1 ), .store_data_word(store_data_word[20:18]), .\tran_frame_test[fcrc] (\tran_frame_test[fcrc] ), .\tran_frame_test_reg[fcrc] (i_mac_crc_top_n_29)); mac_fc_top i_mac_fc_top (.D({D[6],D[3],D[1:0]}), .DI(DI), .E(err_detected), .\FSM_sequential_curr_state[1]_i_11 (curr_state[0]), .\FSM_sequential_curr_state_reg[0] (i_mac_fc_top_n_43), .\FSM_sequential_curr_state_reg[0]_0 (i_mac_fc_top_n_44), .\FSM_sequential_curr_state_reg[0]_1 (i_mac_fc_top_n_45), .\FSM_sequential_curr_state_reg[0]_2 (i_mac_fc_top_n_57), .\FSM_sequential_curr_state_reg[0]_3 (\cc_stat[is_err_active] ), .\FSM_sequential_curr_state_reg[0]_4 (i_mac_fc_top_n_73), .\FSM_sequential_curr_state_reg[0]_5 (tx_frame_no_sof_q_reg), .\FSM_sequential_curr_state_reg[0]_6 (destuffed), .\FSM_sequential_curr_state_reg[0]_7 (err_frm_req_reg_1), .\FSM_sequential_curr_state_reg[1] (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_0 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_1 (i_mac_fc_top_n_55), .\FSM_sequential_curr_state_reg[1]_2 (i_mac_fc_top_n_68), .Q(Q), .S(i_mac_pc_top_n_85), .adress_IBUF(adress_IBUF), .\cc_stat[is_bus_off] (\cc_stat[is_bus_off] ), .\cc_stat[is_err_passive] (\cc_stat[is_err_passive] ), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\ctrl_ctr_q[8]_i_21 ({i_mac_pc_top_n_24,i_mac_pc_top_n_25}), .\curr_state[0]_i_7 (i_mac_pc_top_n_74), .\curr_state[5]_i_18 (i_mac_bit_destuffing_n_4), .\curr_state_reg[0] (i_mac_fc_top_n_71), .\data_err_ctr_q_reg[0] (i_mac_fc_top_n_65), .\data_err_ctr_q_reg[0]_0 (\i_mac_fc_err_counters/data_err_ctr_ce ), .\data_err_ctr_q_reg[15] (\data_err_ctr_q_reg[15] ), .\data_err_ctr_q_reg[2] (i_mac_fc_top_n_28), .\data_err_ctr_q_reg[4] (\data_err_ctr_q_reg[4] ), .\data_err_ctr_q_reg[5] (\data_err_ctr_q_reg[5] ), .\data_err_ctr_q_reg[8] (\data_err_ctr_q_reg[8] ), .data_in_IBUF(data_in_IBUF[0]), .destuff_enable_i_4(curr_state[1]), .err_warning_limit_q(err_warning_limit_q), .err_warning_limit_q1_carry__0(S), .err_warning_limit_q_reg(reg_q_reg_1), .int_status_reg(int_status_reg_0), .int_status_reg_0(int_status_reg_1[0]), .int_status_reg_1(int_status_reg_2), .int_status_reg_2(mr_status_pexs_reg), .mr_ctr_pres_efd_q(\i_mac_fc_err_counters/mr_ctr_pres_efd_q ), .mr_ctr_pres_enorm_q(\i_mac_fc_err_counters/mr_ctr_pres_enorm_q ), .mr_ctr_pres_ptx_q(\i_mac_fc_err_counters/mr_ctr_pres_ptx_q ), .\mr_ctrl_out[btr_fd_ph2_fd] (\mr_ctrl_out[btr_fd_ph2_fd] ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] ), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] ), .\mr_ctrl_out[ctr_pres_efd] (\mr_ctrl_out[ctr_pres_efd] ), .\mr_ctrl_out[ctr_pres_enorm] (\mr_ctrl_out[ctr_pres_enorm] ), .\mr_ctrl_out[ctr_pres_prx] (\mr_ctrl_out[ctr_pres_prx] ), .\mr_ctrl_out[ctr_pres_ptx] (\mr_ctrl_out[ctr_pres_ptx] ), .\mr_ctrl_out[erp_erp_limit] (\mr_ctrl_out[erp_erp_limit] ), .\mr_ctrl_out[ewl_ew_limit] (\mr_ctrl_out[ewl_ew_limit] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_tbfbo] (\mr_ctrl_out[settings_tbfbo] ), .mr_int_stat_fcsi_o(mr_int_stat_fcsi_o), .next_state2_carry__0(next_state2_carry__0), .\next_state2_inferred__0/i__carry__0 (\next_state2_inferred__0/i__carry__0 ), .\nom_err_ctr_q_reg[0] (\nom_err_ctr_q_reg[0] ), .\nom_err_ctr_q_reg[0]_0 (\sp_control_q_i_reg[1] ), .\nom_err_ctr_q_reg[0]_1 (\i_mac_fc_err_counters/nom_err_ctr_ce ), .\nom_err_ctr_q_reg[11] (\nom_err_ctr_q_reg[11] ), .\nom_err_ctr_q_reg[13] ({\cc_stat[norm_err_ctr] ,\nom_err_ctr_q_reg[12] }), .\nom_err_ctr_q_reg[15] (i_mac_fc_top_n_66), .\nom_err_ctr_q_reg[2] (\nom_err_ctr_q_reg[2] ), .\r_data[0]_i_2 (\r_data[0]_i_2 ), .\r_data[11]_i_2__0 (\r_data[11]_i_2__0 ), .\r_data[19]_i_2 (\r_data[19]_i_2 ), .\r_data[1]_i_2__0 (\r_data[1]_i_2__0 ), .\r_data[4]_i_2 (\r_data[4]_i_2 ), .\r_data[5]_i_2 (\r_data[5]_i_2 ), .\r_data[6]_i_2 (\r_data[6]_i_2 ), .\r_data_reg[14] (i_mac_pc_top_n_19), .\r_data_reg[14]_0 (\r_data_reg[14] ), .\r_data_reg[14]_i_2 (\r_data_reg[14]_i_2 ), .\r_data_reg[15] (\r_data_reg[15]_2 ), .\r_data_reg[16] (\r_data_reg[13]_1 ), .\r_data_reg[16]_0 (\r_data_reg[16]_1 ), .\r_data_reg[17] (i_mac_pc_top_n_20), .\r_data_reg[17]_0 (\r_data_reg[17] ), .\r_data_reg[17]_1 (\r_data_reg[17]_0 ), .\r_data_reg[20] (\r_data_reg[20] ), .\r_data_reg[20]_0 (\r_data_reg[20]_0 ), .\r_data_reg[20]_1 (\r_data_reg[20]_1 ), .\r_data_reg[20]_2 (\r_data_reg[20]_2 ), .\r_data_reg[21] (\r_data_reg[21] ), .\r_data_reg[22] (\r_data_reg[22] ), .\r_data_reg[23] (\r_data_reg[23] ), .\r_data_reg[24] (\r_data_reg[24] ), .\r_data_reg[2] (\r_data_reg[2] ), .\r_data_reg[3]_i_5 (\r_data_reg[3]_i_5 ), .\r_data_reg[4] (\r_data_reg[4] ), .\r_data_reg[4]_0 (\r_data_reg[4]_0 ), .\r_data_reg[4]_1 (i_mac_operation_control_n_0), .\r_data_reg[6] (\r_data_reg[6] ), .\r_data_reg[6]_0 (\r_data_reg[6]_0 ), .\r_data_reg[6]_1 (\r_data_reg[6]_1 ), .\r_data_reg[7]_i_6 (\r_data_reg[7]_i_6 ), .\r_data_reg[8]_i_4 (\r_data_reg[8]_i_4 ), .reg_q_reg(i_mac_fc_top_n_42), .reg_q_reg_0(i_mac_fc_top_n_56), .reg_q_reg_1(i_mac_fc_top_n_67), .reg_q_reg_2(i_mac_fc_top_n_69), .reg_q_reg_3(i_mac_fc_top_n_70), .reg_q_reg_4(i_mac_fc_top_n_72), .reg_q_reg_5(reg_q_reg_2), .rst_n_out_OBUF(rst_n_out_OBUF), .\rx_err_ctr_q[2]_i_2 (i_mac_pc_top_n_83), .\rx_err_ctr_q_reg[0] (i_mac_pc_top_n_80), .\rx_err_ctr_q_reg[0]_0 (i_mac_pc_top_n_133), .\rx_err_ctr_q_reg[1] (\rx_err_ctr_q_reg[1] ), .\rx_err_ctr_q_reg[1]_0 (i_mac_pc_top_n_84), .\rx_err_ctr_q_reg[3] (\rx_err_ctr_q_reg[3] ), .\rx_err_ctr_q_reg[3]_0 (i_mac_operation_control_n_9), .\rx_err_ctr_q_reg[4] (i_mac_pc_top_n_86), .\rx_err_ctr_q_reg[5] (\rx_err_ctr_q_reg[5] ), .\rx_err_ctr_q_reg[7] (\rx_err_ctr_q_reg[7] ), .\rx_err_ctr_q_reg[8] (\rx_err_ctr_q_reg[8] ), .\rx_err_ctr_q_reg[8]_0 (\rx_err_ctr_q_reg[8]_0 ), .sbe_IBUF(sbe_IBUF), .scan_mode_IBUF(scan_mode_IBUF), .tran_frame_valid(tran_frame_valid), .tx_err_ctr_q(\i_mac_fc_err_counters/tx_err_ctr_q ), .\tx_err_ctr_q_reg[0] (\tx_err_ctr_q_reg[7] [0]), .\tx_err_ctr_q_reg[1] (\tx_err_ctr_q_reg[7] [1]), .\tx_err_ctr_q_reg[2] (\tx_err_ctr_q_reg[7] [2]), .\tx_err_ctr_q_reg[3] (\tx_err_ctr_q_reg[7] [3]), .\tx_err_ctr_q_reg[3]_0 (i_mac_fc_top_n_31), .\tx_err_ctr_q_reg[4] (\tx_err_ctr_q_reg[7] [4]), .\tx_err_ctr_q_reg[5] (\tx_err_ctr_q_reg[7] [5]), .\tx_err_ctr_q_reg[6] (\tx_err_ctr_q_reg[7] [6]), .\tx_err_ctr_q_reg[6]_0 (\tx_err_ctr_q_reg[6] ), .\tx_err_ctr_q_reg[7] (\tx_err_ctr_q_reg[7] [7]), .\tx_err_ctr_q_reg[7]_0 (\tx_err_ctr_q_reg[7]_0 ), .\tx_err_ctr_q_reg[8] (i_mac_fc_top_n_53), .tx_frame_no_sof_q_i_2(pc_rx_data_nbs)); mac_operation_control i_mac_operation_control (.D({store_data_word[2],store_data_word[0],pc_rx_data_nbs}), .E(rx_store_dlc), .\FSM_sequential_curr_state[1]_i_16 (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state[1]_i_6 (i_mac_pc_top_n_74), .\FSM_sequential_curr_state_reg[0]_0 (curr_state[0]), .\FSM_sequential_curr_state_reg[0]_1 (i_mac_operation_control_n_15), .\FSM_sequential_curr_state_reg[0]_2 (i_mac_operation_control_n_16), .\FSM_sequential_curr_state_reg[0]_3 (i_mac_operation_control_n_23), .\FSM_sequential_curr_state_reg[0]_4 (reg_q_reg_1), .\FSM_sequential_curr_state_reg[0]_5 (i_mac_pc_top_n_186), .\FSM_sequential_curr_state_reg[1]_0 (curr_state[1]), .\FSM_sequential_curr_state_reg[1]_1 (i_mac_operation_control_n_4), .\FSM_sequential_curr_state_reg[1]_2 (i_mac_operation_control_n_5), .\FSM_sequential_curr_state_reg[1]_3 (i_mac_operation_control_n_6), .\FSM_sequential_curr_state_reg[1]_4 (i_mac_operation_control_n_9), .\FSM_sequential_curr_state_reg[1]_5 (i_mac_operation_control_n_17), .\FSM_sequential_curr_state_reg[1]_6 (\cc_stat[is_transmitter] ), .\FSM_sequential_curr_state_reg[1]_7 (i_mac_operation_control_n_22), .\FSM_sequential_curr_state_reg[1]_8 (i_mac_pc_top_n_185), .Q(\curr_state_reg[3] ), .\adress[4] (i_mac_operation_control_n_0), .adress_IBUF(adress_IBUF[2:0]), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\ctrl_ctr_q[3]_i_10 (\ctrl_ctr_q_reg[5]_0 ), .\ctrl_ctr_q[4]_i_4 (\ctrl_ctr_q_reg[1] ), .\ctrl_ctr_q_reg[6] (\ctrl_ctr_q_reg[6] ), .\ctrl_ctr_q_reg[6]_0 (i_mac_pc_top_n_165), .\exp_seg_length_q[8]_i_9 (i_mac_pc_top_n_109), .\exp_seg_length_q[8]_i_9_0 (i_mac_pc_top_n_184), .\g_bit[0].reg_value_r_reg[0] (i_mac_operation_control_n_7), .\g_bit[0].reg_value_r_reg[0]_0 (i_mac_operation_control_n_10), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[0].reg_value_r_reg[0]_2 (i_mac_operation_control_n_14), .\g_bit[0].reg_value_r_reg[0]_3 (i_mac_operation_control_n_20), .\g_bit[0].reg_value_r_reg[0]_4 (i_mac_operation_control_n_21), .\g_bit[0].reg_value_r_reg[0]_5 (i_mac_operation_control_n_24), .mr_ctr_pres_ptx_q(\i_mac_fc_err_counters/mr_ctr_pres_ptx_q ), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[ssp_cfg_ssp_src] (\mr_ctrl_out[ssp_cfg_ssp_src] ), .p_131_in(\i_mac_pc_fsm/p_131_in ), .\r_data[4]_i_2 (\r_data[4]_i_2_0 ), .rec_frame_type_i_reg(i_mac_operation_control_n_12), .rec_lbpf(rec_lbpf), .rx_err_ctr_sat1_carry_i_9(i_mac_pc_top_n_83), .\shift_regs[28]_i_8 (\shift_regs_reg[13] ), .\shift_regs[31]_i_15 (rec_frame_type), .\tran_dlc_com_reg[0] (i_mac_operation_control_n_18), .tran_frame_type(tran_frame_type), .tran_ident_type(tran_ident_type), .tran_ident_type_com_reg(i_mac_operation_control_n_13), .tx_err_ctr_q(\i_mac_fc_err_counters/tx_err_ctr_q ), .\tx_err_ctr_q_reg[0] (i_mac_fc_top_n_53), .\tx_err_ctr_q_reg[0]_0 (i_mac_pc_top_n_84), .\txtb_hw_cmd_q[arbl]_i_2 (tx_frame_no_sof_q_reg), .\txtb_hw_cmd_q[arbl]_i_2_0 (destuffed)); mac_pc_top i_mac_pc_top (.D({D[8:7],D[5:4],D[2]}), .E(err_detected), .\FSM_onehot_curr_state_reg[1] (\FSM_onehot_curr_state_reg[1] ), .\FSM_onehot_curr_state_reg[5] (\FSM_onehot_curr_state_reg[5] ), .\FSM_onehot_curr_state_reg[5]_0 (\FSM_onehot_curr_state_reg[5]_0 ), .\FSM_onehot_current_state_reg[2] (i_mac_pc_top_n_101), .\FSM_sequential_curr_state[0]_i_7 (\FSM_sequential_curr_state[0]_i_7 ), .\FSM_sequential_curr_state[0]_i_7_0 (\FSM_sequential_curr_state[0]_i_7_0 ), .\FSM_sequential_curr_state[1]_i_2__0 (\FSM_sequential_curr_state[1]_i_2__0 ), .\FSM_sequential_curr_state[1]_i_2__2 (\FSM_sequential_curr_state[1]_i_2__2 ), .\FSM_sequential_curr_state[1]_i_2__4 (i_mac_operation_control_n_22), .\FSM_sequential_curr_state[1]_i_4__2 (i_mac_fc_top_n_69), .\FSM_sequential_curr_state[2]_i_3__3 (\FSM_sequential_curr_state[2]_i_3__3 ), .\FSM_sequential_curr_state[2]_i_3__3_0 (\FSM_sequential_curr_state[2]_i_3__3_0 ), .\FSM_sequential_curr_state_reg[0] (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_0 (i_mac_fc_top_n_45), .\FSM_sequential_curr_state_reg[1] (i_mac_pc_top_n_96), .\FSM_sequential_curr_state_reg[1]_0 (i_mac_pc_top_n_185), .\FSM_sequential_curr_state_reg[1]_1 (i_mac_pc_top_n_186), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[2] (\FSM_sequential_curr_state_reg[2] ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_1 (\FSM_sequential_curr_state_reg[2]_1 ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_2 ), .Q({i_mac_pc_top_n_22,\curr_state_reg[3] ,i_mac_pc_top_n_24,i_mac_pc_top_n_25}), .S({i_mac_crc_top_n_40,i_mac_crc_top_n_41,i_mac_crc_top_n_42}), .abort_applied(abort_applied), .abort_applied_5(abort_applied_5), .abort_or_skipped(abort_or_skipped), .abort_or_skipped_3(abort_or_skipped_3), .adress_IBUF(adress_IBUF), .\alc_alc_bit_reg[0] (i_mac_operation_control_n_5), .\alc_alc_bit_reg[4] (\alc_alc_bit_reg[4] ), .\alc_alc_id_field_reg[2] (\alc_alc_id_field_reg[2] ), .bds_data_in(bds_data_in), .bit_err(bit_err), .bit_err_enable(bit_err_enable), .bit_err_q_i_2(bit_err_q_i_2), .br_shifted(br_shifted), .btmc_meas_running_q(btmc_meas_running_q), .btmc_meas_running_q_reg(btmc_meas_running_q_reg), .btmc_meas_running_q_reg_0(reg_q_reg_3), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[dst_ctr] (\cc_stat[dst_ctr] ), .\cc_stat[err_erp] (\cc_stat[err_erp] ), .\cc_stat[is_bus_off] (\cc_stat[is_bus_off] ), .\cc_stat[is_err_passive] (\cc_stat[is_err_passive] ), .\cc_stat[is_receiver] (\cc_stat[is_receiver] ), .\cc_stat[status_pexs] (\cc_stat[status_pexs] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\compl_ctr_q_reg[7] ({\compl_ctr_q_reg[7] ,\curr_state_reg[3]_0 }), .crc_data_rx_wbs(crc_data_rx_wbs), .crc_match_c5_carry__0({i_mac_crc_top_n_44,i_mac_crc_top_n_45,i_mac_crc_top_n_46,i_mac_crc_top_n_47}), .crc_match_c5_carry__0_0(crc_21), .crc_match_c6_carry__0({crc_17[14:12],crc_17[2:0]}), .\crc_match_c6_inferred__0/i__carry__0 ({i_mac_crc_top_n_50,i_mac_crc_top_n_51,i_mac_crc_top_n_52}), .crc_match_q_i_2(i_mac_crc_top_n_43), .crc_match_q_i_2_0(i_mac_crc_top_n_53), .crc_match_q_i_2_1(\shift_regs_reg[13] ), .crc_match_q_i_3({i_mac_crc_top_n_48,i_mac_crc_top_n_49}), .crc_match_q_reg(i_mac_operation_control_n_12), .\crc_q[14]_i_11 (i_mac_operation_control_n_16), .\crc_q[14]_i_6 (i_mac_operation_control_n_23), .\crc_q_reg[0] (i_mac_bit_stuffing_n_8), .\crc_q_reg[0]_0 (i_mac_crc_top_n_11), .\crc_q_reg[14] ({crc_d[14],crc_d[10],crc_d[8:7],crc_d[4:3],i_mac_pc_top_n_193}), .\crc_q_reg[14]_0 ({crc_15[14:13],crc_15[9],crc_15[7:2]}), .\crc_q_reg[20] (i_mac_bit_destuffing_n_6), .\ctrl_ctr_q[2]_i_3 (i_mac_operation_control_n_7), .\ctrl_ctr_q[3]_i_3 (i_mac_bit_destuffing_n_18), .\ctrl_ctr_q[3]_i_3_0 (i_mac_fc_top_n_57), .\ctrl_ctr_q[8]_i_11 (i_mac_fc_top_n_55), .\ctrl_ctr_q[8]_i_11_0 (i_mac_bit_destuffing_n_13), .\ctrl_ctr_q_reg[1] (\ctrl_ctr_q_reg[1] ), .\ctrl_ctr_q_reg[1]_0 (i_mac_operation_control_n_10), .\ctrl_ctr_q_reg[4] (\g_bit[0].reg_value_r_reg[0]_0 ), .\ctrl_ctr_q_reg[4]_0 (i_mac_operation_control_n_21), .\ctrl_ctr_q_reg[5] (i_mac_operation_control_n_18), .\ctrl_ctr_q_reg[5]_0 (\ctrl_ctr_q_reg[5] ), .\ctrl_ctr_q_reg[5]_1 (\ctrl_ctr_q_reg[5]_0 [2:1]), .\ctrl_ctr_q_reg[6] (i_mac_operation_control_n_17), .\ctrl_ctr_q_reg[7] (i_mac_pc_top_n_74), .\ctrl_ctr_q_reg[8] (\ctrl_ctr_q_reg[8] ), .\ctrl_ctr_q_reg[8]_0 (\ctrl_ctr_q_reg[8]_0 ), .\curr_state[0]_i_3 (i_mac_fc_top_n_67), .\curr_state[0]_i_3_0 (\curr_state[0]_i_3 ), .\curr_state[1]_i_4 (i_mac_fc_top_n_70), .\curr_state[5]_i_10 (i_mac_fc_top_n_56), .\curr_state[5]_i_5 (i_mac_fc_top_n_44), .curr_state_0(curr_state_0), .curr_state_1(curr_state_1), .curr_state_2(curr_state_2), .curr_state_4(curr_state_4), .curr_state_6(curr_state_6), .\curr_state_reg[0] (\curr_state_reg[0] ), .\curr_state_reg[0]_0 (\curr_state_reg[0]_0 ), .\curr_state_reg[0]_1 (rx_store_dlc), .\curr_state_reg[0]_2 (\curr_state_reg[0]_1 ), .\curr_state_reg[0]_3 (\cc_stat[is_err_active] ), .\curr_state_reg[1] (\curr_state_reg[1] ), .\curr_state_reg[1]_0 (i_mac_pc_top_n_83), .\curr_state_reg[1]_1 (\curr_state_reg[1]_0 ), .\curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1] ), .\curr_state_reg[2] (\curr_state_reg[2] ), .\curr_state_reg[2]_0 (\curr_state_reg[2]_0 ), .\curr_state_reg[2]_1 (\curr_state_reg[2]_1 ), .\curr_state_reg[2]_2 (\curr_state_reg[2]_2 ), .\curr_state_reg[3] (\curr_state_reg[3]_1 ), .\curr_state_reg[3]_0 (i_mac_pc_top_n_184), .\curr_state_reg[4] (i_mac_pc_top_n_109), .\curr_state_reg[4]_0 (i_mac_operation_control_n_15), .\curr_state_reg[4]_1 (i_mac_bit_destuffing_n_11), .\curr_state_reg[5] (\curr_state_reg[5] ), .\curr_state_reg[5]_0 (\curr_state_reg[5]_0 ), .\curr_state_reg[5]_1 (\curr_state_reg[5]_1 ), .\curr_state_reg[5]_2 (i_mac_pc_top_n_177), .data_halt_d1_out(data_halt_d1_out), .data_in_IBUF(data_in_IBUF), .destuff_enable(destuff_enable), .destuff_enable_reg(i_mac_bit_destuffing_n_4), .destuff_enable_reg_0(i_mac_fc_top_n_42), .destuff_enable_reg_1(destuff_enable_reg), .destuff_enable_reg_2(i_mac_bit_destuffing_n_10), .enable_prev(enable_prev), .err_capt_err_erp_reg(err_capt_err_erp_reg), .\err_capt_err_pos_q_reg[0] (\err_capt_err_pos_q_reg[0] ), .\err_capt_err_pos_q_reg[0]_0 (i_mac_operation_control_n_13), .\err_capt_err_pos_q_reg[3] (\err_capt_err_pos_q_reg[3] ), .\err_capt_err_type_q[2]_i_8 (\err_capt_err_type_q[2]_i_8 ), .\err_capt_err_type_q_reg[0] (\err_capt_err_type_q_reg[0] ), .\err_capt_err_type_q_reg[1] (i_mac_bit_destuffing_n_17), .\err_capt_err_type_q_reg[2] (\err_capt_err_type_q_reg[2] ), .err_frm_req_reg(err_frm_req), .err_frm_req_reg_0(arbitration_lost), .err_frm_req_reg_1(i_mac_pc_top_n_135), .err_frm_req_reg_2(err_frm_req_reg), .err_frm_req_reg_3(err_frm_req_reg_0), .err_frm_req_reg_4(i_mac_pc_top_n_176), .err_frm_req_reg_5(err_frm_req_reg_1), .err_frm_req_reg_6(err_frm_req_reg_2), .\exp_seg_length_q_reg[0] (\exp_seg_length_q_reg[0] ), .\exp_seg_length_q_reg[0]_0 (\exp_seg_length_q_reg[0]_0 ), .first_ssp_q0(first_ssp_q0), .fixed_prev_q(fixed_prev_q), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[0].reg_value_r_reg[0]_0 (i_mac_pc_top_n_80), .\g_bit[0].reg_value_r_reg[0]_1 (i_mac_pc_top_n_84), .\g_bit[0].reg_value_r_reg[0]_2 (i_mac_pc_top_n_85), .\g_bit[0].reg_value_r_reg[0]_3 (i_mac_pc_top_n_86), .\g_bit[1].reg_value_r_reg[1] (\g_bit[1].reg_value_r_reg[1] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][0] (pc_rx_data_nbs), .\g_byte_shift_reg[0].shift_reg_q_reg[0][1] (\g_byte_shift_reg[0].shift_reg_q_reg[0][1] ), .\g_byte_shift_reg[0].shift_reg_q_reg[0][2] (i_mac_pc_top_n_165), .\g_byte_shift_reg[1].shift_reg_q_reg[1][1] ({store_data_word[9:0],store_data_word[16:10]}), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg_0 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_1 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_2 ), .\g_ram_rst_false.ram_memory_reg_i_55 (\g_ram_rst_false.ram_memory_reg_i_55 ), .ident_valid_q(ident_valid_q), .ident_valid_q_reg(E), .int_status_i_2__1(i_mac_fc_top_n_73), .int_status_i_2__1_0(int_status_i_2__1), .int_status_i_4(int_status_i_4), .int_status_reg(int_status_reg), .int_status_reg_0(int_status_reg_2), .int_status_reg_1(int_status_reg_3), .int_status_reg_2(int_status_reg_1[1]), .is_tseg1(is_tseg1), .is_tseg2(is_tseg2), .mr_ctr_pres_efd_q(\i_mac_fc_err_counters/mr_ctr_pres_efd_q ), .mr_ctr_pres_efd_q_reg(\i_mac_fc_err_counters/data_err_ctr_ce ), .mr_ctr_pres_enorm_q(\i_mac_fc_err_counters/mr_ctr_pres_enorm_q ), .mr_ctr_pres_enorm_q_reg(\i_mac_fc_err_counters/nom_err_ctr_ce ), .\mr_ctrl_out[mode_bmm] (\mr_ctrl_out[mode_bmm] ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_ctrl_out[mode_fde] (\mr_ctrl_out[mode_fde] ), .\mr_ctrl_out[mode_rom] (\mr_ctrl_out[mode_rom] ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_ctrl_out[settings_ena] (\mr_ctrl_out[settings_ena] ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .\mr_ctrl_out[settings_rtrth] (\mr_ctrl_out[settings_rtrth] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .\mr_ctrl_out[ssp_cfg_ssp_src] (\mr_ctrl_out[ssp_cfg_ssp_src] ), .mr_int_stat_txbhci_o(mr_int_stat_txbhci_o), .mr_status_pexs_reg(mr_status_pexs_reg), .mr_status_pexs_reg_0(mr_status_pexs_reg_0), .\mr_tx_priority[0] (\mr_tx_priority[0] ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .p_0_out(p_0_out), .p_131_in(\i_mac_pc_fsm/p_131_in ), .\pc_dbg[is_arbitration] (\pc_dbg[is_arbitration] ), .prev_val_d(prev_val_d), .\r_data[0]_i_5 (\r_data[0]_i_5 ), .\r_data[19]_i_2 (\r_data[19]_i_2_0 ), .\r_data[7]_i_3__0 (\r_data[7]_i_3__0 ), .\r_data_reg[12] (\r_data_reg[12] ), .\r_data_reg[12]_0 (\r_data_reg[12]_0 ), .\r_data_reg[13] (\r_data_reg[13] ), .\r_data_reg[13]_0 (\r_data_reg[13]_0 ), .\r_data_reg[13]_1 (\cc_stat[norm_err_ctr] ), .\r_data_reg[13]_2 (\r_data_reg[13]_1 ), .\r_data_reg[13]_3 (\r_data_reg[13]_2 ), .\r_data_reg[13]_4 (\r_data_reg[13]_3 ), .\r_data_reg[15] (i_mac_fc_top_n_66), .\r_data_reg[15]_0 (\r_data_reg[15] ), .\r_data_reg[15]_1 (\r_data_reg[15]_0 ), .\r_data_reg[15]_2 (\r_data_reg[15]_1 ), .\r_data_reg[16] (\r_data_reg[16] ), .\r_data_reg[16]_0 (\r_data_reg[16]_0 ), .\r_data_reg[16]_1 (i_mac_fc_top_n_65), .\r_data_reg[18] (\r_data_reg[18] ), .\r_data_reg[18]_0 (\r_data_reg[18]_0 ), .\r_data_reg[18]_1 (\r_data_reg[18]_1 ), .\r_data_reg[18]_2 (\r_data_reg[18]_2 ), .\r_data_reg[18]_3 (i_mac_fc_top_n_28), .\r_data_reg[18]_4 (\r_data_reg[18]_3 ), .\r_data_reg[18]_5 (\r_data_reg[18]_4 ), .\r_data_reg[19] (\r_data_reg[19] ), .\r_data_reg[19]_0 (i_mac_fc_top_n_31), .\r_data_reg[19]_1 (\r_data_reg[19]_0 ), .\r_data_reg[5]_i_5 (\r_data_reg[5]_i_5 ), .rec_abort_f(rec_abort_f), .rec_abort_reg(rec_abort), .rec_abort_reg_0(rec_abort_reg), .rec_brs(rec_brs), .rec_brs_reg(i_mac_bit_destuffing_n_20), .\rec_dlc_reg[0] (i_mac_bit_destuffing_n_9), .\rec_dlc_reg[1] (\rec_dlc_reg[1] ), .\rec_dlc_reg[1]_0 (\rec_dlc_reg[1]_0 ), .\rec_dlc_reg[2] (\rec_dlc_reg[2] ), .\rec_dlc_reg[2]_0 (\rec_dlc_reg[2]_0 ), .\rec_dlc_reg[3] (\rec_dlc_reg[3] ), .\rec_dlc_reg[3]_0 (\rec_dlc_reg[3]_0 ), .rec_esi(rec_esi), .rec_frame_type_i_reg(rec_frame_type), .\rec_ident_reg[28] (\rec_ident_reg[28] ), .rec_ident_type(rec_ident_type), .rec_is_rtr(rec_is_rtr), .rec_is_rtr_i_reg(rec_is_rtr_i), .rec_ivld(rec_ivld), .rec_ivld_q_reg(i_mac_fc_top_n_72), .rec_lbpf(rec_lbpf), .rec_lbpf_q_reg(i_mac_operation_control_n_24), .rec_valid_reg(rec_valid), .rec_valid_reg_0(rec_valid_reg), .rec_valid_reg_1(i_mac_operation_control_n_14), .reg_q(reg_q), .reg_q_reg(reg_q_reg), .reg_q_reg_0(reg_q_reg_0), .reg_q_reg_1(\i_mac_crc_calc_17_rx/crc_ce ), .reg_q_reg_10(reg_q_reg_5), .reg_q_reg_11(crc_data_tx_wbs), .reg_q_reg_2(i_mac_pc_top_n_94), .reg_q_reg_3(\i_mac_crc_calc_15/crc_ce ), .reg_q_reg_4(i_mac_pc_top_n_98), .reg_q_reg_5(i_mac_pc_top_n_103), .reg_q_reg_6(i_mac_pc_top_n_179), .reg_q_reg_7(i_mac_bit_destuffing_n_3), .reg_q_reg_8(i_mac_bit_destuffing_n_8), .reg_q_reg_9(reg_q_reg_4), .\retr_ctr_q_reg[3] (\retr_ctr_q_reg[3] ), .\retr_ctr_q_reg[3]_0 (\retr_ctr_q_reg[3]_0 ), .rst_n_out_OBUF(rst_n_out_OBUF), .rx_data_nbs_prev(\i_mac_pc_fsm/rx_data_nbs_prev ), .rx_data_nbs_prev_reg(i_mac_bit_destuffing_n_19), .rx_data_sync_prev_reg(i_mac_operation_control_n_4), .rx_data_wbs(rx_data_wbs), .\same_bits_q_reg[2] (\same_bits_q_reg[2] ), .sbe_IBUF(sbe_IBUF[2:1]), .scan_mode_IBUF(scan_mode_IBUF), .\segm_counter_q_reg[0] (\segm_counter_q_reg[0] ), .\segm_counter_q_reg[0]_0 (\segm_counter_q_reg[0]_0 ), .\segm_counter_q_reg[0]_1 (\segm_counter_q_reg[0]_1 ), .\segm_counter_q_reg[0]_2 (\segm_counter_q_reg[0]_2 ), .\shift_regs[31]_i_7 (i_mac_operation_control_n_20), .\shift_regs_reg[0] (reg_q_reg_1), .\shift_regs_reg[0]_0 (curr_state[0]), .\shift_regs_reg[0]_1 (curr_state[1]), .\shift_regs_reg[0]_2 (\shift_regs_reg[0] ), .\shift_regs_reg[11] (\shift_regs_reg[11] ), .\shift_regs_reg[11]_0 (\shift_regs_reg[11]_0 ), .\shift_regs_reg[12] (\shift_regs_reg[12] ), .\shift_regs_reg[12]_0 (\shift_regs_reg[12]_0 ), .\shift_regs_reg[13] (i_mac_crc_top_n_21), .\shift_regs_reg[14] (i_mac_crc_top_n_22), .\shift_regs_reg[14]_0 (\shift_regs_reg[14] ), .\shift_regs_reg[15] (i_mac_crc_top_n_23), .\shift_regs_reg[15]_0 (\shift_regs_reg[15] ), .\shift_regs_reg[16] (\shift_regs_reg[16] ), .\shift_regs_reg[16]_0 (i_mac_crc_top_n_24), .\shift_regs_reg[16]_1 (\shift_regs_reg[16]_0 ), .\shift_regs_reg[17] (\shift_regs_reg[17] ), .\shift_regs_reg[17]_0 (\shift_regs_reg[17]_0 ), .\shift_regs_reg[18] (\shift_regs_reg[18] ), .\shift_regs_reg[18]_0 (\shift_regs_reg[18]_0 ), .\shift_regs_reg[19] (\shift_regs_reg[19] ), .\shift_regs_reg[19]_0 (\shift_regs_reg[19]_0 ), .\shift_regs_reg[1] (\shift_regs_reg[1] ), .\shift_regs_reg[20] (i_mac_crc_top_n_25), .\shift_regs_reg[20]_0 (\shift_regs_reg[20] ), .\shift_regs_reg[21] (i_mac_crc_top_n_26), .\shift_regs_reg[21]_0 (\shift_regs_reg[21] ), .\shift_regs_reg[22] (i_mac_crc_top_n_27), .\shift_regs_reg[22]_0 (\shift_regs_reg[22] ), .\shift_regs_reg[23] (i_mac_crc_top_n_28), .\shift_regs_reg[24] (\shift_regs_reg[24] ), .\shift_regs_reg[25] (\shift_regs_reg[25] ), .\shift_regs_reg[25]_0 (\shift_regs_reg[25]_0 ), .\shift_regs_reg[26] (\shift_regs_reg[26] ), .\shift_regs_reg[26]_0 (\shift_regs_reg[26]_0 ), .\shift_regs_reg[27] (\shift_regs_reg[27] ), .\shift_regs_reg[27]_0 (\shift_regs_reg[27]_0 ), .\shift_regs_reg[28] (\shift_regs_reg[28] ), .\shift_regs_reg[28]_0 (\shift_regs_reg[28]_0 ), .\shift_regs_reg[28]_1 (\shift_regs_reg[28]_1 ), .\shift_regs_reg[28]_2 (\shift_regs_reg[28]_2 ), .\shift_regs_reg[28]_3 (i_mac_crc_top_n_31), .\shift_regs_reg[29] (i_mac_bit_stuffing_n_2), .\shift_regs_reg[29]_0 (\shift_regs_reg[29] ), .\shift_regs_reg[29]_1 (\shift_regs_reg[29]_0 ), .\shift_regs_reg[29]_2 (i_mac_crc_top_n_32), .\shift_regs_reg[2] (\shift_regs_reg[2] ), .\shift_regs_reg[30] (i_mac_crc_top_n_29), .\shift_regs_reg[30]_0 (i_mac_bit_stuffing_n_5), .\shift_regs_reg[30]_1 (\shift_regs_reg[30] ), .\shift_regs_reg[31] (\shift_regs_reg[31] ), .\shift_regs_reg[31]_0 (\shift_regs_reg[31]_0 ), .\shift_regs_reg[31]_1 (i_mac_crc_top_n_30), .\shift_regs_reg[31]_2 (\shift_regs_reg[31]_1 ), .\sp_control_q_i_reg[0] (\sp_control_q_i_reg[0] ), .\sp_control_q_i_reg[0]_0 (\sp_control_q_i_reg[0]_0 ), .\sp_control_q_i_reg[1] (\sp_control_q_i_reg[1] ), .\sp_control_q_i_reg[1]_0 (\cc_stat[is_transmitter] ), .sspc_ena_q(sspc_ena_q), .sspc_ena_q_reg(sspc_ena_q_reg), .store_data_word(store_data_word[31:17]), .store_metadata_reg(store_metadata), .store_metadata_reg_0(i_mac_operation_control_n_6), .stuff_enable(stuff_enable), .stuff_err(stuff_err), .stuff_err_d(stuff_err_d), .\sync_control_q_reg[0] (\sync_control_q_reg[0] ), .\sync_control_q_reg[0]_0 (\sync_control_q_reg[0]_0 ), .\sync_control_q_reg[1] (\sync_control_q_reg[1] ), .sync_edge(sync_edge), .sync_edge3__0(sync_edge3__0), .sync_flag(sync_flag), .\timestamp[14] (i_mac_pc_top_n_19), .\timestamp[17] (i_mac_pc_top_n_20), .\timestamp[41] (\timestamp[41] ), .\timestamp[42] (\timestamp[42] ), .\timestamp[43] (\timestamp[43] ), .\timestamp[7] (\timestamp[7] ), .\timestamp[8] (\timestamp[8] ), .timestamp_IBUF(timestamp_IBUF), .\timestamp_capture_reg[63] (i_mac_fc_top_n_71), .\tq_counter_q_reg[7] (\tq_counter_q_reg[7] ), .tran_brs(tran_brs), .tran_delay_meas(tran_delay_meas), .\tran_frame_test[fcrc] (\tran_frame_test[fcrc] ), .tran_frame_valid(tran_frame_valid), .tran_ident_type(tran_ident_type), .tran_is_rtr(tran_is_rtr), .tran_word(tran_word), .tx_data_prev(tx_data_prev), .tx_frame_no_sof(tx_frame_no_sof), .tx_frame_no_sof_q_reg(i_mac_pc_top_n_134), .tx_frame_no_sof_q_reg_0(i_mac_bit_destuffing_n_12), .tx_frame_no_sof_q_reg_1(i_mac_fc_top_n_68), .tx_frame_no_sof_q_reg_2(tx_frame_no_sof_q_reg), .tx_frame_no_sof_q_reg_3(destuffed), .tx_trigger_q(tx_trigger_q), .txtb_allow_bb(txtb_allow_bb), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .\txtb_hw_cmd_q[err] (\txtb_hw_cmd_q[err] ), .\txtb_hw_cmd_q_reg[arbl] (\txtb_hw_cmd_q_reg[arbl] ), .\txtb_hw_cmd_q_reg[err] (\txtb_hw_cmd_q_reg[err] ), .\txtb_hw_cmd_q_reg[failed] (\txtb_hw_cmd[failed] ), .\txtb_hw_cmd_q_reg[failed]_0 (\txtb_hw_cmd_q_reg[failed] ), .\txtb_hw_cmd_q_reg[failed]_1 (\txtb_hw_cmd_q_reg[failed]_0 ), .\txtb_hw_cmd_q_reg[failed]_2 (\txtb_hw_cmd_q_reg[failed]_1 ), .\txtb_hw_cmd_q_reg[failed]_3 (\txtb_hw_cmd_q_reg[failed]_2 ), .\txtb_hw_cmd_q_reg[failed]_4 (\txtb_hw_cmd_q_reg[failed]_3 ), .\txtb_hw_cmd_q_reg[failed]_5 (\txtb_hw_cmd_q_reg[failed]_4 ), .\txtb_hw_cmd_q_reg[failed]_6 (\txtb_hw_cmd_q_reg[failed]_5 ), .\txtb_hw_cmd_q_reg[lock] (\txtb_hw_cmd[lock] ), .\txtb_hw_cmd_q_reg[lock]_0 (\txtb_hw_cmd_q_reg[lock] ), .\txtb_hw_cmd_q_reg[lock]_1 (\txtb_hw_cmd_q_reg[lock]_0 ), .\txtb_hw_cmd_q_reg[lock]_2 (\txtb_hw_cmd_q_reg[lock]_1 ), .\txtb_hw_cmd_q_reg[lock]_3 (i_mac_fc_top_n_43), .\txtb_hw_cmd_q_reg[valid] (\txtb_hw_cmd[valid] ), .\txtb_hw_cmd_q_reg[valid]_0 (\txtb_hw_cmd_q_reg[valid] ), .\txtb_hw_cmd_q_reg[valid]_1 (\txtb_hw_cmd_q_reg[valid]_0 ), .\txtb_hw_cmd_q_reg[valid]_2 (i_mac_pc_top_n_133), .\txtb_ptr_q_reg[4] (\txtb_ptr_q_reg[4] ), .\txtb_ptr_q_reg[4]_0 (\txtb_ptr_q_reg[4]_0 ), .\txtb_ptr_q_reg[4]_1 (\txtb_ptr_q_reg[4]_1 ), .\txtb_ptr_q_reg[4]_2 (\txtb_ptr_q_reg[4]_2 )); mac_trigger_mux i_mac_trigger_mux (.bds_data_in(bds_data_in), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_rx_wbs(crc_data_rx_wbs), .reg_q_reg(reg_q_reg_3), .reg_q_reg_0(reg_q_reg_1), .reg_q_reg_1(reg_q_reg_4), .tx_trigger_q(tx_trigger_q), .tx_trigger_ssp(tx_trigger_ssp), .\write_pointer_q_reg[0] (\write_pointer_q_reg[0] ), .\write_pointer_q_reg[0]_0 (\g_bit[1].reg_value_r_reg[1] ), .\write_pointer_q_reg[0]_1 (\write_pointer_q_reg[0]_0 )); endmodule module mac_trigger_mux (tx_trigger_q, tx_trigger_ssp, \write_pointer_q_reg[0] , crc_data_rx_wbs, reg_q_reg, clk_sys_IBUF_BUFG, reg_q_reg_0, \write_pointer_q_reg[0]_0 , \write_pointer_q_reg[0]_1 , bds_data_in, reg_q_reg_1); output tx_trigger_q; output tx_trigger_ssp; output \write_pointer_q_reg[0] ; output crc_data_rx_wbs; input reg_q_reg; input clk_sys_IBUF_BUFG; input reg_q_reg_0; input \write_pointer_q_reg[0]_0 ; input [0:0]\write_pointer_q_reg[0]_1 ; input bds_data_in; input reg_q_reg_1; wire bds_data_in; wire clk_sys_IBUF_BUFG; wire crc_data_rx_wbs; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire tx_trigger_q; wire tx_trigger_ssp; wire \write_pointer_q_reg[0] ; wire \write_pointer_q_reg[0]_0 ; wire [0:0]\write_pointer_q_reg[0]_1 ; dff_arst_ce i_crc_data_rx_wbs_reg (.bds_data_in(bds_data_in), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_rx_wbs(crc_data_rx_wbs), .reg_q_reg_0(reg_q_reg_1), .reg_q_reg_1(reg_q_reg_0)); dff_arst_57 i_crc_trig_tx_wbs_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .tx_trigger_q(tx_trigger_q), .tx_trigger_ssp(tx_trigger_ssp), .\write_pointer_q_reg[0] (\write_pointer_q_reg[0] ), .\write_pointer_q_reg[0]_0 (\write_pointer_q_reg[0]_0 ), .\write_pointer_q_reg[0]_1 (\write_pointer_q_reg[0]_1 )); endmodule module memory_reg_rw (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_13 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_14 (D, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , sbe_IBUF, adress_IBUF, \r_data_reg[7] , \r_data_reg[7]_0 , \r_data_reg[7]_1 , \r_data_reg[7]_2 ); output [0:0]D; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [0:0]sbe_IBUF; input [2:0]adress_IBUF; input \r_data_reg[7] ; input \r_data_reg[7]_0 ; input \r_data_reg[7]_1 ; input \r_data_reg[7]_2 ; wire [0:0]D; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg_n_0_[0] ; wire \r_data[7]_i_2__0_n_0 ; wire \r_data_reg[7] ; wire \r_data_reg[7]_0 ; wire \r_data_reg[7]_1 ; wire \r_data_reg[7]_2 ; wire [0:0]sbe_IBUF; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg_n_0_[0] )); LUT6 #( .INIT(64'h020202020202A202)) \r_data[7]_i_1 (.I0(sbe_IBUF), .I1(\r_data[7]_i_2__0_n_0 ), .I2(adress_IBUF[2]), .I3(\r_data_reg[7] ), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(D)); LUT6 #( .INIT(64'hD0DDFFFFD0DD0000)) \r_data[7]_i_2__0 (.I0(\g_bit[0].reg_value_r_reg_n_0_[0] ), .I1(\r_data_reg[7]_0 ), .I2(\r_data_reg[7]_1 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\r_data_reg[7]_2 ), .O(\r_data[7]_i_2__0_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_15 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_16 (D, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , sbe_IBUF, adress_IBUF, \r_data_reg[5] , \r_data_reg[5]_0 , \r_data_reg[5]_1 , \r_data_reg[5]_2 ); output [0:0]D; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [0:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[5] ; input \r_data_reg[5]_0 ; input \r_data_reg[5]_1 ; input \r_data_reg[5]_2 ; wire [0:0]D; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg_n_0_[0] ; wire \r_data[5]_i_2_n_0 ; wire \r_data[5]_i_4_n_0 ; wire \r_data_reg[5] ; wire \r_data_reg[5]_0 ; wire \r_data_reg[5]_1 ; wire \r_data_reg[5]_2 ; wire [0:0]sbe_IBUF; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg_n_0_[0] )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[5]_i_1 (.I0(sbe_IBUF), .I1(\r_data[5]_i_2_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[5] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D)); LUT6 #( .INIT(64'h1F5010501F5F105F)) \r_data[5]_i_2 (.I0(\r_data[5]_i_4_n_0 ), .I1(\r_data_reg[5]_0 ), .I2(adress_IBUF[4]), .I3(adress_IBUF[3]), .I4(\r_data_reg[5]_1 ), .I5(\r_data_reg[5]_2 ), .O(\r_data[5]_i_2_n_0 )); LUT5 #( .INIT(32'h00800000)) \r_data[5]_i_4 (.I0(\g_bit[0].reg_value_r_reg_n_0_[0] ), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[3]), .I4(adress_IBUF[0]), .O(\r_data[5]_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_17 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_18 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_19 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, \adress[2] , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , adress_IBUF); output \g_bit[0].reg_value_r_reg[0]_0 ; output wr_en; output \adress[2] ; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input \g_bit[0].reg_value_r_reg[0]_2 ; input [5:0]adress_IBUF; wire \adress[2] ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire wr_en; LUT6 #( .INIT(64'h0002000000000000)) \g_bit[0].reg_value_r[0]_i_1__26 (.I0(\g_bit[0].reg_value_r_reg[0]_2 ), .I1(adress_IBUF[5]), .I2(adress_IBUF[3]), .I3(\adress[2] ), .I4(adress_IBUF[2]), .I5(adress_IBUF[4]), .O(wr_en)); LUT2 #( .INIT(4'h7)) \g_bit[0].reg_value_r[0]_i_2__5 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .O(\adress[2] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_20 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_21 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_22 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_23 (D, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , sbe_IBUF, \r_data_reg[12] , \r_data_reg[12]_0 , adress_IBUF, \r_data_reg[12]_1 , \r_data_reg[12]_2 , \mr_ctrl_out[mode_erfm] , \r_data_reg[12]_3 , \r_data_reg[12]_4 ); output [0:0]D; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [0:0]sbe_IBUF; input \r_data_reg[12] ; input \r_data_reg[12]_0 ; input [0:0]adress_IBUF; input \r_data_reg[12]_1 ; input \r_data_reg[12]_2 ; input \mr_ctrl_out[mode_erfm] ; input \r_data_reg[12]_3 ; input \r_data_reg[12]_4 ; wire [0:0]D; wire [0:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg_n_0_[0] ; wire \mr_ctrl_out[mode_erfm] ; wire \r_data[12]_i_2_n_0 ; wire \r_data_reg[12] ; wire \r_data_reg[12]_0 ; wire \r_data_reg[12]_1 ; wire \r_data_reg[12]_2 ; wire \r_data_reg[12]_3 ; wire \r_data_reg[12]_4 ; wire [0:0]sbe_IBUF; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg_n_0_[0] )); LUT6 #( .INIT(64'h00008A88AAAA8A88)) \r_data[12]_i_1 (.I0(sbe_IBUF), .I1(\r_data[12]_i_2_n_0 ), .I2(\r_data_reg[12] ), .I3(\r_data_reg[12]_0 ), .I4(adress_IBUF), .I5(\r_data_reg[12]_1 ), .O(D)); LUT5 #( .INIT(32'hFFFF44F4)) \r_data[12]_i_2 (.I0(\r_data_reg[12]_2 ), .I1(\g_bit[0].reg_value_r_reg_n_0_[0] ), .I2(\mr_ctrl_out[mode_erfm] ), .I3(\r_data_reg[12]_3 ), .I4(\r_data_reg[12]_4 ), .O(\r_data[12]_i_2_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_24 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_25 (\mr_ctrl_out[mode_acf] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 ); output \mr_ctrl_out[mode_acf] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_ctrl_out[mode_acf] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[mode_acf] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_26 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_27 (\g_bit[0].reg_value_r_reg[0]_0 , can_tx_OBUF, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_3 , tx_data_prev_reg, crc_data_tx_wbs, \FSM_sequential_curr_state_reg[0] , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output can_tx_OBUF; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[0].reg_value_r_reg[0]_2 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_3 ; input tx_data_prev_reg; input crc_data_tx_wbs; input \FSM_sequential_curr_state_reg[0] ; input \FSM_sequential_curr_state_reg[0]_0 ; input [1:0]\FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire [1:0]\FSM_sequential_curr_state_reg[0]_1 ; wire can_tx_OBUF; wire clk_sys_IBUF_BUFG; wire crc_data_tx_wbs; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire tx_data_prev_reg; wire wr_en; (* SOFT_HLUTNM = "soft_lutpair291" *) LUT5 #( .INIT(32'hEEEEEEFE)) \FSM_sequential_curr_state[0]_i_3__4 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[0] ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_1 [1]), .I4(\FSM_sequential_curr_state_reg[0]_1 [0]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT3 #( .INIT(8'hFB)) can_tx_OBUF_inst_i_1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(tx_data_prev_reg), .I2(crc_data_tx_wbs), .O(can_tx_OBUF)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_3 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair291" *) LUT4 #( .INIT(16'h000E)) int_status_i_7 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[0] ), .I2(\FSM_sequential_curr_state_reg[0]_1 [0]), .I3(\FSM_sequential_curr_state_reg[0]_1 [1]), .O(\g_bit[0].reg_value_r_reg[0]_2 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_28 (\mr_ctrl_out[mode_erfm] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 ); output \mr_ctrl_out[mode_erfm] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_ctrl_out[mode_erfm] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[mode_erfm] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_30 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_32 (\mr_ctrl_out[mode_sam] , \g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , \mr_ctrl_out[mode_acf] , curr_state); output \mr_ctrl_out[mode_sam] ; output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input \mr_ctrl_out[mode_acf] ; input [1:0]curr_state; wire clk_sys_IBUF_BUFG; wire [1:0]curr_state; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \mr_ctrl_out[mode_acf] ; wire \mr_ctrl_out[mode_sam] ; wire wr_en; LUT4 #( .INIT(16'h5FCF)) bit_err_q_i_10 (.I0(\mr_ctrl_out[mode_sam] ), .I1(\mr_ctrl_out[mode_acf] ), .I2(curr_state[1]), .I3(curr_state[0]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[mode_sam] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_33 (\mr_ctrl_out[mode_stm] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , adress_IBUF, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 ); output \mr_ctrl_out[mode_stm] ; output wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [3:0]adress_IBUF; input \g_bit[0].reg_value_r_reg[0]_1 ; input \g_bit[0].reg_value_r_reg[0]_2 ; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \mr_ctrl_out[mode_stm] ; wire wr_en; LUT6 #( .INIT(64'h0000000000010000)) \g_bit[0].reg_value_r[0]_i_1 (.I0(adress_IBUF[1]), .I1(adress_IBUF[2]), .I2(adress_IBUF[0]), .I3(adress_IBUF[3]), .I4(\g_bit[0].reg_value_r_reg[0]_1 ), .I5(\g_bit[0].reg_value_r_reg[0]_2 ), .O(wr_en)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[mode_stm] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_34 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en_7, wr_en, wr_en_0, wr_en_1, wr_en_2, wr_en_3, wr_en_4, wr_en_5, \mr_tst_out[tst_control_twrstb] , \g_bit[0].reg_value_r_reg[0]_1 , wr_en_6, wr_en_8, wr_en_9, \mr_ctrl_out[ctr_pres_ptx] , wr_en_10, \mr_ctrl_out[ctr_pres_prx] , \mr_ctrl_out[ctr_pres_enorm] , \mr_ctrl_out[ctr_pres_efd] , wr_en_11, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , \g_bit[0].reg_value_r_reg[0]_4 , adress_IBUF, \g_bit[7].reg_value_r_reg[7] , \g_bit[0].reg_value_r_reg[0]_5 , swr_IBUF, sbe_IBUF, \g_bit[7].reg_value_r_reg[7]_0 , \g_bit[0].reg_value_r_reg[0]_6 , \g_bit[0].reg_value_r_reg[0]_7 , \g_bit[0].reg_value_r_reg[0]_8 , \g_bit[0].reg_value_r_reg[0]_9 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output wr_en_7; output wr_en; output wr_en_0; output wr_en_1; output wr_en_2; output wr_en_3; output wr_en_4; output wr_en_5; output \mr_tst_out[tst_control_twrstb] ; output \g_bit[0].reg_value_r_reg[0]_1 ; output wr_en_6; output wr_en_8; output wr_en_9; output \mr_ctrl_out[ctr_pres_ptx] ; output wr_en_10; output \mr_ctrl_out[ctr_pres_prx] ; output \mr_ctrl_out[ctr_pres_enorm] ; output \mr_ctrl_out[ctr_pres_efd] ; output wr_en_11; input [5:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_2 ; input \g_bit[0].reg_value_r_reg[0]_3 ; input \g_bit[0].reg_value_r_reg[0]_4 ; input [5:0]adress_IBUF; input \g_bit[7].reg_value_r_reg[7] ; input \g_bit[0].reg_value_r_reg[0]_5 ; input swr_IBUF; input [3:0]sbe_IBUF; input \g_bit[7].reg_value_r_reg[7]_0 ; input \g_bit[0].reg_value_r_reg[0]_6 ; input \g_bit[0].reg_value_r_reg[0]_7 ; input \g_bit[0].reg_value_r_reg[0]_8 ; input \g_bit[0].reg_value_r_reg[0]_9 ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [5:0]data_in_IBUF; wire \g_bit[0].reg_value_r[0]_i_2__8_n_0 ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[0].reg_value_r_reg[0]_5 ; wire \g_bit[0].reg_value_r_reg[0]_6 ; wire \g_bit[0].reg_value_r_reg[0]_7 ; wire \g_bit[0].reg_value_r_reg[0]_8 ; wire \g_bit[0].reg_value_r_reg[0]_9 ; wire \g_bit[7].reg_value_r_reg[7] ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire \g_ram_rst_false.ram_memory_reg_i_126_n_0 ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire \mr_tst_out[tst_control_twrstb] ; wire [3:0]sbe_IBUF; wire swr_IBUF; wire wr_en; wire wr_en_0; wire wr_en_1; wire wr_en_10; wire wr_en_11; wire wr_en_2; wire wr_en_3; wire wr_en_4; wire wr_en_5; wire wr_en_6; wire wr_en_7; wire wr_en_8; wire wr_en_9; LUT6 #( .INIT(64'h0000000000000008)) \g_bit[0].reg_value_r[0]_i_1__0 (.I0(\g_bit[0].reg_value_r_reg[0]_3 ), .I1(\g_bit[0].reg_value_r_reg[0]_4 ), .I2(adress_IBUF[5]), .I3(adress_IBUF[2]), .I4(adress_IBUF[4]), .I5(adress_IBUF[3]), .O(wr_en_7)); LUT6 #( .INIT(64'h0000000008000000)) \g_bit[0].reg_value_r[0]_i_1__15 (.I0(sbe_IBUF[0]), .I1(swr_IBUF), .I2(\g_bit[0].reg_value_r_reg[0]_5 ), .I3(\g_bit[0].reg_value_r_reg[0]_0 ), .I4(\g_bit[0].reg_value_r_reg[0]_6 ), .I5(\g_bit[0].reg_value_r_reg[0]_7 ), .O(wr_en_6)); LUT6 #( .INIT(64'h0000000000080000)) \g_bit[0].reg_value_r[0]_i_1__17 (.I0(sbe_IBUF[0]), .I1(swr_IBUF), .I2(\g_bit[0].reg_value_r_reg[0]_8 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\g_bit[0].reg_value_r[0]_i_2__8_n_0 ), .O(wr_en_8)); (* SOFT_HLUTNM = "soft_lutpair292" *) LUT4 #( .INIT(16'h0100)) \g_bit[0].reg_value_r[0]_i_1__18 (.I0(\g_bit[0].reg_value_r_reg[0]_9 ), .I1(\g_bit[0].reg_value_r[0]_i_2__8_n_0 ), .I2(adress_IBUF[2]), .I3(adress_IBUF[0]), .O(wr_en_9)); LUT6 #( .INIT(64'h0000000000080000)) \g_bit[0].reg_value_r[0]_i_1__21 (.I0(swr_IBUF), .I1(sbe_IBUF[1]), .I2(\g_bit[0].reg_value_r_reg[0]_8 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\g_bit[0].reg_value_r[0]_i_2__8_n_0 ), .O(wr_en_10)); (* SOFT_HLUTNM = "soft_lutpair292" *) LUT4 #( .INIT(16'h0200)) \g_bit[0].reg_value_r[0]_i_1__22 (.I0(\g_bit[0].reg_value_r_reg[0]_3 ), .I1(\g_bit[0].reg_value_r[0]_i_2__8_n_0 ), .I2(adress_IBUF[2]), .I3(adress_IBUF[0]), .O(wr_en_11)); LUT6 #( .INIT(64'h0020000000000000)) \g_bit[0].reg_value_r[0]_i_1__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_bit[7].reg_value_r_reg[7] ), .I2(\g_bit[0].reg_value_r_reg[0]_4 ), .I3(\g_bit[0].reg_value_r_reg[0]_5 ), .I4(swr_IBUF), .I5(sbe_IBUF[2]), .O(wr_en)); LUT6 #( .INIT(64'h0020000000000000)) \g_bit[0].reg_value_r[0]_i_1__4 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_bit[7].reg_value_r_reg[7] ), .I2(\g_bit[0].reg_value_r_reg[0]_4 ), .I3(\g_bit[0].reg_value_r_reg[0]_5 ), .I4(swr_IBUF), .I5(sbe_IBUF[1]), .O(wr_en_0)); LUT6 #( .INIT(64'h0000080000000000)) \g_bit[0].reg_value_r[0]_i_1__5 (.I0(swr_IBUF), .I1(sbe_IBUF[0]), .I2(\g_bit[0].reg_value_r_reg[0]_5 ), .I3(\g_bit[0].reg_value_r_reg[0]_0 ), .I4(\g_bit[7].reg_value_r_reg[7] ), .I5(\g_bit[0].reg_value_r_reg[0]_4 ), .O(wr_en_1)); LUT6 #( .INIT(64'h0000040000000000)) \g_bit[0].reg_value_r[0]_i_1__6 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(sbe_IBUF[3]), .I2(\g_bit[7].reg_value_r_reg[7] ), .I3(\g_bit[0].reg_value_r_reg[0]_0 ), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(wr_en_2)); LUT6 #( .INIT(64'h0000000000400000)) \g_bit[0].reg_value_r[0]_i_1__7 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(sbe_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\g_bit[0].reg_value_r_reg[0]_0 ), .I5(\g_bit[7].reg_value_r_reg[7] ), .O(wr_en_3)); LUT6 #( .INIT(64'h0000000000400000)) \g_bit[0].reg_value_r[0]_i_1__8 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(sbe_IBUF[1]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\g_bit[0].reg_value_r_reg[0]_0 ), .I5(\g_bit[7].reg_value_r_reg[7] ), .O(wr_en_4)); LUT6 #( .INIT(64'h0000000000400000)) \g_bit[0].reg_value_r[0]_i_1__9 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(sbe_IBUF[0]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\g_bit[0].reg_value_r_reg[0]_0 ), .I5(\g_bit[7].reg_value_r_reg[7] ), .O(wr_en_5)); LUT5 #( .INIT(32'hFFDFFFFF)) \g_bit[0].reg_value_r[0]_i_2__8 (.I0(adress_IBUF[3]), .I1(adress_IBUF[5]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(adress_IBUF[4]), .I4(adress_IBUF[1]), .O(\g_bit[0].reg_value_r[0]_i_2__8_n_0 )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_7), .CLR(\g_bit[0].reg_value_r_reg[0]_2 ), .D(data_in_IBUF[1]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair293" *) LUT2 #( .INIT(4'h2)) \g_ram_rst_false.ram_memory_reg_i_110 (.I0(data_in_IBUF[0]), .I1(\g_ram_rst_false.ram_memory_reg_i_126_n_0 ), .O(\mr_tst_out[tst_control_twrstb] )); LUT6 #( .INIT(64'hFFBFFFFFFFFFFFFF)) \g_ram_rst_false.ram_memory_reg_i_126 (.I0(\g_bit[0].reg_value_r_reg[0]_7 ), .I1(\g_bit[0].reg_value_r_reg[0]_6 ), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[0].reg_value_r_reg[0]_5 ), .I4(swr_IBUF), .I5(sbe_IBUF[0]), .O(\g_ram_rst_false.ram_memory_reg_i_126_n_0 )); (* SOFT_HLUTNM = "soft_lutpair295" *) LUT2 #( .INIT(4'h8)) mr_ctr_pres_efd_q_i_1 (.I0(data_in_IBUF[5]), .I1(wr_en_10), .O(\mr_ctrl_out[ctr_pres_efd] )); (* SOFT_HLUTNM = "soft_lutpair295" *) LUT2 #( .INIT(4'h8)) mr_ctr_pres_enorm_q_i_1 (.I0(data_in_IBUF[4]), .I1(wr_en_10), .O(\mr_ctrl_out[ctr_pres_enorm] )); (* SOFT_HLUTNM = "soft_lutpair294" *) LUT2 #( .INIT(4'h8)) mr_ctr_pres_prx_q_i_1 (.I0(data_in_IBUF[3]), .I1(wr_en_10), .O(\mr_ctrl_out[ctr_pres_prx] )); (* SOFT_HLUTNM = "soft_lutpair294" *) LUT2 #( .INIT(4'h8)) mr_ctr_pres_ptx_q_i_1 (.I0(data_in_IBUF[2]), .I1(wr_en_10), .O(\mr_ctrl_out[ctr_pres_ptx] )); (* SOFT_HLUTNM = "soft_lutpair293" *) LUT2 #( .INIT(4'hB)) \r_data[1]_i_3 (.I0(\g_ram_rst_false.ram_memory_reg_i_126_n_0 ), .I1(data_in_IBUF[0]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_35 (\mr_ctrl_out[mode_tttm] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 ); output \mr_ctrl_out[mode_tttm] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_ctrl_out[mode_tttm] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[mode_tttm] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_36 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , abort_applied, \g_bit[0].reg_value_r_reg[0]_2 , abort_applied_3, \g_bit[0].reg_value_r_reg[0]_3 , \g_bit[2].reg_value_r_reg[2] , \g_bit[2].reg_value_r_reg[2]_0 , tx_command_txcr_valid, tx_command_txce_valid, tx_command_txcr_valid_4, tx_command_txce_valid_5, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_4 , \FSM_sequential_curr_state[0]_i_2__0 , txtb_allow_bb, txtb_hw_cmd_cs, \FSM_sequential_curr_state[0]_i_2__0_0 , \FSM_sequential_curr_state[0]_i_2__2 , fsm_wait_state_q_i_4, fsm_wait_state_q_i_4_0, fsm_wait_state_q_i_4_1, fsm_wait_state_q_i_4_2, \mr_tx_priority[2] , \mr_tx_priority[3] , txtb_available, \select_buf_index_reg_reg[1] , \mr_tx_priority[1] , \mr_tx_priority[0] , mr_tx_command_txcr_q, \FSM_sequential_curr_state[0]_i_4__2 , \FSM_sequential_curr_state[0]_i_4__2_0 , mr_tx_command_txce_q, mr_tx_command_txca_q, fsm_wait_state_q_i_5, fsm_wait_state_q_i_5_0); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output abort_applied; output \g_bit[0].reg_value_r_reg[0]_2 ; output abort_applied_3; output \g_bit[0].reg_value_r_reg[0]_3 ; output \g_bit[2].reg_value_r_reg[2] ; output \g_bit[2].reg_value_r_reg[2]_0 ; output tx_command_txcr_valid; output tx_command_txce_valid; output tx_command_txcr_valid_4; output tx_command_txce_valid_5; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_4 ; input \FSM_sequential_curr_state[0]_i_2__0 ; input [1:0]txtb_allow_bb; input [1:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state[0]_i_2__0_0 ; input \FSM_sequential_curr_state[0]_i_2__2 ; input fsm_wait_state_q_i_4; input fsm_wait_state_q_i_4_0; input fsm_wait_state_q_i_4_1; input fsm_wait_state_q_i_4_2; input [0:0]\mr_tx_priority[2] ; input [0:0]\mr_tx_priority[3] ; input [2:0]txtb_available; input \select_buf_index_reg_reg[1] ; input [0:0]\mr_tx_priority[1] ; input [0:0]\mr_tx_priority[0] ; input mr_tx_command_txcr_q; input \FSM_sequential_curr_state[0]_i_4__2 ; input \FSM_sequential_curr_state[0]_i_4__2_0 ; input mr_tx_command_txce_q; input mr_tx_command_txca_q; input fsm_wait_state_q_i_5; input fsm_wait_state_q_i_5_0; wire \FSM_sequential_curr_state[0]_i_2__0 ; wire \FSM_sequential_curr_state[0]_i_2__0_0 ; wire \FSM_sequential_curr_state[0]_i_2__2 ; wire \FSM_sequential_curr_state[0]_i_4__2 ; wire \FSM_sequential_curr_state[0]_i_4__2_0 ; wire abort_applied; wire abort_applied_3; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire fsm_wait_state_q_i_4; wire fsm_wait_state_q_i_4_0; wire fsm_wait_state_q_i_4_1; wire fsm_wait_state_q_i_4_2; wire fsm_wait_state_q_i_5; wire fsm_wait_state_q_i_5_0; wire fsm_wait_state_q_i_9_n_0; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[2].reg_value_r_reg[2] ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txcr_q; wire [0:0]\mr_tx_priority[0] ; wire [0:0]\mr_tx_priority[1] ; wire [0:0]\mr_tx_priority[2] ; wire [0:0]\mr_tx_priority[3] ; wire \select_buf_index_reg_reg[1] ; wire tx_command_txce_valid; wire tx_command_txce_valid_5; wire tx_command_txcr_valid; wire tx_command_txcr_valid_4; wire [1:0]txtb_allow_bb; wire [2:0]txtb_available; wire [1:0]txtb_hw_cmd_cs; wire wr_en; (* SOFT_HLUTNM = "soft_lutpair296" *) LUT4 #( .INIT(16'hAA80)) \FSM_sequential_curr_state[2]_i_10__2 (.I0(mr_tx_command_txcr_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(\FSM_sequential_curr_state[0]_i_4__2 ), .I3(\FSM_sequential_curr_state[0]_i_4__2_0 ), .O(tx_command_txcr_valid)); (* SOFT_HLUTNM = "soft_lutpair297" *) LUT4 #( .INIT(16'hAA80)) \FSM_sequential_curr_state[2]_i_10__3 (.I0(mr_tx_command_txcr_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(fsm_wait_state_q_i_5), .I3(fsm_wait_state_q_i_5_0), .O(tx_command_txcr_valid_4)); (* SOFT_HLUTNM = "soft_lutpair296" *) LUT4 #( .INIT(16'hAA80)) \FSM_sequential_curr_state[2]_i_6__2 (.I0(mr_tx_command_txca_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(\FSM_sequential_curr_state[0]_i_4__2 ), .I3(\FSM_sequential_curr_state[0]_i_4__2_0 ), .O(abort_applied_3)); (* SOFT_HLUTNM = "soft_lutpair297" *) LUT4 #( .INIT(16'hAA80)) \FSM_sequential_curr_state[2]_i_6__3 (.I0(mr_tx_command_txca_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(fsm_wait_state_q_i_5), .I3(fsm_wait_state_q_i_5_0), .O(abort_applied)); LUT6 #( .INIT(64'hFFFF8000FFFFFFFF)) \FSM_sequential_curr_state[2]_i_8 (.I0(\FSM_sequential_curr_state[0]_i_2__0 ), .I1(txtb_allow_bb[0]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(txtb_hw_cmd_cs[0]), .I4(abort_applied), .I5(\FSM_sequential_curr_state[0]_i_2__0_0 ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'hFFFF8000FFFFFFFF)) \FSM_sequential_curr_state[2]_i_8__1 (.I0(\FSM_sequential_curr_state[0]_i_2__0 ), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(txtb_allow_bb[1]), .I3(txtb_hw_cmd_cs[1]), .I4(abort_applied_3), .I5(\FSM_sequential_curr_state[0]_i_2__2 ), .O(\g_bit[0].reg_value_r_reg[0]_2 )); LUT4 #( .INIT(16'hAA80)) \FSM_sequential_curr_state[2]_i_9__2 (.I0(mr_tx_command_txce_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(\FSM_sequential_curr_state[0]_i_4__2 ), .I3(\FSM_sequential_curr_state[0]_i_4__2_0 ), .O(tx_command_txce_valid)); LUT4 #( .INIT(16'hAA80)) \FSM_sequential_curr_state[2]_i_9__3 (.I0(mr_tx_command_txce_q), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(fsm_wait_state_q_i_5), .I3(fsm_wait_state_q_i_5_0), .O(tx_command_txce_valid_5)); LUT6 #( .INIT(64'h00000000BABABAFB)) fsm_wait_state_q_i_7 (.I0(fsm_wait_state_q_i_9_n_0), .I1(fsm_wait_state_q_i_4), .I2(fsm_wait_state_q_i_4_0), .I3(fsm_wait_state_q_i_4_1), .I4(fsm_wait_state_q_i_4_2), .I5(\g_bit[2].reg_value_r_reg[2] ), .O(\g_bit[0].reg_value_r_reg[0]_3 )); LUT6 #( .INIT(64'h00000000FFFA0D00)) fsm_wait_state_q_i_9 (.I0(txtb_available[1]), .I1(txtb_available[2]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\mr_tx_priority[3] ), .I4(\mr_tx_priority[2] ), .I5(\g_bit[2].reg_value_r_reg[2]_0 ), .O(fsm_wait_state_q_i_9_n_0)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_4 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h515553FF000000FF)) \select_buf_index_reg[0]_i_5 (.I0(\mr_tx_priority[2] ), .I1(\mr_tx_priority[3] ), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(txtb_available[2]), .I4(txtb_available[1]), .I5(\g_bit[2].reg_value_r_reg[2]_0 ), .O(\g_bit[2].reg_value_r_reg[2] )); LUT6 #( .INIT(64'hFFFFFFF000002F00)) \select_buf_index_reg[1]_i_6 (.I0(\select_buf_index_reg_reg[1] ), .I1(abort_applied), .I2(txtb_available[0]), .I3(\mr_tx_priority[1] ), .I4(\g_bit[0].reg_value_r_reg[0]_0 ), .I5(\mr_tx_priority[0] ), .O(\g_bit[2].reg_value_r_reg[2]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_37 (\mr_ctrl_out[rx_settings_rtsop] , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , adress_IBUF, \g_bit[0].reg_value_r_reg[0]_2 ); output \mr_ctrl_out[rx_settings_rtsop] ; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input \g_bit[0].reg_value_r_reg[0]_1 ; input [3:0]adress_IBUF; input \g_bit[0].reg_value_r_reg[0]_2 ; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire wr_en; LUT6 #( .INIT(64'h0000000002000000)) \g_bit[0].reg_value_r[0]_i_1__10 (.I0(\g_bit[0].reg_value_r_reg[0]_1 ), .I1(adress_IBUF[3]), .I2(adress_IBUF[0]), .I3(adress_IBUF[2]), .I4(adress_IBUF[1]), .I5(\g_bit[0].reg_value_r_reg[0]_2 ), .O(wr_en)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[rx_settings_rtsop] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_38 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , wr_en, wr_en_0, wr_en_1, \g_bit[0].reg_value_r_reg[0]_3 , wr_en_2, wr_en_3, wr_en_4, swr, wr_en_5, \g_bit[0].reg_value_r_reg[0]_4 , \g_bit[0].reg_value_r_reg[0]_5 , bit_err_d0_out, wr_en_6, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_6 , reg_q_reg, adress_IBUF, reg_q_reg_0, \g_bit[3].reg_value_r_reg[3] , swr_IBUF, sbe_IBUF, \g_bit[0].reg_value_r_reg[0]_7 , \g_bit[2].reg_value_r_reg[2] , \g_bit[0].reg_value_r_reg[0]_8 , \g_bit[0].reg_value_r_reg[0]_9 , \g_bit[0].reg_value_r_reg[0]_10 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[3].reg_value_r_reg[3]_1 , mr_settings_ena_reg, current_state_reg, bit_err_enable, bit_err_q_reg, bit_err_q_reg_0, bit_err_d2, crc_data_tx_wbs, bit_err_q_reg_1, rx_data_wbs); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[0].reg_value_r_reg[0]_2 ; output wr_en; output wr_en_0; output wr_en_1; output \g_bit[0].reg_value_r_reg[0]_3 ; output wr_en_2; output wr_en_3; output wr_en_4; output swr; output wr_en_5; output [0:0]\g_bit[0].reg_value_r_reg[0]_4 ; output \g_bit[0].reg_value_r_reg[0]_5 ; output bit_err_d0_out; input wr_en_6; input [1:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_6 ; input reg_q_reg; input [5:0]adress_IBUF; input reg_q_reg_0; input \g_bit[3].reg_value_r_reg[3] ; input swr_IBUF; input [1:0]sbe_IBUF; input \g_bit[0].reg_value_r_reg[0]_7 ; input \g_bit[2].reg_value_r_reg[2] ; input \g_bit[0].reg_value_r_reg[0]_8 ; input \g_bit[0].reg_value_r_reg[0]_9 ; input \g_bit[0].reg_value_r_reg[0]_10 ; input \g_bit[3].reg_value_r_reg[3]_0 ; input \g_bit[3].reg_value_r_reg[3]_1 ; input mr_settings_ena_reg; input [0:0]current_state_reg; input bit_err_enable; input bit_err_q_reg; input bit_err_q_reg_0; input bit_err_d2; input crc_data_tx_wbs; input bit_err_q_reg_1; input rx_data_wbs; wire [5:0]adress_IBUF; wire bit_err_d0_out; wire bit_err_d2; wire bit_err_enable; wire bit_err_q_reg; wire bit_err_q_reg_0; wire bit_err_q_reg_1; wire clk_sys_IBUF_BUFG; wire crc_data_tx_wbs; wire [0:0]current_state_reg; wire [1:0]data_in_IBUF; wire \g_bit[0].reg_value_r[0]_i_2__3_n_0 ; wire \g_bit[0].reg_value_r[0]_i_2_n_0 ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_10 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[0].reg_value_r_reg[0]_5 ; wire \g_bit[0].reg_value_r_reg[0]_6 ; wire \g_bit[0].reg_value_r_reg[0]_7 ; wire \g_bit[0].reg_value_r_reg[0]_8 ; wire \g_bit[0].reg_value_r_reg[0]_9 ; wire \g_bit[2].reg_value_r_reg[2] ; wire \g_bit[3].reg_value_r_reg[3] ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \i_bm_top/i_bm_bit_err_detector/bit_err_d3__0 ; wire mr_settings_ena_reg; wire reg_q_reg; wire reg_q_reg_0; wire rx_data_wbs; wire [1:0]sbe_IBUF; wire swr; wire swr_IBUF; wire wr_en; wire wr_en_0; wire wr_en_1; wire wr_en_2; wire wr_en_3; wire wr_en_4; wire wr_en_5; wire wr_en_6; LUT6 #( .INIT(64'hA8A0000008000000)) bit_err_q_i_1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(bit_err_enable), .I2(bit_err_q_reg), .I3(\i_bm_top/i_bm_bit_err_detector/bit_err_d3__0 ), .I4(bit_err_q_reg_0), .I5(bit_err_d2), .O(bit_err_d0_out)); (* SOFT_HLUTNM = "soft_lutpair300" *) LUT4 #( .INIT(16'h04FB)) bit_err_q_i_3 (.I0(crc_data_tx_wbs), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(bit_err_q_reg_1), .I3(rx_data_wbs), .O(\i_bm_top/i_bm_bit_err_detector/bit_err_d3__0 )); (* SOFT_HLUTNM = "soft_lutpair301" *) LUT2 #( .INIT(4'h1)) \g_bit[0].reg_value_r[0]_i_1__11 (.I0(reg_q_reg), .I1(\g_bit[0].reg_value_r[0]_i_2_n_0 ), .O(\g_bit[0].reg_value_r_reg[0]_2 )); (* SOFT_HLUTNM = "soft_lutpair298" *) LUT4 #( .INIT(16'h0040)) \g_bit[0].reg_value_r[0]_i_1__12 (.I0(\g_bit[3].reg_value_r_reg[3] ), .I1(swr_IBUF), .I2(sbe_IBUF[1]), .I3(\g_bit[0].reg_value_r[0]_i_2_n_0 ), .O(wr_en)); (* SOFT_HLUTNM = "soft_lutpair302" *) LUT2 #( .INIT(4'h2)) \g_bit[0].reg_value_r[0]_i_1__13 (.I0(\g_bit[0].reg_value_r_reg[0]_7 ), .I1(\g_bit[0].reg_value_r[0]_i_2_n_0 ), .O(wr_en_0)); (* SOFT_HLUTNM = "soft_lutpair299" *) LUT4 #( .INIT(16'h0040)) \g_bit[0].reg_value_r[0]_i_1__14 (.I0(\g_bit[3].reg_value_r_reg[3] ), .I1(swr_IBUF), .I2(sbe_IBUF[0]), .I3(\g_bit[0].reg_value_r[0]_i_2_n_0 ), .O(wr_en_1)); (* SOFT_HLUTNM = "soft_lutpair301" *) LUT2 #( .INIT(4'h1)) \g_bit[0].reg_value_r[0]_i_1__16 (.I0(reg_q_reg), .I1(\g_bit[0].reg_value_r[0]_i_2__3_n_0 ), .O(\g_bit[0].reg_value_r_reg[0]_3 )); (* SOFT_HLUTNM = "soft_lutpair302" *) LUT2 #( .INIT(4'h2)) \g_bit[0].reg_value_r[0]_i_1__23 (.I0(\g_bit[0].reg_value_r_reg[0]_7 ), .I1(\g_bit[0].reg_value_r[0]_i_2__3_n_0 ), .O(wr_en_2)); LUT5 #( .INIT(32'h00080000)) \g_bit[0].reg_value_r[0]_i_1__27 (.I0(\g_bit[0].reg_value_r_reg[0]_8 ), .I1(adress_IBUF[5]), .I2(adress_IBUF[4]), .I3(\g_bit[0].reg_value_r_reg[0]_0 ), .I4(\g_bit[0].reg_value_r_reg[0]_9 ), .O(wr_en_3)); (* SOFT_HLUTNM = "soft_lutpair299" *) LUT4 #( .INIT(16'h0040)) \g_bit[0].reg_value_r[0]_i_1__28 (.I0(\g_bit[3].reg_value_r_reg[3] ), .I1(swr_IBUF), .I2(sbe_IBUF[0]), .I3(\g_bit[0].reg_value_r[0]_i_2__3_n_0 ), .O(wr_en_4)); (* SOFT_HLUTNM = "soft_lutpair298" *) LUT4 #( .INIT(16'h0040)) \g_bit[0].reg_value_r[0]_i_1__29 (.I0(\g_bit[3].reg_value_r_reg[3] ), .I1(swr_IBUF), .I2(sbe_IBUF[1]), .I3(\g_bit[0].reg_value_r[0]_i_2__3_n_0 ), .O(swr)); LUT6 #( .INIT(64'h0000004000000000)) \g_bit[0].reg_value_r[0]_i_1__30 (.I0(\g_bit[0].reg_value_r_reg[0]_10 ), .I1(sbe_IBUF[1]), .I2(adress_IBUF[5]), .I3(adress_IBUF[4]), .I4(\g_bit[0].reg_value_r_reg[0]_0 ), .I5(\g_bit[0].reg_value_r_reg[0]_9 ), .O(wr_en_5)); LUT6 #( .INIT(64'hFFFFFEFFFFFFFFFF)) \g_bit[0].reg_value_r[0]_i_2 (.I0(adress_IBUF[2]), .I1(adress_IBUF[4]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[2].reg_value_r_reg[2] ), .I4(adress_IBUF[5]), .I5(adress_IBUF[3]), .O(\g_bit[0].reg_value_r[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \g_bit[0].reg_value_r[0]_i_2__3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\g_bit[3].reg_value_r_reg[3]_1 ), .I2(\g_bit[3].reg_value_r_reg[3] ), .I3(adress_IBUF[2]), .I4(adress_IBUF[4]), .I5(\g_bit[0].reg_value_r_reg[0]_0 ), .O(\g_bit[0].reg_value_r[0]_i_2__3_n_0 )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[0].reg_value_r_reg[0]_6 ), .D(data_in_IBUF[1]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAA2AA)) reg_q_i_1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(reg_q_reg), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(reg_q_reg_0), .O(\g_bit[0].reg_value_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair300" *) LUT2 #( .INIT(4'h7)) \test_probe[tx_trigger]_INST_0_i_2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(current_state_reg), .O(\g_bit[0].reg_value_r_reg[0]_5 )); LUT2 #( .INIT(4'h2)) \tseg1_nbt[7]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(mr_settings_ena_reg), .O(\g_bit[0].reg_value_r_reg[0]_4 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_39 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_4 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , adress_IBUF, \g_bit[0].reg_value_r_reg[0]_3 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input \g_bit[0].reg_value_r_reg[0]_2 ; input [2:0]adress_IBUF; input \g_bit[0].reg_value_r_reg[0]_3 ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire wr_en; LUT5 #( .INIT(32'h02000000)) \g_bit[0].reg_value_r[0]_i_1__25 (.I0(\g_bit[0].reg_value_r_reg[0]_2 ), .I1(adress_IBUF[2]), .I2(\g_bit[0].reg_value_r_reg[0]_3 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .O(wr_en)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_40 (\mr_ctrl_out[settings_ilbp] , D, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , sbe_IBUF, \r_data_reg[21] , adress_IBUF, \r_data_reg[21]_0 , \r_data_reg[21]_1 , \r_data_reg[21]_2 , \r_data_reg[21]_3 , \r_data_reg[21]_4 , \r_data_reg[21]_5 ); output \mr_ctrl_out[settings_ilbp] ; output [0:0]D; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [0:0]sbe_IBUF; input \r_data_reg[21] ; input [1:0]adress_IBUF; input \r_data_reg[21]_0 ; input \r_data_reg[21]_1 ; input \r_data_reg[21]_2 ; input \r_data_reg[21]_3 ; input [0:0]\r_data_reg[21]_4 ; input \r_data_reg[21]_5 ; wire [0:0]D; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_ctrl_out[settings_ilbp] ; wire \r_data[21]_i_2_n_0 ; wire \r_data_reg[21] ; wire \r_data_reg[21]_0 ; wire \r_data_reg[21]_1 ; wire \r_data_reg[21]_2 ; wire \r_data_reg[21]_3 ; wire [0:0]\r_data_reg[21]_4 ; wire \r_data_reg[21]_5 ; wire [0:0]sbe_IBUF; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[settings_ilbp] )); LUT6 #( .INIT(64'h008A008A008AAA8A)) \r_data[21]_i_1 (.I0(sbe_IBUF), .I1(\r_data[21]_i_2_n_0 ), .I2(\r_data_reg[21] ), .I3(adress_IBUF[1]), .I4(\r_data_reg[21]_0 ), .I5(\r_data_reg[21]_1 ), .O(D)); LUT6 #( .INIT(64'hF4F4F4F4FFF4F4F4)) \r_data[21]_i_2 (.I0(\r_data_reg[21]_2 ), .I1(\mr_ctrl_out[settings_ilbp] ), .I2(\r_data_reg[21]_3 ), .I3(\r_data_reg[21]_4 ), .I4(adress_IBUF[0]), .I5(\r_data_reg[21]_5 ), .O(\r_data[21]_i_2_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_41 (\mr_ctrl_out[settings_nisofd] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 ); output \mr_ctrl_out[settings_nisofd] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_ctrl_out[settings_nisofd] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[settings_nisofd] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_42 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_43 (\mr_ctrl_out[settings_pex] , wr_en, \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , swr_IBUF, sbe_IBUF, adress_IBUF, \g_bit[0].reg_value_r_reg[0]_4 , pc_rx_data_nbs, \err_capt_err_type_q[2]_i_13 , \err_capt_err_type_q[2]_i_13_0 ); output \mr_ctrl_out[settings_pex] ; output wr_en; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_2 ; input \g_bit[0].reg_value_r_reg[0]_3 ; input swr_IBUF; input [0:0]sbe_IBUF; input [1:0]adress_IBUF; input \g_bit[0].reg_value_r_reg[0]_4 ; input pc_rx_data_nbs; input \err_capt_err_type_q[2]_i_13 ; input [0:0]\err_capt_err_type_q[2]_i_13_0 ; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \err_capt_err_type_q[2]_i_13 ; wire [0:0]\err_capt_err_type_q[2]_i_13_0 ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \mr_ctrl_out[settings_pex] ; wire pc_rx_data_nbs; wire [0:0]sbe_IBUF; wire swr_IBUF; wire wr_en; (* SOFT_HLUTNM = "soft_lutpair303" *) LUT3 #( .INIT(8'h08)) destuff_enable_i_5 (.I0(\mr_ctrl_out[settings_pex] ), .I1(pc_rx_data_nbs), .I2(\err_capt_err_type_q[2]_i_13 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair303" *) LUT4 #( .INIT(16'h1000)) \err_capt_err_type_q[2]_i_16 (.I0(\mr_ctrl_out[settings_pex] ), .I1(\err_capt_err_type_q[2]_i_13 ), .I2(\err_capt_err_type_q[2]_i_13_0 ), .I3(pc_rx_data_nbs), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'h0000000000004000)) \g_bit[0].reg_value_r[0]_i_1__2 (.I0(\g_bit[0].reg_value_r_reg[0]_3 ), .I1(swr_IBUF), .I2(sbe_IBUF), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\g_bit[0].reg_value_r_reg[0]_4 ), .O(wr_en)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_2 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[settings_pex] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_44 (\mr_ctrl_out[settings_rtrle] , \g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , adress_IBUF); output \mr_ctrl_out[settings_rtrle] ; output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input [4:0]adress_IBUF; wire [4:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \mr_ctrl_out[settings_rtrle] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[settings_rtrle] )); LUT6 #( .INIT(64'h0000010000000101)) \r_data[16]_i_7 (.I0(adress_IBUF[2]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(\mr_ctrl_out[settings_rtrle] ), .I4(adress_IBUF[1]), .I5(adress_IBUF[0]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_47 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw_48 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_1 ), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2_10 (D, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , sbe_IBUF, adress_IBUF, \r_data_reg[3] , \r_data_reg[3]_0 , \r_data_reg[3]_1 , \r_data_reg[3]_2 ); output [0:0]D; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [0:0]sbe_IBUF; input [2:0]adress_IBUF; input \r_data_reg[3] ; input \r_data_reg[3]_0 ; input \r_data_reg[3]_1 ; input \r_data_reg[3]_2 ; wire [0:0]D; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg_n_0_[0] ; wire \r_data[3]_i_2_n_0 ; wire \r_data_reg[3] ; wire \r_data_reg[3]_0 ; wire \r_data_reg[3]_1 ; wire \r_data_reg[3]_2 ; wire [0:0]sbe_IBUF; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_0 ), .Q(\g_bit[0].reg_value_r_reg_n_0_[0] )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[3]_i_1 (.I0(sbe_IBUF), .I1(\r_data[3]_i_2_n_0 ), .I2(adress_IBUF[2]), .I3(\r_data_reg[3] ), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(D)); LUT6 #( .INIT(64'hD0DDFFFFD0DD0000)) \r_data[3]_i_2 (.I0(\g_bit[0].reg_value_r_reg_n_0_[0] ), .I1(\r_data_reg[3]_0 ), .I2(\r_data_reg[3]_1 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\r_data_reg[3]_2 ), .O(\r_data[3]_i_2_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2_11 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[0].reg_value_r_reg[0]_2 , adress_IBUF, \g_bit[0].reg_value_r_reg[0]_3 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input \g_bit[0].reg_value_r_reg[0]_2 ; input [3:0]adress_IBUF; input \g_bit[0].reg_value_r_reg[0]_3 ; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire wr_en; LUT6 #( .INIT(64'h0001000000000000)) \g_bit[0].reg_value_r[0]_i_1__20 (.I0(\g_bit[0].reg_value_r_reg[0]_2 ), .I1(adress_IBUF[3]), .I2(adress_IBUF[1]), .I3(\g_bit[0].reg_value_r_reg[0]_3 ), .I4(adress_IBUF[0]), .I5(adress_IBUF[2]), .O(wr_en)); FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_1 ), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2_12 (\g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , adress_IBUF); output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input [2:0]adress_IBUF; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg_n_0_[0] ; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_1 ), .Q(\g_bit[0].reg_value_r_reg_n_0_[0] )); LUT4 #( .INIT(16'h7FFF)) \r_data[1]_i_5 (.I0(\g_bit[0].reg_value_r_reg_n_0_[0] ), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(adress_IBUF[2]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2_29 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_2 , tran_frame_type); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_2 ; input tran_frame_type; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire tran_frame_type; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_2 ), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); LUT2 #( .INIT(4'h7)) reg_q_i_2__4 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(tran_frame_type), .O(\g_bit[0].reg_value_r_reg[0]_1 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2_31 (\mr_ctrl_out[mode_rxbam] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 ); output \mr_ctrl_out[mode_rxbam] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_ctrl_out[mode_rxbam] ; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_0 ), .Q(\mr_ctrl_out[mode_rxbam] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized2_45 (\g_bit[0].reg_value_r_reg[0]_0 , \FSM_sequential_curr_state_reg[0] , \FSM_sequential_curr_state_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , \FSM_sequential_curr_state_reg[2] , \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[2]_1 , txtb_allow_bb); output \g_bit[0].reg_value_r_reg[0]_0 ; output \FSM_sequential_curr_state_reg[0] ; output \FSM_sequential_curr_state_reg[0]_0 ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input [1:0]\FSM_sequential_curr_state_reg[2] ; input \FSM_sequential_curr_state_reg[2]_0 ; input \FSM_sequential_curr_state_reg[2]_1 ; input [1:0]txtb_allow_bb; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire [1:0]\FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire [1:0]txtb_allow_bb; wire wr_en; LUT6 #( .INIT(64'hFFFFFF1000000000)) \FSM_sequential_curr_state[2]_i_4 (.I0(\FSM_sequential_curr_state_reg[2] [0]), .I1(\FSM_sequential_curr_state_reg[2] [1]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_1 ), .I5(txtb_allow_bb[0]), .O(\FSM_sequential_curr_state_reg[0] )); LUT6 #( .INIT(64'hFFFFFF1000000000)) \FSM_sequential_curr_state[2]_i_4__1 (.I0(\FSM_sequential_curr_state_reg[2] [0]), .I1(\FSM_sequential_curr_state_reg[2] [1]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_1 ), .I5(txtb_allow_bb[1]), .O(\FSM_sequential_curr_state_reg[0]_0 )); FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_1 ), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized4 (wr_en, \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \txtb_hw_cmd_q[err] , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[3].reg_value_r_reg[3]_1 , \g_bit[3].reg_value_r_reg[3]_2 , \g_bit[3].reg_value_r_reg[3]_3 , adress_IBUF, \r_data[17]_i_2 , \r_data[17]_i_2_0 , \r_data[17]_i_2_1 , \txtb_hw_cmd_q_reg[err] , \mr_ctrl_out[settings_rtrle] , \txtb_hw_cmd_q_reg[err]_0 ); output wr_en; output [1:0]\g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \txtb_hw_cmd_q[err] ; output \g_bit[0].reg_value_r_reg[0]_1 ; input [3:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[3].reg_value_r_reg[3]_1 ; input \g_bit[3].reg_value_r_reg[3]_2 ; input \g_bit[3].reg_value_r_reg[3]_3 ; input [5:0]adress_IBUF; input \r_data[17]_i_2 ; input \r_data[17]_i_2_0 ; input [0:0]\r_data[17]_i_2_1 ; input \txtb_hw_cmd_q_reg[err] ; input \mr_ctrl_out[settings_rtrle] ; input [3:0]\txtb_hw_cmd_q_reg[err]_0 ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [3:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire [1:0]\g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[3].reg_value_r_reg[3]_2 ; wire \g_bit[3].reg_value_r_reg[3]_3 ; wire \mr_ctrl_out[settings_rtrle] ; wire [1:0]\mr_ctrl_out[settings_rtrth] ; wire \r_data[17]_i_2 ; wire \r_data[17]_i_2_0 ; wire [0:0]\r_data[17]_i_2_1 ; wire \txtb_hw_cmd_q[err] ; wire \txtb_hw_cmd_q[err]_i_4_n_0 ; wire \txtb_hw_cmd_q_reg[err] ; wire [3:0]\txtb_hw_cmd_q_reg[err]_0 ; wire wr_en; LUT6 #( .INIT(64'h0000000000000008)) \g_bit[0].reg_value_r[0]_i_1__1 (.I0(\g_bit[3].reg_value_r_reg[3]_2 ), .I1(\g_bit[3].reg_value_r_reg[3]_3 ), .I2(adress_IBUF[5]), .I3(adress_IBUF[2]), .I4(adress_IBUF[4]), .I5(adress_IBUF[3]), .O(wr_en)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[settings_rtrth] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[settings_rtrth] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[2]), .Q(\g_bit[3].reg_value_r_reg[3]_0 [0])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 [1])); LUT6 #( .INIT(64'h7300FFFF73007300)) \r_data[17]_i_5 (.I0(adress_IBUF[1]), .I1(adress_IBUF[0]), .I2(\mr_ctrl_out[settings_rtrth] [0]), .I3(\r_data[17]_i_2 ), .I4(\r_data[17]_i_2_0 ), .I5(\r_data[17]_i_2_1 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h0000010000000101)) \r_data[18]_i_9 (.I0(adress_IBUF[2]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(\mr_ctrl_out[settings_rtrth] [1]), .I4(adress_IBUF[1]), .I5(adress_IBUF[0]), .O(\g_bit[1].reg_value_r_reg[1]_0 )); LUT2 #( .INIT(4'h1)) \txtb_hw_cmd_q[err]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0]_1 ), .I1(\txtb_hw_cmd_q_reg[err] ), .O(\txtb_hw_cmd_q[err] )); LUT4 #( .INIT(16'h2002)) \txtb_hw_cmd_q[err]_i_2 (.I0(\mr_ctrl_out[settings_rtrle] ), .I1(\txtb_hw_cmd_q[err]_i_4_n_0 ), .I2(\txtb_hw_cmd_q_reg[err]_0 [3]), .I3(\g_bit[3].reg_value_r_reg[3]_0 [1]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \txtb_hw_cmd_q[err]_i_4 (.I0(\mr_ctrl_out[settings_rtrth] [0]), .I1(\txtb_hw_cmd_q_reg[err]_0 [0]), .I2(\txtb_hw_cmd_q_reg[err]_0 [1]), .I3(\mr_ctrl_out[settings_rtrth] [1]), .I4(\txtb_hw_cmd_q_reg[err]_0 [2]), .I5(\g_bit[3].reg_value_r_reg[3]_0 [0]), .O(\txtb_hw_cmd_q[err]_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized6 (\mr_tx_priority[0] , wr_en, \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_1 , \g_bit[2].reg_value_r_reg[2]_2 , \g_bit[2].reg_value_r_reg[2]_3 , \g_bit[2].reg_value_r_reg[2]_4 , adress_IBUF, \select_buf_index_reg_reg[0] , \mr_tx_priority[1] , txtb_available); output [2:0]\mr_tx_priority[0] ; output wr_en; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[1].reg_value_r_reg[1]_0 ; input \g_bit[2].reg_value_r_reg[2]_1 ; input \g_bit[2].reg_value_r_reg[2]_2 ; input \g_bit[2].reg_value_r_reg[2]_3 ; input \g_bit[2].reg_value_r_reg[2]_4 ; input [1:0]adress_IBUF; input \select_buf_index_reg_reg[0] ; input [2:0]\mr_tx_priority[1] ; input [1:0]txtb_available; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire \g_bit[2].reg_value_r_reg[2]_2 ; wire \g_bit[2].reg_value_r_reg[2]_3 ; wire \g_bit[2].reg_value_r_reg[2]_4 ; wire [2:0]\mr_tx_priority[0] ; wire [2:0]\mr_tx_priority[1] ; wire \select_buf_index_reg[0]_i_8_n_0 ; wire \select_buf_index_reg_reg[0] ; wire [1:0]txtb_available; wire wr_en; LUT6 #( .INIT(64'h0001000000000000)) \g_bit[0].reg_value_r[0]_i_1__19 (.I0(\g_bit[2].reg_value_r_reg[2]_1 ), .I1(\g_bit[2].reg_value_r_reg[2]_2 ), .I2(\g_bit[2].reg_value_r_reg[2]_3 ), .I3(\g_bit[2].reg_value_r_reg[2]_4 ), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(wr_en)); FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[0]), .PRE(\g_bit[1].reg_value_r_reg[1]_0 ), .Q(\mr_tx_priority[0] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[1]), .Q(\mr_tx_priority[0] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[2]), .Q(\mr_tx_priority[0] [2])); LUT6 #( .INIT(64'h57510000FFFFFFFF)) \select_buf_index_reg[0]_i_6 (.I0(\select_buf_index_reg[0]_i_8_n_0 ), .I1(\mr_tx_priority[0] [2]), .I2(\select_buf_index_reg_reg[0] ), .I3(\mr_tx_priority[1] [2]), .I4(txtb_available[1]), .I5(txtb_available[0]), .O(\g_bit[2].reg_value_r_reg[2]_0 )); LUT5 #( .INIT(32'hFBFFF0FB)) \select_buf_index_reg[0]_i_8 (.I0(\mr_tx_priority[0] [0]), .I1(\mr_tx_priority[1] [0]), .I2(\select_buf_index_reg_reg[0] ), .I3(\mr_tx_priority[1] [1]), .I4(\mr_tx_priority[0] [1]), .O(\select_buf_index_reg[0]_i_8_n_0 )); LUT4 #( .INIT(16'hB8AA)) \select_buf_index_reg[1]_i_10 (.I0(\mr_tx_priority[0] [0]), .I1(\select_buf_index_reg_reg[0] ), .I2(\mr_tx_priority[1] [0]), .I3(\g_bit[2].reg_value_r_reg[2]_0 ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT4 #( .INIT(16'hEF40)) \select_buf_index_reg[1]_i_12 (.I0(\select_buf_index_reg_reg[0] ), .I1(\mr_tx_priority[1] [1]), .I2(\g_bit[2].reg_value_r_reg[2]_0 ), .I3(\mr_tx_priority[0] [1]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized8 (\mr_tx_priority[2] , wr_en, \txtb_hw_cmd_q_reg[lock] , \select_buf_index_reg_reg[0] , \FSM_sequential_curr_state_reg[0] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \select_buf_index_reg_reg[0]_0 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[2].reg_value_r_reg[2]_1 , \g_bit[2].reg_value_r_reg[2]_2 , \g_bit[2].reg_value_r_reg[2]_3 , adress_IBUF, \txtb_hw_cmd[lock] , tran_frame_valid_com_reg, fsm_wait_state_q, \select_buf_index_reg_reg[0]_1 , fsm_wait_state_q_reg, \select_buf_index_reg_reg[1] , fsm_wait_state_q_reg_0, txtb_available, \select_buf_index_reg_reg[0]_2 , \select_buf_index_reg_reg[1]_0 , \select_buf_index_reg_reg[1]_1 , \select_buf_index_reg_reg[1]_2 , \select_buf_index_reg_reg[1]_3 , \select_buf_index_reg_reg[1]_4 , \mr_tx_priority[3] ); output [2:0]\mr_tx_priority[2] ; output wr_en; output \txtb_hw_cmd_q_reg[lock] ; output \select_buf_index_reg_reg[0] ; output [1:0]\FSM_sequential_curr_state_reg[0] ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \select_buf_index_reg_reg[0]_0 ; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[1].reg_value_r_reg[1]_0 ; input \g_bit[2].reg_value_r_reg[2]_0 ; input \g_bit[2].reg_value_r_reg[2]_1 ; input \g_bit[2].reg_value_r_reg[2]_2 ; input \g_bit[2].reg_value_r_reg[2]_3 ; input [1:0]adress_IBUF; input \txtb_hw_cmd[lock] ; input tran_frame_valid_com_reg; input fsm_wait_state_q; input \select_buf_index_reg_reg[0]_1 ; input [1:0]fsm_wait_state_q_reg; input \select_buf_index_reg_reg[1] ; input fsm_wait_state_q_reg_0; input [3:0]txtb_available; input \select_buf_index_reg_reg[0]_2 ; input \select_buf_index_reg_reg[1]_0 ; input \select_buf_index_reg_reg[1]_1 ; input \select_buf_index_reg_reg[1]_2 ; input \select_buf_index_reg_reg[1]_3 ; input \select_buf_index_reg_reg[1]_4 ; input [1:0]\mr_tx_priority[3] ; wire [1:0]\FSM_sequential_curr_state_reg[0] ; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire fsm_wait_state_q; wire [1:0]fsm_wait_state_q_reg; wire fsm_wait_state_q_reg_0; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire \g_bit[2].reg_value_r_reg[2]_2 ; wire \g_bit[2].reg_value_r_reg[2]_3 ; wire [2:0]\mr_tx_priority[2] ; wire [1:0]\mr_tx_priority[3] ; wire \select_buf_index_reg[0]_i_2_n_0 ; wire \select_buf_index_reg[0]_i_7_n_0 ; wire \select_buf_index_reg[1]_i_5_n_0 ; wire \select_buf_index_reg[1]_i_7_n_0 ; wire \select_buf_index_reg_reg[0] ; wire \select_buf_index_reg_reg[0]_0 ; wire \select_buf_index_reg_reg[0]_1 ; wire \select_buf_index_reg_reg[0]_2 ; wire \select_buf_index_reg_reg[1] ; wire \select_buf_index_reg_reg[1]_0 ; wire \select_buf_index_reg_reg[1]_1 ; wire \select_buf_index_reg_reg[1]_2 ; wire \select_buf_index_reg_reg[1]_3 ; wire \select_buf_index_reg_reg[1]_4 ; wire tran_frame_valid_com_reg; wire [3:0]txtb_available; wire \txtb_hw_cmd[lock] ; wire \txtb_hw_cmd_q_reg[lock] ; wire wr_en; (* SOFT_HLUTNM = "soft_lutpair288" *) LUT2 #( .INIT(4'h1)) \FSM_sequential_curr_state[2]_i_7__3 (.I0(\select_buf_index_reg_reg[0] ), .I1(tran_frame_valid_com_reg), .O(\select_buf_index_reg_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair288" *) LUT4 #( .INIT(16'hFFFE)) \curr_txtb_index_i[1]_i_2 (.I0(\select_buf_index_reg_reg[0] ), .I1(\txtb_hw_cmd[lock] ), .I2(tran_frame_valid_com_reg), .I3(fsm_wait_state_q), .O(\txtb_hw_cmd_q_reg[lock] )); LUT6 #( .INIT(64'h5A5A5AFFFFFFFF3C)) fsm_wait_state_q_i_4 (.I0(\select_buf_index_reg[0]_i_2_n_0 ), .I1(\select_buf_index_reg_reg[0]_1 ), .I2(fsm_wait_state_q_reg[0]), .I3(\select_buf_index_reg_reg[1] ), .I4(fsm_wait_state_q_reg_0), .I5(fsm_wait_state_q_reg[1]), .O(\select_buf_index_reg_reg[0] )); LUT6 #( .INIT(64'h0002000000000000)) \g_bit[0].reg_value_r[0]_i_1__24 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_bit[2].reg_value_r_reg[2]_1 ), .I2(\g_bit[2].reg_value_r_reg[2]_2 ), .I3(\g_bit[2].reg_value_r_reg[2]_3 ), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(wr_en)); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[0]), .Q(\mr_tx_priority[2] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[1]), .Q(\mr_tx_priority[2] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[2]), .Q(\mr_tx_priority[2] [2])); LUT6 #( .INIT(64'hFEAAFEFE02AA0202)) \select_buf_index_reg[0]_i_1 (.I0(\select_buf_index_reg[0]_i_2_n_0 ), .I1(txtb_available[0]), .I2(txtb_available[1]), .I3(\select_buf_index_reg_reg[0]_2 ), .I4(\select_buf_index_reg[1]_i_7_n_0 ), .I5(\select_buf_index_reg_reg[0]_1 ), .O(\FSM_sequential_curr_state_reg[0] [0])); LUT6 #( .INIT(64'hAAA20200FFFFFFFF)) \select_buf_index_reg[0]_i_2 (.I0(txtb_available[3]), .I1(\mr_tx_priority[2] [2]), .I2(\select_buf_index_reg_reg[1]_4 ), .I3(\select_buf_index_reg_reg[1]_3 ), .I4(\select_buf_index_reg[0]_i_7_n_0 ), .I5(txtb_available[2]), .O(\select_buf_index_reg[0]_i_2_n_0 )); LUT5 #( .INIT(32'h040F0004)) \select_buf_index_reg[0]_i_7 (.I0(\mr_tx_priority[2] [0]), .I1(\mr_tx_priority[3] [0]), .I2(\select_buf_index_reg_reg[1]_4 ), .I3(\mr_tx_priority[2] [1]), .I4(\mr_tx_priority[3] [1]), .O(\select_buf_index_reg[0]_i_7_n_0 )); LUT6 #( .INIT(64'hFEAAFEFEAAAAAAAA)) \select_buf_index_reg[1]_i_1 (.I0(\select_buf_index_reg_reg[1] ), .I1(txtb_available[2]), .I2(txtb_available[3]), .I3(\select_buf_index_reg[1]_i_5_n_0 ), .I4(\select_buf_index_reg_reg[1]_0 ), .I5(\select_buf_index_reg[1]_i_7_n_0 ), .O(\FSM_sequential_curr_state_reg[0] [1])); LUT4 #( .INIT(16'hEF40)) \select_buf_index_reg[1]_i_11 (.I0(\select_buf_index_reg_reg[1]_4 ), .I1(\mr_tx_priority[3] [1]), .I2(\select_buf_index_reg[0]_i_2_n_0 ), .I3(\mr_tx_priority[2] [1]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT5 #( .INIT(32'hAEAAACAC)) \select_buf_index_reg[1]_i_5 (.I0(\mr_tx_priority[2] [2]), .I1(\select_buf_index_reg_reg[1]_3 ), .I2(\select_buf_index_reg_reg[1]_4 ), .I3(txtb_available[3]), .I4(txtb_available[2]), .O(\select_buf_index_reg[1]_i_5_n_0 )); LUT6 #( .INIT(64'h10F110F1FFFF10F1)) \select_buf_index_reg[1]_i_7 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\select_buf_index_reg_reg[1]_1 ), .I2(\g_bit[0].reg_value_r_reg[0]_1 ), .I3(\select_buf_index_reg_reg[1]_2 ), .I4(\select_buf_index_reg[1]_i_5_n_0 ), .I5(\select_buf_index_reg_reg[1]_0 ), .O(\select_buf_index_reg[1]_i_7_n_0 )); LUT4 #( .INIT(16'h4755)) \select_buf_index_reg[1]_i_9 (.I0(\mr_tx_priority[2] [0]), .I1(\select_buf_index_reg_reg[1]_4 ), .I2(\mr_tx_priority[3] [0]), .I3(\select_buf_index_reg[0]_i_2_n_0 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized8_49 (\mr_tx_priority[1] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[2].reg_value_r_reg[2]_0 ); output [2:0]\mr_tx_priority[1] ; input wr_en; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[2].reg_value_r_reg[2]_0 ; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire [2:0]\mr_tx_priority[1] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[0]), .Q(\mr_tx_priority[1] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[1]), .Q(\mr_tx_priority[1] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[2]), .Q(\mr_tx_priority[1] [2])); endmodule (* ORIG_REF_NAME = "memory_reg_rw" *) module memory_reg_rw__parameterized8_5 (\mr_tx_priority[3] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[2].reg_value_r_reg[2]_0 ); output [2:0]\mr_tx_priority[3] ; input wr_en; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[2].reg_value_r_reg[2]_0 ; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire [2:0]\mr_tx_priority[3] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[0]), .Q(\mr_tx_priority[3] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[1]), .Q(\mr_tx_priority[3] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[2]), .Q(\mr_tx_priority[3] [2])); endmodule module memory_reg_rw_lock (mr_btr_prop, \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[6].reg_value_r_reg[6]_0 , adress_IBUF, \mr_ctrl_out[btr_fd_prop_fd] , \r_data[4]_i_4 , \r_data[2]_i_3__0 , \r_data[1]_i_6 , \r_data[5]_i_6 , \r_data[3]_i_10 , \r_data[0]_i_6 ); output [6:0]mr_btr_prop; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[0].reg_value_r_reg[0]_0 ; input \g_bit[0].reg_value_r_reg[0]_1 ; input [6:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[6].reg_value_r_reg[6]_0 ; input [2:0]adress_IBUF; input [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; input \r_data[4]_i_4 ; input \r_data[2]_i_3__0 ; input \r_data[1]_i_6 ; input \r_data[5]_i_6 ; input \r_data[3]_i_10 ; input \r_data[0]_i_6 ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [6:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire [6:0]mr_btr_prop; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; wire \r_data[0]_i_6 ; wire \r_data[1]_i_6 ; wire \r_data[2]_i_3__0 ; wire \r_data[3]_i_10 ; wire \r_data[4]_i_4 ; wire \r_data[5]_i_6 ; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF[0]), .PRE(\g_bit[6].reg_value_r_reg[6]_0 ), .Q(mr_btr_prop[0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[6].reg_value_r_reg[6]_0 ), .D(data_in_IBUF[1]), .Q(mr_btr_prop[1])); FDPE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF[2]), .PRE(\g_bit[6].reg_value_r_reg[6]_0 ), .Q(mr_btr_prop[2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[6].reg_value_r_reg[6]_0 ), .D(data_in_IBUF[3]), .Q(mr_btr_prop[3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[6].reg_value_r_reg[6]_0 ), .D(data_in_IBUF[4]), .Q(mr_btr_prop[4])); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[6].reg_value_r_reg[6]_0 ), .D(data_in_IBUF[5]), .Q(mr_btr_prop[5])); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[6].reg_value_r_reg[6]_0 ), .D(data_in_IBUF[6]), .Q(mr_btr_prop[6])); LUT6 #( .INIT(64'hAABFAFBFFABFFFBF)) \r_data[0]_i_11 (.I0(adress_IBUF[2]), .I1(mr_btr_prop[0]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\mr_ctrl_out[btr_fd_prop_fd] [0]), .I5(\r_data[0]_i_6 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[1]_i_11 (.I0(mr_btr_prop[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_prop_fd] [1]), .I4(\r_data[1]_i_6 ), .I5(adress_IBUF[2]), .O(\g_bit[1].reg_value_r_reg[1]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[2]_i_8 (.I0(mr_btr_prop[2]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_prop_fd] [2]), .I4(\r_data[2]_i_3__0 ), .I5(adress_IBUF[2]), .O(\g_bit[2].reg_value_r_reg[2]_0 )); LUT6 #( .INIT(64'hAABFAFBFFABFFFBF)) \r_data[3]_i_13 (.I0(adress_IBUF[2]), .I1(mr_btr_prop[3]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\mr_ctrl_out[btr_fd_prop_fd] [3]), .I5(\r_data[3]_i_10 ), .O(\g_bit[3].reg_value_r_reg[3]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[4]_i_8 (.I0(mr_btr_prop[4]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_prop_fd] [4]), .I4(\r_data[4]_i_4 ), .I5(adress_IBUF[2]), .O(\g_bit[4].reg_value_r_reg[4]_0 )); LUT6 #( .INIT(64'hAABFAFBFFABFFFBF)) \r_data[5]_i_11 (.I0(adress_IBUF[2]), .I1(mr_btr_prop[5]), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\mr_ctrl_out[btr_fd_prop_fd] [5]), .I5(\r_data[5]_i_6 ), .O(\g_bit[5].reg_value_r_reg[5]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized1 (\mr_ctrl_out[btr_fd_ph1_fd] , \g_bit[0].reg_value_r_reg[0]_0 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 ); output [0:0]\mr_ctrl_out[btr_fd_ph1_fd] ; input \g_bit[0].reg_value_r_reg[0]_0 ; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire [0:0]\mr_ctrl_out[btr_fd_ph1_fd] ; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_1 ), .Q(\mr_ctrl_out[btr_fd_ph1_fd] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized11 (\mr_ctrl_out[btr_fd_sjw_fd] , \adress[8] , \adress[2] , \adress[7] , \segm_counter_q_reg[6] , \g_bit[4].reg_value_r_reg[4]_0 , \FSM_onehot_current_state_reg[2] , \g_bit[3].reg_value_r_reg[3]_0 , \FSM_onehot_current_state_reg[2]_0 , \tseg1_dbt_reg[3] , \tseg1_dbt_reg[4] , \g_bit[3].reg_value_r_reg[3]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[4].reg_value_r_reg[4]_1 , adress_IBUF, scs_IBUF, \exp_seg_length_q[6]_i_2 , CO, \exp_seg_length_q[6]_i_2_0 , \exp_seg_length_q[7]_i_11_0 , is_tseg2, O, \exp_seg_length_d9_inferred__0/i__carry , \test_probe[tx_trigger]_INST_0_i_9_0 , \exp_seg_length_d9_inferred__0/i__carry_0 , \test_probe[tx_trigger]_INST_0_i_9_1 , \exp_seg_length_d9_inferred__0/i__carry_1 , \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 , \test_probe[tx_trigger]_INST_0_i_4 , \test_probe[tx_trigger]_INST_0_i_4_0 , \exp_seg_length_q_reg[7]_i_2__0 , \exp_seg_length_q_reg[7]_i_2__0_0 , \exp_seg_length_q_reg[3]_i_2__0 , \exp_seg_length_q_reg[7]_i_2__0_1 ); output [4:0]\mr_ctrl_out[btr_fd_sjw_fd] ; output \adress[8] ; output \adress[2] ; output \adress[7] ; output \segm_counter_q_reg[6] ; output \g_bit[4].reg_value_r_reg[4]_0 ; output [1:0]\FSM_onehot_current_state_reg[2] ; output [1:0]\g_bit[3].reg_value_r_reg[3]_0 ; output \FSM_onehot_current_state_reg[2]_0 ; output [3:0]\tseg1_dbt_reg[3] ; output [0:0]\tseg1_dbt_reg[4] ; input \g_bit[3].reg_value_r_reg[3]_1 ; input [4:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[4].reg_value_r_reg[4]_1 ; input [7:0]adress_IBUF; input scs_IBUF; input \exp_seg_length_q[6]_i_2 ; input [0:0]CO; input \exp_seg_length_q[6]_i_2_0 ; input [5:0]\exp_seg_length_q[7]_i_11_0 ; input is_tseg2; input [1:0]O; input \exp_seg_length_d9_inferred__0/i__carry ; input \test_probe[tx_trigger]_INST_0_i_9_0 ; input [1:0]\exp_seg_length_d9_inferred__0/i__carry_0 ; input \test_probe[tx_trigger]_INST_0_i_9_1 ; input \exp_seg_length_d9_inferred__0/i__carry_1 ; input \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 ; input \test_probe[tx_trigger]_INST_0_i_4 ; input \test_probe[tx_trigger]_INST_0_i_4_0 ; input [3:0]\exp_seg_length_q_reg[7]_i_2__0 ; input \exp_seg_length_q_reg[7]_i_2__0_0 ; input [2:0]\exp_seg_length_q_reg[3]_i_2__0 ; input [0:0]\exp_seg_length_q_reg[7]_i_2__0_1 ; wire [0:0]CO; wire [1:0]\FSM_onehot_current_state_reg[2] ; wire \FSM_onehot_current_state_reg[2]_0 ; wire [1:0]O; wire \adress[2] ; wire \adress[7] ; wire \adress[8] ; wire [7:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [4:0]data_in_IBUF; wire \exp_seg_length_d9_inferred__0/i__carry ; wire [1:0]\exp_seg_length_d9_inferred__0/i__carry_0 ; wire \exp_seg_length_d9_inferred__0/i__carry_1 ; wire \exp_seg_length_q[3]_i_12_n_0 ; wire \exp_seg_length_q[3]_i_13_n_0 ; wire \exp_seg_length_q[3]_i_14_n_0 ; wire \exp_seg_length_q[6]_i_2 ; wire \exp_seg_length_q[6]_i_2_0 ; wire [5:0]\exp_seg_length_q[7]_i_11_0 ; wire \exp_seg_length_q[7]_i_12_n_0 ; wire \exp_seg_length_q[7]_i_13_n_0 ; wire [2:0]\exp_seg_length_q_reg[3]_i_2__0 ; wire [3:0]\exp_seg_length_q_reg[7]_i_2__0 ; wire \exp_seg_length_q_reg[7]_i_2__0_0 ; wire [0:0]\exp_seg_length_q_reg[7]_i_2__0_1 ; wire [1:0]\g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 ; wire is_tseg2; wire [4:0]\mr_ctrl_out[btr_fd_sjw_fd] ; wire scs_IBUF; wire \segm_counter_q_reg[6] ; wire \test_probe[tx_trigger]_INST_0_i_17_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_18_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_25_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_27_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_28_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_4 ; wire \test_probe[tx_trigger]_INST_0_i_4_0 ; wire \test_probe[tx_trigger]_INST_0_i_9_0 ; wire \test_probe[tx_trigger]_INST_0_i_9_1 ; wire [3:0]\tseg1_dbt_reg[3] ; wire [0:0]\tseg1_dbt_reg[4] ; LUT4 #( .INIT(16'hFFE2)) \exp_seg_length_q[3]_i_11__0 (.I0(\exp_seg_length_q[7]_i_11_0 [0]), .I1(CO), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .I3(\segm_counter_q_reg[6] ), .O(\tseg1_dbt_reg[3] [0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[3]_i_12 (.I0(\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 ), .I1(\segm_counter_q_reg[6] ), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [3]), .I3(CO), .I4(\exp_seg_length_q[7]_i_11_0 [3]), .O(\exp_seg_length_q[3]_i_12_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[3]_i_13 (.I0(\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 ), .I1(\segm_counter_q_reg[6] ), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .I3(CO), .I4(\exp_seg_length_q[7]_i_11_0 [2]), .O(\exp_seg_length_q[3]_i_13_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[3]_i_14 (.I0(\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 ), .I1(\segm_counter_q_reg[6] ), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .I3(CO), .I4(\exp_seg_length_q[7]_i_11_0 [1]), .O(\exp_seg_length_q[3]_i_14_n_0 )); LUT4 #( .INIT(16'hABAA)) \exp_seg_length_q[7]_i_11 (.I0(\exp_seg_length_q[6]_i_2 ), .I1(\exp_seg_length_q[7]_i_13_n_0 ), .I2(CO), .I3(\exp_seg_length_q[6]_i_2_0 ), .O(\segm_counter_q_reg[6] )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h9A999AAA)) \exp_seg_length_q[7]_i_12 (.I0(\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10_0 ), .I1(\segm_counter_q_reg[6] ), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [4]), .I3(CO), .I4(\exp_seg_length_q[7]_i_11_0 [4]), .O(\exp_seg_length_q[7]_i_12_n_0 )); LUT5 #( .INIT(32'h00044404)) \exp_seg_length_q[7]_i_13 (.I0(\test_probe[tx_trigger]_INST_0_i_17_n_0 ), .I1(\test_probe[tx_trigger]_INST_0_i_18_n_0 ), .I2(\exp_seg_length_q[7]_i_11_0 [5]), .I3(is_tseg2), .I4(O[1]), .O(\exp_seg_length_q[7]_i_13_n_0 )); LUT5 #( .INIT(32'hFFFFFEFF)) \g_bit[0].reg_value_r[0]_i_2__4 (.I0(adress_IBUF[4]), .I1(adress_IBUF[7]), .I2(adress_IBUF[6]), .I3(scs_IBUF), .I4(adress_IBUF[5]), .O(\adress[8] )); LUT2 #( .INIT(4'hB)) \g_bit[0].reg_value_r[0]_i_2__6 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .O(\adress[2] )); LUT2 #( .INIT(4'hB)) \g_bit[0].reg_value_r[0]_i_2__9 (.I0(adress_IBUF[3]), .I1(adress_IBUF[2]), .O(\adress[7] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[3].reg_value_r_reg[3]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[btr_fd_sjw_fd] [0])); FDPE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[1]), .PRE(\g_bit[4].reg_value_r_reg[4]_1 ), .Q(\mr_ctrl_out[btr_fd_sjw_fd] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[3].reg_value_r_reg[3]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_fd_sjw_fd] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[3].reg_value_r_reg[3]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[3]), .Q(\mr_ctrl_out[btr_fd_sjw_fd] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[3].reg_value_r_reg[3]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[btr_fd_sjw_fd] [4])); LUT6 #( .INIT(64'h44444444DDD444D4)) i__carry_i_3__3 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [3]), .I1(\exp_seg_length_d9_inferred__0/i__carry_1 ), .I2(\exp_seg_length_q[7]_i_11_0 [2]), .I3(is_tseg2), .I4(\exp_seg_length_d9_inferred__0/i__carry_0 [1]), .I5(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .O(\g_bit[3].reg_value_r_reg[3]_0 [1])); LUT6 #( .INIT(64'h54040000FFFF5404)) i__carry_i_4__3 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .I1(\exp_seg_length_q[7]_i_11_0 [0]), .I2(is_tseg2), .I3(\exp_seg_length_d9_inferred__0/i__carry_0 [0]), .I4(\exp_seg_length_d9_inferred__0/i__carry ), .I5(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .O(\g_bit[3].reg_value_r_reg[3]_0 [0])); LUT6 #( .INIT(64'hB84700000000B847)) i__carry_i_7__2 (.I0(\exp_seg_length_d9_inferred__0/i__carry_0 [1]), .I1(is_tseg2), .I2(\exp_seg_length_q[7]_i_11_0 [2]), .I3(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .I4(\exp_seg_length_d9_inferred__0/i__carry_1 ), .I5(\mr_ctrl_out[btr_fd_sjw_fd] [3]), .O(\FSM_onehot_current_state_reg[2] [1])); LUT6 #( .INIT(64'h9099900009000999)) i__carry_i_8__2 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .I1(\exp_seg_length_d9_inferred__0/i__carry ), .I2(\exp_seg_length_d9_inferred__0/i__carry_0 [0]), .I3(is_tseg2), .I4(\exp_seg_length_q[7]_i_11_0 [0]), .I5(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .O(\FSM_onehot_current_state_reg[2] [0])); LUT4 #( .INIT(16'h56A6)) \i_btl_segment_meter_dbt/exp_seg_length_q[3]_i_10 (.I0(\exp_seg_length_q[3]_i_14_n_0 ), .I1(\exp_seg_length_q_reg[7]_i_2__0 [0]), .I2(\exp_seg_length_q_reg[7]_i_2__0_0 ), .I3(\exp_seg_length_q_reg[3]_i_2__0 [0]), .O(\tseg1_dbt_reg[3] [1])); LUT4 #( .INIT(16'h56A6)) \i_btl_segment_meter_dbt/exp_seg_length_q[3]_i_8 (.I0(\exp_seg_length_q[3]_i_12_n_0 ), .I1(\exp_seg_length_q_reg[7]_i_2__0 [2]), .I2(\exp_seg_length_q_reg[7]_i_2__0_0 ), .I3(\exp_seg_length_q_reg[3]_i_2__0 [2]), .O(\tseg1_dbt_reg[3] [3])); LUT4 #( .INIT(16'h56A6)) \i_btl_segment_meter_dbt/exp_seg_length_q[3]_i_9 (.I0(\exp_seg_length_q[3]_i_13_n_0 ), .I1(\exp_seg_length_q_reg[7]_i_2__0 [1]), .I2(\exp_seg_length_q_reg[7]_i_2__0_0 ), .I3(\exp_seg_length_q_reg[3]_i_2__0 [1]), .O(\tseg1_dbt_reg[3] [2])); LUT4 #( .INIT(16'h56A6)) \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 (.I0(\exp_seg_length_q[7]_i_12_n_0 ), .I1(\exp_seg_length_q_reg[7]_i_2__0 [3]), .I2(\exp_seg_length_q_reg[7]_i_2__0_0 ), .I3(\exp_seg_length_q_reg[7]_i_2__0_1 ), .O(\tseg1_dbt_reg[4] )); (* SOFT_HLUTNM = "soft_lutpair289" *) LUT5 #( .INIT(32'h00000001)) \test_probe[tx_trigger]_INST_0_i_11 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [4]), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .I3(\mr_ctrl_out[btr_fd_sjw_fd] [3]), .I4(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .O(\g_bit[4].reg_value_r_reg[4]_0 )); LUT6 #( .INIT(64'hFFFFFFFFD6BFBFD6)) \test_probe[tx_trigger]_INST_0_i_17 (.I0(\exp_seg_length_d9_inferred__0/i__carry ), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .I3(\test_probe[tx_trigger]_INST_0_i_9_0 ), .I4(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .I5(\test_probe[tx_trigger]_INST_0_i_25_n_0 ), .O(\test_probe[tx_trigger]_INST_0_i_17_n_0 )); LUT6 #( .INIT(64'h0003030090000003)) \test_probe[tx_trigger]_INST_0_i_18 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [4]), .I1(\test_probe[tx_trigger]_INST_0_i_9_1 ), .I2(\test_probe[tx_trigger]_INST_0_i_27_n_0 ), .I3(\mr_ctrl_out[btr_fd_sjw_fd] [3]), .I4(\test_probe[tx_trigger]_INST_0_i_28_n_0 ), .I5(\exp_seg_length_d9_inferred__0/i__carry_1 ), .O(\test_probe[tx_trigger]_INST_0_i_18_n_0 )); LUT4 #( .INIT(16'hA959)) \test_probe[tx_trigger]_INST_0_i_25 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .I1(\exp_seg_length_q[7]_i_11_0 [0]), .I2(is_tseg2), .I3(\exp_seg_length_d9_inferred__0/i__carry_0 [0]), .O(\test_probe[tx_trigger]_INST_0_i_25_n_0 )); LUT4 #( .INIT(16'h56A6)) \test_probe[tx_trigger]_INST_0_i_27 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [4]), .I1(\exp_seg_length_q[7]_i_11_0 [4]), .I2(is_tseg2), .I3(O[0]), .O(\test_probe[tx_trigger]_INST_0_i_27_n_0 )); (* SOFT_HLUTNM = "soft_lutpair289" *) LUT3 #( .INIT(8'h80)) \test_probe[tx_trigger]_INST_0_i_28 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .I2(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .O(\test_probe[tx_trigger]_INST_0_i_28_n_0 )); LUT6 #( .INIT(64'hFFFFFB00FFFFFFFF)) \test_probe[tx_trigger]_INST_0_i_9 (.I0(\test_probe[tx_trigger]_INST_0_i_17_n_0 ), .I1(\test_probe[tx_trigger]_INST_0_i_18_n_0 ), .I2(\test_probe[tx_trigger]_INST_0_i_4 ), .I3(CO), .I4(\test_probe[tx_trigger]_INST_0_i_4_0 ), .I5(is_tseg2), .O(\FSM_onehot_current_state_reg[2]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized11_9 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[1].reg_value_r_reg[1]_1 , \g_bit[2].reg_value_r_reg[2]_1 , \g_bit[3].reg_value_r_reg[3]_1 , \g_bit[4].reg_value_r_reg[4]_1 , \g_bit[1].reg_value_r_reg[1]_2 , \g_bit[4].reg_value_r_reg[4]_2 , \FSM_onehot_current_state_reg[2] , \g_bit[2].reg_value_r_reg[2]_2 , \g_bit[1].reg_value_r_reg[1]_3 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[3].reg_value_r_reg[3]_2 , \mr_ctrl_out[btr_fd_sjw_fd] , adress_IBUF, \r_data_reg[31] , \test_probe[tx_trigger]_INST_0_i_7 , \exp_seg_length_d9_inferred__0/i__carry , \test_probe[tx_trigger]_INST_0_i_7_0 , \test_probe[tx_trigger]_INST_0_i_7_1 , \exp_seg_length_d9_inferred__0/i__carry_0 , neg_phase_err, is_tseg2, \exp_seg_length_d9_inferred__0/i__carry_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[1].reg_value_r_reg[1]_1 ; output \g_bit[2].reg_value_r_reg[2]_1 ; output \g_bit[3].reg_value_r_reg[3]_1 ; output \g_bit[4].reg_value_r_reg[4]_1 ; output \g_bit[1].reg_value_r_reg[1]_2 ; output \g_bit[4].reg_value_r_reg[4]_2 ; output [0:0]\FSM_onehot_current_state_reg[2] ; output [0:0]\g_bit[2].reg_value_r_reg[2]_2 ; output \g_bit[1].reg_value_r_reg[1]_3 ; input wr_en; input [4:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[3].reg_value_r_reg[3]_2 ; input [4:0]\mr_ctrl_out[btr_fd_sjw_fd] ; input [2:0]adress_IBUF; input [4:0]\r_data_reg[31] ; input \test_probe[tx_trigger]_INST_0_i_7 ; input \exp_seg_length_d9_inferred__0/i__carry ; input \test_probe[tx_trigger]_INST_0_i_7_0 ; input \test_probe[tx_trigger]_INST_0_i_7_1 ; input \exp_seg_length_d9_inferred__0/i__carry_0 ; input [2:0]neg_phase_err; input is_tseg2; input [2:0]\exp_seg_length_d9_inferred__0/i__carry_1 ; wire [0:0]\FSM_onehot_current_state_reg[2] ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [4:0]data_in_IBUF; wire \exp_seg_length_d9_inferred__0/i__carry ; wire \exp_seg_length_d9_inferred__0/i__carry_0 ; wire [2:0]\exp_seg_length_d9_inferred__0/i__carry_1 ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[1].reg_value_r_reg[1]_1 ; wire \g_bit[1].reg_value_r_reg[1]_2 ; wire \g_bit[1].reg_value_r_reg[1]_3 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire [0:0]\g_bit[2].reg_value_r_reg[2]_2 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[3].reg_value_r_reg[3]_2 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire \g_bit[4].reg_value_r_reg[4]_2 ; wire is_tseg2; wire [4:0]\mr_ctrl_out[btr_fd_sjw_fd] ; wire [2:0]neg_phase_err; wire [4:0]\r_data_reg[31] ; wire \test_probe[tx_trigger]_INST_0_i_20_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_23_n_0 ; wire \test_probe[tx_trigger]_INST_0_i_7 ; wire \test_probe[tx_trigger]_INST_0_i_7_0 ; wire \test_probe[tx_trigger]_INST_0_i_7_1 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_2 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDPE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[1]), .PRE(\g_bit[3].reg_value_r_reg[3]_2 ), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_2 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_2 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_2 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair290" *) LUT5 #( .INIT(32'h00000001)) \g_segm_end_req_capture[1].segm_end_req_capt_q[1]_i_3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(\g_bit[2].reg_value_r_reg[2]_0 ), .I3(\g_bit[4].reg_value_r_reg[4]_0 ), .I4(\g_bit[3].reg_value_r_reg[3]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_3 )); LUT6 #( .INIT(64'h5404FFFF00005404)) i__carry_i_3__4 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\exp_seg_length_d9_inferred__0/i__carry_1 [1]), .I2(is_tseg2), .I3(neg_phase_err[1]), .I4(\g_bit[3].reg_value_r_reg[3]_0 ), .I5(\exp_seg_length_d9_inferred__0/i__carry_0 ), .O(\g_bit[2].reg_value_r_reg[2]_2 )); LUT6 #( .INIT(64'hB84700000000B847)) i__carry_i_7__3 (.I0(neg_phase_err[2]), .I1(is_tseg2), .I2(\exp_seg_length_d9_inferred__0/i__carry_1 [2]), .I3(\g_bit[3].reg_value_r_reg[3]_0 ), .I4(\exp_seg_length_d9_inferred__0/i__carry ), .I5(\g_bit[2].reg_value_r_reg[2]_0 ), .O(\FSM_onehot_current_state_reg[2] )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[27]_i_4 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [0]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[31] [0]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[28]_i_3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [1]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[31] [1]), .O(\g_bit[1].reg_value_r_reg[1]_1 )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[29]_i_3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[31] [2]), .O(\g_bit[2].reg_value_r_reg[2]_1 )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[30]_i_3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [3]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[31] [3]), .O(\g_bit[3].reg_value_r_reg[3]_1 )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[31]_i_4 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\mr_ctrl_out[btr_fd_sjw_fd] [4]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[31] [4]), .O(\g_bit[4].reg_value_r_reg[4]_1 )); LUT6 #( .INIT(64'hFFFFFFFFD6BFBFD6)) \test_probe[tx_trigger]_INST_0_i_15 (.I0(\test_probe[tx_trigger]_INST_0_i_7 ), .I1(\g_bit[1].reg_value_r_reg[1]_0 ), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\exp_seg_length_d9_inferred__0/i__carry ), .I4(\g_bit[2].reg_value_r_reg[2]_0 ), .I5(\test_probe[tx_trigger]_INST_0_i_20_n_0 ), .O(\g_bit[1].reg_value_r_reg[1]_2 )); LUT6 #( .INIT(64'hFFCFCFFFF6FFFFCF)) \test_probe[tx_trigger]_INST_0_i_16 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\test_probe[tx_trigger]_INST_0_i_7_0 ), .I2(\test_probe[tx_trigger]_INST_0_i_7_1 ), .I3(\g_bit[3].reg_value_r_reg[3]_0 ), .I4(\test_probe[tx_trigger]_INST_0_i_23_n_0 ), .I5(\exp_seg_length_d9_inferred__0/i__carry_0 ), .O(\g_bit[4].reg_value_r_reg[4]_2 )); LUT4 #( .INIT(16'hA959)) \test_probe[tx_trigger]_INST_0_i_20 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\exp_seg_length_d9_inferred__0/i__carry_1 [0]), .I2(is_tseg2), .I3(neg_phase_err[0]), .O(\test_probe[tx_trigger]_INST_0_i_20_n_0 )); (* SOFT_HLUTNM = "soft_lutpair290" *) LUT3 #( .INIT(8'h80)) \test_probe[tx_trigger]_INST_0_i_23 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_bit[1].reg_value_r_reg[1]_0 ), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .O(\test_probe[tx_trigger]_INST_0_i_23_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized13 (\mr_ctrl_out[btr_fd_prop_fd] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[4].reg_value_r_reg[4]_0 , \mr_ctrl_out[btr_fd_ph1_fd] ); output [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; output [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; input \g_bit[0].reg_value_r_reg[0]_1 ; input [5:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[4].reg_value_r_reg[4]_0 ; input [0:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire clk_sys_IBUF_BUFG; wire [5:0]data_in_IBUF; wire [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire [0:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF[0]), .PRE(\g_bit[4].reg_value_r_reg[4]_0 ), .Q(\mr_ctrl_out[btr_fd_prop_fd] [0])); FDPE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF[1]), .PRE(\g_bit[4].reg_value_r_reg[4]_0 ), .Q(\mr_ctrl_out[btr_fd_prop_fd] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_0 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_fd_prop_fd] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_0 ), .D(data_in_IBUF[3]), .Q(\mr_ctrl_out[btr_fd_prop_fd] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_0 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[btr_fd_prop_fd] [4])); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[4].reg_value_r_reg[4]_0 ), .D(data_in_IBUF[5]), .Q(\mr_ctrl_out[btr_fd_prop_fd] [5])); LUT2 #( .INIT(4'h9)) \tseg1_dbt[0]_i_1 (.I0(\mr_ctrl_out[btr_fd_prop_fd] [0]), .I1(\mr_ctrl_out[btr_fd_ph1_fd] ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized15 (\mr_ctrl_out[btr_fd_ph1_fd] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[3].reg_value_r_reg[3]_0 ); output [3:0]\mr_ctrl_out[btr_fd_ph1_fd] ; input wr_en; input [3:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[3].reg_value_r_reg[3]_0 ; wire clk_sys_IBUF_BUFG; wire [3:0]data_in_IBUF; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire [3:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[0]), .PRE(\g_bit[3].reg_value_r_reg[3]_0 ), .Q(\mr_ctrl_out[btr_fd_ph1_fd] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[btr_fd_ph1_fd] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_fd_ph1_fd] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[3]), .Q(\mr_ctrl_out[btr_fd_ph1_fd] [3])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized17 (DI, CO, O, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[1].reg_value_r_reg[1]_0 , i__carry_i_4__3, S, i__carry_i_11__0_0); output [2:0]DI; output [0:0]CO; output [3:0]O; input wr_en; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[1].reg_value_r_reg[1]_0 ; input i__carry_i_4__3; input [0:0]S; input [2:0]i__carry_i_11__0_0; wire [0:0]CO; wire [2:0]DI; wire [3:0]O; wire [0:0]S; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire [2:0]i__carry_i_11__0_0; wire i__carry_i_17_n_0; wire i__carry_i_18__0_n_0; wire i__carry_i_19_n_0; wire i__carry_i_4__3; wire wr_en; wire [2:0]NLW_i__carry_i_11__0_CO_UNCONNECTED; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[0]), .PRE(\g_bit[1].reg_value_r_reg[1]_0 ), .Q(DI[0])); FDPE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[1]), .PRE(\g_bit[1].reg_value_r_reg[1]_0 ), .Q(DI[1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[2]), .Q(DI[2])); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 i__carry_i_11__0 (.CI(1'b0), .CO({CO,NLW_i__carry_i_11__0_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({i__carry_i_4__3,DI}), .O(O), .S({S,i__carry_i_17_n_0,i__carry_i_18__0_n_0,i__carry_i_19_n_0})); LUT2 #( .INIT(4'h9)) i__carry_i_17 (.I0(DI[2]), .I1(i__carry_i_11__0_0[2]), .O(i__carry_i_17_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_18__0 (.I0(DI[1]), .I1(i__carry_i_11__0_0[1]), .O(i__carry_i_18__0_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_19 (.I0(DI[0]), .I1(i__carry_i_11__0_0[0]), .O(i__carry_i_19_n_0)); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized19 (\g_bit[0].reg_value_r_reg[0]_0 , DI, \segm_counter_q_reg[4] , O, \g_bit[4].reg_value_r_reg[4] , S, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_1 , \exp_seg_length_d9_inferred__0/i__carry , \mr_ctrl_out[btr_fd_sjw_fd] , is_tseg2, CO, \test_probe[tx_trigger]_INST_0_i_27 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output [0:0]DI; output [0:0]\segm_counter_q_reg[4] ; output [2:0]O; output [0:0]\g_bit[4].reg_value_r_reg[4] ; output [0:0]S; input wr_en; input [1:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_1 ; input [2:0]\exp_seg_length_d9_inferred__0/i__carry ; input [0:0]\mr_ctrl_out[btr_fd_sjw_fd] ; input is_tseg2; input [0:0]CO; input [1:0]\test_probe[tx_trigger]_INST_0_i_27 ; wire [0:0]CO; wire [0:0]DI; wire [2:0]O; wire [0:0]S; wire clk_sys_IBUF_BUFG; wire [1:0]data_in_IBUF; wire [2:0]\exp_seg_length_d9_inferred__0/i__carry ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire [0:0]\g_bit[4].reg_value_r_reg[4] ; wire i__carry_i_15__0_n_0; wire is_tseg2; wire [0:0]\mr_ctrl_out[btr_fd_sjw_fd] ; wire [0:0]\segm_counter_q_reg[4] ; wire [1:0]\test_probe[tx_trigger]_INST_0_i_27 ; wire wr_en; wire [3:0]NLW_i__carry_i_9__0_CO_UNCONNECTED; wire [3:3]NLW_i__carry_i_9__0_O_UNCONNECTED; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF[1]), .Q(DI)); LUT2 #( .INIT(4'h9)) i__carry_i_15__0 (.I0(DI), .I1(\exp_seg_length_d9_inferred__0/i__carry [1]), .O(i__carry_i_15__0_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_16__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\exp_seg_length_d9_inferred__0/i__carry [0]), .O(S)); LUT6 #( .INIT(64'hFFFFFF504444FF50)) i__carry_i_2__3 (.I0(\mr_ctrl_out[btr_fd_sjw_fd] ), .I1(O[0]), .I2(\exp_seg_length_d9_inferred__0/i__carry [1]), .I3(\exp_seg_length_d9_inferred__0/i__carry [2]), .I4(is_tseg2), .I5(O[1]), .O(\g_bit[4].reg_value_r_reg[4] )); LUT6 #( .INIT(64'h000000C3A5A500C3)) i__carry_i_6__2 (.I0(O[0]), .I1(\exp_seg_length_d9_inferred__0/i__carry [1]), .I2(\mr_ctrl_out[btr_fd_sjw_fd] ), .I3(\exp_seg_length_d9_inferred__0/i__carry [2]), .I4(is_tseg2), .I5(O[1]), .O(\segm_counter_q_reg[4] )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY4 i__carry_i_9__0 (.CI(CO), .CO(NLW_i__carry_i_9__0_CO_UNCONNECTED[3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,DI}), .O({NLW_i__carry_i_9__0_O_UNCONNECTED[3],O}), .S({1'b0,\test_probe[tx_trigger]_INST_0_i_27 ,i__carry_i_15__0_n_0})); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized19_46 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , D, \g_bit[0].reg_value_r_reg[0]_1 , \adress[5] , \g_bit[1].reg_value_r_reg[1]_1 , \adress[9] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[1].reg_value_r_reg[1]_2 , sbe_IBUF, adress_IBUF, \r_data_reg[25] , \r_data_reg[25]_0 , \r_data_reg[25]_1 , timestamp_IBUF, \r_data_reg[24] , \mr_ctrl_out[ssp_cfg_ssp_offset] , trv_delay_sum, scs_IBUF, swr_IBUF); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output [0:0]D; output \g_bit[0].reg_value_r_reg[0]_1 ; output \adress[5] ; output [8:0]\g_bit[1].reg_value_r_reg[1]_1 ; output \adress[9] ; input wr_en; input [1:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[1].reg_value_r_reg[1]_2 ; input [0:0]sbe_IBUF; input [9:0]adress_IBUF; input \r_data_reg[25] ; input \r_data_reg[25]_0 ; input \r_data_reg[25]_1 ; input [3:0]timestamp_IBUF; input \r_data_reg[24] ; input [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; input [8:0]trv_delay_sum; input scs_IBUF; input swr_IBUF; wire [0:0]D; wire \adress[5] ; wire \adress[9] ; wire [9:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [1:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire [8:0]\g_bit[1].reg_value_r_reg[1]_1 ; wire \g_bit[1].reg_value_r_reg[1]_2 ; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire \r_data[25]_i_2_n_0 ; wire \r_data[25]_i_4_n_0 ; wire \r_data_reg[24] ; wire \r_data_reg[25] ; wire \r_data_reg[25]_0 ; wire \r_data_reg[25]_1 ; wire [0:0]sbe_IBUF; wire scs_IBUF; wire swr_IBUF; wire [3:0]timestamp_IBUF; wire [8:0]trv_delay_sum; wire wr_en; LUT4 #( .INIT(16'h0001)) \g_bit[0].reg_value_r[0]_i_2__10 (.I0(adress_IBUF[3]), .I1(adress_IBUF[2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .O(\adress[5] )); LUT6 #( .INIT(64'hFFFFFFFBFFFFFFFF)) \g_bit[0].reg_value_r[0]_i_2__13 (.I0(adress_IBUF[7]), .I1(scs_IBUF), .I2(adress_IBUF[8]), .I3(adress_IBUF[9]), .I4(adress_IBUF[6]), .I5(swr_IBUF), .O(\adress[9] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_2 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_2 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); LUT6 #( .INIT(64'hFF5F3FF0FF5F3FFF)) \r_data[24]_i_4 (.I0(timestamp_IBUF[0]), .I1(timestamp_IBUF[2]), .I2(\r_data_reg[24] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\g_bit[0].reg_value_r_reg[0]_0 ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT5 #( .INIT(32'h8888888A)) \r_data[25]_i_1 (.I0(sbe_IBUF), .I1(\r_data[25]_i_2_n_0 ), .I2(adress_IBUF[4]), .I3(adress_IBUF[5]), .I4(\r_data_reg[25] ), .O(D)); LUT6 #( .INIT(64'h0004000400043004)) \r_data[25]_i_2 (.I0(\r_data[25]_i_4_n_0 ), .I1(adress_IBUF[5]), .I2(adress_IBUF[3]), .I3(adress_IBUF[4]), .I4(\r_data_reg[25]_0 ), .I5(\r_data_reg[25]_1 ), .O(\r_data[25]_i_2_n_0 )); LUT6 #( .INIT(64'hFF5F3F00FF5F3F0F)) \r_data[25]_i_4 (.I0(timestamp_IBUF[1]), .I1(timestamp_IBUF[3]), .I2(\r_data_reg[24] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\r_data[25]_i_4_n_0 )); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[0]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [0]), .I1(trv_delay_sum[0]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [0])); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[1]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [1]), .I1(trv_delay_sum[1]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [1])); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[2]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [2]), .I1(trv_delay_sum[2]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [2])); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[3]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [3]), .I1(trv_delay_sum[3]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [3])); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[4]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [4]), .I1(trv_delay_sum[4]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [4])); (* SOFT_HLUTNM = "soft_lutpair304" *) LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[5]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [5]), .I1(trv_delay_sum[5]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [5])); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[6]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [6]), .I1(trv_delay_sum[6]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [6])); LUT4 #( .INIT(16'h0A0C)) \ssp_delay_shadowed[7]_i_1 (.I0(\mr_ctrl_out[ssp_cfg_ssp_offset] [7]), .I1(trv_delay_sum[7]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\g_bit[1].reg_value_r_reg[1]_0 ), .O(\g_bit[1].reg_value_r_reg[1]_1 [7])); (* SOFT_HLUTNM = "soft_lutpair304" *) LUT3 #( .INIT(8'h10)) \ssp_delay_shadowed[8]_i_1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(trv_delay_sum[8]), .O(\g_bit[1].reg_value_r_reg[1]_1 [8])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized1_7 (\mr_ctrl_out[btr_ph1] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_2 , adress_IBUF, \mr_ctrl_out[btr_fd_ph1_fd] , \r_data[7]_i_11 ); output [0:0]\mr_ctrl_out[btr_ph1] ; output \g_bit[0].reg_value_r_reg[0]_0 ; input \g_bit[0].reg_value_r_reg[0]_1 ; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_2 ; input [2:0]adress_IBUF; input [0:0]\mr_ctrl_out[btr_fd_ph1_fd] ; input \r_data[7]_i_11 ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire [0:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [0:0]\mr_ctrl_out[btr_ph1] ; wire \r_data[7]_i_11 ; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .D(data_in_IBUF), .PRE(\g_bit[0].reg_value_r_reg[0]_2 ), .Q(\mr_ctrl_out[btr_ph1] )); LUT6 #( .INIT(64'hAABFAFBFFABFFFBF)) \r_data[7]_i_15 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_ph1] ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\mr_ctrl_out[btr_fd_ph1_fd] ), .I5(\r_data[7]_i_11 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized21 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[3].reg_value_r_reg[3]_1 , \segm_counter_q[6]_i_3 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[4].reg_value_r_reg[4]_1 , adress_IBUF, \mr_ctrl_out[btr_brp] , \segm_counter_q[6]_i_3_0 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[3].reg_value_r_reg[3]_1 ; input [0:0]\segm_counter_q[6]_i_3 ; input wr_en; input [4:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[4].reg_value_r_reg[4]_1 ; input [2:0]adress_IBUF; input [4:0]\mr_ctrl_out[btr_brp] ; input [5:0]\segm_counter_q[6]_i_3_0 ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [4:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire [4:0]\mr_ctrl_out[btr_brp] ; wire [4:0]\mr_ctrl_out[btr_fd_brp_fd] ; wire [0:0]\segm_counter_q[6]_i_3 ; wire [5:0]\segm_counter_q[6]_i_3_0 ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [1])); FDPE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[2]), .PRE(\g_bit[4].reg_value_r_reg[4]_1 ), .Q(\mr_ctrl_out[btr_fd_brp_fd] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[3]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [4])); LUT5 #( .INIT(32'hF0BFFFBF)) \r_data[19]_i_7 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [0]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\mr_ctrl_out[btr_brp] [0]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT5 #( .INIT(32'hF0BFFFBF)) \r_data[20]_i_7 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [1]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\mr_ctrl_out[btr_brp] [1]), .O(\g_bit[1].reg_value_r_reg[1]_0 )); LUT5 #( .INIT(32'hF0BFFFBF)) \r_data[21]_i_6 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [2]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\mr_ctrl_out[btr_brp] [2]), .O(\g_bit[2].reg_value_r_reg[2]_0 )); LUT5 #( .INIT(32'hF0BFFFBF)) \r_data[22]_i_6 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [3]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\mr_ctrl_out[btr_brp] [3]), .O(\g_bit[3].reg_value_r_reg[3]_0 )); LUT5 #( .INIT(32'hF0BFFFBF)) \r_data[23]_i_6 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [4]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\mr_ctrl_out[btr_brp] [4]), .O(\g_bit[4].reg_value_r_reg[4]_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \segm_counter_q[6]_i_5 (.I0(\mr_ctrl_out[btr_fd_brp_fd] [0]), .I1(\segm_counter_q[6]_i_3_0 [0]), .I2(\segm_counter_q[6]_i_3_0 [2]), .I3(\mr_ctrl_out[btr_fd_brp_fd] [2]), .I4(\segm_counter_q[6]_i_3_0 [1]), .I5(\mr_ctrl_out[btr_fd_brp_fd] [1]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \segm_counter_q[6]_i_6 (.I0(\mr_ctrl_out[btr_fd_brp_fd] [3]), .I1(\segm_counter_q[6]_i_3_0 [3]), .I2(\segm_counter_q[6]_i_3_0 [5]), .I3(\segm_counter_q[6]_i_3 ), .I4(\segm_counter_q[6]_i_3_0 [4]), .I5(\mr_ctrl_out[btr_fd_brp_fd] [4]), .O(\g_bit[3].reg_value_r_reg[3]_1 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized23 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , \g_bit[6].reg_value_r_reg[6]_1 , S, \g_bit[7].reg_value_r_reg[7]_1 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_2 , adress_IBUF, mr_btr_prop, err_warning_limit_q1_carry, \err_warning_limit_q1_inferred__0/i__carry ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output \g_bit[6].reg_value_r_reg[6]_1 ; output [3:0]S; output [3:0]\g_bit[7].reg_value_r_reg[7]_1 ; input wr_en; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_2 ; input [2:0]adress_IBUF; input [0:0]mr_btr_prop; input [7:0]err_warning_limit_q1_carry; input [7:0]\err_warning_limit_q1_inferred__0/i__carry ; wire [3:0]S; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire [7:0]err_warning_limit_q1_carry; wire [7:0]\err_warning_limit_q1_inferred__0/i__carry ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[6].reg_value_r_reg[6]_1 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire \g_bit[7].reg_value_r_reg[7]_2 ; wire [0:0]mr_btr_prop; wire wr_en; LUT4 #( .INIT(16'h9009)) err_warning_limit_q1_carry_i_5 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(err_warning_limit_q1_carry[7]), .I2(\g_bit[6].reg_value_r_reg[6]_0 ), .I3(err_warning_limit_q1_carry[6]), .O(S[3])); LUT4 #( .INIT(16'h9009)) err_warning_limit_q1_carry_i_6 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(err_warning_limit_q1_carry[5]), .I2(\g_bit[4].reg_value_r_reg[4]_0 ), .I3(err_warning_limit_q1_carry[4]), .O(S[2])); LUT4 #( .INIT(16'h9009)) err_warning_limit_q1_carry_i_7 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(err_warning_limit_q1_carry[3]), .I2(\g_bit[2].reg_value_r_reg[2]_0 ), .I3(err_warning_limit_q1_carry[2]), .O(S[1])); LUT4 #( .INIT(16'h9009)) err_warning_limit_q1_carry_i_8 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(err_warning_limit_q1_carry[1]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(err_warning_limit_q1_carry[0]), .O(S[0])); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_2 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_2 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_2 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_2 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_2 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDPE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[5]), .PRE(\g_bit[7].reg_value_r_reg[7]_2 ), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDPE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[6]), .PRE(\g_bit[7].reg_value_r_reg[7]_2 ), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_2 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT4 #( .INIT(16'h44D4)) i__carry_i_1__1 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(\err_warning_limit_q1_inferred__0/i__carry [7]), .I2(\err_warning_limit_q1_inferred__0/i__carry [6]), .I3(\g_bit[6].reg_value_r_reg[6]_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [3])); LUT4 #( .INIT(16'h44D4)) i__carry_i_2__1 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(\err_warning_limit_q1_inferred__0/i__carry [5]), .I2(\err_warning_limit_q1_inferred__0/i__carry [4]), .I3(\g_bit[4].reg_value_r_reg[4]_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [2])); LUT4 #( .INIT(16'h44D4)) i__carry_i_3__1 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\err_warning_limit_q1_inferred__0/i__carry [3]), .I2(\err_warning_limit_q1_inferred__0/i__carry [2]), .I3(\g_bit[2].reg_value_r_reg[2]_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [1])); LUT4 #( .INIT(16'h44D4)) i__carry_i_4__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\err_warning_limit_q1_inferred__0/i__carry [1]), .I2(\err_warning_limit_q1_inferred__0/i__carry [0]), .I3(\g_bit[0].reg_value_r_reg[0]_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [0])); LUT5 #( .INIT(32'hB0FFBFFF)) \r_data[6]_i_11 (.I0(adress_IBUF[2]), .I1(\g_bit[6].reg_value_r_reg[6]_0 ), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(mr_btr_prop), .O(\g_bit[6].reg_value_r_reg[6]_1 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized25 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_3 , next_state2_carry, \next_state2_inferred__0/i__carry ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [3:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [3:0]\g_bit[7].reg_value_r_reg[7]_2 ; input wr_en; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_3 ; input [7:0]next_state2_carry; input [7:0]\next_state2_inferred__0/i__carry ; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire \g_bit[7].reg_value_r_reg[7]_3 ; wire [7:0]next_state2_carry; wire [7:0]\next_state2_inferred__0/i__carry ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_3 ), .D(data_in_IBUF[6]), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDPE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[7]), .PRE(\g_bit[7].reg_value_r_reg[7]_3 ), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT4 #( .INIT(16'h9009)) i__carry_i_5__0 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(\next_state2_inferred__0/i__carry [7]), .I2(\g_bit[6].reg_value_r_reg[6]_0 ), .I3(\next_state2_inferred__0/i__carry [6]), .O(\g_bit[7].reg_value_r_reg[7]_2 [3])); LUT4 #( .INIT(16'h9009)) i__carry_i_6__0 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(\next_state2_inferred__0/i__carry [5]), .I2(\g_bit[4].reg_value_r_reg[4]_0 ), .I3(\next_state2_inferred__0/i__carry [4]), .O(\g_bit[7].reg_value_r_reg[7]_2 [2])); LUT4 #( .INIT(16'h9009)) i__carry_i_7__0 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\next_state2_inferred__0/i__carry [3]), .I2(\g_bit[2].reg_value_r_reg[2]_0 ), .I3(\next_state2_inferred__0/i__carry [2]), .O(\g_bit[7].reg_value_r_reg[7]_2 [1])); LUT4 #( .INIT(16'h9009)) i__carry_i_8__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\next_state2_inferred__0/i__carry [1]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(\next_state2_inferred__0/i__carry [0]), .O(\g_bit[7].reg_value_r_reg[7]_2 [0])); LUT4 #( .INIT(16'h9009)) next_state2_carry_i_5 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(next_state2_carry[7]), .I2(\g_bit[6].reg_value_r_reg[6]_0 ), .I3(next_state2_carry[6]), .O(\g_bit[7].reg_value_r_reg[7]_1 [3])); LUT4 #( .INIT(16'h9009)) next_state2_carry_i_6 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(next_state2_carry[5]), .I2(\g_bit[4].reg_value_r_reg[4]_0 ), .I3(next_state2_carry[4]), .O(\g_bit[7].reg_value_r_reg[7]_1 [2])); LUT4 #( .INIT(16'h9009)) next_state2_carry_i_7 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(next_state2_carry[3]), .I2(\g_bit[2].reg_value_r_reg[2]_0 ), .I3(next_state2_carry[2]), .O(\g_bit[7].reg_value_r_reg[7]_1 [1])); LUT4 #( .INIT(16'h9009)) next_state2_carry_i_8 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(next_state2_carry[1]), .I2(\g_bit[0].reg_value_r_reg[0]_0 ), .I3(next_state2_carry[0]), .O(\g_bit[7].reg_value_r_reg[7]_1 [0])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27 (\mr_ctrl_out[ctr_pres_ctpv] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_0 ); output [7:0]\mr_ctrl_out[ctr_pres_ctpv] ; input wr_en; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_0 ; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [7:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[3]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [4])); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[5]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [5])); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[6]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [6])); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[7]), .Q(\mr_ctrl_out[ctr_pres_ctpv] [7])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27_51 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , D, ADDRARDADDR, \g_bit[4].reg_value_r_reg[4]_1 , ADDRBWRADDR, \g_bit[4].reg_value_r_reg[4]_2 , \g_bit[4].reg_value_r_reg[4]_3 , \g_bit[4].reg_value_r_reg[4]_4 , \g_bit[4].reg_value_r_reg[4]_5 , \g_bit[4].reg_value_r_reg[4]_6 , \g_bit[4].reg_value_r_reg[4]_7 , wr_en_0, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_1 , adress_IBUF, sbe_IBUF, \r_data_reg[1] , \r_data_reg[1]_0 , \r_data_reg[1]_1 , \g_ram_rst_false.ram_memory_reg , Q, \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_ram_rst_false.ram_memory_reg_4 , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , \g_ram_rst_false.ram_memory_reg_7 , \g_ram_rst_false.ram_memory_reg_8 , \g_ram_rst_false.ram_memory_reg_9 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [0:0]D; output [0:0]ADDRARDADDR; output [3:0]\g_bit[4].reg_value_r_reg[4]_1 ; output [4:0]ADDRBWRADDR; output [3:0]\g_bit[4].reg_value_r_reg[4]_2 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_3 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_4 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_5 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_6 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_7 ; input wr_en_0; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_1 ; input [5:0]adress_IBUF; input [0:0]sbe_IBUF; input \r_data_reg[1] ; input \r_data_reg[1]_0 ; input \r_data_reg[1]_1 ; input \g_ram_rst_false.ram_memory_reg ; input [0:0]Q; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input [3:0]\g_ram_rst_false.ram_memory_reg_2 ; input \g_ram_rst_false.ram_memory_reg_3 ; input \g_ram_rst_false.ram_memory_reg_4 ; input \g_ram_rst_false.ram_memory_reg_5 ; input \g_ram_rst_false.ram_memory_reg_6 ; input \g_ram_rst_false.ram_memory_reg_7 ; input \g_ram_rst_false.ram_memory_reg_8 ; input \g_ram_rst_false.ram_memory_reg_9 ; wire [0:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [0:0]D; wire [0:0]Q; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_1 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_2 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_3 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_4 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_5 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_6 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_7 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire \g_bit[7].reg_value_r_reg[7]_1 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire \g_ram_rst_false.ram_memory_reg_7 ; wire \g_ram_rst_false.ram_memory_reg_8 ; wire \g_ram_rst_false.ram_memory_reg_9 ; wire \r_data[1]_i_2_n_0 ; wire \r_data_reg[1] ; wire \r_data_reg[1]_0 ; wire \r_data_reg[1]_1 ; wire [0:0]sbe_IBUF; wire wr_en_0; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[6]), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_0), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_10__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(adress_IBUF[0]), .O(ADDRBWRADDR[0])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_10__1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(adress_IBUF[0]), .O(\g_bit[4].reg_value_r_reg[4]_3 [0])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_10__2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(adress_IBUF[0]), .O(\g_bit[4].reg_value_r_reg[4]_5 [0])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_10__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(adress_IBUF[0]), .O(\g_bit[4].reg_value_r_reg[4]_7 [0])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_1__0 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [3]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_1 [3])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_1__1 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [3]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_2 [3])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_1__2 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [3]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_4 [3])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_1__3 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [3]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_6 [3])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_3__0 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [2]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_1 [2])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_3__1 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [2]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_2 [2])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_3__2 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [2]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_4 [2])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_3__3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [2]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_6 ), .O(\g_bit[4].reg_value_r_reg[4]_6 [2])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_4__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [1]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_5 ), .O(\g_bit[4].reg_value_r_reg[4]_1 [1])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_4__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [1]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_5 ), .O(\g_bit[4].reg_value_r_reg[4]_2 [1])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_4__2 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [1]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_5 ), .O(\g_bit[4].reg_value_r_reg[4]_4 [1])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_4__3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [1]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_5 ), .O(\g_bit[4].reg_value_r_reg[4]_6 [1])); LUT4 #( .INIT(16'hB88B)) \g_ram_rst_false.ram_memory_reg_i_5 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg ), .I2(Q), .I3(\g_ram_rst_false.ram_memory_reg_0 ), .O(ADDRARDADDR)); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_5__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [0]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_4 ), .O(\g_bit[4].reg_value_r_reg[4]_1 [0])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_5__1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [0]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_4 ), .O(\g_bit[4].reg_value_r_reg[4]_2 [0])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_5__2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [0]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_4 ), .O(\g_bit[4].reg_value_r_reg[4]_4 [0])); LUT5 #( .INIT(32'hB8BBB888)) \g_ram_rst_false.ram_memory_reg_i_5__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(\g_ram_rst_false.ram_memory_reg_2 [0]), .I3(\g_ram_rst_false.ram_memory_reg_3 ), .I4(\g_ram_rst_false.ram_memory_reg_4 ), .O(\g_bit[4].reg_value_r_reg[4]_6 [0])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_6__0 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(adress_IBUF[4]), .O(ADDRBWRADDR[4])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_6__1 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(adress_IBUF[4]), .O(\g_bit[4].reg_value_r_reg[4]_3 [4])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_6__2 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(adress_IBUF[4]), .O(\g_bit[4].reg_value_r_reg[4]_5 [4])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_6__3 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(adress_IBUF[4]), .O(\g_bit[4].reg_value_r_reg[4]_7 [4])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_7__0 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(adress_IBUF[3]), .O(ADDRBWRADDR[3])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_7__1 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(adress_IBUF[3]), .O(\g_bit[4].reg_value_r_reg[4]_3 [3])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_7__2 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(adress_IBUF[3]), .O(\g_bit[4].reg_value_r_reg[4]_5 [3])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_7__3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(adress_IBUF[3]), .O(\g_bit[4].reg_value_r_reg[4]_7 [3])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_8__0 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(adress_IBUF[2]), .O(ADDRBWRADDR[2])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_8__1 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(adress_IBUF[2]), .O(\g_bit[4].reg_value_r_reg[4]_3 [2])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_8__2 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(adress_IBUF[2]), .O(\g_bit[4].reg_value_r_reg[4]_5 [2])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_8__3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(adress_IBUF[2]), .O(\g_bit[4].reg_value_r_reg[4]_7 [2])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_9__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_1 ), .I2(adress_IBUF[1]), .O(ADDRBWRADDR[1])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_9__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 ), .I2(adress_IBUF[1]), .O(\g_bit[4].reg_value_r_reg[4]_3 [1])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_9__2 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_8 ), .I2(adress_IBUF[1]), .O(\g_bit[4].reg_value_r_reg[4]_5 [1])); LUT3 #( .INIT(8'hB8)) \g_ram_rst_false.ram_memory_reg_i_9__3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_9 ), .I2(adress_IBUF[1]), .O(\g_bit[4].reg_value_r_reg[4]_7 [1])); LUT6 #( .INIT(64'h0000000000010000)) \r_data[1]_i_1__0 (.I0(adress_IBUF[5]), .I1(adress_IBUF[2]), .I2(adress_IBUF[4]), .I3(adress_IBUF[3]), .I4(sbe_IBUF), .I5(\r_data[1]_i_2_n_0 ), .O(D)); LUT6 #( .INIT(64'h00000000A02AAA2A)) \r_data[1]_i_2 (.I0(\r_data_reg[1] ), .I1(\g_bit[1].reg_value_r_reg[1]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[1]_0 ), .I5(\r_data_reg[1]_1 ), .O(\r_data[1]_i_2_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27_52 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , wr_en_1, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_1 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; input wr_en_1; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_1 ; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire \g_bit[7].reg_value_r_reg[7]_1 ; wire wr_en_1; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[6]), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_1), .CLR(\g_bit[7].reg_value_r_reg[7]_1 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27_53 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , D, \adress[7] , \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \g_bit[7].reg_value_r_reg[7]_3 , \g_bit[7].reg_value_r_reg[7]_4 , \adress[11] , wr_en_3, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_5 , \r_data_reg[2] , adress_IBUF, \r_data_reg[2]_0 , \r_data_reg[2]_1 , \r_data_reg[3] , \r_data_reg[3]_0 , \r_data_reg[4] , \r_data_reg[4]_0 , \r_data_reg[5] , \r_data_reg[5]_0 , \r_data_reg[6] , \r_data_reg[6]_0 , \r_data_reg[7] , \r_data_reg[7]_0 , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , scs_IBUF, swr_IBUF); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [5:0]D; output \adress[7] ; output [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_4 ; output \adress[11] ; input wr_en_3; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_5 ; input \r_data_reg[2] ; input [9:0]adress_IBUF; input \r_data_reg[2]_0 ; input \r_data_reg[2]_1 ; input \r_data_reg[3] ; input \r_data_reg[3]_0 ; input \r_data_reg[4] ; input \r_data_reg[4]_0 ; input \r_data_reg[5] ; input \r_data_reg[5]_0 ; input \r_data_reg[6] ; input \r_data_reg[6]_0 ; input \r_data_reg[7] ; input \r_data_reg[7]_0 ; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \g_ram_rst_false.ram_memory_reg_2 ; input scs_IBUF; input swr_IBUF; wire [5:0]D; wire \adress[11] ; wire \adress[7] ; wire [9:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_4 ; wire \g_bit[7].reg_value_r_reg[7]_5 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire \r_data_reg[2] ; wire \r_data_reg[2]_0 ; wire \r_data_reg[2]_1 ; wire \r_data_reg[3] ; wire \r_data_reg[3]_0 ; wire \r_data_reg[4] ; wire \r_data_reg[4]_0 ; wire \r_data_reg[5] ; wire \r_data_reg[5]_0 ; wire \r_data_reg[6] ; wire \r_data_reg[6]_0 ; wire \r_data_reg[7] ; wire \r_data_reg[7]_0 ; wire scs_IBUF; wire swr_IBUF; wire wr_en_3; LUT6 #( .INIT(64'hFFFFF7FFFFFFFFFF)) \g_bit[0].reg_value_r[0]_i_2__12 (.I0(adress_IBUF[9]), .I1(adress_IBUF[6]), .I2(adress_IBUF[7]), .I3(scs_IBUF), .I4(adress_IBUF[8]), .I5(swr_IBUF), .O(\adress[11] )); LUT4 #( .INIT(16'hFFFE)) \g_bit[0].reg_value_r[0]_i_3 (.I0(adress_IBUF[5]), .I1(adress_IBUF[2]), .I2(adress_IBUF[4]), .I3(adress_IBUF[3]), .O(\adress[7] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[6]), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_3), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_19__0 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_19__1 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_19__2 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_19__3 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_20__0 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_20__1 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_20__2 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_20__3 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_21__0 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_21__1 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_21__2 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_21__3 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_22__0 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_22__1 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_22__2 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_22__3 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_23__0 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_23__1 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_23__2 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_23__3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_24__0 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_24__1 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_24__2 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_24__3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_25__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_25__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_25__2 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_25__3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_26__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_26__1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_26__2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_26__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [0])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[2]_i_1__0 (.I0(\r_data_reg[2] ), .I1(\g_bit[2].reg_value_r_reg[2]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[2]_0 ), .I5(\r_data_reg[2]_1 ), .O(D[0])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[3]_i_1__0 (.I0(\r_data_reg[2] ), .I1(\g_bit[3].reg_value_r_reg[3]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[3] ), .I5(\r_data_reg[3]_0 ), .O(D[1])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[4]_i_1__0 (.I0(\r_data_reg[2] ), .I1(\g_bit[4].reg_value_r_reg[4]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[4] ), .I5(\r_data_reg[4]_0 ), .O(D[2])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[5]_i_1__0 (.I0(\r_data_reg[2] ), .I1(\g_bit[5].reg_value_r_reg[5]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[5] ), .I5(\r_data_reg[5]_0 ), .O(D[3])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[6]_i_1__0 (.I0(\r_data_reg[2] ), .I1(\g_bit[6].reg_value_r_reg[6]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[6] ), .I5(\r_data_reg[6]_0 ), .O(D[4])); LUT6 #( .INIT(64'hAAAAAAAA08A00800)) \r_data[7]_i_1__0 (.I0(\r_data_reg[2] ), .I1(\g_bit[7].reg_value_r_reg[7]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[7] ), .I5(\r_data_reg[7]_0 ), .O(D[5])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27_54 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \mr_tst_out[tst_wdata_tst_wdata] , \g_bit[7].reg_value_r_reg[7]_0 , D, \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \g_bit[7].reg_value_r_reg[7]_3 , \g_bit[7].reg_value_r_reg[7]_4 , wr_en_4, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_5 , \r_data_reg[8] , adress_IBUF, \r_data_reg[8]_0 , \r_data_reg[8]_1 , \r_data_reg[9] , \r_data_reg[9]_0 , \r_data_reg[10] , \r_data_reg[10]_0 , \r_data_reg[11] , \r_data_reg[11]_0 , \r_data_reg[12] , \r_data_reg[12]_0 , \r_data_reg[13] , \r_data_reg[13]_0 , \r_data_reg[14] , \r_data_reg[14]_0 , \r_data_reg[15] , \r_data_reg[15]_0 , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output [0:0]\mr_tst_out[tst_wdata_tst_wdata] ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [7:0]D; output [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_4 ; input wr_en_4; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_5 ; input \r_data_reg[8] ; input [1:0]adress_IBUF; input \r_data_reg[8]_0 ; input \r_data_reg[8]_1 ; input \r_data_reg[9] ; input \r_data_reg[9]_0 ; input \r_data_reg[10] ; input \r_data_reg[10]_0 ; input \r_data_reg[11] ; input \r_data_reg[11]_0 ; input \r_data_reg[12] ; input \r_data_reg[12]_0 ; input \r_data_reg[13] ; input \r_data_reg[13]_0 ; input \r_data_reg[14] ; input \r_data_reg[14]_0 ; input \r_data_reg[15] ; input \r_data_reg[15]_0 ; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \g_ram_rst_false.ram_memory_reg_2 ; wire [7:0]D; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_4 ; wire \g_bit[7].reg_value_r_reg[7]_5 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire [0:0]\mr_tst_out[tst_wdata_tst_wdata] ; wire \r_data_reg[10] ; wire \r_data_reg[10]_0 ; wire \r_data_reg[11] ; wire \r_data_reg[11]_0 ; wire \r_data_reg[12] ; wire \r_data_reg[12]_0 ; wire \r_data_reg[13] ; wire \r_data_reg[13]_0 ; wire \r_data_reg[14] ; wire \r_data_reg[14]_0 ; wire \r_data_reg[15] ; wire \r_data_reg[15]_0 ; wire \r_data_reg[8] ; wire \r_data_reg[8]_0 ; wire \r_data_reg[8]_1 ; wire \r_data_reg[9] ; wire \r_data_reg[9]_0 ; wire wr_en_4; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[6]), .Q(\mr_tst_out[tst_wdata_tst_wdata] )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_4), .CLR(\g_bit[7].reg_value_r_reg[7]_5 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_11__0 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_11__1 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_11__2 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_11__3 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_12__0 (.I0(\mr_tst_out[tst_wdata_tst_wdata] ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_12__1 (.I0(\mr_tst_out[tst_wdata_tst_wdata] ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_12__2 (.I0(\mr_tst_out[tst_wdata_tst_wdata] ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_12__3 (.I0(\mr_tst_out[tst_wdata_tst_wdata] ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_13__0 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_13__1 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_13__2 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_13__3 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_14__0 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_14__1 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_14__2 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_14__3 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_15__0 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_15__1 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_15__2 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_15__3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_16__0 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_16__1 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_16__2 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_16__3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_17__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_17__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_17__2 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_17__3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_18__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(\g_bit[7].reg_value_r_reg[7]_1 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_18__1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_18__2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_18__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_4 [0])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[10]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[2].reg_value_r_reg[2]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[10] ), .I5(\r_data_reg[10]_0 ), .O(D[2])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[11]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[3].reg_value_r_reg[3]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[11] ), .I5(\r_data_reg[11]_0 ), .O(D[3])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[12]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[4].reg_value_r_reg[4]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[12] ), .I5(\r_data_reg[12]_0 ), .O(D[4])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[13]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[5].reg_value_r_reg[5]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[13] ), .I5(\r_data_reg[13]_0 ), .O(D[5])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[14]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\mr_tst_out[tst_wdata_tst_wdata] ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[14] ), .I5(\r_data_reg[14]_0 ), .O(D[6])); LUT6 #( .INIT(64'hAAAAAAAA08A00800)) \r_data[15]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[7].reg_value_r_reg[7]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[15] ), .I5(\r_data_reg[15]_0 ), .O(D[7])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[8]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[8]_0 ), .I5(\r_data_reg[8]_1 ), .O(D[0])); LUT6 #( .INIT(64'h08A00800AAAAAAAA)) \r_data[9]_i_1__0 (.I0(\r_data_reg[8] ), .I1(\g_bit[1].reg_value_r_reg[1]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data_reg[9] ), .I5(\r_data_reg[9]_0 ), .O(D[1])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27_55 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , DIBDI, \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \g_bit[7].reg_value_r_reg[7]_3 , wr_en_5, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_4 , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [7:0]DIBDI; output [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; input wr_en_5; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_4 ; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \g_ram_rst_false.ram_memory_reg_2 ; wire [7:0]DIBDI; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire \g_bit[7].reg_value_r_reg[7]_4 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire wr_en_5; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[6]), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_5), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_35__0 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_35__1 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_35__2 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_35__3 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_36__0 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_36__1 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_36__2 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_36__3 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_37__0 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_37__1 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_37__2 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_37__3 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_38__0 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_38__1 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_38__2 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_38__3 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_39__0 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_39__1 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_39__2 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_39__3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_40__0 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_40__1 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_40__2 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_40__3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_41__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_41__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_41__2 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_41__3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_42__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_42__1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_42__2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_42__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [0])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized27_56 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_0 , DIBDI, \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \g_bit[7].reg_value_r_reg[7]_3 , wr_en_6, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_4 , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 ); output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output [7:0]DIBDI; output [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; output [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; input wr_en_6; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_4 ; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \g_ram_rst_false.ram_memory_reg_2 ; wire [7:0]DIBDI; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire [7:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire \g_bit[7].reg_value_r_reg[7]_4 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire wr_en_6; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[1]), .Q(\g_bit[1].reg_value_r_reg[1]_0 )); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[2]), .Q(\g_bit[2].reg_value_r_reg[2]_0 )); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[3]), .Q(\g_bit[3].reg_value_r_reg[3]_0 )); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[4]), .Q(\g_bit[4].reg_value_r_reg[4]_0 )); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[5]), .Q(\g_bit[5].reg_value_r_reg[5]_0 )); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[6]), .Q(\g_bit[6].reg_value_r_reg[6]_0 )); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_6), .CLR(\g_bit[7].reg_value_r_reg[7]_4 ), .D(data_in_IBUF[7]), .Q(\g_bit[7].reg_value_r_reg[7]_0 )); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_27__0 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_27__1 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_27__2 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_27__3 (.I0(\g_bit[7].reg_value_r_reg[7]_0 ), .I1(data_in_IBUF[7]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [7])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_28__0 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_28__1 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_28__2 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_28__3 (.I0(\g_bit[6].reg_value_r_reg[6]_0 ), .I1(data_in_IBUF[6]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [6])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_29__0 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_29__1 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_29__2 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_29__3 (.I0(\g_bit[5].reg_value_r_reg[5]_0 ), .I1(data_in_IBUF[5]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [5])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_30__0 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_30__1 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_30__2 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_30__3 (.I0(\g_bit[4].reg_value_r_reg[4]_0 ), .I1(data_in_IBUF[4]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [4])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_31__0 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_31__1 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_31__2 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_31__3 (.I0(\g_bit[3].reg_value_r_reg[3]_0 ), .I1(data_in_IBUF[3]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [3])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_32__0 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_32__1 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_32__2 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_32__3 (.I0(\g_bit[2].reg_value_r_reg[2]_0 ), .I1(data_in_IBUF[2]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [2])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_33__0 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_33__1 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_33__2 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_33__3 (.I0(\g_bit[1].reg_value_r_reg[1]_0 ), .I1(data_in_IBUF[1]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [1])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_34__0 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg ), .O(DIBDI[0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_34__1 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_0 ), .O(\g_bit[7].reg_value_r_reg[7]_1 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_34__2 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_1 ), .O(\g_bit[7].reg_value_r_reg[7]_2 [0])); LUT3 #( .INIT(8'hAC)) \g_ram_rst_false.ram_memory_reg_i_34__3 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(data_in_IBUF[0]), .I2(\g_ram_rst_false.ram_memory_reg_2 ), .O(\g_bit[7].reg_value_r_reg[7]_3 [0])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized29 (\mr_ctrl_out[ctr_pres_ctpv] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 ); output [0:0]\mr_ctrl_out[ctr_pres_ctpv] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire [0:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_ctrl_out[ctr_pres_ctpv] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized29_50 (\mr_tst_out[tst_control_tmaena] , \adress[10] , \adress[7] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[0].reg_value_r_reg[0]_0 , adress_IBUF, scs_IBUF); output \mr_tst_out[tst_control_tmaena] ; output \adress[10] ; output \adress[7] ; input wr_en; input [0:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[0].reg_value_r_reg[0]_0 ; input [5:0]adress_IBUF; input scs_IBUF; wire \adress[10] ; wire \adress[7] ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \mr_tst_out[tst_control_tmaena] ; wire scs_IBUF; wire wr_en; LUT5 #( .INIT(32'hFBFFFFFF)) \g_bit[0].reg_value_r[0]_i_2__0 (.I0(adress_IBUF[4]), .I1(scs_IBUF), .I2(adress_IBUF[3]), .I3(adress_IBUF[2]), .I4(adress_IBUF[5]), .O(\adress[10] )); LUT2 #( .INIT(4'hE)) \g_bit[0].reg_value_r[0]_i_3__1 (.I0(adress_IBUF[1]), .I1(adress_IBUF[0]), .O(\adress[7] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[0].reg_value_r_reg[0]_0 ), .D(data_in_IBUF), .Q(\mr_tst_out[tst_control_tmaena] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized3 (\mr_ctrl_out[btr_ph1] , \g_bit[4].reg_value_r_reg[4]_0 , \nom_err_ctr_q_reg[9] , \nom_err_ctr_q_reg[10] , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[0].reg_value_r_reg[0]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[4].reg_value_r_reg[4]_1 , \r_data_reg[12] , adress_IBUF, \r_data_reg[12]_0 , \mr_ctrl_out[btr_fd_ph1_fd] , \r_data[11]_i_6 , \r_data[10]_i_8_0 , \r_data[9]_i_8_0 , \r_data[8]_i_7 ); output [4:0]\mr_ctrl_out[btr_ph1] ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \nom_err_ctr_q_reg[9] ; output \nom_err_ctr_q_reg[10] ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[0].reg_value_r_reg[0]_0 ; input wr_en; input [4:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[4].reg_value_r_reg[4]_1 ; input \r_data_reg[12] ; input [2:0]adress_IBUF; input [2:0]\r_data_reg[12]_0 ; input [3:0]\mr_ctrl_out[btr_fd_ph1_fd] ; input \r_data[11]_i_6 ; input \r_data[10]_i_8_0 ; input \r_data[9]_i_8_0 ; input \r_data[8]_i_7 ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [4:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire [3:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [4:0]\mr_ctrl_out[btr_ph1] ; wire \nom_err_ctr_q_reg[10] ; wire \nom_err_ctr_q_reg[9] ; wire \r_data[10]_i_11_n_0 ; wire \r_data[10]_i_8_0 ; wire \r_data[11]_i_6 ; wire \r_data[8]_i_7 ; wire \r_data[9]_i_11_n_0 ; wire \r_data[9]_i_8_0 ; wire \r_data_reg[12] ; wire [2:0]\r_data_reg[12]_0 ; wire wr_en; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[0]), .PRE(\g_bit[4].reg_value_r_reg[4]_1 ), .Q(\mr_ctrl_out[btr_ph1] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[btr_ph1] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_ph1] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[3]), .Q(\mr_ctrl_out[btr_ph1] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[4].reg_value_r_reg[4]_1 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[btr_ph1] [4])); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[10]_i_11 (.I0(\mr_ctrl_out[btr_ph1] [2]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [2]), .I4(\r_data[10]_i_8_0 ), .I5(adress_IBUF[2]), .O(\r_data[10]_i_11_n_0 )); LUT5 #( .INIT(32'hAEAAAAAA)) \r_data[10]_i_8 (.I0(\r_data[10]_i_11_n_0 ), .I1(\r_data_reg[12]_0 [1]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .O(\nom_err_ctr_q_reg[10] )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[11]_i_10 (.I0(\mr_ctrl_out[btr_ph1] [3]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [3]), .I4(\r_data[11]_i_6 ), .I5(adress_IBUF[2]), .O(\g_bit[3].reg_value_r_reg[3]_0 )); LUT6 #( .INIT(64'hF0FF35FFFFFF35FF)) \r_data[12]_i_3 (.I0(\mr_ctrl_out[btr_ph1] [4]), .I1(\r_data_reg[12] ), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[12]_0 [2]), .O(\g_bit[4].reg_value_r_reg[4]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[8]_i_10 (.I0(\mr_ctrl_out[btr_ph1] [0]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [0]), .I4(\r_data[8]_i_7 ), .I5(adress_IBUF[2]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[9]_i_11 (.I0(\mr_ctrl_out[btr_ph1] [1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_ctrl_out[btr_fd_ph1_fd] [1]), .I4(\r_data[9]_i_8_0 ), .I5(adress_IBUF[2]), .O(\r_data[9]_i_11_n_0 )); LUT5 #( .INIT(32'hAEAAAAAA)) \r_data[9]_i_8 (.I0(\r_data[9]_i_11_n_0 ), .I1(\r_data_reg[12]_0 [0]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .O(\nom_err_ctr_q_reg[9] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized31 (\mr_ctrl_out[ssp_cfg_ssp_offset] , D, \g_bit[4].reg_value_r_reg[4]_0 , \sbe[2] , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[5].reg_value_r_reg[5]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_0 , sbe_IBUF, \r_data_reg[23] , adress_IBUF, \r_data_reg[23]_0 , \r_data_reg[23]_1 , \mr_ctrl_out[settings_nisofd] , \r_data_reg[23]_2 , \r_data_reg[22] , \r_data_reg[22]_0 , \r_data_reg[22]_1 , timestamp_IBUF, \r_data_reg[20] , swr_IBUF, \g_bit[3].reg_value_r_reg[3]_1 ); output [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; output [1:0]D; output \g_bit[4].reg_value_r_reg[4]_0 ; output \sbe[2] ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[5].reg_value_r_reg[5]_0 ; input wr_en; input [7:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_0 ; input [0:0]sbe_IBUF; input \r_data_reg[23] ; input [4:0]adress_IBUF; input \r_data_reg[23]_0 ; input \r_data_reg[23]_1 ; input \mr_ctrl_out[settings_nisofd] ; input \r_data_reg[23]_2 ; input \r_data_reg[22] ; input \r_data_reg[22]_0 ; input \r_data_reg[22]_1 ; input [9:0]timestamp_IBUF; input \r_data_reg[20] ; input swr_IBUF; input \g_bit[3].reg_value_r_reg[3]_1 ; wire [1:0]D; wire [4:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [7:0]data_in_IBUF; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire \mr_ctrl_out[settings_nisofd] ; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire \r_data[22]_i_2_n_0 ; wire \r_data[22]_i_4_n_0 ; wire \r_data[23]_i_2_n_0 ; wire \r_data[23]_i_4_n_0 ; wire \r_data_reg[20] ; wire \r_data_reg[22] ; wire \r_data_reg[22]_0 ; wire \r_data_reg[22]_1 ; wire \r_data_reg[23] ; wire \r_data_reg[23]_0 ; wire \r_data_reg[23]_1 ; wire \r_data_reg[23]_2 ; wire \sbe[2] ; wire [0:0]sbe_IBUF; wire swr_IBUF; wire [9:0]timestamp_IBUF; wire wr_en; LUT3 #( .INIT(8'h08)) \g_bit[0].reg_value_r[0]_i_2__2 (.I0(sbe_IBUF), .I1(swr_IBUF), .I2(\g_bit[3].reg_value_r_reg[3]_1 ), .O(\sbe[2] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [0])); FDPE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[1]), .PRE(\g_bit[7].reg_value_r_reg[7]_0 ), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [2])); FDPE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[3]), .PRE(\g_bit[7].reg_value_r_reg[7]_0 ), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [4])); FDCE \g_bit[5].reg_value_r_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[5]), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [5])); FDCE \g_bit[6].reg_value_r_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[6]), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [6])); FDCE \g_bit[7].reg_value_r_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[7].reg_value_r_reg[7]_0 ), .D(data_in_IBUF[7]), .Q(\mr_ctrl_out[ssp_cfg_ssp_offset] [7])); LUT6 #( .INIT(64'h0000C0C0A0A0FFF0)) \r_data[19]_i_3__0 (.I0(timestamp_IBUF[5]), .I1(timestamp_IBUF[0]), .I2(\r_data_reg[20] ), .I3(\mr_ctrl_out[ssp_cfg_ssp_offset] [3]), .I4(adress_IBUF[1]), .I5(adress_IBUF[0]), .O(\g_bit[3].reg_value_r_reg[3]_0 )); LUT6 #( .INIT(64'hFF5F3FF0FF5F3FFF)) \r_data[20]_i_4 (.I0(timestamp_IBUF[1]), .I1(timestamp_IBUF[6]), .I2(\r_data_reg[20] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\mr_ctrl_out[ssp_cfg_ssp_offset] [4]), .O(\g_bit[4].reg_value_r_reg[4]_0 )); LUT6 #( .INIT(64'hFF3F5F00FF3F5F0F)) \r_data[21]_i_4 (.I0(timestamp_IBUF[7]), .I1(timestamp_IBUF[2]), .I2(\r_data_reg[20] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\mr_ctrl_out[ssp_cfg_ssp_offset] [5]), .O(\g_bit[5].reg_value_r_reg[5]_0 )); LUT6 #( .INIT(64'h88888888888A8888)) \r_data[22]_i_1 (.I0(sbe_IBUF), .I1(\r_data[22]_i_2_n_0 ), .I2(\r_data_reg[22] ), .I3(adress_IBUF[4]), .I4(adress_IBUF[2]), .I5(adress_IBUF[3]), .O(D[0])); LUT6 #( .INIT(64'h101F10101F1F1F1F)) \r_data[22]_i_2 (.I0(\r_data_reg[23]_0 ), .I1(\r_data[22]_i_4_n_0 ), .I2(adress_IBUF[4]), .I3(\r_data_reg[23]_1 ), .I4(\r_data_reg[22]_0 ), .I5(\r_data_reg[22]_1 ), .O(\r_data[22]_i_2_n_0 )); LUT6 #( .INIT(64'hFF5F3FF0FF5F3FFF)) \r_data[22]_i_4 (.I0(timestamp_IBUF[3]), .I1(timestamp_IBUF[8]), .I2(\r_data_reg[20] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\mr_ctrl_out[ssp_cfg_ssp_offset] [6]), .O(\r_data[22]_i_4_n_0 )); LUT6 #( .INIT(64'h88888888888A8888)) \r_data[23]_i_1 (.I0(sbe_IBUF), .I1(\r_data[23]_i_2_n_0 ), .I2(\r_data_reg[23] ), .I3(adress_IBUF[4]), .I4(adress_IBUF[2]), .I5(adress_IBUF[3]), .O(D[1])); LUT6 #( .INIT(64'h101F10101F1F1F1F)) \r_data[23]_i_2 (.I0(\r_data_reg[23]_0 ), .I1(\r_data[23]_i_4_n_0 ), .I2(adress_IBUF[4]), .I3(\r_data_reg[23]_1 ), .I4(\mr_ctrl_out[settings_nisofd] ), .I5(\r_data_reg[23]_2 ), .O(\r_data[23]_i_2_n_0 )); LUT6 #( .INIT(64'hFF3F5F00FF3F5F0F)) \r_data[23]_i_4 (.I0(timestamp_IBUF[9]), .I1(timestamp_IBUF[4]), .I2(\r_data_reg[20] ), .I3(adress_IBUF[1]), .I4(adress_IBUF[0]), .I5(\mr_ctrl_out[ssp_cfg_ssp_offset] [7]), .O(\r_data[23]_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized33 (D, \g_bit[0].reg_value_r_reg[0]_0 , \g_ram_rst_false.ram_memory_reg , \g_bit[0].reg_value_r_reg[0]_1 , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_ram_rst_false.ram_memory_reg_4 , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , \g_ram_rst_false.ram_memory_reg_7 , \g_ram_rst_false.ram_memory_reg_8 , \g_ram_rst_false.ram_memory_reg_9 , \g_ram_rst_false.ram_memory_reg_10 , \g_ram_rst_false.ram_memory_reg_11 , \g_ram_rst_false.ram_memory_reg_12 , \g_ram_rst_false.ram_memory_reg_13 , \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , \g_bit[0].reg_value_r_reg[0]_4 , DIADI, wr_en_2, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[3].reg_value_r_reg[3]_0 , adress_IBUF, sbe_IBUF, \r_data_reg[16] , \r_data_reg[16]_0 , \r_data_reg[17] , \r_data_reg[18] , \r_data_reg[19] , \r_data_reg[20] , \r_data_reg[21] , \r_data_reg[22] , \r_data_reg[23] , \r_data_reg[24] , \r_data_reg[24]_0 , \r_data_reg[25] , \r_data_reg[26] , \r_data_reg[27] , \r_data_reg[28] , \r_data_reg[29] , \r_data_reg[30] , \r_data_reg[31] , \mr_tst_out[tst_control_tmaena] , \r_data_reg[0] , \r_data_reg[0]_0 , txtb_port_b_data_out_i, rxb_port_b_data_out_i, txtb_port_b_data_out_i_6, txtb_port_b_data_out_i_7, txtb_port_b_data_out_i_8, \g_ram_rst_false.ram_memory_reg_14 , \g_ram_rst_false.ram_memory_reg_15 , \mr_tst_out[tst_wdata_tst_wdata] ); output [16:0]D; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_ram_rst_false.ram_memory_reg ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_ram_rst_false.ram_memory_reg_0 ; output \g_ram_rst_false.ram_memory_reg_1 ; output \g_ram_rst_false.ram_memory_reg_2 ; output \g_ram_rst_false.ram_memory_reg_3 ; output \g_ram_rst_false.ram_memory_reg_4 ; output \g_ram_rst_false.ram_memory_reg_5 ; output \g_ram_rst_false.ram_memory_reg_6 ; output \g_ram_rst_false.ram_memory_reg_7 ; output \g_ram_rst_false.ram_memory_reg_8 ; output \g_ram_rst_false.ram_memory_reg_9 ; output \g_ram_rst_false.ram_memory_reg_10 ; output \g_ram_rst_false.ram_memory_reg_11 ; output \g_ram_rst_false.ram_memory_reg_12 ; output \g_ram_rst_false.ram_memory_reg_13 ; output \g_bit[0].reg_value_r_reg[0]_2 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \g_bit[0].reg_value_r_reg[0]_4 ; output [0:0]DIADI; input wr_en_2; input [3:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[3].reg_value_r_reg[3]_0 ; input [5:0]adress_IBUF; input [0:0]sbe_IBUF; input \r_data_reg[16] ; input \r_data_reg[16]_0 ; input \r_data_reg[17] ; input \r_data_reg[18] ; input \r_data_reg[19] ; input \r_data_reg[20] ; input \r_data_reg[21] ; input \r_data_reg[22] ; input \r_data_reg[23] ; input \r_data_reg[24] ; input \r_data_reg[24]_0 ; input \r_data_reg[25] ; input \r_data_reg[26] ; input \r_data_reg[27] ; input \r_data_reg[28] ; input \r_data_reg[29] ; input \r_data_reg[30] ; input \r_data_reg[31] ; input \mr_tst_out[tst_control_tmaena] ; input \r_data_reg[0] ; input \r_data_reg[0]_0 ; input [31:0]txtb_port_b_data_out_i; input [31:0]rxb_port_b_data_out_i; input [31:0]txtb_port_b_data_out_i_6; input [31:0]txtb_port_b_data_out_i_7; input [31:0]txtb_port_b_data_out_i_8; input \g_ram_rst_false.ram_memory_reg_14 ; input \g_ram_rst_false.ram_memory_reg_15 ; input [0:0]\mr_tst_out[tst_wdata_tst_wdata] ; wire [16:0]D; wire [0:0]DIADI; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [3:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_10 ; wire \g_ram_rst_false.ram_memory_reg_11 ; wire \g_ram_rst_false.ram_memory_reg_12 ; wire \g_ram_rst_false.ram_memory_reg_13 ; wire \g_ram_rst_false.ram_memory_reg_14 ; wire \g_ram_rst_false.ram_memory_reg_15 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire \g_ram_rst_false.ram_memory_reg_7 ; wire \g_ram_rst_false.ram_memory_reg_8 ; wire \g_ram_rst_false.ram_memory_reg_9 ; wire memory_reg_rw_l1_net; wire memory_reg_rw_l1_net_1; wire memory_reg_rw_l1_net_10; wire memory_reg_rw_l1_net_11; wire memory_reg_rw_l1_net_12; wire memory_reg_rw_l1_net_13; wire memory_reg_rw_l1_net_14; wire memory_reg_rw_l1_net_15; wire memory_reg_rw_l1_net_16; wire memory_reg_rw_l1_net_17; wire memory_reg_rw_l1_net_18; wire memory_reg_rw_l1_net_19; wire memory_reg_rw_l1_net_2; wire memory_reg_rw_l1_net_20; wire memory_reg_rw_l1_net_21; wire memory_reg_rw_l1_net_22; wire memory_reg_rw_l1_net_23; wire memory_reg_rw_l1_net_24; wire memory_reg_rw_l1_net_25; wire memory_reg_rw_l1_net_26; wire memory_reg_rw_l1_net_27; wire memory_reg_rw_l1_net_28; wire memory_reg_rw_l1_net_29; wire memory_reg_rw_l1_net_3; wire memory_reg_rw_l1_net_30; wire memory_reg_rw_l1_net_31; wire memory_reg_rw_l1_net_32; wire memory_reg_rw_l1_net_33; wire memory_reg_rw_l1_net_34; wire memory_reg_rw_l1_net_35; wire memory_reg_rw_l1_net_36; wire memory_reg_rw_l1_net_37; wire memory_reg_rw_l1_net_38; wire memory_reg_rw_l1_net_39; wire memory_reg_rw_l1_net_4; wire memory_reg_rw_l1_net_40; wire memory_reg_rw_l1_net_41; wire memory_reg_rw_l1_net_42; wire memory_reg_rw_l1_net_43; wire memory_reg_rw_l1_net_44; wire memory_reg_rw_l1_net_45; wire memory_reg_rw_l1_net_46; wire memory_reg_rw_l1_net_47; wire memory_reg_rw_l1_net_48; wire memory_reg_rw_l1_net_49; wire memory_reg_rw_l1_net_5; wire memory_reg_rw_l1_net_50; wire memory_reg_rw_l1_net_51; wire memory_reg_rw_l1_net_52; wire memory_reg_rw_l1_net_53; wire memory_reg_rw_l1_net_54; wire memory_reg_rw_l1_net_55; wire memory_reg_rw_l1_net_56; wire memory_reg_rw_l1_net_57; wire memory_reg_rw_l1_net_58; wire memory_reg_rw_l1_net_59; wire memory_reg_rw_l1_net_6; wire memory_reg_rw_l1_net_60; wire memory_reg_rw_l1_net_61; wire memory_reg_rw_l1_net_62; wire memory_reg_rw_l1_net_63; wire memory_reg_rw_l1_net_64; wire memory_reg_rw_l1_net_65; wire memory_reg_rw_l1_net_66; wire memory_reg_rw_l1_net_67; wire memory_reg_rw_l1_net_68; wire memory_reg_rw_l1_net_69; wire memory_reg_rw_l1_net_7; wire memory_reg_rw_l1_net_70; wire memory_reg_rw_l1_net_71; wire memory_reg_rw_l1_net_72; wire memory_reg_rw_l1_net_73; wire memory_reg_rw_l1_net_74; wire memory_reg_rw_l1_net_75; wire memory_reg_rw_l1_net_76; wire memory_reg_rw_l1_net_77; wire memory_reg_rw_l1_net_78; wire memory_reg_rw_l1_net_79; wire memory_reg_rw_l1_net_8; wire memory_reg_rw_l1_net_80; wire memory_reg_rw_l1_net_81; wire memory_reg_rw_l1_net_82; wire memory_reg_rw_l1_net_83; wire memory_reg_rw_l1_net_84; wire memory_reg_rw_l1_net_85; wire memory_reg_rw_l1_net_86; wire memory_reg_rw_l1_net_87; wire memory_reg_rw_l1_net_88; wire memory_reg_rw_l1_net_89; wire memory_reg_rw_l1_net_9; wire memory_reg_rw_l1_net_90; wire memory_reg_rw_l1_net_91; wire memory_reg_rw_l1_net_92; wire memory_reg_rw_l1_net_93; wire memory_reg_rw_l1_net_94; wire memory_reg_rw_l1_net_95; wire memory_reg_rw_l1_net_96; wire memory_reg_rw_l1_net_97; wire memory_reg_rw_l1_net_98; wire memory_reg_rw_l1_net_99; wire \mr_tst_out[tst_control_tmaena] ; wire [3:0]\mr_tst_out[tst_dest_tst_mtgt] ; wire [0:0]\mr_tst_out[tst_wdata_tst_wdata] ; wire \r_data[13]_i_4__0_n_0 ; wire \r_data[18]_i_3__0_n_0 ; wire \r_data[18]_i_4_n_0 ; wire \r_data_reg[0] ; wire \r_data_reg[0]_0 ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[17] ; wire \r_data_reg[18] ; wire \r_data_reg[18]_i_2_n_0 ; wire \r_data_reg[19] ; wire \r_data_reg[20] ; wire \r_data_reg[21] ; wire \r_data_reg[22] ; wire \r_data_reg[23] ; wire \r_data_reg[24] ; wire \r_data_reg[24]_0 ; wire \r_data_reg[25] ; wire \r_data_reg[26] ; wire \r_data_reg[27] ; wire \r_data_reg[28] ; wire \r_data_reg[29] ; wire \r_data_reg[30] ; wire \r_data_reg[31] ; wire [31:0]rxb_port_b_data_out_i; wire [0:0]sbe_IBUF; wire [31:0]txtb_port_b_data_out_i; wire [31:0]txtb_port_b_data_out_i_6; wire [31:0]txtb_port_b_data_out_i_7; wire [31:0]txtb_port_b_data_out_i_8; wire wr_en_2; assign \g_bit[0].reg_value_r_reg[0]_0 = memory_reg_rw_l1_net_10; assign \g_bit[0].reg_value_r_reg[0]_2 = memory_reg_rw_l1_net_2; assign \g_bit[0].reg_value_r_reg[0]_3 = memory_reg_rw_l1_net_1; assign \g_bit[0].reg_value_r_reg[0]_4 = memory_reg_rw_l1_net_3; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_2), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[0]), .Q(\mr_tst_out[tst_dest_tst_mtgt] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_2), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[1]), .Q(\mr_tst_out[tst_dest_tst_mtgt] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_2), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[2]), .Q(\mr_tst_out[tst_dest_tst_mtgt] [2])); FDCE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en_2), .CLR(\g_bit[3].reg_value_r_reg[3]_0 ), .D(data_in_IBUF[3]), .Q(\mr_tst_out[tst_dest_tst_mtgt] [3])); (* SOFT_HLUTNM = "soft_lutpair287" *) LUT5 #( .INIT(32'h00000008)) \g_ram_rst_false.ram_memory_reg_i_44 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I1(\mr_tst_out[tst_control_tmaena] ), .I2(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT2 #( .INIT(4'h1)) memory_reg_rw_l1_LUT2 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [1]), .O(memory_reg_rw_l1_net_8)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT2 #( .INIT(4'h1)) memory_reg_rw_l1_LUT2_1 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [1]), .O(memory_reg_rw_l1_net_6)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT2 #( .INIT(4'h1)) memory_reg_rw_l1_LUT2_2 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [2]), .O(memory_reg_rw_l1_net_13)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'hD8)) memory_reg_rw_l1_LUT3 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .O(memory_reg_rw_l1_net)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'h08)) memory_reg_rw_l1_LUT3_1 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_5)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'h4C)) memory_reg_rw_l1_LUT3_2 (.I0(txtb_port_b_data_out_i_7[28]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I2(memory_reg_rw_l1_net_1), .O(memory_reg_rw_l1_net_26)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'h20)) memory_reg_rw_l1_LUT3_3 (.I0(rxb_port_b_data_out_i[16]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I2(\g_bit[0].reg_value_r_reg[0]_1 ), .O(memory_reg_rw_l1_net_41)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT3 #( .INIT(8'h80)) memory_reg_rw_l1_LUT3_4 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[24]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .O(memory_reg_rw_l1_net_66)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'hF044)) memory_reg_rw_l1_LUT4 (.I0(\g_ram_rst_false.ram_memory_reg_14 ), .I1(\g_ram_rst_false.ram_memory_reg_15 ), .I2(\mr_tst_out[tst_wdata_tst_wdata] ), .I3(\g_bit[0].reg_value_r_reg[0]_1 ), .O(DIADI)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h8F00)) memory_reg_rw_l1_LUT4_1 (.I0(txtb_port_b_data_out_i_8[0]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_4), .I3(memory_reg_rw_l1_net_5), .O(memory_reg_rw_l1_net_7)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'hB030)) memory_reg_rw_l1_LUT4_2 (.I0(txtb_port_b_data_out_i[28]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_5), .I3(memory_reg_rw_l1_net_10), .O(memory_reg_rw_l1_net_28)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h153F)) memory_reg_rw_l1_LUT4_3 (.I0(txtb_port_b_data_out_i_6[31]), .I1(txtb_port_b_data_out_i_8[31]), .I2(memory_reg_rw_l1_net_3), .I3(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_38)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h153F)) memory_reg_rw_l1_LUT4_4 (.I0(txtb_port_b_data_out_i[17]), .I1(txtb_port_b_data_out_i_6[17]), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_10), .O(memory_reg_rw_l1_net_45)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h153F)) memory_reg_rw_l1_LUT4_5 (.I0(txtb_port_b_data_out_i[18]), .I1(txtb_port_b_data_out_i_6[18]), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_10), .O(\r_data[18]_i_3__0_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'hDFCC)) memory_reg_rw_l1_LUT4_6 (.I0(txtb_port_b_data_out_i_8[18]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [3]), .I2(memory_reg_rw_l1_net_3), .I3(memory_reg_rw_l1_net_47), .O(\r_data[18]_i_4_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h153F)) memory_reg_rw_l1_LUT4_7 (.I0(txtb_port_b_data_out_i_7[19]), .I1(txtb_port_b_data_out_i_8[19]), .I2(memory_reg_rw_l1_net_3), .I3(memory_reg_rw_l1_net_1), .O(memory_reg_rw_l1_net_50)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h8F00)) memory_reg_rw_l1_LUT4_8 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I1(\g_bit[0].reg_value_r_reg[0]_1 ), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_5), .O(memory_reg_rw_l1_net_48)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h153F)) memory_reg_rw_l1_LUT4_9 (.I0(txtb_port_b_data_out_i_6[12]), .I1(txtb_port_b_data_out_i_7[12]), .I2(memory_reg_rw_l1_net_1), .I3(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_75)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00000080)) memory_reg_rw_l1_LUT5 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_3)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00000800)) memory_reg_rw_l1_LUT5_1 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_1)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0804000)) memory_reg_rw_l1_LUT5_10 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[26] ), .I4(memory_reg_rw_l1_net_21), .O(D[11])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00FF007F)) memory_reg_rw_l1_LUT5_11 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[27]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_23)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0804000)) memory_reg_rw_l1_LUT5_12 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[27] ), .I4(memory_reg_rw_l1_net_25), .O(D[12])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0C04000)) memory_reg_rw_l1_LUT5_13 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[28] ), .I4(memory_reg_rw_l1_net_29), .O(D[13])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00FF007F)) memory_reg_rw_l1_LUT5_14 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[29]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_31)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0804000)) memory_reg_rw_l1_LUT5_15 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[29] ), .I4(memory_reg_rw_l1_net_33), .O(D[14])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00FF007F)) memory_reg_rw_l1_LUT5_16 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[30]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_35)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0804000)) memory_reg_rw_l1_LUT5_17 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[30] ), .I4(memory_reg_rw_l1_net_37), .O(D[15])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h153F0000)) memory_reg_rw_l1_LUT5_18 (.I0(txtb_port_b_data_out_i[31]), .I1(txtb_port_b_data_out_i_7[31]), .I2(memory_reg_rw_l1_net_1), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_38), .O(memory_reg_rw_l1_net_39)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h7FFF0000)) memory_reg_rw_l1_LUT5_19 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[31]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_39), .O(memory_reg_rw_l1_net_40)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00000200)) memory_reg_rw_l1_LUT5_2 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_2)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h3133F5FF)) memory_reg_rw_l1_LUT5_20 (.I0(rxb_port_b_data_out_i[17]), .I1(txtb_port_b_data_out_i_7[17]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I3(\g_bit[0].reg_value_r_reg[0]_1 ), .I4(memory_reg_rw_l1_net_1), .O(memory_reg_rw_l1_net_44)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h13335FFF)) memory_reg_rw_l1_LUT5_21 (.I0(rxb_port_b_data_out_i[18]), .I1(txtb_port_b_data_out_i_7[18]), .I2(\g_bit[0].reg_value_r_reg[0]_1 ), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_1), .O(memory_reg_rw_l1_net_47)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hB0300000)) memory_reg_rw_l1_LUT5_22 (.I0(txtb_port_b_data_out_i_8[18]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I2(\g_bit[0].reg_value_r_reg[0]_1 ), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_5), .O(memory_reg_rw_l1_net_49)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h000080FF)) memory_reg_rw_l1_LUT5_23 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[20]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_54), .O(memory_reg_rw_l1_net_55)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0C04000)) memory_reg_rw_l1_LUT5_24 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[20] ), .I4(memory_reg_rw_l1_net_55), .O(D[5])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h45CF44CC)) memory_reg_rw_l1_LUT5_25 (.I0(txtb_port_b_data_out_i[21]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_56), .O(memory_reg_rw_l1_net_57)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h80FF0000)) memory_reg_rw_l1_LUT5_26 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[21]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_5), .O(memory_reg_rw_l1_net_58)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00FF007F)) memory_reg_rw_l1_LUT5_27 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[22]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_60)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0804000)) memory_reg_rw_l1_LUT5_28 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[22] ), .I4(memory_reg_rw_l1_net_62), .O(D[7])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h45CF44CC)) memory_reg_rw_l1_LUT5_29 (.I0(txtb_port_b_data_out_i[23]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_63), .O(memory_reg_rw_l1_net_64)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h80FF0000)) memory_reg_rw_l1_LUT5_3 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_7), .O(memory_reg_rw_l1_net_9)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h80FF0000)) memory_reg_rw_l1_LUT5_30 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[23]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_5), .O(memory_reg_rw_l1_net_65)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_31 (.I0(txtb_port_b_data_out_i_6[1]), .I1(txtb_port_b_data_out_i_7[1]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_69)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_32 (.I0(txtb_port_b_data_out_i_8[1]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_69), .O(memory_reg_rw_l1_net_70)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_33 (.I0(txtb_port_b_data_out_i_6[2]), .I1(txtb_port_b_data_out_i_7[2]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_71)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_34 (.I0(txtb_port_b_data_out_i_8[2]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_71), .O(memory_reg_rw_l1_net_72)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_35 (.I0(txtb_port_b_data_out_i_6[3]), .I1(txtb_port_b_data_out_i_8[3]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_73)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h4CFFFFFF)) memory_reg_rw_l1_LUT5_36 (.I0(txtb_port_b_data_out_i[3]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_74), .O(\g_ram_rst_false.ram_memory_reg_1 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h80FF0000)) memory_reg_rw_l1_LUT5_37 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[13]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_5), .O(memory_reg_rw_l1_net_79)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_38 (.I0(txtb_port_b_data_out_i_6[14]), .I1(txtb_port_b_data_out_i_7[14]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_80)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_39 (.I0(txtb_port_b_data_out_i_8[14]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_80), .O(memory_reg_rw_l1_net_81)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00000020)) memory_reg_rw_l1_LUT5_4 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_10)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_40 (.I0(txtb_port_b_data_out_i_6[15]), .I1(txtb_port_b_data_out_i_7[15]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_82)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_41 (.I0(txtb_port_b_data_out_i_8[15]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_82), .O(memory_reg_rw_l1_net_83)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_42 (.I0(txtb_port_b_data_out_i_6[4]), .I1(txtb_port_b_data_out_i_7[4]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_84)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_43 (.I0(txtb_port_b_data_out_i_8[4]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_84), .O(memory_reg_rw_l1_net_85)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_44 (.I0(txtb_port_b_data_out_i_6[5]), .I1(txtb_port_b_data_out_i_7[5]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_86)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_45 (.I0(txtb_port_b_data_out_i_8[5]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_86), .O(memory_reg_rw_l1_net_87)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_46 (.I0(txtb_port_b_data_out_i_6[6]), .I1(txtb_port_b_data_out_i_7[6]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_88)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_47 (.I0(txtb_port_b_data_out_i_8[6]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_88), .O(memory_reg_rw_l1_net_89)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_48 (.I0(txtb_port_b_data_out_i_6[7]), .I1(txtb_port_b_data_out_i_7[7]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_90)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_49 (.I0(txtb_port_b_data_out_i_8[7]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_90), .O(memory_reg_rw_l1_net_91)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h76325410)) memory_reg_rw_l1_LUT5_5 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\mr_tst_out[tst_control_tmaena] ), .I3(\r_data_reg[0] ), .I4(\r_data_reg[0]_0 ), .O(memory_reg_rw_l1_net_11)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_50 (.I0(txtb_port_b_data_out_i_6[8]), .I1(txtb_port_b_data_out_i_7[8]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_92)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_51 (.I0(txtb_port_b_data_out_i_8[8]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_92), .O(memory_reg_rw_l1_net_93)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_52 (.I0(txtb_port_b_data_out_i_6[9]), .I1(txtb_port_b_data_out_i_8[9]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_94)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h4CFFFFFF)) memory_reg_rw_l1_LUT5_53 (.I0(txtb_port_b_data_out_i[9]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_95), .O(\g_ram_rst_false.ram_memory_reg_7 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_54 (.I0(txtb_port_b_data_out_i_6[10]), .I1(txtb_port_b_data_out_i_7[10]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_96)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_55 (.I0(txtb_port_b_data_out_i_8[10]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_96), .O(memory_reg_rw_l1_net_97)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h0105030F)) memory_reg_rw_l1_LUT5_56 (.I0(txtb_port_b_data_out_i_6[11]), .I1(txtb_port_b_data_out_i_7[11]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_98)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h77770700)) memory_reg_rw_l1_LUT5_57 (.I0(txtb_port_b_data_out_i_8[11]), .I1(memory_reg_rw_l1_net_3), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_13), .I4(memory_reg_rw_l1_net_98), .O(memory_reg_rw_l1_net_99)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00010000)) memory_reg_rw_l1_LUT5_6 (.I0(adress_IBUF[2]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(adress_IBUF[5]), .I4(sbe_IBUF), .O(memory_reg_rw_l1_net_12)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00FF007F)) memory_reg_rw_l1_LUT5_7 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[25]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_15)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hC0804000)) memory_reg_rw_l1_LUT5_8 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[25] ), .I4(memory_reg_rw_l1_net_17), .O(D[10])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00FF007F)) memory_reg_rw_l1_LUT5_9 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[26]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .O(memory_reg_rw_l1_net_19)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h55005500FF30FFF0)) memory_reg_rw_l1_LUT6 (.I0(txtb_port_b_data_out_i_6[0]), .I1(txtb_port_b_data_out_i_7[0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_4)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFFFB03000000000)) memory_reg_rw_l1_LUT6_1 (.I0(txtb_port_b_data_out_i[0]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_9), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_11), .I5(memory_reg_rw_l1_net_12), .O(D[0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000F0F0FEFC)) memory_reg_rw_l1_LUT6_10 (.I0(txtb_port_b_data_out_i[27]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_23), .I5(memory_reg_rw_l1_net_24), .O(memory_reg_rw_l1_net_25)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h55557F7F15003F00)) memory_reg_rw_l1_LUT6_11 (.I0(txtb_port_b_data_out_i_6[28]), .I1(txtb_port_b_data_out_i_8[28]), .I2(memory_reg_rw_l1_net_3), .I3(memory_reg_rw_l1_net), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_26), .O(memory_reg_rw_l1_net_27)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000080FF00000000)) memory_reg_rw_l1_LUT6_12 (.I0(\mr_tst_out[tst_control_tmaena] ), .I1(rxb_port_b_data_out_i[28]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_6), .I4(memory_reg_rw_l1_net_27), .I5(memory_reg_rw_l1_net_28), .O(memory_reg_rw_l1_net_29)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_13 (.I0(txtb_port_b_data_out_i_7[29]), .I1(txtb_port_b_data_out_i_8[29]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_30)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_14 (.I0(txtb_port_b_data_out_i_6[29]), .I1(txtb_port_b_data_out_i_8[29]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_30), .O(memory_reg_rw_l1_net_32)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000F0F0FEFC)) memory_reg_rw_l1_LUT6_15 (.I0(txtb_port_b_data_out_i[29]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_31), .I5(memory_reg_rw_l1_net_32), .O(memory_reg_rw_l1_net_33)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_16 (.I0(txtb_port_b_data_out_i_7[30]), .I1(txtb_port_b_data_out_i_8[30]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_34)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_17 (.I0(txtb_port_b_data_out_i_6[30]), .I1(txtb_port_b_data_out_i_8[30]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_34), .O(memory_reg_rw_l1_net_36)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000F0F0FEFC)) memory_reg_rw_l1_LUT6_18 (.I0(txtb_port_b_data_out_i[30]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_35), .I5(memory_reg_rw_l1_net_36), .O(memory_reg_rw_l1_net_37)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h400040004000C080)) memory_reg_rw_l1_LUT6_19 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[31] ), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .I5(memory_reg_rw_l1_net_40), .O(D[16])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_2 (.I0(txtb_port_b_data_out_i_7[25]), .I1(txtb_port_b_data_out_i_8[25]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_14)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0000000002220AAA)) memory_reg_rw_l1_LUT6_20 (.I0(adress_IBUF[1]), .I1(txtb_port_b_data_out_i_7[16]), .I2(txtb_port_b_data_out_i_8[16]), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_41), .O(memory_reg_rw_l1_net_42)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h115533FF0105030F)) memory_reg_rw_l1_LUT6_21 (.I0(txtb_port_b_data_out_i[16]), .I1(txtb_port_b_data_out_i_6[16]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I3(memory_reg_rw_l1_net_2), .I4(memory_reg_rw_l1_net_10), .I5(memory_reg_rw_l1_net_42), .O(memory_reg_rw_l1_net_43)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h40004000E0A0C080)) memory_reg_rw_l1_LUT6_22 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[16]_0 ), .I4(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I5(memory_reg_rw_l1_net_43), .O(D[1])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h8000CC00FF00FF00)) memory_reg_rw_l1_LUT6_23 (.I0(txtb_port_b_data_out_i_8[17]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(memory_reg_rw_l1_net_3), .I3(memory_reg_rw_l1_net_5), .I4(memory_reg_rw_l1_net_44), .I5(memory_reg_rw_l1_net_45), .O(memory_reg_rw_l1_net_46)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0F0F0F060204000)) memory_reg_rw_l1_LUT6_24 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[17] ), .I4(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I5(memory_reg_rw_l1_net_46), .O(D[2])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h60204000E0A0C080)) memory_reg_rw_l1_LUT6_25 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[18] ), .I4(\mr_tst_out[tst_dest_tst_mtgt] [2]), .I5(\r_data_reg[18]_i_2_n_0 ), .O(D[3])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h8A0A0000CF0F0000)) memory_reg_rw_l1_LUT6_26 (.I0(rxb_port_b_data_out_i[19]), .I1(txtb_port_b_data_out_i[19]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_48), .I5(memory_reg_rw_l1_net_49), .O(memory_reg_rw_l1_net_51)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFEFCFFFF00000000)) memory_reg_rw_l1_LUT6_27 (.I0(txtb_port_b_data_out_i_6[19]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_2), .I4(memory_reg_rw_l1_net_50), .I5(memory_reg_rw_l1_net_51), .O(memory_reg_rw_l1_net_52)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0F0F0F060204000)) memory_reg_rw_l1_LUT6_28 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[19] ), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .I5(memory_reg_rw_l1_net_52), .O(D[4])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0111055503330FFF)) memory_reg_rw_l1_LUT6_29 (.I0(txtb_port_b_data_out_i_6[20]), .I1(txtb_port_b_data_out_i_7[20]), .I2(txtb_port_b_data_out_i_8[20]), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_53)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_3 (.I0(txtb_port_b_data_out_i_6[25]), .I1(txtb_port_b_data_out_i_8[25]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_14), .O(memory_reg_rw_l1_net_16)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h45FFCFFF44FFCCFF)) memory_reg_rw_l1_LUT6_30 (.I0(txtb_port_b_data_out_i[20]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_5), .I4(memory_reg_rw_l1_net_10), .I5(memory_reg_rw_l1_net_53), .O(memory_reg_rw_l1_net_54)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0111055503330FFF)) memory_reg_rw_l1_LUT6_31 (.I0(txtb_port_b_data_out_i_6[21]), .I1(txtb_port_b_data_out_i_7[21]), .I2(txtb_port_b_data_out_i_8[21]), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_56)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h4000C0C040004000)) memory_reg_rw_l1_LUT6_32 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[21] ), .I4(memory_reg_rw_l1_net_57), .I5(memory_reg_rw_l1_net_58), .O(D[6])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_33 (.I0(txtb_port_b_data_out_i_7[22]), .I1(txtb_port_b_data_out_i_8[22]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_59)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_34 (.I0(txtb_port_b_data_out_i_6[22]), .I1(txtb_port_b_data_out_i_8[22]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_59), .O(memory_reg_rw_l1_net_61)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000F0F0FEFC)) memory_reg_rw_l1_LUT6_35 (.I0(txtb_port_b_data_out_i[22]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_60), .I5(memory_reg_rw_l1_net_61), .O(memory_reg_rw_l1_net_62)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0111055503330FFF)) memory_reg_rw_l1_LUT6_36 (.I0(txtb_port_b_data_out_i_6[23]), .I1(txtb_port_b_data_out_i_7[23]), .I2(txtb_port_b_data_out_i_8[23]), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_63)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h4000C0C040004000)) memory_reg_rw_l1_LUT6_37 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[16] ), .I3(\r_data_reg[23] ), .I4(memory_reg_rw_l1_net_64), .I5(memory_reg_rw_l1_net_65), .O(D[8])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0111055503330FFF)) memory_reg_rw_l1_LUT6_38 (.I0(txtb_port_b_data_out_i_6[24]), .I1(txtb_port_b_data_out_i_7[24]), .I2(txtb_port_b_data_out_i_8[24]), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_2), .O(memory_reg_rw_l1_net_67)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h45CFF5FF44CCF4FC)) memory_reg_rw_l1_LUT6_39 (.I0(txtb_port_b_data_out_i[24]), .I1(memory_reg_rw_l1_net_8), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_66), .I5(memory_reg_rw_l1_net_67), .O(memory_reg_rw_l1_net_68)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000F0F0FEFC)) memory_reg_rw_l1_LUT6_4 (.I0(txtb_port_b_data_out_i[25]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_15), .I5(memory_reg_rw_l1_net_16), .O(memory_reg_rw_l1_net_17)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h400040004000C080)) memory_reg_rw_l1_LUT6_40 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .I2(\r_data_reg[24] ), .I3(\r_data_reg[24]_0 ), .I4(\mr_tst_out[tst_dest_tst_mtgt] [3]), .I5(memory_reg_rw_l1_net_68), .O(D[9])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h8000C000AA00FF00)) memory_reg_rw_l1_LUT6_41 (.I0(rxb_port_b_data_out_i[1]), .I1(txtb_port_b_data_out_i[1]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_70), .O(\g_ram_rst_false.ram_memory_reg )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_42 (.I0(rxb_port_b_data_out_i[2]), .I1(txtb_port_b_data_out_i[2]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_72), .O(\g_ram_rst_false.ram_memory_reg_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hA8A0FCF0AAAAFFFF)) memory_reg_rw_l1_LUT6_43 (.I0(rxb_port_b_data_out_i[3]), .I1(txtb_port_b_data_out_i_7[3]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_73), .O(memory_reg_rw_l1_net_74)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h153F1133050F0000)) memory_reg_rw_l1_LUT6_44 (.I0(txtb_port_b_data_out_i[12]), .I1(memory_reg_rw_l1_net_6), .I2(memory_reg_rw_l1_net_2), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_13), .I5(memory_reg_rw_l1_net_75), .O(memory_reg_rw_l1_net_76)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_45 (.I0(rxb_port_b_data_out_i[12]), .I1(txtb_port_b_data_out_i_8[12]), .I2(memory_reg_rw_l1_net_3), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_76), .O(\g_ram_rst_false.ram_memory_reg_10 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_46 (.I0(txtb_port_b_data_out_i_7[13]), .I1(txtb_port_b_data_out_i_8[13]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_77)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_47 (.I0(txtb_port_b_data_out_i_6[13]), .I1(txtb_port_b_data_out_i_8[13]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_77), .O(memory_reg_rw_l1_net_78)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFFF505CFFFFFFFF)) memory_reg_rw_l1_LUT6_48 (.I0(txtb_port_b_data_out_i[13]), .I1(memory_reg_rw_l1_net_9), .I2(memory_reg_rw_l1_net_10), .I3(\r_data[13]_i_4__0_n_0 ), .I4(memory_reg_rw_l1_net_78), .I5(memory_reg_rw_l1_net_79), .O(\g_ram_rst_false.ram_memory_reg_11 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_49 (.I0(rxb_port_b_data_out_i[14]), .I1(txtb_port_b_data_out_i[14]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_81), .O(\g_ram_rst_false.ram_memory_reg_12 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_5 (.I0(txtb_port_b_data_out_i_7[26]), .I1(txtb_port_b_data_out_i_8[26]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_18)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h8000C000AA00FF00)) memory_reg_rw_l1_LUT6_50 (.I0(rxb_port_b_data_out_i[15]), .I1(txtb_port_b_data_out_i[15]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_83), .O(\g_ram_rst_false.ram_memory_reg_13 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_51 (.I0(rxb_port_b_data_out_i[4]), .I1(txtb_port_b_data_out_i[4]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_85), .O(\g_ram_rst_false.ram_memory_reg_2 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_52 (.I0(rxb_port_b_data_out_i[5]), .I1(txtb_port_b_data_out_i[5]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_87), .O(\g_ram_rst_false.ram_memory_reg_3 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_53 (.I0(rxb_port_b_data_out_i[6]), .I1(txtb_port_b_data_out_i[6]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_89), .O(\g_ram_rst_false.ram_memory_reg_4 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h8000C000AA00FF00)) memory_reg_rw_l1_LUT6_54 (.I0(rxb_port_b_data_out_i[7]), .I1(txtb_port_b_data_out_i[7]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_91), .O(\g_ram_rst_false.ram_memory_reg_5 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_55 (.I0(rxb_port_b_data_out_i[8]), .I1(txtb_port_b_data_out_i[8]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_93), .O(\g_ram_rst_false.ram_memory_reg_6 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hA8A0FCF0AAAAFFFF)) memory_reg_rw_l1_LUT6_56 (.I0(rxb_port_b_data_out_i[9]), .I1(txtb_port_b_data_out_i_7[9]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_1), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_94), .O(memory_reg_rw_l1_net_95)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_57 (.I0(rxb_port_b_data_out_i[10]), .I1(txtb_port_b_data_out_i[10]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_97), .O(\g_ram_rst_false.ram_memory_reg_8 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h7FFF3FFF55FF00FF)) memory_reg_rw_l1_LUT6_58 (.I0(rxb_port_b_data_out_i[11]), .I1(txtb_port_b_data_out_i[11]), .I2(memory_reg_rw_l1_net_10), .I3(memory_reg_rw_l1_net_48), .I4(memory_reg_rw_l1_net_49), .I5(memory_reg_rw_l1_net_99), .O(\g_ram_rst_false.ram_memory_reg_9 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_6 (.I0(txtb_port_b_data_out_i_6[26]), .I1(txtb_port_b_data_out_i_8[26]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_18), .O(memory_reg_rw_l1_net_20)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000F0F0FEFC)) memory_reg_rw_l1_LUT6_7 (.I0(txtb_port_b_data_out_i[26]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I2(\mr_tst_out[tst_dest_tst_mtgt] [1]), .I3(memory_reg_rw_l1_net_10), .I4(memory_reg_rw_l1_net_19), .I5(memory_reg_rw_l1_net_20), .O(memory_reg_rw_l1_net_21)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000FEFAFCF0)) memory_reg_rw_l1_LUT6_8 (.I0(txtb_port_b_data_out_i_7[27]), .I1(txtb_port_b_data_out_i_8[27]), .I2(memory_reg_rw_l1_net_6), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_1), .I5(memory_reg_rw_l1_net_13), .O(memory_reg_rw_l1_net_22)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h000000000505070F)) memory_reg_rw_l1_LUT6_9 (.I0(txtb_port_b_data_out_i_6[27]), .I1(txtb_port_b_data_out_i_8[27]), .I2(memory_reg_rw_l1_net_8), .I3(memory_reg_rw_l1_net_3), .I4(memory_reg_rw_l1_net_2), .I5(memory_reg_rw_l1_net_22), .O(memory_reg_rw_l1_net_24)); (* SOFT_HLUTNM = "soft_lutpair287" *) LUT2 #( .INIT(4'hE)) \r_data[13]_i_4__0 (.I0(\mr_tst_out[tst_dest_tst_mtgt] [0]), .I1(\mr_tst_out[tst_dest_tst_mtgt] [1]), .O(\r_data[13]_i_4__0_n_0 )); MUXF7 \r_data_reg[18]_i_2 (.I0(\r_data[18]_i_3__0_n_0 ), .I1(\r_data[18]_i_4_n_0 ), .O(\r_data_reg[18]_i_2_n_0 ), .S(\mr_tst_out[tst_dest_tst_mtgt] [0])); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized5 (DI, \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[0].reg_value_r_reg[0]_0 , CO, neg_phase_err, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[1].reg_value_r_reg[1]_1 , adress_IBUF, \r_data[15]_i_3__0 , \r_data[15]_i_3__0_0 , \r_data[14]_i_4__0 , \r_data_reg[13] , i__carry_i_8__3, S, i__carry_i_10__0_0); output [2:0]DI; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output [0:0]CO; output [3:0]neg_phase_err; input wr_en; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[1].reg_value_r_reg[1]_1 ; input [2:0]adress_IBUF; input [2:0]\r_data[15]_i_3__0 ; input \r_data[15]_i_3__0_0 ; input \r_data[14]_i_4__0 ; input \r_data_reg[13] ; input [0:0]i__carry_i_8__3; input [0:0]S; input [2:0]i__carry_i_10__0_0; wire [0:0]CO; wire [2:0]DI; wire [0:0]S; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[1].reg_value_r_reg[1]_1 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire [2:0]i__carry_i_10__0_0; wire i__carry_i_19__0_n_0; wire i__carry_i_20_n_0; wire i__carry_i_21_n_0; wire [0:0]i__carry_i_8__3; wire [3:0]neg_phase_err; wire \r_data[14]_i_4__0 ; wire [2:0]\r_data[15]_i_3__0 ; wire \r_data[15]_i_3__0_0 ; wire \r_data_reg[13] ; wire wr_en; wire [2:0]NLW_i__carry_i_10__0_CO_UNCONNECTED; FDPE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[0]), .PRE(\g_bit[1].reg_value_r_reg[1]_1 ), .Q(DI[0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[1].reg_value_r_reg[1]_1 ), .D(data_in_IBUF[1]), .Q(DI[1])); FDPE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[2]), .PRE(\g_bit[1].reg_value_r_reg[1]_1 ), .Q(DI[2])); (* ADDER_THRESHOLD = "35" *) CARRY4 i__carry_i_10__0 (.CI(1'b0), .CO({CO,NLW_i__carry_i_10__0_CO_UNCONNECTED[2:0]}), .CYINIT(1'b1), .DI({i__carry_i_8__3,DI}), .O(neg_phase_err), .S({S,i__carry_i_19__0_n_0,i__carry_i_20_n_0,i__carry_i_21_n_0})); LUT2 #( .INIT(4'h9)) i__carry_i_19__0 (.I0(DI[2]), .I1(i__carry_i_10__0_0[2]), .O(i__carry_i_19__0_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_20 (.I0(DI[1]), .I1(i__carry_i_10__0_0[1]), .O(i__carry_i_20_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_21 (.I0(DI[0]), .I1(i__carry_i_10__0_0[0]), .O(i__carry_i_21_n_0)); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[13]_i_3 (.I0(DI[0]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\r_data[15]_i_3__0 [0]), .I4(\r_data_reg[13] ), .I5(adress_IBUF[2]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[14]_i_7 (.I0(DI[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\r_data[15]_i_3__0 [1]), .I4(\r_data[14]_i_4__0 ), .I5(adress_IBUF[2]), .O(\g_bit[1].reg_value_r_reg[1]_0 )); LUT6 #( .INIT(64'h00000000F8C83808)) \r_data[15]_i_7 (.I0(DI[2]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\r_data[15]_i_3__0 [2]), .I4(\r_data[15]_i_3__0_0 ), .I5(adress_IBUF[2]), .O(\g_bit[2].reg_value_r_reg[2]_0 )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized7 (\g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[2].reg_value_r_reg[2]_0 , \tq_counter_q_reg[6] , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[2].reg_value_r_reg[2]_1 , adress_IBUF, \r_data_reg[25] , \mr_ctrl_out[btr_fd_brp_fd] , \r_data_reg[26] , \segm_counter_q_reg[0] , \segm_counter_q_reg[0]_0 , \segm_counter_q_reg[0]_1 ); output [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \tq_counter_q_reg[6] ; input wr_en; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[2].reg_value_r_reg[2]_1 ; input [3:0]adress_IBUF; input \r_data_reg[25] ; input [1:0]\mr_ctrl_out[btr_fd_brp_fd] ; input [1:0]\r_data_reg[26] ; input [1:0]\segm_counter_q_reg[0] ; input \segm_counter_q_reg[0]_0 ; input \segm_counter_q_reg[0]_1 ; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire [7:6]\mr_ctrl_out[btr_brp] ; wire [1:0]\mr_ctrl_out[btr_fd_brp_fd] ; wire \r_data[25]_i_6_n_0 ; wire \r_data_reg[25] ; wire [1:0]\r_data_reg[26] ; wire [1:0]\segm_counter_q_reg[0] ; wire \segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire \tq_counter_q_reg[6] ; wire wr_en; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_1 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_1 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[btr_brp] [6])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_1 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_brp] [7])); LUT6 #( .INIT(64'hBBBBBBBBB8B8BBB8)) \r_data[25]_i_3 (.I0(\r_data[25]_i_6_n_0 ), .I1(adress_IBUF[3]), .I2(adress_IBUF[2]), .I3(adress_IBUF[0]), .I4(\r_data_reg[25] ), .I5(adress_IBUF[1]), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[25]_i_6 (.I0(\mr_ctrl_out[btr_brp] [6]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [0]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[26] [0]), .O(\r_data[25]_i_6_n_0 )); LUT6 #( .INIT(64'hF0FFF53FFFFFF53F)) \r_data[26]_i_4 (.I0(\mr_ctrl_out[btr_brp] [7]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [1]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(adress_IBUF[2]), .I5(\r_data_reg[26] [1]), .O(\g_bit[2].reg_value_r_reg[2]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFF6FF6)) \segm_counter_q[7]_i_4 (.I0(\segm_counter_q_reg[0] [0]), .I1(\mr_ctrl_out[btr_brp] [6]), .I2(\segm_counter_q_reg[0] [1]), .I3(\mr_ctrl_out[btr_brp] [7]), .I4(\segm_counter_q_reg[0]_0 ), .I5(\segm_counter_q_reg[0]_1 ), .O(\tq_counter_q_reg[6] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized7_6 (\mr_ctrl_out[btr_fd_brp_fd] , \g_bit[0].reg_value_r_reg[0]_0 , \tq_counter_q_reg[7] , \g_bit[0].reg_value_r_reg[0]_1 , data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[1].reg_value_r_reg[1]_0 , adress_IBUF, \r_data[24]_i_3__0 , \segm_counter_q_reg[0] , \segm_counter_q_reg[0]_0 , \segm_counter_q_reg[0]_1 ); output [2:0]\mr_ctrl_out[btr_fd_brp_fd] ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \tq_counter_q_reg[7] ; input \g_bit[0].reg_value_r_reg[0]_1 ; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[1].reg_value_r_reg[1]_0 ; input [2:0]adress_IBUF; input [0:0]\r_data[24]_i_3__0 ; input [1:0]\segm_counter_q_reg[0] ; input \segm_counter_q_reg[0]_0 ; input \segm_counter_q_reg[0]_1 ; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire [2:0]\mr_ctrl_out[btr_fd_brp_fd] ; wire [0:0]\r_data[24]_i_3__0 ; wire [1:0]\segm_counter_q_reg[0] ; wire \segm_counter_q_reg[0]_0 ; wire \segm_counter_q_reg[0]_1 ; wire \tq_counter_q_reg[7] ; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [0])); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_1 ), .CLR(\g_bit[1].reg_value_r_reg[1]_0 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_fd_brp_fd] [2])); LUT5 #( .INIT(32'hF0BFFFBF)) \r_data[24]_i_6 (.I0(adress_IBUF[2]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [0]), .I2(adress_IBUF[1]), .I3(adress_IBUF[0]), .I4(\r_data[24]_i_3__0 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h0000000000009009)) \segm_counter_q[6]_i_3 (.I0(\segm_counter_q_reg[0] [1]), .I1(\mr_ctrl_out[btr_fd_brp_fd] [2]), .I2(\segm_counter_q_reg[0] [0]), .I3(\mr_ctrl_out[btr_fd_brp_fd] [1]), .I4(\segm_counter_q_reg[0]_0 ), .I5(\segm_counter_q_reg[0]_1 ), .O(\tq_counter_q_reg[7] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized7_8 (\g_bit[0].reg_value_r_reg[0]_0 , \mr_ctrl_out[btr_ph2] , \g_bit[4].reg_value_r_reg[4] , neg_phase_err, \FSM_onehot_current_state_reg[2] , \g_bit[0].reg_value_r_reg[0]_1 , S, wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[2].reg_value_r_reg[2]_0 , \test_probe[tx_trigger]_INST_0_i_16 , i__carry_i_9_0, is_tseg2, CO, i__carry_i_2__4, adress_IBUF, \r_data[16]_i_4__0 , \cc_stat[is_err_active] ); output [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; output [1:0]\mr_ctrl_out[btr_ph2] ; output [0:0]\g_bit[4].reg_value_r_reg[4] ; output [3:0]neg_phase_err; output \FSM_onehot_current_state_reg[2] ; output \g_bit[0].reg_value_r_reg[0]_1 ; output [0:0]S; input wr_en; input [2:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[2].reg_value_r_reg[2]_0 ; input \test_probe[tx_trigger]_INST_0_i_16 ; input [2:0]i__carry_i_9_0; input is_tseg2; input [0:0]CO; input [1:0]i__carry_i_2__4; input [2:0]adress_IBUF; input \r_data[16]_i_4__0 ; input \cc_stat[is_err_active] ; wire [0:0]CO; wire \FSM_onehot_current_state_reg[2] ; wire [0:0]S; wire [2:0]adress_IBUF; wire \cc_stat[is_err_active] ; wire clk_sys_IBUF_BUFG; wire [2:0]data_in_IBUF; wire [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire [0:0]\g_bit[4].reg_value_r_reg[4] ; wire i__carry_i_16_n_0; wire i__carry_i_17__0_n_0; wire [1:0]i__carry_i_2__4; wire [2:0]i__carry_i_9_0; wire is_tseg2; wire [1:0]\mr_ctrl_out[btr_ph2] ; wire [3:0]neg_phase_err; wire \r_data[16]_i_4__0 ; wire \test_probe[tx_trigger]_INST_0_i_16 ; wire wr_en; wire [3:0]NLW_i__carry_i_9_CO_UNCONNECTED; FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[0]), .Q(\g_bit[0].reg_value_r_reg[0]_0 )); FDCE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[1]), .Q(\mr_ctrl_out[btr_ph2] [0])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[2].reg_value_r_reg[2]_0 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_ph2] [1])); LUT2 #( .INIT(4'h9)) i__carry_i_16 (.I0(\mr_ctrl_out[btr_ph2] [1]), .I1(i__carry_i_9_0[2]), .O(i__carry_i_16_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_17__0 (.I0(\mr_ctrl_out[btr_ph2] [0]), .I1(i__carry_i_9_0[1]), .O(i__carry_i_17__0_n_0)); LUT2 #( .INIT(4'h9)) i__carry_i_18 (.I0(\g_bit[0].reg_value_r_reg[0]_0 ), .I1(i__carry_i_9_0[0]), .O(S)); LUT6 #( .INIT(64'h00000099A5A50099)) i__carry_i_6__3 (.I0(\test_probe[tx_trigger]_INST_0_i_16 ), .I1(i__carry_i_9_0[1]), .I2(neg_phase_err[0]), .I3(i__carry_i_9_0[2]), .I4(is_tseg2), .I5(neg_phase_err[1]), .O(\g_bit[4].reg_value_r_reg[4] )); (* ADDER_THRESHOLD = "35" *) CARRY4 i__carry_i_9 (.CI(CO), .CO(NLW_i__carry_i_9_CO_UNCONNECTED[3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,\mr_ctrl_out[btr_ph2] }), .O(neg_phase_err), .S({i__carry_i_2__4,i__carry_i_16_n_0,i__carry_i_17__0_n_0})); LUT6 #( .INIT(64'hAABFAFBFFABFFFBF)) \r_data[16]_i_8 (.I0(adress_IBUF[2]), .I1(\g_bit[0].reg_value_r_reg[0]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(\r_data[16]_i_4__0 ), .I5(\cc_stat[is_err_active] ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); LUT4 #( .INIT(16'hB847)) \test_probe[tx_trigger]_INST_0_i_22 (.I0(neg_phase_err[0]), .I1(is_tseg2), .I2(i__carry_i_9_0[1]), .I3(\test_probe[tx_trigger]_INST_0_i_16 ), .O(\FSM_onehot_current_state_reg[2] )); endmodule (* ORIG_REF_NAME = "memory_reg_rw_lock" *) module memory_reg_rw_lock__parameterized9 (\mr_ctrl_out[btr_brp] , \adress[2] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[3].reg_value_r_reg[3]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[3].reg_value_r_reg[3]_1 , adress_IBUF, \segm_counter_q[7]_i_4 , \segm_counter_q[7]_i_4_0 ); output [4:0]\mr_ctrl_out[btr_brp] ; output \adress[2] ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; input wr_en; input [4:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[3].reg_value_r_reg[3]_1 ; input [1:0]adress_IBUF; input [5:0]\segm_counter_q[7]_i_4 ; input [0:0]\segm_counter_q[7]_i_4_0 ; wire \adress[2] ; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [4:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire [4:0]\mr_ctrl_out[btr_brp] ; wire [5:0]\segm_counter_q[7]_i_4 ; wire [0:0]\segm_counter_q[7]_i_4_0 ; wire wr_en; LUT2 #( .INIT(4'h2)) \g_bit[0].reg_value_r[0]_i_3__0 (.I0(adress_IBUF[0]), .I1(adress_IBUF[1]), .O(\adress[2] )); FDCE \g_bit[0].reg_value_r_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[0]), .Q(\mr_ctrl_out[btr_brp] [0])); FDPE \g_bit[1].reg_value_r_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[1]), .PRE(\g_bit[3].reg_value_r_reg[3]_1 ), .Q(\mr_ctrl_out[btr_brp] [1])); FDCE \g_bit[2].reg_value_r_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[2]), .Q(\mr_ctrl_out[btr_brp] [2])); FDPE \g_bit[3].reg_value_r_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .D(data_in_IBUF[3]), .PRE(\g_bit[3].reg_value_r_reg[3]_1 ), .Q(\mr_ctrl_out[btr_brp] [3])); FDCE \g_bit[4].reg_value_r_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(wr_en), .CLR(\g_bit[3].reg_value_r_reg[3]_1 ), .D(data_in_IBUF[4]), .Q(\mr_ctrl_out[btr_brp] [4])); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \segm_counter_q[7]_i_6 (.I0(\mr_ctrl_out[btr_brp] [0]), .I1(\segm_counter_q[7]_i_4 [0]), .I2(\segm_counter_q[7]_i_4 [2]), .I3(\mr_ctrl_out[btr_brp] [2]), .I4(\segm_counter_q[7]_i_4 [1]), .I5(\mr_ctrl_out[btr_brp] [1]), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) \segm_counter_q[7]_i_7 (.I0(\mr_ctrl_out[btr_brp] [3]), .I1(\segm_counter_q[7]_i_4 [3]), .I2(\segm_counter_q[7]_i_4 [4]), .I3(\mr_ctrl_out[btr_brp] [4]), .I4(\segm_counter_q[7]_i_4 [5]), .I5(\segm_counter_q[7]_i_4_0 ), .O(\g_bit[3].reg_value_r_reg[3]_0 )); endmodule module mr_top (\mr_ctrl_out[mode_bmm] , reg_q_reg, \mr_ctrl_out[mode_stm] , \g_bit[0].reg_value_r_reg[0] , \mr_ctrl_out[mode_fde] , \mr_ctrl_out[mode_tttm] , \mr_ctrl_out[mode_rom] , \mr_ctrl_out[mode_acf] , \mr_ctrl_out[mode_tstm] , \mr_ctrl_out[mode_rxbam] , \mr_ctrl_out[mode_txbbm] , \mr_ctrl_out[mode_sam] , \mr_ctrl_out[mode_erfm] , \mr_ctrl_out[settings_rtrle] , \g_bit[3].reg_value_r_reg[3] , \mr_ctrl_out[settings_ilbp] , \mr_ctrl_out[settings_ena] , \mr_ctrl_out[settings_nisofd] , \mr_ctrl_out[settings_pex] , \mr_ctrl_out[settings_tbfbo] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , mr_btr_prop, \mr_ctrl_out[btr_ph1] , \mr_ctrl_out[btr_ph2] , \mr_ctrl_out[btr_sjw] , \mr_ctrl_out[btr_fd_prop_fd] , \mr_ctrl_out[btr_fd_ph1_fd] , \mr_ctrl_out[btr_fd_ph2_fd] , \mr_ctrl_out[ewl_ew_limit] , \mr_ctrl_out[erp_erp_limit] , \mr_ctrl_out[ctr_pres_ctpv] , \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , \g_bit[0].reg_value_r_reg[0]_4 , \g_bit[0].reg_value_r_reg[0]_5 , \g_bit[0].reg_value_r_reg[0]_6 , \g_bit[0].reg_value_r_reg[0]_7 , \g_bit[0].reg_value_r_reg[0]_8 , \g_bit[0].reg_value_r_reg[0]_9 , \g_bit[0].reg_value_r_reg[0]_10 , \g_bit[0].reg_value_r_reg[0]_11 , \g_bit[0].reg_value_r_reg[0]_12 , \mr_ctrl_out[rx_settings_rtsop] , mr_tx_command_txbi, \mr_tx_priority[0] , \mr_tx_priority[1] , \mr_tx_priority[2] , \mr_tx_priority[3] , \mr_ctrl_out[ssp_cfg_ssp_offset] , \mr_ctrl_out[ssp_cfg_ssp_src] , \mr_tst_out[tst_dest_tst_addr] , \g_bit[7].reg_value_r_reg[7] , soft_res_d_n, q_i, \adress[2] , \adress[5] , \adress[3] , \timestamp[26] , \timestamp[27] , \timestamp[28] , \timestamp[61] , \timestamp[62] , \timestamp[63] , \adress[5]_0 , \adress[8] , \g_bit[6].reg_value_r_reg[6] , \g_bit[0].reg_value_r_reg[0]_13 , \g_bit[1].reg_value_r_reg[1] , \g_bit[4].reg_value_r_reg[4] , \adress[4] , \g_bit[2].reg_value_r_reg[2] , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[0].reg_value_r_reg[0]_14 , \adress[4]_0 , \g_bit[0].reg_value_r_reg[0]_15 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[0].reg_value_r_reg[0]_16 , \adress[2]_0 , \adress[3]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_1 , \g_bit[3].reg_value_r_reg[3]_1 , \g_bit[4].reg_value_r_reg[4]_1 , \mr_tst_out[tst_control_twrstb] , \mr_ctrl_out[ctr_pres_ptx] , \mr_ctrl_out[ctr_pres_prx] , \mr_ctrl_out[ctr_pres_enorm] , \mr_ctrl_out[ctr_pres_efd] , E, \g_bit[0].reg_value_r_reg[0]_17 , tst_ena, \g_bit[0].reg_value_r_reg[0]_18 , tst_ena_0, tst_ena_1, \g_bit[0].reg_value_r_reg[0]_19 , \adress[5]_1 , \adress[5]_2 , \nom_err_ctr_q_reg[9] , \nom_err_ctr_q_reg[10] , \g_bit[3].reg_value_r_reg[3]_2 , \adress[4]_1 , \g_bit[0].reg_value_r_reg[0]_20 , \g_bit[1].reg_value_r_reg[1]_1 , \adress[6] , \timestamp[50] , \g_bit[2].reg_value_r_reg[2]_2 , \g_bit[1].reg_value_r_reg[1]_2 , \g_bit[0].reg_value_r_reg[0]_21 , \timestamp[44] , \g_bit[3].reg_value_r_reg[3]_3 , \g_bit[0].reg_value_r_reg[0]_22 , \timestamp[38] , \g_bit[4].reg_value_r_reg[4]_2 , \g_bit[2].reg_value_r_reg[2]_3 , \g_bit[1].reg_value_r_reg[1]_3 , tst_ena_2, reg_q_reg_0, ADDRARDADDR, DIADI, reg_q_reg_1, \g_bit[7].reg_value_r_reg[7]_0 , DIBDI, \g_bit[4].reg_value_r_reg[4]_3 , ADDRBWRADDR, \FSM_sequential_curr_state_reg[0] , \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \g_bit[4].reg_value_r_reg[4]_4 , \g_bit[4].reg_value_r_reg[4]_5 , \g_bit[0].reg_value_r_reg[0]_23 , abort_applied, \g_bit[7].reg_value_r_reg[7]_3 , \g_bit[7].reg_value_r_reg[7]_4 , \g_bit[4].reg_value_r_reg[4]_6 , \g_bit[4].reg_value_r_reg[4]_7 , \FSM_sequential_curr_state_reg[0]_0 , \g_bit[7].reg_value_r_reg[7]_5 , \g_bit[7].reg_value_r_reg[7]_6 , \g_bit[4].reg_value_r_reg[4]_8 , \g_bit[4].reg_value_r_reg[4]_9 , \g_bit[0].reg_value_r_reg[0]_24 , abort_applied_3, \txtb_hw_cmd_q_reg[lock] , \select_buf_index_reg_reg[0] , \FSM_sequential_curr_state_reg[0]_1 , reg_q_reg_2, \g_bit[0].reg_value_r_reg[0]_25 , \txtb_hw_cmd_q[err] , \g_bit[0].reg_value_r_reg[0]_26 , can_tx_OBUF, \g_bit[0].reg_value_r_reg[0]_27 , \g_bit[0].reg_value_r_reg[0]_28 , \g_bit[0].reg_value_r_reg[0]_29 , S, DI, \g_bit[7].reg_value_r_reg[7]_7 , \g_bit[7].reg_value_r_reg[7]_8 , \segm_counter_q_reg[6] , \g_bit[0].reg_value_r_reg[0]_30 , \tq_counter_q_reg[6] , \g_bit[4].reg_value_r_reg[4]_10 , O, \segm_counter_q_reg[4] , \g_bit[4].reg_value_r_reg[4]_11 , \g_bit[0].reg_value_r_reg[0]_31 , \tq_counter_q_reg[7] , \g_bit[1].reg_value_r_reg[1]_4 , \g_bit[4].reg_value_r_reg[4]_12 , \g_bit[4].reg_value_r_reg[4]_13 , neg_phase_err, \g_bit[2].reg_value_r_reg[2]_4 , \g_bit[1].reg_value_r_reg[1]_5 , \g_bit[0].reg_value_r_reg[0]_32 , bit_err_d0_out, \g_bit[1].reg_value_r_reg[1]_6 , tx_command_txcr_valid, tx_command_txce_valid, tx_command_txcr_valid_4, tx_command_txce_valid_5, \adress[4]_2 , \adress[6]_0 , \g_bit[0].reg_value_r_reg[0]_33 , \g_bit[0].reg_value_r_reg[0]_34 , \g_bit[5].reg_value_r_reg[5] , \g_bit[3].reg_value_r_reg[3]_4 , \g_bit[0].reg_value_r_reg[0]_35 , \select_buf_index_reg_reg[0]_0 , \FSM_onehot_current_state_reg[2] , \g_bit[0].reg_value_r_reg[0]_36 , \g_bit[0].reg_value_r_reg[0]_37 , \g_bit[0].reg_value_r_reg[0]_38 , \tseg1_dbt_reg[3] , \tseg1_dbt_reg[4] , data_out_OBUF, data_in_IBUF, clk_sys_IBUF_BUFG, reg_q_reg_3, D, sbe_IBUF, adress_IBUF, \r_data_reg[25] , \r_data_reg[23] , \r_data_reg[23]_0 , \r_data_reg[22] , \r_data_reg[22]_0 , \r_data_reg[7] , timestamp_IBUF, \r_data_reg[3] , \r_data_reg[5] , \r_data_reg[5]_0 , \r_data_reg[5]_1 , \r_data_reg[5]_2 , \r_data_reg[12] , \r_data_reg[21] , reg_q_reg_4, \g_bit[0].reg_value_r_reg[0]_39 , swr_IBUF, \r_data_reg[3]_0 , \r_data_reg[3]_1 , \r_data_reg[12]_0 , \r_data_reg[7]_0 , \r_data_reg[7]_1 , \r_data_reg[31] , \r_data_reg[12]_1 , \r_data_reg[21]_0 , \r_data_reg[21]_1 , scs_IBUF, srd_IBUF, \g_bit[0].reg_value_r_reg[0]_40 , txtb_port_b_data_out_i, rxb_port_b_data_out_i, txtb_port_b_data_out_i_6, txtb_port_b_data_out_i_7, \r_data[17]_i_2 , txtb_port_b_data_out_i_8, scan_mode_IBUF, rst_n_out_OBUF, reg_q_reg_5, Q, \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_ram_rst_false.ram_memory_reg_4 , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , \FSM_sequential_curr_state_reg[2] , txtb_allow_bb, \FSM_sequential_curr_state[0]_i_2__0 , txtb_hw_cmd_cs, \FSM_sequential_curr_state[0]_i_2__0_0 , \FSM_sequential_curr_state[0]_i_2__2 , \txtb_hw_cmd[lock] , tran_frame_valid_com_reg, fsm_wait_state_q, fsm_wait_state_q_reg, \select_buf_index_reg_reg[1] , txtb_available, \select_buf_index_reg_reg[1]_0 , reg_q_reg_6, curr_state, \txtb_hw_cmd_q_reg[err] , crc_data_tx_wbs, \txtb_hw_cmd_q_reg[err]_0 , tran_frame_type, pc_rx_data_nbs, \err_capt_err_type_q[2]_i_13 , next_state2_carry, \next_state2_inferred__0/i__carry , \exp_seg_length_q[6]_i_2 , CO, \exp_seg_length_q[6]_i_2_0 , mr_settings_ena_reg, \segm_counter_q_reg[0] , \exp_seg_length_q[7]_i_11 , is_tseg2, \exp_seg_length_d9_inferred__0/i__carry , \test_probe[tx_trigger]_INST_0_i_9 , \test_probe[tx_trigger]_INST_0_i_9_0 , \exp_seg_length_d9_inferred__0/i__carry_0 , \segm_counter_q_reg[0]_0 , \test_probe[tx_trigger]_INST_0_i_7 , \exp_seg_length_d9_inferred__0/i__carry_1 , \test_probe[tx_trigger]_INST_0_i_7_0 , \exp_seg_length_d9_inferred__0/i__carry_2 , i__carry_i_9, current_state_reg, i__carry_i_2__4, \test_probe[tx_trigger]_INST_0_i_27 , bit_err_enable, bit_err_q_reg, bit_err_q_reg_0, bit_err_d2, rx_data_wbs, trv_delay_sum, mr_tx_command_txcr_q, mr_tx_command_txce_q, mr_tx_command_txca_q, \cc_stat[is_err_active] , \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 , \test_probe[tx_trigger]_INST_0_i_4 , \test_probe[tx_trigger]_INST_0_i_4_0 , \exp_seg_length_q_reg[7]_i_2__0 , \exp_seg_length_q_reg[7]_i_2__0_0 ); output \mr_ctrl_out[mode_bmm] ; output reg_q_reg; output \mr_ctrl_out[mode_stm] ; output \g_bit[0].reg_value_r_reg[0] ; output \mr_ctrl_out[mode_fde] ; output \mr_ctrl_out[mode_tttm] ; output \mr_ctrl_out[mode_rom] ; output \mr_ctrl_out[mode_acf] ; output \mr_ctrl_out[mode_tstm] ; output \mr_ctrl_out[mode_rxbam] ; output \mr_ctrl_out[mode_txbbm] ; output \mr_ctrl_out[mode_sam] ; output \mr_ctrl_out[mode_erfm] ; output \mr_ctrl_out[settings_rtrle] ; output [1:0]\g_bit[3].reg_value_r_reg[3] ; output \mr_ctrl_out[settings_ilbp] ; output \mr_ctrl_out[settings_ena] ; output \mr_ctrl_out[settings_nisofd] ; output \mr_ctrl_out[settings_pex] ; output \mr_ctrl_out[settings_tbfbo] ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output [6:0]mr_btr_prop; output [5:0]\mr_ctrl_out[btr_ph1] ; output [5:0]\mr_ctrl_out[btr_ph2] ; output [4:0]\mr_ctrl_out[btr_sjw] ; output [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; output [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; output [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; output [7:0]\mr_ctrl_out[ewl_ew_limit] ; output [7:0]\mr_ctrl_out[erp_erp_limit] ; output [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; output \g_bit[0].reg_value_r_reg[0]_2 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \g_bit[0].reg_value_r_reg[0]_4 ; output \g_bit[0].reg_value_r_reg[0]_5 ; output \g_bit[0].reg_value_r_reg[0]_6 ; output \g_bit[0].reg_value_r_reg[0]_7 ; output \g_bit[0].reg_value_r_reg[0]_8 ; output \g_bit[0].reg_value_r_reg[0]_9 ; output \g_bit[0].reg_value_r_reg[0]_10 ; output \g_bit[0].reg_value_r_reg[0]_11 ; output \g_bit[0].reg_value_r_reg[0]_12 ; output \mr_ctrl_out[rx_settings_rtsop] ; output [1:0]mr_tx_command_txbi; output [2:0]\mr_tx_priority[0] ; output [2:0]\mr_tx_priority[1] ; output [2:0]\mr_tx_priority[2] ; output [2:0]\mr_tx_priority[3] ; output [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; output [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; output [4:0]\mr_tst_out[tst_dest_tst_addr] ; output [30:0]\g_bit[7].reg_value_r_reg[7] ; output soft_res_d_n; output q_i; output \adress[2] ; output \adress[5] ; output \adress[3] ; output \timestamp[26] ; output \timestamp[27] ; output \timestamp[28] ; output \timestamp[61] ; output \timestamp[62] ; output \timestamp[63] ; output \adress[5]_0 ; output \adress[8] ; output \g_bit[6].reg_value_r_reg[6] ; output \g_bit[0].reg_value_r_reg[0]_13 ; output \g_bit[1].reg_value_r_reg[1] ; output \g_bit[4].reg_value_r_reg[4] ; output \adress[4] ; output \g_bit[2].reg_value_r_reg[2] ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[0].reg_value_r_reg[0]_14 ; output \adress[4]_0 ; output \g_bit[0].reg_value_r_reg[0]_15 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[0].reg_value_r_reg[0]_16 ; output \adress[2]_0 ; output \adress[3]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_1 ; output \g_bit[3].reg_value_r_reg[3]_1 ; output \g_bit[4].reg_value_r_reg[4]_1 ; output \mr_tst_out[tst_control_twrstb] ; output \mr_ctrl_out[ctr_pres_ptx] ; output \mr_ctrl_out[ctr_pres_prx] ; output \mr_ctrl_out[ctr_pres_enorm] ; output \mr_ctrl_out[ctr_pres_efd] ; output [0:0]E; output \g_bit[0].reg_value_r_reg[0]_17 ; output tst_ena; output \g_bit[0].reg_value_r_reg[0]_18 ; output tst_ena_0; output tst_ena_1; output \g_bit[0].reg_value_r_reg[0]_19 ; output \adress[5]_1 ; output \adress[5]_2 ; output \nom_err_ctr_q_reg[9] ; output \nom_err_ctr_q_reg[10] ; output \g_bit[3].reg_value_r_reg[3]_2 ; output \adress[4]_1 ; output \g_bit[0].reg_value_r_reg[0]_20 ; output \g_bit[1].reg_value_r_reg[1]_1 ; output \adress[6] ; output \timestamp[50] ; output \g_bit[2].reg_value_r_reg[2]_2 ; output \g_bit[1].reg_value_r_reg[1]_2 ; output \g_bit[0].reg_value_r_reg[0]_21 ; output \timestamp[44] ; output \g_bit[3].reg_value_r_reg[3]_3 ; output \g_bit[0].reg_value_r_reg[0]_22 ; output \timestamp[38] ; output \g_bit[4].reg_value_r_reg[4]_2 ; output \g_bit[2].reg_value_r_reg[2]_3 ; output \g_bit[1].reg_value_r_reg[1]_3 ; output tst_ena_2; output reg_q_reg_0; output [0:0]ADDRARDADDR; output [0:0]DIADI; output reg_q_reg_1; output [15:0]\g_bit[7].reg_value_r_reg[7]_0 ; output [15:0]DIBDI; output [3:0]\g_bit[4].reg_value_r_reg[4]_3 ; output [4:0]ADDRBWRADDR; output \FSM_sequential_curr_state_reg[0] ; output [15:0]\g_bit[7].reg_value_r_reg[7]_1 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_2 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_4 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_5 ; output \g_bit[0].reg_value_r_reg[0]_23 ; output abort_applied; output [15:0]\g_bit[7].reg_value_r_reg[7]_3 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_4 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_6 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_7 ; output \FSM_sequential_curr_state_reg[0]_0 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_5 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_6 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_8 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_9 ; output \g_bit[0].reg_value_r_reg[0]_24 ; output abort_applied_3; output \txtb_hw_cmd_q_reg[lock] ; output \select_buf_index_reg_reg[0] ; output [1:0]\FSM_sequential_curr_state_reg[0]_1 ; output reg_q_reg_2; output \g_bit[0].reg_value_r_reg[0]_25 ; output \txtb_hw_cmd_q[err] ; output \g_bit[0].reg_value_r_reg[0]_26 ; output can_tx_OBUF; output \g_bit[0].reg_value_r_reg[0]_27 ; output \g_bit[0].reg_value_r_reg[0]_28 ; output \g_bit[0].reg_value_r_reg[0]_29 ; output [3:0]S; output [3:0]DI; output [3:0]\g_bit[7].reg_value_r_reg[7]_7 ; output [3:0]\g_bit[7].reg_value_r_reg[7]_8 ; output \segm_counter_q_reg[6] ; output [0:0]\g_bit[0].reg_value_r_reg[0]_30 ; output \tq_counter_q_reg[6] ; output \g_bit[4].reg_value_r_reg[4]_10 ; output [1:0]O; output [2:0]\segm_counter_q_reg[4] ; output [2:0]\g_bit[4].reg_value_r_reg[4]_11 ; output [2:0]\g_bit[0].reg_value_r_reg[0]_31 ; output \tq_counter_q_reg[7] ; output \g_bit[1].reg_value_r_reg[1]_4 ; output \g_bit[4].reg_value_r_reg[4]_12 ; output [1:0]\g_bit[4].reg_value_r_reg[4]_13 ; output [7:0]neg_phase_err; output [0:0]\g_bit[2].reg_value_r_reg[2]_4 ; output \g_bit[1].reg_value_r_reg[1]_5 ; output \g_bit[0].reg_value_r_reg[0]_32 ; output bit_err_d0_out; output [8:0]\g_bit[1].reg_value_r_reg[1]_6 ; output tx_command_txcr_valid; output tx_command_txce_valid; output tx_command_txcr_valid_4; output tx_command_txce_valid_5; output \adress[4]_2 ; output \adress[6]_0 ; output \g_bit[0].reg_value_r_reg[0]_33 ; output \g_bit[0].reg_value_r_reg[0]_34 ; output \g_bit[5].reg_value_r_reg[5] ; output \g_bit[3].reg_value_r_reg[3]_4 ; output \g_bit[0].reg_value_r_reg[0]_35 ; output \select_buf_index_reg_reg[0]_0 ; output \FSM_onehot_current_state_reg[2] ; output \g_bit[0].reg_value_r_reg[0]_36 ; output \g_bit[0].reg_value_r_reg[0]_37 ; output [0:0]\g_bit[0].reg_value_r_reg[0]_38 ; output [3:0]\tseg1_dbt_reg[3] ; output [0:0]\tseg1_dbt_reg[4] ; output [31:0]data_out_OBUF; input [31:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input reg_q_reg_3; input [23:0]D; input [3:0]sbe_IBUF; input [9:0]adress_IBUF; input \r_data_reg[25] ; input \r_data_reg[23] ; input \r_data_reg[23]_0 ; input \r_data_reg[22] ; input \r_data_reg[22]_0 ; input \r_data_reg[7] ; input [31:0]timestamp_IBUF; input \r_data_reg[3] ; input \r_data_reg[5] ; input \r_data_reg[5]_0 ; input \r_data_reg[5]_1 ; input \r_data_reg[5]_2 ; input \r_data_reg[12] ; input \r_data_reg[21] ; input reg_q_reg_4; input \g_bit[0].reg_value_r_reg[0]_39 ; input swr_IBUF; input \r_data_reg[3]_0 ; input \r_data_reg[3]_1 ; input [2:0]\r_data_reg[12]_0 ; input \r_data_reg[7]_0 ; input \r_data_reg[7]_1 ; input [6:0]\r_data_reg[31] ; input \r_data_reg[12]_1 ; input \r_data_reg[21]_0 ; input [0:0]\r_data_reg[21]_1 ; input scs_IBUF; input srd_IBUF; input \g_bit[0].reg_value_r_reg[0]_40 ; input [31:0]txtb_port_b_data_out_i; input [31:0]rxb_port_b_data_out_i; input [31:0]txtb_port_b_data_out_i_6; input [31:0]txtb_port_b_data_out_i_7; input [0:0]\r_data[17]_i_2 ; input [31:0]txtb_port_b_data_out_i_8; input scan_mode_IBUF; input rst_n_out_OBUF; input reg_q_reg_5; input [0:0]Q; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input [3:0]\g_ram_rst_false.ram_memory_reg_2 ; input \g_ram_rst_false.ram_memory_reg_3 ; input \g_ram_rst_false.ram_memory_reg_4 ; input \g_ram_rst_false.ram_memory_reg_5 ; input \g_ram_rst_false.ram_memory_reg_6 ; input [1:0]\FSM_sequential_curr_state_reg[2] ; input [1:0]txtb_allow_bb; input \FSM_sequential_curr_state[0]_i_2__0 ; input [1:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state[0]_i_2__0_0 ; input \FSM_sequential_curr_state[0]_i_2__2 ; input \txtb_hw_cmd[lock] ; input tran_frame_valid_com_reg; input fsm_wait_state_q; input [1:0]fsm_wait_state_q_reg; input \select_buf_index_reg_reg[1] ; input [3:0]txtb_available; input \select_buf_index_reg_reg[1]_0 ; input reg_q_reg_6; input [1:0]curr_state; input \txtb_hw_cmd_q_reg[err] ; input crc_data_tx_wbs; input [3:0]\txtb_hw_cmd_q_reg[err]_0 ; input tran_frame_type; input pc_rx_data_nbs; input [0:0]\err_capt_err_type_q[2]_i_13 ; input [7:0]next_state2_carry; input [7:0]\next_state2_inferred__0/i__carry ; input \exp_seg_length_q[6]_i_2 ; input [0:0]CO; input \exp_seg_length_q[6]_i_2_0 ; input mr_settings_ena_reg; input [7:0]\segm_counter_q_reg[0] ; input [6:0]\exp_seg_length_q[7]_i_11 ; input is_tseg2; input \exp_seg_length_d9_inferred__0/i__carry ; input \test_probe[tx_trigger]_INST_0_i_9 ; input \test_probe[tx_trigger]_INST_0_i_9_0 ; input \exp_seg_length_d9_inferred__0/i__carry_0 ; input [7:0]\segm_counter_q_reg[0]_0 ; input \test_probe[tx_trigger]_INST_0_i_7 ; input \exp_seg_length_d9_inferred__0/i__carry_1 ; input \test_probe[tx_trigger]_INST_0_i_7_0 ; input \exp_seg_length_d9_inferred__0/i__carry_2 ; input [5:0]i__carry_i_9; input [0:0]current_state_reg; input [1:0]i__carry_i_2__4; input [1:0]\test_probe[tx_trigger]_INST_0_i_27 ; input bit_err_enable; input bit_err_q_reg; input bit_err_q_reg_0; input bit_err_d2; input rx_data_wbs; input [8:0]trv_delay_sum; input mr_tx_command_txcr_q; input mr_tx_command_txce_q; input mr_tx_command_txca_q; input \cc_stat[is_err_active] ; input \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 ; input \test_probe[tx_trigger]_INST_0_i_4 ; input \test_probe[tx_trigger]_INST_0_i_4_0 ; input [3:0]\exp_seg_length_q_reg[7]_i_2__0 ; input \exp_seg_length_q_reg[7]_i_2__0_0 ; wire [0:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [0:0]CO; wire [23:0]D; wire [3:0]DI; wire [0:0]DIADI; wire [15:0]DIBDI; wire [0:0]E; wire \FSM_onehot_current_state_reg[2] ; wire \FSM_sequential_curr_state[0]_i_2__0 ; wire \FSM_sequential_curr_state[0]_i_2__0_0 ; wire \FSM_sequential_curr_state[0]_i_2__2 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire [1:0]\FSM_sequential_curr_state_reg[0]_1 ; wire [1:0]\FSM_sequential_curr_state_reg[2] ; wire [1:0]O; wire [0:0]Q; wire [3:0]S; wire abort_applied; wire abort_applied_3; wire \adress[2] ; wire \adress[2]_0 ; wire \adress[3] ; wire \adress[3]_0 ; wire \adress[4] ; wire \adress[4]_0 ; wire \adress[4]_1 ; wire \adress[4]_2 ; wire \adress[5] ; wire \adress[5]_0 ; wire \adress[5]_1 ; wire \adress[5]_2 ; wire \adress[6] ; wire \adress[6]_0 ; wire \adress[8] ; wire [9:0]adress_IBUF; wire bit_err_d0_out; wire bit_err_d2; wire bit_err_enable; wire bit_err_q_reg; wire bit_err_q_reg_0; wire can_tx_OBUF; wire \cc_stat[is_err_active] ; wire clk_sys_IBUF_BUFG; wire control_registers_cs_reg; wire [31:0]control_registers_rdata; wire crc_data_tx_wbs; wire [1:0]curr_state; wire [0:0]current_state_reg; wire [31:0]data_in_IBUF; wire [31:0]data_out_OBUF; wire [0:0]\err_capt_err_type_q[2]_i_13 ; wire \exp_seg_length_d9_inferred__0/i__carry ; wire \exp_seg_length_d9_inferred__0/i__carry_0 ; wire \exp_seg_length_d9_inferred__0/i__carry_1 ; wire \exp_seg_length_d9_inferred__0/i__carry_2 ; wire \exp_seg_length_q[6]_i_2 ; wire \exp_seg_length_q[6]_i_2_0 ; wire [6:0]\exp_seg_length_q[7]_i_11 ; wire [3:0]\exp_seg_length_q_reg[7]_i_2__0 ; wire \exp_seg_length_q_reg[7]_i_2__0_0 ; wire fsm_wait_state_q; wire [1:0]fsm_wait_state_q_reg; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_10 ; wire \g_bit[0].reg_value_r_reg[0]_11 ; wire \g_bit[0].reg_value_r_reg[0]_12 ; wire \g_bit[0].reg_value_r_reg[0]_13 ; wire \g_bit[0].reg_value_r_reg[0]_14 ; wire \g_bit[0].reg_value_r_reg[0]_15 ; wire \g_bit[0].reg_value_r_reg[0]_16 ; wire \g_bit[0].reg_value_r_reg[0]_17 ; wire \g_bit[0].reg_value_r_reg[0]_18 ; wire \g_bit[0].reg_value_r_reg[0]_19 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_20 ; wire \g_bit[0].reg_value_r_reg[0]_21 ; wire \g_bit[0].reg_value_r_reg[0]_22 ; wire \g_bit[0].reg_value_r_reg[0]_23 ; wire \g_bit[0].reg_value_r_reg[0]_24 ; wire \g_bit[0].reg_value_r_reg[0]_25 ; wire \g_bit[0].reg_value_r_reg[0]_26 ; wire \g_bit[0].reg_value_r_reg[0]_27 ; wire \g_bit[0].reg_value_r_reg[0]_28 ; wire \g_bit[0].reg_value_r_reg[0]_29 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_30 ; wire [2:0]\g_bit[0].reg_value_r_reg[0]_31 ; wire \g_bit[0].reg_value_r_reg[0]_32 ; wire \g_bit[0].reg_value_r_reg[0]_33 ; wire \g_bit[0].reg_value_r_reg[0]_34 ; wire \g_bit[0].reg_value_r_reg[0]_35 ; wire \g_bit[0].reg_value_r_reg[0]_36 ; wire \g_bit[0].reg_value_r_reg[0]_37 ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_38 ; wire \g_bit[0].reg_value_r_reg[0]_39 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[0].reg_value_r_reg[0]_40 ; wire \g_bit[0].reg_value_r_reg[0]_5 ; wire \g_bit[0].reg_value_r_reg[0]_6 ; wire \g_bit[0].reg_value_r_reg[0]_7 ; wire \g_bit[0].reg_value_r_reg[0]_8 ; wire \g_bit[0].reg_value_r_reg[0]_9 ; wire \g_bit[1].reg_value_r_reg[1] ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[1].reg_value_r_reg[1]_1 ; wire \g_bit[1].reg_value_r_reg[1]_2 ; wire \g_bit[1].reg_value_r_reg[1]_3 ; wire \g_bit[1].reg_value_r_reg[1]_4 ; wire \g_bit[1].reg_value_r_reg[1]_5 ; wire [8:0]\g_bit[1].reg_value_r_reg[1]_6 ; wire \g_bit[2].reg_value_r_reg[2] ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire \g_bit[2].reg_value_r_reg[2]_2 ; wire \g_bit[2].reg_value_r_reg[2]_3 ; wire [0:0]\g_bit[2].reg_value_r_reg[2]_4 ; wire [1:0]\g_bit[3].reg_value_r_reg[3] ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[3].reg_value_r_reg[3]_2 ; wire \g_bit[3].reg_value_r_reg[3]_3 ; wire \g_bit[3].reg_value_r_reg[3]_4 ; wire \g_bit[4].reg_value_r_reg[4] ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire \g_bit[4].reg_value_r_reg[4]_10 ; wire [2:0]\g_bit[4].reg_value_r_reg[4]_11 ; wire \g_bit[4].reg_value_r_reg[4]_12 ; wire [1:0]\g_bit[4].reg_value_r_reg[4]_13 ; wire \g_bit[4].reg_value_r_reg[4]_2 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_3 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_4 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_5 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_6 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_7 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_8 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_9 ; wire \g_bit[5].reg_value_r_reg[5] ; wire \g_bit[6].reg_value_r_reg[6] ; wire [30:0]\g_bit[7].reg_value_r_reg[7] ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_0 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_1 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_2 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_4 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_5 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_6 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_7 ; wire [3:0]\g_bit[7].reg_value_r_reg[7]_8 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire \g_test_registers_true.i_test_registers_reg_map_n_210 ; wire \g_test_registers_true.i_test_registers_reg_map_n_36 ; wire \g_test_registers_true.i_test_registers_reg_map_n_37 ; wire \g_test_registers_true.i_test_registers_reg_map_n_42 ; wire [1:0]i__carry_i_2__4; wire [5:0]i__carry_i_9; wire \i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 ; wire i_control_registers_reg_map_n_133; wire i_control_registers_reg_map_n_163; wire \i_tst_control_tmaena_reg/wr_en ; wire \i_tst_dest_tst_addr_slice_1_reg/wr_en ; wire \i_tst_dest_tst_addr_slice_2_reg/wr_en ; wire \i_tst_dest_tst_mtgt_reg/wr_en ; wire \i_tst_wdata_tst_wdata_slice_1_reg/wr_en ; wire \i_tst_wdata_tst_wdata_slice_2_reg/wr_en ; wire \i_tst_wdata_tst_wdata_slice_3_reg/wr_en ; wire \i_tst_wdata_tst_wdata_slice_4_reg/wr_en ; wire is_tseg2; wire [6:0]mr_btr_prop; wire [4:0]\mr_ctrl_out[btr_fd_ph1_fd] ; wire [4:0]\mr_ctrl_out[btr_fd_ph2_fd] ; wire [5:0]\mr_ctrl_out[btr_fd_prop_fd] ; wire [5:0]\mr_ctrl_out[btr_ph1] ; wire [5:0]\mr_ctrl_out[btr_ph2] ; wire [4:0]\mr_ctrl_out[btr_sjw] ; wire [8:0]\mr_ctrl_out[ctr_pres_ctpv] ; wire \mr_ctrl_out[ctr_pres_efd] ; wire \mr_ctrl_out[ctr_pres_enorm] ; wire \mr_ctrl_out[ctr_pres_prx] ; wire \mr_ctrl_out[ctr_pres_ptx] ; wire [7:0]\mr_ctrl_out[erp_erp_limit] ; wire [7:0]\mr_ctrl_out[ewl_ew_limit] ; wire \mr_ctrl_out[mode_acf] ; wire \mr_ctrl_out[mode_bmm] ; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_rom] ; wire \mr_ctrl_out[mode_rxbam] ; wire \mr_ctrl_out[mode_sam] ; wire \mr_ctrl_out[mode_stm] ; wire \mr_ctrl_out[mode_tstm] ; wire \mr_ctrl_out[mode_tttm] ; wire \mr_ctrl_out[mode_txbbm] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_ena] ; wire \mr_ctrl_out[settings_ilbp] ; wire \mr_ctrl_out[settings_nisofd] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_ctrl_out[settings_rtrle] ; wire \mr_ctrl_out[settings_tbfbo] ; wire [7:0]\mr_ctrl_out[ssp_cfg_ssp_offset] ; wire [1:0]\mr_ctrl_out[ssp_cfg_ssp_src] ; wire mr_settings_ena_reg; wire \mr_tst_out[tst_control_twrstb] ; wire [4:0]\mr_tst_out[tst_dest_tst_addr] ; wire [1:0]mr_tx_command_txbi; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txcr_q; wire [2:0]\mr_tx_priority[0] ; wire [2:0]\mr_tx_priority[1] ; wire [2:0]\mr_tx_priority[2] ; wire [2:0]\mr_tx_priority[3] ; wire [7:0]neg_phase_err; wire [7:0]next_state2_carry; wire [7:0]\next_state2_inferred__0/i__carry ; wire \nom_err_ctr_q_reg[10] ; wire \nom_err_ctr_q_reg[9] ; wire p_13_in; wire p_14_in; wire pc_rx_data_nbs; wire q_i; wire [0:0]\r_data[17]_i_2 ; wire \r_data_reg[12] ; wire [2:0]\r_data_reg[12]_0 ; wire \r_data_reg[12]_1 ; wire \r_data_reg[21] ; wire \r_data_reg[21]_0 ; wire [0:0]\r_data_reg[21]_1 ; wire \r_data_reg[22] ; wire \r_data_reg[22]_0 ; wire \r_data_reg[23] ; wire \r_data_reg[23]_0 ; wire \r_data_reg[25] ; wire [6:0]\r_data_reg[31] ; wire \r_data_reg[3] ; wire \r_data_reg[3]_0 ; wire \r_data_reg[3]_1 ; wire \r_data_reg[5] ; wire \r_data_reg[5]_0 ; wire \r_data_reg[5]_1 ; wire \r_data_reg[5]_2 ; wire \r_data_reg[7] ; wire \r_data_reg[7]_0 ; wire \r_data_reg[7]_1 ; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire rst_n_out_OBUF; wire rx_data_wbs; wire [31:0]rxb_port_b_data_out_i; wire [3:0]sbe_IBUF; wire scan_mode_IBUF; wire scs_IBUF; wire [7:0]\segm_counter_q_reg[0] ; wire [7:0]\segm_counter_q_reg[0]_0 ; wire [2:0]\segm_counter_q_reg[4] ; wire \segm_counter_q_reg[6] ; wire \select_buf_index_reg_reg[0] ; wire \select_buf_index_reg_reg[0]_0 ; wire \select_buf_index_reg_reg[1] ; wire \select_buf_index_reg_reg[1]_0 ; wire soft_res_d_n; wire srd_IBUF; wire swr_IBUF; wire [1:0]\test_probe[tx_trigger]_INST_0_i_27 ; wire \test_probe[tx_trigger]_INST_0_i_4 ; wire \test_probe[tx_trigger]_INST_0_i_4_0 ; wire \test_probe[tx_trigger]_INST_0_i_7 ; wire \test_probe[tx_trigger]_INST_0_i_7_0 ; wire \test_probe[tx_trigger]_INST_0_i_9 ; wire \test_probe[tx_trigger]_INST_0_i_9_0 ; wire test_registers_cs_reg; wire [31:0]test_registers_rdata; wire \timestamp[26] ; wire \timestamp[27] ; wire \timestamp[28] ; wire \timestamp[38] ; wire \timestamp[44] ; wire \timestamp[50] ; wire \timestamp[61] ; wire \timestamp[62] ; wire \timestamp[63] ; wire [31:0]timestamp_IBUF; wire \tq_counter_q_reg[6] ; wire \tq_counter_q_reg[7] ; wire tran_frame_type; wire tran_frame_valid_com_reg; wire [8:0]trv_delay_sum; wire [3:0]\tseg1_dbt_reg[3] ; wire [0:0]\tseg1_dbt_reg[4] ; wire tst_ena; wire tst_ena_0; wire tst_ena_1; wire tst_ena_2; wire tx_command_txce_valid; wire tx_command_txce_valid_5; wire tx_command_txcr_valid; wire tx_command_txcr_valid_4; wire [1:0]txtb_allow_bb; wire [3:0]txtb_available; wire \txtb_hw_cmd[lock] ; wire [1:0]txtb_hw_cmd_cs; wire \txtb_hw_cmd_q[err] ; wire \txtb_hw_cmd_q_reg[err] ; wire [3:0]\txtb_hw_cmd_q_reg[err]_0 ; wire \txtb_hw_cmd_q_reg[lock] ; wire [31:0]txtb_port_b_data_out_i; wire [31:0]txtb_port_b_data_out_i_6; wire [31:0]txtb_port_b_data_out_i_7; wire [31:0]txtb_port_b_data_out_i_8; (* SOFT_HLUTNM = "soft_lutpair314" *) LUT5 #( .INIT(32'h00000004)) control_registers_cs_reg_i_1 (.I0(adress_IBUF[7]), .I1(scs_IBUF), .I2(adress_IBUF[8]), .I3(adress_IBUF[9]), .I4(adress_IBUF[6]), .O(p_14_in)); FDCE control_registers_cs_reg_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_3), .D(p_14_in), .Q(control_registers_cs_reg)); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[0]_inst_i_1 (.I0(control_registers_rdata[0]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[0]), .O(data_out_OBUF[0])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[10]_inst_i_1 (.I0(control_registers_rdata[10]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[10]), .O(data_out_OBUF[10])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[11]_inst_i_1 (.I0(control_registers_rdata[11]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[11]), .O(data_out_OBUF[11])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[12]_inst_i_1 (.I0(control_registers_rdata[12]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[12]), .O(data_out_OBUF[12])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[13]_inst_i_1 (.I0(control_registers_rdata[13]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[13]), .O(data_out_OBUF[13])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[14]_inst_i_1 (.I0(control_registers_rdata[14]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[14]), .O(data_out_OBUF[14])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[15]_inst_i_1 (.I0(control_registers_rdata[15]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[15]), .O(data_out_OBUF[15])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[16]_inst_i_1 (.I0(control_registers_rdata[16]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[16]), .O(data_out_OBUF[16])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[17]_inst_i_1 (.I0(control_registers_rdata[17]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[17]), .O(data_out_OBUF[17])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[18]_inst_i_1 (.I0(control_registers_rdata[18]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[18]), .O(data_out_OBUF[18])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[19]_inst_i_1 (.I0(control_registers_rdata[19]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[19]), .O(data_out_OBUF[19])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[1]_inst_i_1 (.I0(control_registers_rdata[1]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[1]), .O(data_out_OBUF[1])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[20]_inst_i_1 (.I0(control_registers_rdata[20]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[20]), .O(data_out_OBUF[20])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[21]_inst_i_1 (.I0(control_registers_rdata[21]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[21]), .O(data_out_OBUF[21])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[22]_inst_i_1 (.I0(control_registers_rdata[22]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[22]), .O(data_out_OBUF[22])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[23]_inst_i_1 (.I0(control_registers_rdata[23]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[23]), .O(data_out_OBUF[23])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[24]_inst_i_1 (.I0(control_registers_rdata[24]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[24]), .O(data_out_OBUF[24])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[25]_inst_i_1 (.I0(control_registers_rdata[25]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[25]), .O(data_out_OBUF[25])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[26]_inst_i_1 (.I0(control_registers_rdata[26]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[26]), .O(data_out_OBUF[26])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[27]_inst_i_1 (.I0(control_registers_rdata[27]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[27]), .O(data_out_OBUF[27])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[28]_inst_i_1 (.I0(control_registers_rdata[28]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[28]), .O(data_out_OBUF[28])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[29]_inst_i_1 (.I0(control_registers_rdata[29]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[29]), .O(data_out_OBUF[29])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[2]_inst_i_1 (.I0(control_registers_rdata[2]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[2]), .O(data_out_OBUF[2])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[30]_inst_i_1 (.I0(control_registers_rdata[30]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[30]), .O(data_out_OBUF[30])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[31]_inst_i_1 (.I0(control_registers_rdata[31]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[31]), .O(data_out_OBUF[31])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[3]_inst_i_1 (.I0(control_registers_rdata[3]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[3]), .O(data_out_OBUF[3])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[4]_inst_i_1 (.I0(control_registers_rdata[4]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[4]), .O(data_out_OBUF[4])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[5]_inst_i_1 (.I0(control_registers_rdata[5]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[5]), .O(data_out_OBUF[5])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[6]_inst_i_1 (.I0(control_registers_rdata[6]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[6]), .O(data_out_OBUF[6])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[7]_inst_i_1 (.I0(control_registers_rdata[7]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[7]), .O(data_out_OBUF[7])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[8]_inst_i_1 (.I0(control_registers_rdata[8]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[8]), .O(data_out_OBUF[8])); LUT4 #( .INIT(16'hB888)) \data_out_OBUF[9]_inst_i_1 (.I0(control_registers_rdata[9]), .I1(control_registers_cs_reg), .I2(test_registers_cs_reg), .I3(test_registers_rdata[9]), .O(data_out_OBUF[9])); test_registers_reg_map \g_test_registers_true.i_test_registers_reg_map (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .Q(Q), .\adress[10] (\g_test_registers_true.i_test_registers_reg_map_n_37 ), .\adress[11] (\g_test_registers_true.i_test_registers_reg_map_n_210 ), .\adress[7] (\g_test_registers_true.i_test_registers_reg_map_n_36 ), .\adress[7]_0 (\g_test_registers_true.i_test_registers_reg_map_n_42 ), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF), .\g_bit[0].reg_value_r_reg[0] (\mr_tst_out[tst_dest_tst_addr] [0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[7].reg_value_r_reg[7] [0]), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[7].reg_value_r_reg[7] [8]), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[7].reg_value_r_reg[7] [15]), .\g_bit[0].reg_value_r_reg[0]_3 (\g_bit[7].reg_value_r_reg[7] [23]), .\g_bit[0].reg_value_r_reg[0]_4 (tst_ena), .\g_bit[0].reg_value_r_reg[0]_5 (\g_bit[0].reg_value_r_reg[0]_18 ), .\g_bit[0].reg_value_r_reg[0]_6 (tst_ena_0), .\g_bit[0].reg_value_r_reg[0]_7 (tst_ena_1), .\g_bit[0].reg_value_r_reg[0]_8 (tst_ena_2), .\g_bit[1].reg_value_r_reg[1] (\mr_tst_out[tst_dest_tst_addr] [1]), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[7].reg_value_r_reg[7] [1]), .\g_bit[1].reg_value_r_reg[1]_1 (\g_bit[7].reg_value_r_reg[7] [9]), .\g_bit[1].reg_value_r_reg[1]_2 (\g_bit[7].reg_value_r_reg[7] [16]), .\g_bit[1].reg_value_r_reg[1]_3 (\g_bit[7].reg_value_r_reg[7] [24]), .\g_bit[2].reg_value_r_reg[2] (\mr_tst_out[tst_dest_tst_addr] [2]), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[7].reg_value_r_reg[7] [2]), .\g_bit[2].reg_value_r_reg[2]_1 (\g_bit[7].reg_value_r_reg[7] [10]), .\g_bit[2].reg_value_r_reg[2]_2 (\g_bit[7].reg_value_r_reg[7] [17]), .\g_bit[2].reg_value_r_reg[2]_3 (\g_bit[7].reg_value_r_reg[7] [25]), .\g_bit[3].reg_value_r_reg[3] (\mr_tst_out[tst_dest_tst_addr] [3]), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[7].reg_value_r_reg[7] [3]), .\g_bit[3].reg_value_r_reg[3]_1 (\g_bit[7].reg_value_r_reg[7] [11]), .\g_bit[3].reg_value_r_reg[3]_2 (\g_bit[7].reg_value_r_reg[7] [18]), .\g_bit[3].reg_value_r_reg[3]_3 (\g_bit[7].reg_value_r_reg[7] [26]), .\g_bit[4].reg_value_r_reg[4] (\mr_tst_out[tst_dest_tst_addr] [4]), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[7].reg_value_r_reg[7] [4]), .\g_bit[4].reg_value_r_reg[4]_1 (\g_bit[7].reg_value_r_reg[7] [12]), .\g_bit[4].reg_value_r_reg[4]_10 (\g_bit[4].reg_value_r_reg[4]_9 ), .\g_bit[4].reg_value_r_reg[4]_2 (\g_bit[7].reg_value_r_reg[7] [19]), .\g_bit[4].reg_value_r_reg[4]_3 (\g_bit[7].reg_value_r_reg[7] [27]), .\g_bit[4].reg_value_r_reg[4]_4 (\g_bit[4].reg_value_r_reg[4]_3 ), .\g_bit[4].reg_value_r_reg[4]_5 (\g_bit[4].reg_value_r_reg[4]_4 ), .\g_bit[4].reg_value_r_reg[4]_6 (\g_bit[4].reg_value_r_reg[4]_5 ), .\g_bit[4].reg_value_r_reg[4]_7 (\g_bit[4].reg_value_r_reg[4]_6 ), .\g_bit[4].reg_value_r_reg[4]_8 (\g_bit[4].reg_value_r_reg[4]_7 ), .\g_bit[4].reg_value_r_reg[4]_9 (\g_bit[4].reg_value_r_reg[4]_8 ), .\g_bit[5].reg_value_r_reg[5] (\g_bit[7].reg_value_r_reg[7] [5]), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[7].reg_value_r_reg[7] [13]), .\g_bit[5].reg_value_r_reg[5]_1 (\g_bit[7].reg_value_r_reg[7] [20]), .\g_bit[5].reg_value_r_reg[5]_2 (\g_bit[7].reg_value_r_reg[7] [28]), .\g_bit[6].reg_value_r_reg[6] (\g_bit[7].reg_value_r_reg[7] [6]), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[7].reg_value_r_reg[7] [21]), .\g_bit[6].reg_value_r_reg[6]_1 (\g_bit[7].reg_value_r_reg[7] [29]), .\g_bit[7].reg_value_r_reg[7] (\g_bit[7].reg_value_r_reg[7] [7]), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7] [14]), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7] [22]), .\g_bit[7].reg_value_r_reg[7]_10 (reg_q_reg), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7] [30]), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[7].reg_value_r_reg[7]_0 ), .\g_bit[7].reg_value_r_reg[7]_4 (\g_bit[7].reg_value_r_reg[7]_1 ), .\g_bit[7].reg_value_r_reg[7]_5 (\g_bit[7].reg_value_r_reg[7]_2 ), .\g_bit[7].reg_value_r_reg[7]_6 (\g_bit[7].reg_value_r_reg[7]_3 ), .\g_bit[7].reg_value_r_reg[7]_7 (\g_bit[7].reg_value_r_reg[7]_4 ), .\g_bit[7].reg_value_r_reg[7]_8 (\g_bit[7].reg_value_r_reg[7]_5 ), .\g_bit[7].reg_value_r_reg[7]_9 (\g_bit[7].reg_value_r_reg[7]_6 ), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg_0 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_1 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_2 ), .\g_ram_rst_false.ram_memory_reg_3 (\g_ram_rst_false.ram_memory_reg_3 ), .\g_ram_rst_false.ram_memory_reg_4 (\g_ram_rst_false.ram_memory_reg_4 ), .\g_ram_rst_false.ram_memory_reg_5 (\g_ram_rst_false.ram_memory_reg_5 ), .\g_ram_rst_false.ram_memory_reg_6 (\g_ram_rst_false.ram_memory_reg_6 ), .\r_data_reg[1]_0 (i_control_registers_reg_map_n_163), .\r_data_reg[31]_0 (test_registers_rdata), .rxb_port_b_data_out_i(rxb_port_b_data_out_i), .sbe_IBUF(sbe_IBUF), .scs_IBUF(scs_IBUF), .srd_IBUF(srd_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_b_data_out_i(txtb_port_b_data_out_i), .txtb_port_b_data_out_i_6(txtb_port_b_data_out_i_6), .txtb_port_b_data_out_i_7(txtb_port_b_data_out_i_7), .txtb_port_b_data_out_i_8(txtb_port_b_data_out_i_8), .wr_en(\i_tst_control_tmaena_reg/wr_en ), .wr_en_0(\i_tst_dest_tst_addr_slice_1_reg/wr_en ), .wr_en_1(\i_tst_dest_tst_addr_slice_2_reg/wr_en ), .wr_en_2(\i_tst_dest_tst_mtgt_reg/wr_en ), .wr_en_3(\i_tst_wdata_tst_wdata_slice_1_reg/wr_en ), .wr_en_4(\i_tst_wdata_tst_wdata_slice_2_reg/wr_en ), .wr_en_5(\i_tst_wdata_tst_wdata_slice_3_reg/wr_en ), .wr_en_6(\i_tst_wdata_tst_wdata_slice_4_reg/wr_en )); control_registers_reg_map i_control_registers_reg_map (.CO(CO), .D(D), .DI(\mr_ctrl_out[btr_ph2] [3:0]), .E(E), .\FSM_onehot_current_state_reg[2] (\FSM_onehot_current_state_reg[2] ), .\FSM_sequential_curr_state[0]_i_2__0 (\FSM_sequential_curr_state[0]_i_2__0 ), .\FSM_sequential_curr_state[0]_i_2__0_0 (\FSM_sequential_curr_state[0]_i_2__0_0 ), .\FSM_sequential_curr_state[0]_i_2__2 (\FSM_sequential_curr_state[0]_i_2__2 ), .\FSM_sequential_curr_state_reg[0] (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_1 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[2] (\FSM_sequential_curr_state_reg[2] ), .O(O), .Q(control_registers_rdata), .S(S), .abort_applied(abort_applied), .abort_applied_3(abort_applied_3), .\adress[2] (\adress[2] ), .\adress[2]_0 (\adress[2]_0 ), .\adress[3] (\adress[3] ), .\adress[3]_0 (\adress[3]_0 ), .\adress[4] (\adress[4] ), .\adress[4]_0 (\adress[4]_0 ), .\adress[4]_1 (\adress[4]_1 ), .\adress[4]_2 (\adress[4]_2 ), .\adress[5] (\adress[5] ), .\adress[5]_0 (\adress[5]_0 ), .\adress[5]_1 (\adress[5]_1 ), .\adress[5]_2 (\adress[5]_2 ), .\adress[6] (\adress[6] ), .\adress[6]_0 (\adress[6]_0 ), .\adress[8] (\adress[8] ), .adress_IBUF(adress_IBUF), .bit_err_d0_out(bit_err_d0_out), .bit_err_d2(bit_err_d2), .bit_err_enable(bit_err_enable), .bit_err_q_reg(bit_err_q_reg), .bit_err_q_reg_0(bit_err_q_reg_0), .can_tx_OBUF(can_tx_OBUF), .\cc_stat[is_err_active] (\cc_stat[is_err_active] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .crc_data_tx_wbs(crc_data_tx_wbs), .curr_state(curr_state), .current_state_reg(current_state_reg), .data_in_IBUF(data_in_IBUF), .\err_capt_err_type_q[2]_i_13 (\err_capt_err_type_q[2]_i_13 ), .\exp_seg_length_d9_inferred__0/i__carry (\exp_seg_length_d9_inferred__0/i__carry ), .\exp_seg_length_d9_inferred__0/i__carry_0 (\exp_seg_length_d9_inferred__0/i__carry_0 ), .\exp_seg_length_d9_inferred__0/i__carry_1 (\exp_seg_length_d9_inferred__0/i__carry_1 ), .\exp_seg_length_d9_inferred__0/i__carry_2 (\exp_seg_length_d9_inferred__0/i__carry_2 ), .\exp_seg_length_q[6]_i_2 (\exp_seg_length_q[6]_i_2 ), .\exp_seg_length_q[6]_i_2_0 (\exp_seg_length_q[6]_i_2_0 ), .\exp_seg_length_q[7]_i_11 (\exp_seg_length_q[7]_i_11 ), .\exp_seg_length_q_reg[7]_i_2__0 (\exp_seg_length_q_reg[7]_i_2__0 ), .\exp_seg_length_q_reg[7]_i_2__0_0 (\exp_seg_length_q_reg[7]_i_2__0_0 ), .fsm_wait_state_q(fsm_wait_state_q), .fsm_wait_state_q_reg(fsm_wait_state_q_reg), .\g_bit[0].reg_value_r_reg[0] (\mr_ctrl_out[mode_bmm] ), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[0].reg_value_r_reg[0]_1 (\mr_ctrl_out[mode_fde] ), .\g_bit[0].reg_value_r_reg[0]_10 (\mr_ctrl_out[btr_fd_ph2_fd] [3:0]), .\g_bit[0].reg_value_r_reg[0]_11 (\mr_ctrl_out[ewl_ew_limit] [0]), .\g_bit[0].reg_value_r_reg[0]_12 (\mr_ctrl_out[erp_erp_limit] [0]), .\g_bit[0].reg_value_r_reg[0]_13 (\g_bit[0].reg_value_r_reg[0]_2 ), .\g_bit[0].reg_value_r_reg[0]_14 (\g_bit[0].reg_value_r_reg[0]_3 ), .\g_bit[0].reg_value_r_reg[0]_15 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_bit[0].reg_value_r_reg[0]_16 (\g_bit[0].reg_value_r_reg[0]_5 ), .\g_bit[0].reg_value_r_reg[0]_17 (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_bit[0].reg_value_r_reg[0]_18 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_bit[0].reg_value_r_reg[0]_19 (\g_bit[0].reg_value_r_reg[0]_8 ), .\g_bit[0].reg_value_r_reg[0]_2 (\mr_ctrl_out[mode_rom] ), .\g_bit[0].reg_value_r_reg[0]_20 (\g_bit[0].reg_value_r_reg[0]_9 ), .\g_bit[0].reg_value_r_reg[0]_21 (\g_bit[0].reg_value_r_reg[0]_10 ), .\g_bit[0].reg_value_r_reg[0]_22 (\g_bit[0].reg_value_r_reg[0]_11 ), .\g_bit[0].reg_value_r_reg[0]_23 (\g_bit[0].reg_value_r_reg[0]_12 ), .\g_bit[0].reg_value_r_reg[0]_24 (mr_tx_command_txbi[0]), .\g_bit[0].reg_value_r_reg[0]_25 (mr_tx_command_txbi[1]), .\g_bit[0].reg_value_r_reg[0]_26 (\mr_ctrl_out[ssp_cfg_ssp_src] [0]), .\g_bit[0].reg_value_r_reg[0]_27 (i_control_registers_reg_map_n_133), .\g_bit[0].reg_value_r_reg[0]_28 (\g_bit[0].reg_value_r_reg[0]_13 ), .\g_bit[0].reg_value_r_reg[0]_29 (\g_bit[0].reg_value_r_reg[0]_14 ), .\g_bit[0].reg_value_r_reg[0]_3 (\mr_ctrl_out[mode_tstm] ), .\g_bit[0].reg_value_r_reg[0]_30 (\g_bit[0].reg_value_r_reg[0]_15 ), .\g_bit[0].reg_value_r_reg[0]_31 (\g_bit[0].reg_value_r_reg[0]_16 ), .\g_bit[0].reg_value_r_reg[0]_32 (i_control_registers_reg_map_n_163), .\g_bit[0].reg_value_r_reg[0]_33 (\g_bit[0].reg_value_r_reg[0]_17 ), .\g_bit[0].reg_value_r_reg[0]_34 (\g_bit[0].reg_value_r_reg[0]_19 ), .\g_bit[0].reg_value_r_reg[0]_35 (\g_bit[0].reg_value_r_reg[0]_20 ), .\g_bit[0].reg_value_r_reg[0]_36 (\g_bit[0].reg_value_r_reg[0]_21 ), .\g_bit[0].reg_value_r_reg[0]_37 (\g_bit[0].reg_value_r_reg[0]_22 ), .\g_bit[0].reg_value_r_reg[0]_38 (\g_bit[0].reg_value_r_reg[0]_23 ), .\g_bit[0].reg_value_r_reg[0]_39 (\g_bit[0].reg_value_r_reg[0]_24 ), .\g_bit[0].reg_value_r_reg[0]_4 (\mr_ctrl_out[mode_txbbm] ), .\g_bit[0].reg_value_r_reg[0]_40 (\g_bit[0].reg_value_r_reg[0]_25 ), .\g_bit[0].reg_value_r_reg[0]_41 (\g_bit[0].reg_value_r_reg[0]_26 ), .\g_bit[0].reg_value_r_reg[0]_42 (\g_bit[0].reg_value_r_reg[0]_27 ), .\g_bit[0].reg_value_r_reg[0]_43 (\g_bit[0].reg_value_r_reg[0]_28 ), .\g_bit[0].reg_value_r_reg[0]_44 (\g_bit[0].reg_value_r_reg[0]_29 ), .\g_bit[0].reg_value_r_reg[0]_45 (\g_bit[0].reg_value_r_reg[0]_30 ), .\g_bit[0].reg_value_r_reg[0]_46 (\g_bit[0].reg_value_r_reg[0]_31 ), .\g_bit[0].reg_value_r_reg[0]_47 (\g_bit[0].reg_value_r_reg[0]_32 ), .\g_bit[0].reg_value_r_reg[0]_48 (\g_bit[0].reg_value_r_reg[0]_33 ), .\g_bit[0].reg_value_r_reg[0]_49 (\g_bit[0].reg_value_r_reg[0]_34 ), .\g_bit[0].reg_value_r_reg[0]_5 (\mr_ctrl_out[settings_ena] ), .\g_bit[0].reg_value_r_reg[0]_50 (\g_bit[0].reg_value_r_reg[0]_35 ), .\g_bit[0].reg_value_r_reg[0]_51 (\g_bit[0].reg_value_r_reg[0]_36 ), .\g_bit[0].reg_value_r_reg[0]_52 (\g_bit[0].reg_value_r_reg[0]_37 ), .\g_bit[0].reg_value_r_reg[0]_53 (\g_bit[0].reg_value_r_reg[0]_38 ), .\g_bit[0].reg_value_r_reg[0]_54 (\g_test_registers_true.i_test_registers_reg_map_n_36 ), .\g_bit[0].reg_value_r_reg[0]_55 (\g_bit[0].reg_value_r_reg[0]_39 ), .\g_bit[0].reg_value_r_reg[0]_56 (\g_test_registers_true.i_test_registers_reg_map_n_37 ), .\g_bit[0].reg_value_r_reg[0]_57 (\g_test_registers_true.i_test_registers_reg_map_n_42 ), .\g_bit[0].reg_value_r_reg[0]_58 (\g_bit[0].reg_value_r_reg[0]_40 ), .\g_bit[0].reg_value_r_reg[0]_6 (\mr_ctrl_out[settings_tbfbo] ), .\g_bit[0].reg_value_r_reg[0]_7 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[0].reg_value_r_reg[0]_8 (\g_bit[0].reg_value_r_reg[0]_1 ), .\g_bit[0].reg_value_r_reg[0]_9 (\mr_ctrl_out[btr_sjw] [0]), .\g_bit[1].reg_value_r_reg[1] (\mr_ctrl_out[btr_sjw] [1]), .\g_bit[1].reg_value_r_reg[1]_0 (\mr_ctrl_out[btr_fd_ph2_fd] [4]), .\g_bit[1].reg_value_r_reg[1]_1 (\mr_ctrl_out[ewl_ew_limit] [1]), .\g_bit[1].reg_value_r_reg[1]_10 (\g_bit[1].reg_value_r_reg[1]_5 ), .\g_bit[1].reg_value_r_reg[1]_11 (\g_bit[1].reg_value_r_reg[1]_6 ), .\g_bit[1].reg_value_r_reg[1]_2 (\mr_ctrl_out[erp_erp_limit] [1]), .\g_bit[1].reg_value_r_reg[1]_3 (\mr_ctrl_out[ssp_cfg_ssp_src] [1]), .\g_bit[1].reg_value_r_reg[1]_4 (\g_bit[1].reg_value_r_reg[1] ), .\g_bit[1].reg_value_r_reg[1]_5 (\g_bit[1].reg_value_r_reg[1]_0 ), .\g_bit[1].reg_value_r_reg[1]_6 (\g_bit[1].reg_value_r_reg[1]_1 ), .\g_bit[1].reg_value_r_reg[1]_7 (\g_bit[1].reg_value_r_reg[1]_2 ), .\g_bit[1].reg_value_r_reg[1]_8 (\g_bit[1].reg_value_r_reg[1]_3 ), .\g_bit[1].reg_value_r_reg[1]_9 (\g_bit[1].reg_value_r_reg[1]_4 ), .\g_bit[2].reg_value_r_reg[2] (\mr_ctrl_out[btr_sjw] [2]), .\g_bit[2].reg_value_r_reg[2]_0 (\mr_ctrl_out[ewl_ew_limit] [2]), .\g_bit[2].reg_value_r_reg[2]_1 (\mr_ctrl_out[erp_erp_limit] [2]), .\g_bit[2].reg_value_r_reg[2]_2 (\g_bit[2].reg_value_r_reg[2] ), .\g_bit[2].reg_value_r_reg[2]_3 (\g_bit[2].reg_value_r_reg[2]_0 ), .\g_bit[2].reg_value_r_reg[2]_4 (\g_bit[2].reg_value_r_reg[2]_1 ), .\g_bit[2].reg_value_r_reg[2]_5 (\g_bit[2].reg_value_r_reg[2]_2 ), .\g_bit[2].reg_value_r_reg[2]_6 (\g_bit[2].reg_value_r_reg[2]_3 ), .\g_bit[2].reg_value_r_reg[2]_7 (\g_bit[2].reg_value_r_reg[2]_4 ), .\g_bit[2].reg_value_r_reg[2]_8 (reg_q_reg), .\g_bit[2].reg_value_r_reg[2]_9 (reg_q_reg_4), .\g_bit[3].reg_value_r_reg[3] (\g_bit[3].reg_value_r_reg[3] ), .\g_bit[3].reg_value_r_reg[3]_0 (\mr_ctrl_out[btr_sjw] [3]), .\g_bit[3].reg_value_r_reg[3]_1 (\mr_ctrl_out[ewl_ew_limit] [3]), .\g_bit[3].reg_value_r_reg[3]_2 (\mr_ctrl_out[erp_erp_limit] [3]), .\g_bit[3].reg_value_r_reg[3]_3 (\g_bit[3].reg_value_r_reg[3]_0 ), .\g_bit[3].reg_value_r_reg[3]_4 (\g_bit[3].reg_value_r_reg[3]_1 ), .\g_bit[3].reg_value_r_reg[3]_5 (\g_bit[3].reg_value_r_reg[3]_2 ), .\g_bit[3].reg_value_r_reg[3]_6 (\g_bit[3].reg_value_r_reg[3]_3 ), .\g_bit[3].reg_value_r_reg[3]_7 (\g_bit[3].reg_value_r_reg[3]_4 ), .\g_bit[4].reg_value_r_reg[4] (\mr_ctrl_out[btr_sjw] [4]), .\g_bit[4].reg_value_r_reg[4]_0 (\mr_ctrl_out[ewl_ew_limit] [4]), .\g_bit[4].reg_value_r_reg[4]_1 (\mr_ctrl_out[erp_erp_limit] [4]), .\g_bit[4].reg_value_r_reg[4]_2 (\g_bit[4].reg_value_r_reg[4] ), .\g_bit[4].reg_value_r_reg[4]_3 (\g_bit[4].reg_value_r_reg[4]_0 ), .\g_bit[4].reg_value_r_reg[4]_4 (\g_bit[4].reg_value_r_reg[4]_1 ), .\g_bit[4].reg_value_r_reg[4]_5 (\g_bit[4].reg_value_r_reg[4]_2 ), .\g_bit[4].reg_value_r_reg[4]_6 (\g_bit[4].reg_value_r_reg[4]_10 ), .\g_bit[4].reg_value_r_reg[4]_7 (\g_bit[4].reg_value_r_reg[4]_11 ), .\g_bit[4].reg_value_r_reg[4]_8 (\g_bit[4].reg_value_r_reg[4]_12 ), .\g_bit[4].reg_value_r_reg[4]_9 (\g_bit[4].reg_value_r_reg[4]_13 ), .\g_bit[5].reg_value_r_reg[5] (\mr_ctrl_out[ewl_ew_limit] [5]), .\g_bit[5].reg_value_r_reg[5]_0 (\mr_ctrl_out[erp_erp_limit] [5]), .\g_bit[5].reg_value_r_reg[5]_1 (\g_bit[5].reg_value_r_reg[5] ), .\g_bit[6].reg_value_r_reg[6] (\mr_ctrl_out[ewl_ew_limit] [6]), .\g_bit[6].reg_value_r_reg[6]_0 (\mr_ctrl_out[erp_erp_limit] [6]), .\g_bit[6].reg_value_r_reg[6]_1 (\g_bit[6].reg_value_r_reg[6] ), .\g_bit[7].reg_value_r_reg[7] (\mr_ctrl_out[ewl_ew_limit] [7]), .\g_bit[7].reg_value_r_reg[7]_0 (\mr_ctrl_out[erp_erp_limit] [7]), .\g_bit[7].reg_value_r_reg[7]_1 (DI), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7]_7 ), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[7].reg_value_r_reg[7]_8 ), .\g_bit[7].reg_value_r_reg[7]_4 (\g_test_registers_true.i_test_registers_reg_map_n_210 ), .i__carry_i_2__4(i__carry_i_2__4), .i__carry_i_9(i__carry_i_9), .\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 (\i_btl_segment_meter_dbt/exp_seg_length_q[7]_i_10 ), .is_tseg2(is_tseg2), .mr_btr_prop(mr_btr_prop), .\mr_ctrl_out[btr_fd_ph1_fd] (\mr_ctrl_out[btr_fd_ph1_fd] ), .\mr_ctrl_out[btr_fd_prop_fd] (\mr_ctrl_out[btr_fd_prop_fd] ), .\mr_ctrl_out[btr_ph1] (\mr_ctrl_out[btr_ph1] ), .\mr_ctrl_out[btr_ph2] (\mr_ctrl_out[btr_ph2] [5:4]), .\mr_ctrl_out[ctr_pres_ctpv] (\mr_ctrl_out[ctr_pres_ctpv] ), .\mr_ctrl_out[ctr_pres_efd] (\mr_ctrl_out[ctr_pres_efd] ), .\mr_ctrl_out[ctr_pres_enorm] (\mr_ctrl_out[ctr_pres_enorm] ), .\mr_ctrl_out[ctr_pres_prx] (\mr_ctrl_out[ctr_pres_prx] ), .\mr_ctrl_out[ctr_pres_ptx] (\mr_ctrl_out[ctr_pres_ptx] ), .\mr_ctrl_out[mode_acf] (\mr_ctrl_out[mode_acf] ), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .\mr_ctrl_out[mode_sam] (\mr_ctrl_out[mode_sam] ), .\mr_ctrl_out[mode_stm] (\mr_ctrl_out[mode_stm] ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_ctrl_out[settings_ilbp] (\mr_ctrl_out[settings_ilbp] ), .\mr_ctrl_out[settings_nisofd] (\mr_ctrl_out[settings_nisofd] ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\mr_ctrl_out[settings_rtrle] (\mr_ctrl_out[settings_rtrle] ), .\mr_ctrl_out[ssp_cfg_ssp_offset] (\mr_ctrl_out[ssp_cfg_ssp_offset] ), .mr_settings_ena_reg(mr_settings_ena_reg), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .mr_tx_command_txca_q(mr_tx_command_txca_q), .mr_tx_command_txce_q(mr_tx_command_txce_q), .mr_tx_command_txcr_q(mr_tx_command_txcr_q), .\mr_tx_priority[0] (\mr_tx_priority[0] ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .\mr_tx_priority[2] (\mr_tx_priority[2] ), .\mr_tx_priority[3] (\mr_tx_priority[3] ), .neg_phase_err(neg_phase_err), .next_state2_carry(next_state2_carry), .\next_state2_inferred__0/i__carry (\next_state2_inferred__0/i__carry ), .\nom_err_ctr_q_reg[10] (\nom_err_ctr_q_reg[10] ), .\nom_err_ctr_q_reg[9] (\nom_err_ctr_q_reg[9] ), .pc_rx_data_nbs(pc_rx_data_nbs), .\r_data[17]_i_2 (\r_data[17]_i_2 ), .\r_data_reg[12]_0 (\r_data_reg[12] ), .\r_data_reg[12]_1 (\r_data_reg[12]_0 ), .\r_data_reg[12]_2 (\r_data_reg[12]_1 ), .\r_data_reg[21]_0 (\r_data_reg[21] ), .\r_data_reg[21]_1 (\r_data_reg[21]_0 ), .\r_data_reg[21]_2 (\r_data_reg[21]_1 ), .\r_data_reg[22]_0 (\r_data_reg[22] ), .\r_data_reg[22]_1 (\r_data_reg[22]_0 ), .\r_data_reg[23]_0 (\r_data_reg[23] ), .\r_data_reg[23]_1 (\r_data_reg[23]_0 ), .\r_data_reg[25]_0 (\r_data_reg[25] ), .\r_data_reg[31]_0 (\r_data_reg[31] ), .\r_data_reg[3]_0 (\r_data_reg[3] ), .\r_data_reg[3]_1 (\r_data_reg[3]_0 ), .\r_data_reg[3]_2 (\r_data_reg[3]_1 ), .\r_data_reg[5]_0 (\r_data_reg[5] ), .\r_data_reg[5]_1 (\r_data_reg[5]_0 ), .\r_data_reg[5]_2 (\r_data_reg[5]_1 ), .\r_data_reg[5]_3 (\r_data_reg[5]_2 ), .\r_data_reg[7]_0 (\r_data_reg[7] ), .\r_data_reg[7]_1 (\r_data_reg[7]_0 ), .\r_data_reg[7]_2 (\r_data_reg[7]_1 ), .rx_data_wbs(rx_data_wbs), .sbe_IBUF(sbe_IBUF), .scs_IBUF(scs_IBUF), .\segm_counter_q_reg[0] (\segm_counter_q_reg[0] ), .\segm_counter_q_reg[0]_0 (\segm_counter_q_reg[0]_0 ), .\segm_counter_q_reg[4] (\segm_counter_q_reg[4] ), .\segm_counter_q_reg[6] (\segm_counter_q_reg[6] ), .\select_buf_index_reg_reg[0] (\select_buf_index_reg_reg[0] ), .\select_buf_index_reg_reg[0]_0 (\select_buf_index_reg_reg[0]_0 ), .\select_buf_index_reg_reg[1] (\select_buf_index_reg_reg[1] ), .\select_buf_index_reg_reg[1]_0 (\select_buf_index_reg_reg[1]_0 ), .soft_res_d_n(soft_res_d_n), .srd_IBUF(srd_IBUF), .swr_IBUF(swr_IBUF), .\test_probe[tx_trigger]_INST_0_i_27 (\test_probe[tx_trigger]_INST_0_i_27 ), .\test_probe[tx_trigger]_INST_0_i_4 (\test_probe[tx_trigger]_INST_0_i_4 ), .\test_probe[tx_trigger]_INST_0_i_4_0 (\test_probe[tx_trigger]_INST_0_i_4_0 ), .\test_probe[tx_trigger]_INST_0_i_7 (\test_probe[tx_trigger]_INST_0_i_7 ), .\test_probe[tx_trigger]_INST_0_i_7_0 (\test_probe[tx_trigger]_INST_0_i_7_0 ), .\test_probe[tx_trigger]_INST_0_i_9 (\test_probe[tx_trigger]_INST_0_i_9 ), .\test_probe[tx_trigger]_INST_0_i_9_0 (\test_probe[tx_trigger]_INST_0_i_9_0 ), .\timestamp[26] (\timestamp[26] ), .\timestamp[27] (\timestamp[27] ), .\timestamp[28] (\timestamp[28] ), .\timestamp[38] (\timestamp[38] ), .\timestamp[44] (\timestamp[44] ), .\timestamp[50] (\timestamp[50] ), .\timestamp[61] (\timestamp[61] ), .\timestamp[62] (\timestamp[62] ), .\timestamp[63] (\timestamp[63] ), .timestamp_IBUF(timestamp_IBUF), .\tq_counter_q_reg[6] (\tq_counter_q_reg[6] ), .\tq_counter_q_reg[7] (\tq_counter_q_reg[7] ), .tran_frame_type(tran_frame_type), .tran_frame_valid_com_reg(tran_frame_valid_com_reg), .trv_delay_sum(trv_delay_sum), .\tseg1_dbt_reg[3] (\tseg1_dbt_reg[3] ), .\tseg1_dbt_reg[4] (\tseg1_dbt_reg[4] ), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txce_valid_5(tx_command_txce_valid_5), .tx_command_txcr_valid(tx_command_txcr_valid), .tx_command_txcr_valid_4(tx_command_txcr_valid_4), .txtb_allow_bb(txtb_allow_bb), .txtb_available(txtb_available), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .\txtb_hw_cmd_q[err] (\txtb_hw_cmd_q[err] ), .\txtb_hw_cmd_q_reg[err] (\txtb_hw_cmd_q_reg[err] ), .\txtb_hw_cmd_q_reg[err]_0 (\txtb_hw_cmd_q_reg[err]_0 ), .\txtb_hw_cmd_q_reg[lock] (\txtb_hw_cmd_q_reg[lock] ), .wr_en(\i_tst_dest_tst_mtgt_reg/wr_en ), .wr_en_0(\i_tst_dest_tst_addr_slice_2_reg/wr_en ), .wr_en_1(\i_tst_dest_tst_addr_slice_1_reg/wr_en ), .wr_en_2(\i_tst_wdata_tst_wdata_slice_4_reg/wr_en ), .wr_en_3(\i_tst_wdata_tst_wdata_slice_3_reg/wr_en ), .wr_en_4(\i_tst_wdata_tst_wdata_slice_2_reg/wr_en ), .wr_en_5(\i_tst_wdata_tst_wdata_slice_1_reg/wr_en ), .wr_en_6(\i_tst_control_tmaena_reg/wr_en )); rst_reg_0 i_global_rst_rst_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[2]), .reg_q_reg(q_i), .reg_q_reg_0(reg_q_reg_0), .reg_q_reg_1(reg_q_reg_1), .reg_q_reg_2(reg_q_reg_2), .reg_q_reg_3(i_control_registers_reg_map_n_133), .reg_q_reg_4(reg_q_reg_3), .reg_q_reg_5(reg_q_reg_4), .reg_q_reg_6(reg_q_reg_5), .reg_q_reg_7(reg_q_reg_6), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); rst_reg_1 i_soft_rst_rst_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg(reg_q_reg), .reg_q_reg_0(reg_q_reg_3), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF), .soft_res_d_n(soft_res_d_n)); (* SOFT_HLUTNM = "soft_lutpair314" *) LUT5 #( .INIT(32'h00000800)) test_registers_cs_reg_i_1 (.I0(adress_IBUF[9]), .I1(adress_IBUF[6]), .I2(adress_IBUF[7]), .I3(scs_IBUF), .I4(adress_IBUF[8]), .O(p_13_in)); FDCE test_registers_cs_reg_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(reg_q_reg_3), .D(p_13_in), .Q(test_registers_cs_reg)); endmodule module rst_reg (reg_q_reg, reg_q_reg_0, clk_sys_IBUF_BUFG, reg_q_reg_1, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg; input reg_q_reg_0; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire rst_n_out_OBUF; wire scan_mode_IBUF; dff_arst i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .reg_q_reg_2(reg_q_reg_1), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); endmodule (* ORIG_REF_NAME = "rst_reg" *) module rst_reg_0 (reg_q_reg, reg_q_reg_0, reg_q_reg_1, reg_q_reg_2, reg_q_reg_3, clk_sys_IBUF_BUFG, reg_q_reg_4, scan_mode_IBUF, rst_n_out_OBUF, data_in_IBUF, reg_q_reg_5, reg_q_reg_6, reg_q_reg_7); output reg_q_reg; output reg_q_reg_0; output reg_q_reg_1; output reg_q_reg_2; input reg_q_reg_3; input clk_sys_IBUF_BUFG; input reg_q_reg_4; input scan_mode_IBUF; input rst_n_out_OBUF; input [0:0]data_in_IBUF; input reg_q_reg_5; input reg_q_reg_6; input reg_q_reg_7; wire clk_sys_IBUF_BUFG; wire [0:0]data_in_IBUF; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire reg_q_reg_2; wire reg_q_reg_3; wire reg_q_reg_4; wire reg_q_reg_5; wire reg_q_reg_6; wire reg_q_reg_7; wire rst_n_out_OBUF; wire scan_mode_IBUF; dff_arst_3 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .reg_q_reg_2(reg_q_reg_1), .reg_q_reg_3(reg_q_reg_2), .reg_q_reg_4(reg_q_reg_3), .reg_q_reg_5(reg_q_reg_4), .reg_q_reg_6(reg_q_reg_5), .reg_q_reg_7(reg_q_reg_6), .reg_q_reg_8(reg_q_reg_7), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); endmodule (* ORIG_REF_NAME = "rst_reg" *) module rst_reg_1 (reg_q_reg, soft_res_d_n, clk_sys_IBUF_BUFG, reg_q_reg_0, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg; input soft_res_d_n; input clk_sys_IBUF_BUFG; input reg_q_reg_0; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire reg_q_reg; wire reg_q_reg_0; wire rst_n_out_OBUF; wire scan_mode_IBUF; wire soft_res_d_n; dff_arst_2 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF), .soft_res_d_n(soft_res_d_n)); endmodule (* ORIG_REF_NAME = "rst_reg" *) module rst_reg_58 (reg_q_reg, reg_q_reg_0, clk_sys_IBUF_BUFG, reg_q_reg_1, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg; input reg_q_reg_0; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire rst_n_out_OBUF; wire scan_mode_IBUF; dff_arst_59 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .reg_q_reg_2(reg_q_reg_1), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); endmodule (* ORIG_REF_NAME = "rst_reg" *) module rst_reg_60 (reg_q_reg, reg_q_reg_0, clk_sys_IBUF_BUFG, reg_q_reg_1, scan_mode_IBUF, rst_n_out_OBUF); output reg_q_reg; input reg_q_reg_0; input clk_sys_IBUF_BUFG; input reg_q_reg_1; input scan_mode_IBUF; input rst_n_out_OBUF; wire clk_sys_IBUF_BUFG; wire reg_q_reg; wire reg_q_reg_0; wire reg_q_reg_1; wire rst_n_out_OBUF; wire scan_mode_IBUF; dff_arst_61 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0), .reg_q_reg_2(reg_q_reg_1), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); endmodule (* ORIG_REF_NAME = "rst_reg" *) module rst_reg_82 (q_i, reg_q_reg, clk_sys_IBUF_BUFG, reg_q_reg_0); output q_i; input reg_q_reg; input clk_sys_IBUF_BUFG; input reg_q_reg_0; wire clk_sys_IBUF_BUFG; wire q_i; wire reg_q_reg; wire reg_q_reg_0; dff_arst_83 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .q_i(q_i), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(reg_q_reg_0)); endmodule (* ORIG_REF_NAME = "rst_reg" *) module rst_reg_84 (q_i, p_0_out, clk_sys_IBUF_BUFG, reg_q_reg); output q_i; input p_0_out; input clk_sys_IBUF_BUFG; input reg_q_reg; wire clk_sys_IBUF_BUFG; wire p_0_out; wire q_i; wire reg_q_reg; dff_arst_85 i_rx_shift_res_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .p_0_out(p_0_out), .q_i(q_i), .reg_q_reg_0(reg_q_reg)); endmodule module rst_sync (rst_n_out_OBUF, rst_reg_0, clk_sys_IBUF_BUFG, rst_n_IBUF, lopt); output rst_n_out_OBUF; output rst_reg_0; input clk_sys_IBUF_BUFG; input rst_n_IBUF; output lopt; wire clk_sys_IBUF_BUFG; wire rff; wire rff_i_1_n_0; wire rst_n_IBUF; wire rst_n_out_OBUF; wire rst_reg_0; wire rst_reg_lopt_replica_1; assign lopt = rst_reg_lopt_replica_1; LUT1 #( .INIT(2'h1)) reg_q_i_2__0 (.I0(rst_n_out_OBUF), .O(rst_reg_0)); LUT1 #( .INIT(2'h1)) rff_i_1 (.I0(rst_n_IBUF), .O(rff_i_1_n_0)); FDCE rff_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(rff_i_1_n_0), .D(1'b1), .Q(rff)); FDCE rst_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(rff_i_1_n_0), .D(rff), .Q(rst_n_out_OBUF)); (* OPT_INSERTED_REPDRIVER *) (* OPT_MODIFIED = "RESYNTH_AREA" *) FDCE #( .INIT(1'b0)) rst_reg_lopt_replica (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(rff_i_1_n_0), .D(rff), .Q(rst_reg_lopt_replica_1)); endmodule module rxb_fsm (E, data_overrun_i_reg, WEBWE, Q, rxb_port_a_data_in_i, \FSM_onehot_curr_state_reg[1]_0 , \FSM_onehot_curr_state_reg[6]_0 , \FSM_onehot_curr_state_reg[8]_0 , \g_byte_shift_reg[1].shift_reg_q_reg[1][6] , \FSM_onehot_curr_state_reg[7]_0 , \FSM_onehot_curr_state_reg[1]_1 , commit_overrun_abort_reg, \FSM_onehot_curr_state_reg[0]_0 , \FSM_onehot_curr_state_reg[11]_0 , data_overrun_flg_reg, data_overrun_i_reg_0, \rx_mem_free_raw_reg[5] , \write_pointer_raw_i_reg[0] , rec_abort, ident_valid_q, \mr_tst_out[tst_control_twrstb] , \g_ram_rst_false.ram_memory_reg , data_overrun_i, \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_ram_rst_false.ram_memory_reg_4 , data_overrun_i_reg_1, \FSM_onehot_curr_state_reg[11]_1 , \g_ram_rst_false.ram_memory_reg_i_111_0 , \FSM_onehot_curr_state_reg[0]_1 , \FSM_onehot_curr_state_reg[8]_1 , store_data_word, \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , rec_is_rtr, rec_ident_type, rec_frame_type, rec_brs, rec_esi, rec_ivld, rec_lbpf, \g_ram_rst_false.ram_memory_reg_7 , \g_ram_rst_false.ram_memory_reg_8 , \g_ram_rst_false.ram_memory_reg_9 , \mr_ctrl_out[mode_erfm] , rec_abort_f, \FSM_onehot_curr_state_reg[0]_2 , \cc_stat[err_erp] , store_metadata, rec_is_rtr_i, rec_valid, data_in_IBUF, data_overrun_i_reg_2, data_overrun_i_reg_3, commit_rx_frame, rx_data_overrun, clk_sys_IBUF_BUFG, \FSM_onehot_curr_state_reg[11]_2 , \FSM_onehot_curr_state_reg[6]_1 ); output [0:0]E; output data_overrun_i_reg; output [0:0]WEBWE; output [7:0]Q; output [30:0]rxb_port_a_data_in_i; output \FSM_onehot_curr_state_reg[1]_0 ; output [0:0]\FSM_onehot_curr_state_reg[6]_0 ; output \FSM_onehot_curr_state_reg[8]_0 ; output \g_byte_shift_reg[1].shift_reg_q_reg[1][6] ; output \FSM_onehot_curr_state_reg[7]_0 ; output \FSM_onehot_curr_state_reg[1]_1 ; output [0:0]commit_overrun_abort_reg; output \FSM_onehot_curr_state_reg[0]_0 ; output \FSM_onehot_curr_state_reg[11]_0 ; output data_overrun_flg_reg; output data_overrun_i_reg_0; input \rx_mem_free_raw_reg[5] ; input \write_pointer_raw_i_reg[0] ; input rec_abort; input ident_valid_q; input \mr_tst_out[tst_control_twrstb] ; input \g_ram_rst_false.ram_memory_reg ; input data_overrun_i; input [30:0]\g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input \g_ram_rst_false.ram_memory_reg_2 ; input \g_ram_rst_false.ram_memory_reg_3 ; input [63:0]\g_ram_rst_false.ram_memory_reg_4 ; input data_overrun_i_reg_1; input \FSM_onehot_curr_state_reg[11]_1 ; input \g_ram_rst_false.ram_memory_reg_i_111_0 ; input \FSM_onehot_curr_state_reg[0]_1 ; input \FSM_onehot_curr_state_reg[8]_1 ; input [31:0]store_data_word; input [3:0]\g_ram_rst_false.ram_memory_reg_5 ; input [28:0]\g_ram_rst_false.ram_memory_reg_6 ; input rec_is_rtr; input rec_ident_type; input rec_frame_type; input rec_brs; input rec_esi; input rec_ivld; input rec_lbpf; input [1:0]\g_ram_rst_false.ram_memory_reg_7 ; input [2:0]\g_ram_rst_false.ram_memory_reg_8 ; input [3:0]\g_ram_rst_false.ram_memory_reg_9 ; input \mr_ctrl_out[mode_erfm] ; input rec_abort_f; input \FSM_onehot_curr_state_reg[0]_2 ; input \cc_stat[err_erp] ; input store_metadata; input rec_is_rtr_i; input rec_valid; input [1:0]data_in_IBUF; input data_overrun_i_reg_2; input data_overrun_i_reg_3; input commit_rx_frame; input rx_data_overrun; input clk_sys_IBUF_BUFG; input \FSM_onehot_curr_state_reg[11]_2 ; input [2:0]\FSM_onehot_curr_state_reg[6]_1 ; wire [0:0]E; wire \FSM_onehot_curr_state[0]_i_1_n_0 ; wire \FSM_onehot_curr_state[0]_i_2_n_0 ; wire \FSM_onehot_curr_state[10]_i_1_n_0 ; wire \FSM_onehot_curr_state[11]_i_10_n_0 ; wire \FSM_onehot_curr_state[11]_i_11_n_0 ; wire \FSM_onehot_curr_state[11]_i_12_n_0 ; wire \FSM_onehot_curr_state[11]_i_13_n_0 ; wire \FSM_onehot_curr_state[11]_i_14_n_0 ; wire \FSM_onehot_curr_state[11]_i_16_n_0 ; wire \FSM_onehot_curr_state[11]_i_2_n_0 ; wire \FSM_onehot_curr_state[11]_i_4_n_0 ; wire \FSM_onehot_curr_state[11]_i_5_n_0 ; wire \FSM_onehot_curr_state[11]_i_7_n_0 ; wire \FSM_onehot_curr_state[11]_i_8_n_0 ; wire \FSM_onehot_curr_state[11]_i_9_n_0 ; wire \FSM_onehot_curr_state[3]_i_1_n_0 ; wire \FSM_onehot_curr_state[4]_i_1_n_0 ; wire \FSM_onehot_curr_state[5]_i_1_n_0 ; wire \FSM_onehot_curr_state[7]_i_1_n_0 ; wire \FSM_onehot_curr_state[8]_i_1_n_0 ; wire \FSM_onehot_curr_state[9]_i_1_n_0 ; wire \FSM_onehot_curr_state_reg[0]_0 ; wire \FSM_onehot_curr_state_reg[0]_1 ; wire \FSM_onehot_curr_state_reg[0]_2 ; wire \FSM_onehot_curr_state_reg[11]_0 ; wire \FSM_onehot_curr_state_reg[11]_1 ; wire \FSM_onehot_curr_state_reg[11]_2 ; wire \FSM_onehot_curr_state_reg[1]_0 ; wire \FSM_onehot_curr_state_reg[1]_1 ; wire [0:0]\FSM_onehot_curr_state_reg[6]_0 ; wire [2:0]\FSM_onehot_curr_state_reg[6]_1 ; wire \FSM_onehot_curr_state_reg[7]_0 ; wire \FSM_onehot_curr_state_reg[8]_0 ; wire \FSM_onehot_curr_state_reg[8]_1 ; wire \FSM_onehot_curr_state_reg_n_0_[10] ; wire \FSM_onehot_curr_state_reg_n_0_[11] ; wire \FSM_onehot_curr_state_reg_n_0_[4] ; wire \FSM_onehot_curr_state_reg_n_0_[9] ; wire [7:0]Q; wire [0:0]WEBWE; wire \cc_stat[err_erp] ; wire clk_sys_IBUF_BUFG; wire commit_intent; wire [0:0]commit_overrun_abort_reg; wire commit_rx_frame; wire [1:0]data_in_IBUF; wire data_overrun_flg_reg; wire data_overrun_i; wire data_overrun_i_i_2_n_0; wire data_overrun_i_reg; wire data_overrun_i_reg_0; wire data_overrun_i_reg_1; wire data_overrun_i_reg_2; wire data_overrun_i_reg_3; wire [3:1]data_selector; wire \g_byte_shift_reg[1].shift_reg_q_reg[1][6] ; wire \g_ram_rst_false.ram_memory_reg ; wire [30:0]\g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire [63:0]\g_ram_rst_false.ram_memory_reg_4 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_5 ; wire [28:0]\g_ram_rst_false.ram_memory_reg_6 ; wire [1:0]\g_ram_rst_false.ram_memory_reg_7 ; wire [2:0]\g_ram_rst_false.ram_memory_reg_8 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_9 ; wire \g_ram_rst_false.ram_memory_reg_i_100_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_101_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_102_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_103_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_104_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_105_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_106_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_107_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_108_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_109_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_111_0 ; wire \g_ram_rst_false.ram_memory_reg_i_114_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_115_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_120_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_122_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_123_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_125_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_127_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_130_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_47_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_51_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_53_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_54_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_56_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_57_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_58_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_59_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_60_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_61_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_62_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_63_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_64_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_65_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_66_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_67_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_68_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_69_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_70_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_71_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_72_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_73_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_74_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_75_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_76_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_77_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_78_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_79_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_80_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_81_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_83_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_84_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_85_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_86_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_87_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_88_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_89_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_90_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_91_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_92_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_93_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_94_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_95_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_96_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_97_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_98_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_99_n_0 ; wire ident_valid_q; wire \mr_ctrl_out[mode_erfm] ; wire \mr_tst_out[tst_control_twrstb] ; wire rec_abort; wire rec_abort_f; wire rec_brs; wire rec_esi; wire rec_frame_type; wire rec_ident_type; wire rec_is_rtr; wire rec_is_rtr_i; wire rec_ivld; wire rec_lbpf; wire rec_valid; wire rx_data_overrun; wire rx_fsm_ce; wire \rx_mem_free_raw_reg[5] ; wire [30:0]rxb_port_a_data_in_i; wire [31:0]store_data_word; wire store_metadata; wire \write_pointer_raw_i_reg[0] ; LUT6 #( .INIT(64'hFFFFFFFFBBBAAAAA)) \FSM_onehot_curr_state[0]_i_1 (.I0(\FSM_onehot_curr_state[0]_i_2_n_0 ), .I1(\mr_ctrl_out[mode_erfm] ), .I2(Q[4]), .I3(Q[1]), .I4(rec_abort_f), .I5(\FSM_onehot_curr_state_reg[0]_2 ), .O(\FSM_onehot_curr_state[0]_i_1_n_0 )); LUT6 #( .INIT(64'h70000000FFFFFFFF)) \FSM_onehot_curr_state[0]_i_2 (.I0(ident_valid_q), .I1(rec_valid), .I2(Q[4]), .I3(Q[0]), .I4(\FSM_onehot_curr_state_reg[0]_1 ), .I5(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .O(\FSM_onehot_curr_state[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair329" *) LUT3 #( .INIT(8'hBA)) \FSM_onehot_curr_state[10]_i_1 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(\FSM_onehot_curr_state_reg[11]_1 ), .I2(\FSM_onehot_curr_state_reg_n_0_[10] ), .O(\FSM_onehot_curr_state[10]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFEEEEFE)) \FSM_onehot_curr_state[11]_i_1 (.I0(\FSM_onehot_curr_state[11]_i_4_n_0 ), .I1(\FSM_onehot_curr_state[11]_i_5_n_0 ), .I2(\FSM_onehot_curr_state_reg[11]_1 ), .I3(\FSM_onehot_curr_state[11]_i_7_n_0 ), .I4(\FSM_onehot_curr_state[11]_i_8_n_0 ), .I5(\FSM_onehot_curr_state[11]_i_9_n_0 ), .O(rx_fsm_ce)); (* SOFT_HLUTNM = "soft_lutpair321" *) LUT2 #( .INIT(4'hE)) \FSM_onehot_curr_state[11]_i_10 (.I0(Q[7]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .O(\FSM_onehot_curr_state[11]_i_10_n_0 )); LUT5 #( .INIT(32'hFFFFFF80)) \FSM_onehot_curr_state[11]_i_11 (.I0(store_metadata), .I1(ident_valid_q), .I2(Q[0]), .I3(\FSM_onehot_curr_state_reg_n_0_[4] ), .I4(Q[2]), .O(\FSM_onehot_curr_state[11]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair323" *) LUT3 #( .INIT(8'h2A)) \FSM_onehot_curr_state[11]_i_12 (.I0(Q[4]), .I1(ident_valid_q), .I2(rec_abort), .O(\FSM_onehot_curr_state[11]_i_12_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \FSM_onehot_curr_state[11]_i_13 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(Q[5]), .I3(Q[4]), .I4(Q[3]), .I5(Q[1]), .O(\FSM_onehot_curr_state[11]_i_13_n_0 )); (* SOFT_HLUTNM = "soft_lutpair323" *) LUT4 #( .INIT(16'h2AAA)) \FSM_onehot_curr_state[11]_i_14 (.I0(Q[0]), .I1(\mr_ctrl_out[mode_erfm] ), .I2(rec_abort), .I3(ident_valid_q), .O(\FSM_onehot_curr_state[11]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair316" *) LUT2 #( .INIT(4'hE)) \FSM_onehot_curr_state[11]_i_15 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(Q[2]), .O(data_selector[1])); LUT6 #( .INIT(64'h3322BFAA3F22BFAA)) \FSM_onehot_curr_state[11]_i_16 (.I0(Q[4]), .I1(ident_valid_q), .I2(store_metadata), .I3(Q[0]), .I4(rec_abort), .I5(\mr_ctrl_out[mode_erfm] ), .O(\FSM_onehot_curr_state[11]_i_16_n_0 )); LUT3 #( .INIT(8'hBA)) \FSM_onehot_curr_state[11]_i_2 (.I0(\FSM_onehot_curr_state_reg_n_0_[10] ), .I1(\FSM_onehot_curr_state_reg[11]_1 ), .I2(\FSM_onehot_curr_state_reg_n_0_[11] ), .O(\FSM_onehot_curr_state[11]_i_2_n_0 )); LUT6 #( .INIT(64'h0051000000040005)) \FSM_onehot_curr_state[11]_i_4 (.I0(\FSM_onehot_curr_state[11]_i_10_n_0 ), .I1(Q[1]), .I2(\FSM_onehot_curr_state_reg[0]_1 ), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(\FSM_onehot_curr_state_reg[8]_1 ), .I5(\FSM_onehot_curr_state_reg_n_0_[11] ), .O(\FSM_onehot_curr_state[11]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFE0000FFFE0001)) \FSM_onehot_curr_state[11]_i_5 (.I0(\FSM_onehot_curr_state[11]_i_11_n_0 ), .I1(\FSM_onehot_curr_state[11]_i_12_n_0 ), .I2(Q[7]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(\FSM_onehot_curr_state[11]_i_13_n_0 ), .I5(\FSM_onehot_curr_state[11]_i_14_n_0 ), .O(\FSM_onehot_curr_state[11]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFEEFEFEFE)) \FSM_onehot_curr_state[11]_i_7 (.I0(data_selector[3]), .I1(data_selector[1]), .I2(Q[1]), .I3(ident_valid_q), .I4(rec_abort), .I5(\FSM_onehot_curr_state_reg_n_0_[4] ), .O(\FSM_onehot_curr_state[11]_i_7_n_0 )); LUT6 #( .INIT(64'h0000000000000001)) \FSM_onehot_curr_state[11]_i_8 (.I0(\FSM_onehot_curr_state_reg_n_0_[10] ), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(Q[3]), .I3(Q[2]), .I4(Q[6]), .I5(Q[4]), .O(\FSM_onehot_curr_state[11]_i_8_n_0 )); LUT6 #( .INIT(64'h0001000100001110)) \FSM_onehot_curr_state[11]_i_9 (.I0(\FSM_onehot_curr_state_reg_n_0_[4] ), .I1(Q[5]), .I2(Q[4]), .I3(Q[6]), .I4(\FSM_onehot_curr_state[11]_i_16_n_0 ), .I5(Q[3]), .O(\FSM_onehot_curr_state[11]_i_9_n_0 )); (* SOFT_HLUTNM = "soft_lutpair328" *) LUT3 #( .INIT(8'hBA)) \FSM_onehot_curr_state[3]_i_1 (.I0(Q[2]), .I1(\FSM_onehot_curr_state_reg[11]_1 ), .I2(Q[3]), .O(\FSM_onehot_curr_state[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair328" *) LUT3 #( .INIT(8'hBA)) \FSM_onehot_curr_state[4]_i_1 (.I0(Q[3]), .I1(\FSM_onehot_curr_state_reg[11]_1 ), .I2(\FSM_onehot_curr_state_reg_n_0_[4] ), .O(\FSM_onehot_curr_state[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair329" *) LUT3 #( .INIT(8'hBA)) \FSM_onehot_curr_state[5]_i_1 (.I0(\FSM_onehot_curr_state_reg_n_0_[4] ), .I1(\FSM_onehot_curr_state_reg[11]_1 ), .I2(Q[4]), .O(\FSM_onehot_curr_state[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair327" *) LUT3 #( .INIT(8'hCE)) \FSM_onehot_curr_state[7]_i_1 (.I0(Q[6]), .I1(Q[5]), .I2(\FSM_onehot_curr_state_reg[11]_1 ), .O(\FSM_onehot_curr_state[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000FFFF8000C000)) \FSM_onehot_curr_state[8]_i_1 (.I0(Q[1]), .I1(ident_valid_q), .I2(rec_abort), .I3(\mr_ctrl_out[mode_erfm] ), .I4(\FSM_onehot_curr_state_reg[8]_1 ), .I5(Q[7]), .O(\FSM_onehot_curr_state[8]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair326" *) LUT3 #( .INIT(8'hBA)) \FSM_onehot_curr_state[9]_i_1 (.I0(Q[7]), .I1(\FSM_onehot_curr_state_reg[11]_1 ), .I2(\FSM_onehot_curr_state_reg_n_0_[9] ), .O(\FSM_onehot_curr_state[9]_i_1_n_0 )); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDPE #( .INIT(1'b1)) \FSM_onehot_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .D(\FSM_onehot_curr_state[0]_i_1_n_0 ), .PRE(\FSM_onehot_curr_state_reg[11]_2 ), .Q(Q[0])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[10]_i_1_n_0 ), .Q(\FSM_onehot_curr_state_reg_n_0_[10] )); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[11]_i_2_n_0 ), .Q(\FSM_onehot_curr_state_reg_n_0_[11] )); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state_reg[6]_1 [0]), .Q(Q[1])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state_reg[6]_1 [1]), .Q(Q[2])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[3]_i_1_n_0 ), .Q(Q[3])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[4]_i_1_n_0 ), .Q(\FSM_onehot_curr_state_reg_n_0_[4] )); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[5]_i_1_n_0 ), .Q(Q[4])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state_reg[6]_1 [2]), .Q(Q[5])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[7]_i_1_n_0 ), .Q(Q[6])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[8]_i_1_n_0 ), .Q(Q[7])); (* FSM_ENCODED_STATES = "s_rxb_skip_ts_low:000000001000,s_rxb_skip_ts_high:000000010000,s_rxb_store_identifier:000000000100,s_rxb_store_err_ts_high:100000000000,s_rxb_store_err_ts_low:010000000000,s_rxb_store_frame_format:000000000010,s_rxb_idle:000000000001,s_rxb_store_err_identifier:001000000000,s_rxb_store_data:000000100000,s_rxb_store_end_ts_high:000010000000,s_rxb_store_err_frame_format:000100000000,s_rxb_store_end_ts_low:000001000000" *) FDCE #( .INIT(1'b0)) \FSM_onehot_curr_state_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(rx_fsm_ce), .CLR(\FSM_onehot_curr_state_reg[11]_2 ), .D(\FSM_onehot_curr_state[9]_i_1_n_0 ), .Q(\FSM_onehot_curr_state_reg_n_0_[9] )); (* SOFT_HLUTNM = "soft_lutpair324" *) LUT4 #( .INIT(16'hFCA8)) commit_overrun_abort_i_1 (.I0(data_overrun_i), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(Q[6]), .I3(\write_pointer_raw_i_reg[0] ), .O(data_overrun_i_reg_0)); (* SOFT_HLUTNM = "soft_lutpair324" *) LUT4 #( .INIT(16'hEE0E)) commit_rx_frame_i_1 (.I0(\FSM_onehot_curr_state_reg_n_0_[11] ), .I1(Q[6]), .I2(data_overrun_i), .I3(commit_rx_frame), .O(\FSM_onehot_curr_state_reg[11]_0 )); LUT5 #( .INIT(32'hDFDFDF00)) data_overrun_flg_i_1 (.I0(data_in_IBUF[1]), .I1(data_overrun_i_reg_2), .I2(data_overrun_i_reg_3), .I3(data_overrun_i_i_2_n_0), .I4(rx_data_overrun), .O(data_overrun_flg_reg)); LUT6 #( .INIT(64'hFF20FFFFFF20FF20)) data_overrun_i_i_1 (.I0(data_in_IBUF[0]), .I1(data_overrun_i_reg_2), .I2(data_overrun_i_reg_3), .I3(data_overrun_i_i_2_n_0), .I4(Q[0]), .I5(data_overrun_i), .O(\FSM_onehot_curr_state_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair325" *) LUT2 #( .INIT(4'h1)) data_overrun_i_i_2 (.I0(\g_ram_rst_false.ram_memory_reg_i_127_n_0 ), .I1(data_overrun_i_reg_1), .O(data_overrun_i_i_2_n_0)); LUT6 #( .INIT(64'h00000DDD0DDD0DDD)) \g_ram_rst_false.ram_memory_reg_i_100 (.I0(\g_ram_rst_false.ram_memory_reg_4 [52]), .I1(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I2(\cc_stat[err_erp] ), .I3(Q[7]), .I4(Q[4]), .I5(store_data_word[20]), .O(\g_ram_rst_false.ram_memory_reg_i_100_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_101 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [20]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [20]), .O(\g_ram_rst_false.ram_memory_reg_i_101_n_0 )); LUT6 #( .INIT(64'h0000077707770777)) \g_ram_rst_false.ram_memory_reg_i_102 (.I0(data_selector[3]), .I1(\g_ram_rst_false.ram_memory_reg_4 [19]), .I2(Q[4]), .I3(store_data_word[19]), .I4(Q[7]), .I5(\g_ram_rst_false.ram_memory_reg_9 [3]), .O(\g_ram_rst_false.ram_memory_reg_i_102_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_103 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(Q[2]), .I2(\g_ram_rst_false.ram_memory_reg_6 [19]), .I3(Q[6]), .I4(\FSM_onehot_curr_state_reg_n_0_[11] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [51]), .O(\g_ram_rst_false.ram_memory_reg_i_103_n_0 )); LUT6 #( .INIT(64'h0000077707770777)) \g_ram_rst_false.ram_memory_reg_i_104 (.I0(data_selector[3]), .I1(\g_ram_rst_false.ram_memory_reg_4 [18]), .I2(Q[7]), .I3(\g_ram_rst_false.ram_memory_reg_9 [2]), .I4(Q[4]), .I5(store_data_word[18]), .O(\g_ram_rst_false.ram_memory_reg_i_104_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_105 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(Q[2]), .I2(\g_ram_rst_false.ram_memory_reg_6 [18]), .I3(Q[6]), .I4(\FSM_onehot_curr_state_reg_n_0_[11] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [50]), .O(\g_ram_rst_false.ram_memory_reg_i_105_n_0 )); LUT6 #( .INIT(64'h00000DDD0DDD0DDD)) \g_ram_rst_false.ram_memory_reg_i_106 (.I0(\g_ram_rst_false.ram_memory_reg_4 [49]), .I1(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I2(Q[7]), .I3(\g_ram_rst_false.ram_memory_reg_9 [1]), .I4(Q[4]), .I5(store_data_word[17]), .O(\g_ram_rst_false.ram_memory_reg_i_106_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_107 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [17]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [17]), .O(\g_ram_rst_false.ram_memory_reg_i_107_n_0 )); LUT6 #( .INIT(64'h0000077707770777)) \g_ram_rst_false.ram_memory_reg_i_108 (.I0(Q[7]), .I1(\g_ram_rst_false.ram_memory_reg_9 [0]), .I2(Q[4]), .I3(store_data_word[16]), .I4(data_selector[3]), .I5(\g_ram_rst_false.ram_memory_reg_4 [16]), .O(\g_ram_rst_false.ram_memory_reg_i_108_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_109 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(Q[2]), .I2(\g_ram_rst_false.ram_memory_reg_6 [16]), .I3(Q[6]), .I4(\FSM_onehot_curr_state_reg_n_0_[11] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [48]), .O(\g_ram_rst_false.ram_memory_reg_i_109_n_0 )); LUT4 #( .INIT(16'hF404)) \g_ram_rst_false.ram_memory_reg_i_11 (.I0(\g_ram_rst_false.ram_memory_reg_i_47_n_0 ), .I1(\FSM_onehot_curr_state_reg[1]_0 ), .I2(\g_ram_rst_false.ram_memory_reg ), .I3(\g_ram_rst_false.ram_memory_reg_0 [14]), .O(rxb_port_a_data_in_i[14])); (* SOFT_HLUTNM = "soft_lutpair325" *) LUT3 #( .INIT(8'h01)) \g_ram_rst_false.ram_memory_reg_i_111 (.I0(data_overrun_i_i_2_n_0), .I1(\g_ram_rst_false.ram_memory_reg_i_127_n_0 ), .I2(data_overrun_i), .O(data_overrun_i_reg)); (* SOFT_HLUTNM = "soft_lutpair322" *) LUT4 #( .INIT(16'hBFFF)) \g_ram_rst_false.ram_memory_reg_i_113 (.I0(Q[7]), .I1(Q[1]), .I2(\g_ram_rst_false.ram_memory_reg_5 [3]), .I3(rec_frame_type), .O(\FSM_onehot_curr_state_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_114 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [15]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [15]), .O(\g_ram_rst_false.ram_memory_reg_i_114_n_0 )); (* SOFT_HLUTNM = "soft_lutpair317" *) LUT5 #( .INIT(32'hFFE0E0E0)) \g_ram_rst_false.ram_memory_reg_i_115 (.I0(Q[6]), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [47]), .I3(store_data_word[15]), .I4(Q[4]), .O(\g_ram_rst_false.ram_memory_reg_i_115_n_0 )); (* SOFT_HLUTNM = "soft_lutpair317" *) LUT2 #( .INIT(4'hE)) \g_ram_rst_false.ram_memory_reg_i_116 (.I0(\FSM_onehot_curr_state_reg_n_0_[11] ), .I1(Q[6]), .O(commit_intent)); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_117 (.I0(Q[6]), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [46]), .I3(Q[5]), .I4(\FSM_onehot_curr_state_reg_n_0_[10] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [14]), .O(\FSM_onehot_curr_state_reg[7]_0 )); (* SOFT_HLUTNM = "soft_lutpair316" *) LUT5 #( .INIT(32'hFFF88888)) \g_ram_rst_false.ram_memory_reg_i_118 (.I0(store_data_word[14]), .I1(Q[4]), .I2(\FSM_onehot_curr_state_reg_n_0_[9] ), .I3(Q[2]), .I4(\g_ram_rst_false.ram_memory_reg_6 [14]), .O(\g_byte_shift_reg[1].shift_reg_q_reg[1][6] )); (* SOFT_HLUTNM = "soft_lutpair322" *) LUT4 #( .INIT(16'hFF5D)) \g_ram_rst_false.ram_memory_reg_i_119 (.I0(Q[1]), .I1(rec_is_rtr_i), .I2(rec_frame_type), .I3(Q[7]), .O(\FSM_onehot_curr_state_reg[1]_1 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_120 (.I0(Q[6]), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [45]), .I3(Q[5]), .I4(\FSM_onehot_curr_state_reg_n_0_[10] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [13]), .O(\g_ram_rst_false.ram_memory_reg_i_120_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_122 (.I0(Q[6]), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [44]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [12]), .O(\g_ram_rst_false.ram_memory_reg_i_122_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_123 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [11]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [11]), .O(\g_ram_rst_false.ram_memory_reg_i_123_n_0 )); (* SOFT_HLUTNM = "soft_lutpair326" *) LUT3 #( .INIT(8'h1F)) \g_ram_rst_false.ram_memory_reg_i_125 (.I0(Q[1]), .I1(Q[7]), .I2(rec_lbpf), .O(\g_ram_rst_false.ram_memory_reg_i_125_n_0 )); LUT5 #( .INIT(32'h00000100)) \g_ram_rst_false.ram_memory_reg_i_127 (.I0(\g_ram_rst_false.ram_memory_reg_i_111_0 ), .I1(\FSM_onehot_curr_state_reg_n_0_[4] ), .I2(Q[3]), .I3(\g_ram_rst_false.ram_memory_reg_i_130_n_0 ), .I4(Q[2]), .O(\g_ram_rst_false.ram_memory_reg_i_127_n_0 )); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_13 (.I0(\g_ram_rst_false.ram_memory_reg_3 ), .I1(\g_ram_rst_false.ram_memory_reg_i_51_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [13]), .O(rxb_port_a_data_in_i[13])); (* SOFT_HLUTNM = "soft_lutpair321" *) LUT4 #( .INIT(16'h0001)) \g_ram_rst_false.ram_memory_reg_i_130 (.I0(\FSM_onehot_curr_state_reg_n_0_[10] ), .I1(Q[7]), .I2(\FSM_onehot_curr_state_reg_n_0_[9] ), .I3(\FSM_onehot_curr_state_reg_n_0_[11] ), .O(\g_ram_rst_false.ram_memory_reg_i_130_n_0 )); LUT6 #( .INIT(64'hFFFFF1000000F100)) \g_ram_rst_false.ram_memory_reg_i_14 (.I0(\g_ram_rst_false.ram_memory_reg_2 ), .I1(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_i_54_n_0 ), .I3(\FSM_onehot_curr_state_reg[1]_0 ), .I4(\g_ram_rst_false.ram_memory_reg ), .I5(\g_ram_rst_false.ram_memory_reg_0 [12]), .O(rxb_port_a_data_in_i[12])); LUT6 #( .INIT(64'hFFFFF1000000F100)) \g_ram_rst_false.ram_memory_reg_i_15 (.I0(\g_ram_rst_false.ram_memory_reg_1 ), .I1(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_i_56_n_0 ), .I3(\FSM_onehot_curr_state_reg[1]_0 ), .I4(\g_ram_rst_false.ram_memory_reg ), .I5(\g_ram_rst_false.ram_memory_reg_0 [11]), .O(rxb_port_a_data_in_i[11])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_16 (.I0(\g_ram_rst_false.ram_memory_reg_i_57_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_58_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [10]), .O(rxb_port_a_data_in_i[10])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_17 (.I0(\g_ram_rst_false.ram_memory_reg_i_59_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_60_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [9]), .O(rxb_port_a_data_in_i[9])); LUT5 #( .INIT(32'hAAAAF300)) \g_ram_rst_false.ram_memory_reg_i_18 (.I0(\g_ram_rst_false.ram_memory_reg_0 [8]), .I1(\g_ram_rst_false.ram_memory_reg_i_61_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_i_62_n_0 ), .I3(\FSM_onehot_curr_state_reg[1]_0 ), .I4(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[8])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_19 (.I0(\g_ram_rst_false.ram_memory_reg_i_63_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_64_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [7]), .O(rxb_port_a_data_in_i[7])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_20 (.I0(\g_ram_rst_false.ram_memory_reg_i_65_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_66_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [6]), .O(rxb_port_a_data_in_i[6])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_21 (.I0(\g_ram_rst_false.ram_memory_reg_i_67_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_68_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [5]), .O(rxb_port_a_data_in_i[5])); LUT5 #( .INIT(32'hAAAAF300)) \g_ram_rst_false.ram_memory_reg_i_22 (.I0(\g_ram_rst_false.ram_memory_reg_0 [4]), .I1(\g_ram_rst_false.ram_memory_reg_i_69_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_i_70_n_0 ), .I3(\FSM_onehot_curr_state_reg[1]_0 ), .I4(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[4])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_23 (.I0(\g_ram_rst_false.ram_memory_reg_i_71_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_72_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [3]), .O(rxb_port_a_data_in_i[3])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_24 (.I0(\g_ram_rst_false.ram_memory_reg_i_73_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_74_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [2]), .O(rxb_port_a_data_in_i[2])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_25 (.I0(\g_ram_rst_false.ram_memory_reg_i_75_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_76_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [1]), .O(rxb_port_a_data_in_i[1])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_26 (.I0(\g_ram_rst_false.ram_memory_reg_i_77_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_78_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [0]), .O(rxb_port_a_data_in_i[0])); LUT6 #( .INIT(64'hAAAAAAAAFF300000)) \g_ram_rst_false.ram_memory_reg_i_27 (.I0(\g_ram_rst_false.ram_memory_reg_0 [30]), .I1(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_4 [63]), .I3(\g_ram_rst_false.ram_memory_reg_i_80_n_0 ), .I4(\FSM_onehot_curr_state_reg[1]_0 ), .I5(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[30])); LUT6 #( .INIT(64'hAAAAAAAAFF0C0000)) \g_ram_rst_false.ram_memory_reg_i_28 (.I0(\g_ram_rst_false.ram_memory_reg_0 [29]), .I1(\g_ram_rst_false.ram_memory_reg_4 [62]), .I2(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I3(\g_ram_rst_false.ram_memory_reg_i_81_n_0 ), .I4(\FSM_onehot_curr_state_reg[1]_0 ), .I5(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[29])); LUT6 #( .INIT(64'hAAAAAAAAFFC00000)) \g_ram_rst_false.ram_memory_reg_i_29 (.I0(\g_ram_rst_false.ram_memory_reg_0 [28]), .I1(data_selector[3]), .I2(\g_ram_rst_false.ram_memory_reg_4 [29]), .I3(\g_ram_rst_false.ram_memory_reg_i_83_n_0 ), .I4(\FSM_onehot_curr_state_reg[1]_0 ), .I5(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[28])); LUT5 #( .INIT(32'hAAAAF300)) \g_ram_rst_false.ram_memory_reg_i_30 (.I0(\g_ram_rst_false.ram_memory_reg_0 [27]), .I1(\g_ram_rst_false.ram_memory_reg_i_84_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_i_85_n_0 ), .I3(\FSM_onehot_curr_state_reg[1]_0 ), .I4(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[27])); LUT5 #( .INIT(32'hAAAAF300)) \g_ram_rst_false.ram_memory_reg_i_31 (.I0(\g_ram_rst_false.ram_memory_reg_0 [26]), .I1(\g_ram_rst_false.ram_memory_reg_i_86_n_0 ), .I2(\g_ram_rst_false.ram_memory_reg_i_87_n_0 ), .I3(\FSM_onehot_curr_state_reg[1]_0 ), .I4(\g_ram_rst_false.ram_memory_reg ), .O(rxb_port_a_data_in_i[26])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_32 (.I0(\g_ram_rst_false.ram_memory_reg_i_88_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_89_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [25]), .O(rxb_port_a_data_in_i[25])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_33 (.I0(\g_ram_rst_false.ram_memory_reg_i_90_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_91_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [24]), .O(rxb_port_a_data_in_i[24])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_34 (.I0(\g_ram_rst_false.ram_memory_reg_i_92_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_93_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [23]), .O(rxb_port_a_data_in_i[23])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_35 (.I0(\g_ram_rst_false.ram_memory_reg_i_94_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_95_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [22]), .O(rxb_port_a_data_in_i[22])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_36 (.I0(\g_ram_rst_false.ram_memory_reg_i_96_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_97_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [21]), .O(rxb_port_a_data_in_i[21])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_37 (.I0(\g_ram_rst_false.ram_memory_reg_i_98_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_99_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [20]), .O(rxb_port_a_data_in_i[20])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_38 (.I0(\g_ram_rst_false.ram_memory_reg_i_100_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_101_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [19]), .O(rxb_port_a_data_in_i[19])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_39 (.I0(\g_ram_rst_false.ram_memory_reg_i_102_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_103_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [18]), .O(rxb_port_a_data_in_i[18])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_40 (.I0(\g_ram_rst_false.ram_memory_reg_i_104_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_105_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [17]), .O(rxb_port_a_data_in_i[17])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_41 (.I0(\g_ram_rst_false.ram_memory_reg_i_106_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_107_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [16]), .O(rxb_port_a_data_in_i[16])); LUT5 #( .INIT(32'hFFD000D0)) \g_ram_rst_false.ram_memory_reg_i_42 (.I0(\g_ram_rst_false.ram_memory_reg_i_108_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_i_109_n_0 ), .I2(\FSM_onehot_curr_state_reg[1]_0 ), .I3(\g_ram_rst_false.ram_memory_reg ), .I4(\g_ram_rst_false.ram_memory_reg_0 [15]), .O(rxb_port_a_data_in_i[15])); LUT6 #( .INIT(64'hB8B8B8B8BBBBBBB8)) \g_ram_rst_false.ram_memory_reg_i_43 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(\g_ram_rst_false.ram_memory_reg ), .I2(data_overrun_i_reg), .I3(Q[6]), .I4(Q[5]), .I5(data_overrun_i), .O(WEBWE)); LUT6 #( .INIT(64'h000000000000BFFF)) \g_ram_rst_false.ram_memory_reg_i_47 (.I0(\FSM_onehot_curr_state_reg[8]_0 ), .I1(\g_ram_rst_false.ram_memory_reg_5 [1]), .I2(\g_ram_rst_false.ram_memory_reg_5 [0]), .I3(\g_ram_rst_false.ram_memory_reg_5 [2]), .I4(\g_ram_rst_false.ram_memory_reg_i_114_n_0 ), .I5(\g_ram_rst_false.ram_memory_reg_i_115_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_47_n_0 )); LUT6 #( .INIT(64'h000000010001011E)) \g_ram_rst_false.ram_memory_reg_i_48__3 (.I0(Q[1]), .I1(Q[7]), .I2(data_selector[1]), .I3(Q[4]), .I4(data_selector[3]), .I5(commit_intent), .O(\FSM_onehot_curr_state_reg[1]_0 )); LUT6 #( .INIT(64'hFFFFEEEAEEEAEEEA)) \g_ram_rst_false.ram_memory_reg_i_51 (.I0(\g_ram_rst_false.ram_memory_reg_i_120_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_6 [13]), .I2(Q[2]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[4]), .I5(store_data_word[13]), .O(\g_ram_rst_false.ram_memory_reg_i_51_n_0 )); (* SOFT_HLUTNM = "soft_lutpair318" *) LUT2 #( .INIT(4'h1)) \g_ram_rst_false.ram_memory_reg_i_53 (.I0(Q[7]), .I1(Q[1]), .O(\g_ram_rst_false.ram_memory_reg_i_53_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF8F8F888)) \g_ram_rst_false.ram_memory_reg_i_54 (.I0(Q[4]), .I1(store_data_word[12]), .I2(\g_ram_rst_false.ram_memory_reg_4 [12]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(Q[5]), .I5(\g_ram_rst_false.ram_memory_reg_i_122_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_54_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFF8F8F888)) \g_ram_rst_false.ram_memory_reg_i_56 (.I0(Q[4]), .I1(store_data_word[11]), .I2(\g_ram_rst_false.ram_memory_reg_4 [43]), .I3(\FSM_onehot_curr_state_reg_n_0_[11] ), .I4(Q[6]), .I5(\g_ram_rst_false.ram_memory_reg_i_123_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_56_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_57 (.I0(store_data_word[10]), .I1(Q[4]), .I2(Q[7]), .I3(Q[1]), .I4(rec_esi), .O(\g_ram_rst_false.ram_memory_reg_i_57_n_0 )); LUT6 #( .INIT(64'hFFFF88F888F888F8)) \g_ram_rst_false.ram_memory_reg_i_58 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [10]), .I2(\g_ram_rst_false.ram_memory_reg_4 [42]), .I3(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I4(\g_ram_rst_false.ram_memory_reg_4 [10]), .I5(data_selector[3]), .O(\g_ram_rst_false.ram_memory_reg_i_58_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_59 (.I0(store_data_word[9]), .I1(Q[4]), .I2(\FSM_onehot_curr_state_reg_n_0_[9] ), .I3(Q[2]), .I4(\g_ram_rst_false.ram_memory_reg_6 [9]), .O(\g_ram_rst_false.ram_memory_reg_i_59_n_0 )); LUT6 #( .INIT(64'h88F888F8FFFF88F8)) \g_ram_rst_false.ram_memory_reg_i_60 (.I0(data_selector[3]), .I1(\g_ram_rst_false.ram_memory_reg_4 [9]), .I2(\g_ram_rst_false.ram_memory_reg_4 [41]), .I3(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I4(rec_brs), .I5(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_60_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_61 (.I0(store_data_word[8]), .I1(Q[4]), .I2(\FSM_onehot_curr_state_reg_n_0_[9] ), .I3(Q[2]), .I4(\g_ram_rst_false.ram_memory_reg_6 [8]), .O(\g_ram_rst_false.ram_memory_reg_i_61_n_0 )); LUT6 #( .INIT(64'hF444FFFFF444F444)) \g_ram_rst_false.ram_memory_reg_i_62 (.I0(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_4 [40]), .I2(\g_ram_rst_false.ram_memory_reg_4 [8]), .I3(data_selector[3]), .I4(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .I5(rec_lbpf), .O(\g_ram_rst_false.ram_memory_reg_i_62_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_63 (.I0(store_data_word[7]), .I1(Q[4]), .I2(Q[5]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [7]), .O(\g_ram_rst_false.ram_memory_reg_i_63_n_0 )); LUT6 #( .INIT(64'hF444F444FFFFF444)) \g_ram_rst_false.ram_memory_reg_i_64 (.I0(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_4 [39]), .I2(\g_ram_rst_false.ram_memory_reg_6 [7]), .I3(data_selector[1]), .I4(rec_frame_type), .I5(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_64_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_65 (.I0(store_data_word[6]), .I1(Q[4]), .I2(Q[5]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [6]), .O(\g_ram_rst_false.ram_memory_reg_i_65_n_0 )); LUT6 #( .INIT(64'h88F888F8FFFF88F8)) \g_ram_rst_false.ram_memory_reg_i_66 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [6]), .I2(\g_ram_rst_false.ram_memory_reg_4 [38]), .I3(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I4(rec_ident_type), .I5(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_66_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_67 (.I0(store_data_word[5]), .I1(Q[4]), .I2(Q[5]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [5]), .O(\g_ram_rst_false.ram_memory_reg_i_67_n_0 )); LUT6 #( .INIT(64'h88F888F8FFFF88F8)) \g_ram_rst_false.ram_memory_reg_i_68 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [5]), .I2(\g_ram_rst_false.ram_memory_reg_4 [37]), .I3(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I4(rec_is_rtr), .I5(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .O(\g_ram_rst_false.ram_memory_reg_i_68_n_0 )); LUT6 #( .INIT(64'h0000000000575757)) \g_ram_rst_false.ram_memory_reg_i_69 (.I0(\g_ram_rst_false.ram_memory_reg_4 [36]), .I1(Q[6]), .I2(\FSM_onehot_curr_state_reg_n_0_[11] ), .I3(Q[4]), .I4(store_data_word[4]), .I5(Q[7]), .O(\g_ram_rst_false.ram_memory_reg_i_69_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_70 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [4]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [4]), .O(\g_ram_rst_false.ram_memory_reg_i_70_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_71 (.I0(store_data_word[3]), .I1(Q[4]), .I2(Q[7]), .I3(Q[1]), .I4(\g_ram_rst_false.ram_memory_reg_5 [3]), .O(\g_ram_rst_false.ram_memory_reg_i_71_n_0 )); LUT6 #( .INIT(64'hFFFFF444F444F444)) \g_ram_rst_false.ram_memory_reg_i_72 (.I0(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_4 [35]), .I2(\g_ram_rst_false.ram_memory_reg_6 [3]), .I3(data_selector[1]), .I4(\g_ram_rst_false.ram_memory_reg_4 [3]), .I5(data_selector[3]), .O(\g_ram_rst_false.ram_memory_reg_i_72_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_73 (.I0(store_data_word[2]), .I1(Q[4]), .I2(Q[7]), .I3(Q[1]), .I4(\g_ram_rst_false.ram_memory_reg_5 [2]), .O(\g_ram_rst_false.ram_memory_reg_i_73_n_0 )); LUT6 #( .INIT(64'hFFFF88F888F888F8)) \g_ram_rst_false.ram_memory_reg_i_74 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [2]), .I2(\g_ram_rst_false.ram_memory_reg_4 [34]), .I3(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I4(\g_ram_rst_false.ram_memory_reg_4 [2]), .I5(data_selector[3]), .O(\g_ram_rst_false.ram_memory_reg_i_74_n_0 )); (* SOFT_HLUTNM = "soft_lutpair320" *) LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_75 (.I0(store_data_word[1]), .I1(Q[4]), .I2(Q[6]), .I3(\FSM_onehot_curr_state_reg_n_0_[11] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [33]), .O(\g_ram_rst_false.ram_memory_reg_i_75_n_0 )); LUT6 #( .INIT(64'hFFFFF444F444F444)) \g_ram_rst_false.ram_memory_reg_i_76 (.I0(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_5 [1]), .I2(\g_ram_rst_false.ram_memory_reg_6 [1]), .I3(data_selector[1]), .I4(\g_ram_rst_false.ram_memory_reg_4 [1]), .I5(data_selector[3]), .O(\g_ram_rst_false.ram_memory_reg_i_76_n_0 )); (* SOFT_HLUTNM = "soft_lutpair318" *) LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_77 (.I0(Q[4]), .I1(store_data_word[0]), .I2(Q[7]), .I3(Q[1]), .I4(\g_ram_rst_false.ram_memory_reg_5 [0]), .O(\g_ram_rst_false.ram_memory_reg_i_77_n_0 )); LUT6 #( .INIT(64'hFFFF88F888F888F8)) \g_ram_rst_false.ram_memory_reg_i_78 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [0]), .I2(\g_ram_rst_false.ram_memory_reg_4 [32]), .I3(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I4(\g_ram_rst_false.ram_memory_reg_4 [0]), .I5(data_selector[3]), .O(\g_ram_rst_false.ram_memory_reg_i_78_n_0 )); (* SOFT_HLUTNM = "soft_lutpair320" *) LUT2 #( .INIT(4'h1)) \g_ram_rst_false.ram_memory_reg_i_79 (.I0(Q[6]), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .O(\g_ram_rst_false.ram_memory_reg_i_79_n_0 )); (* SOFT_HLUTNM = "soft_lutpair319" *) LUT5 #( .INIT(32'hFFF88888)) \g_ram_rst_false.ram_memory_reg_i_80 (.I0(store_data_word[31]), .I1(Q[4]), .I2(Q[5]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [31]), .O(\g_ram_rst_false.ram_memory_reg_i_80_n_0 )); LUT5 #( .INIT(32'hFFF88888)) \g_ram_rst_false.ram_memory_reg_i_81 (.I0(store_data_word[30]), .I1(Q[4]), .I2(Q[5]), .I3(\FSM_onehot_curr_state_reg_n_0_[10] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [30]), .O(\g_ram_rst_false.ram_memory_reg_i_81_n_0 )); (* SOFT_HLUTNM = "soft_lutpair319" *) LUT2 #( .INIT(4'hE)) \g_ram_rst_false.ram_memory_reg_i_82 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .O(data_selector[3])); LUT5 #( .INIT(32'hFFF88888)) \g_ram_rst_false.ram_memory_reg_i_83 (.I0(store_data_word[29]), .I1(Q[4]), .I2(Q[6]), .I3(\FSM_onehot_curr_state_reg_n_0_[11] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [61]), .O(\g_ram_rst_false.ram_memory_reg_i_83_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_84 (.I0(store_data_word[28]), .I1(Q[4]), .I2(Q[6]), .I3(\FSM_onehot_curr_state_reg_n_0_[11] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [60]), .O(\g_ram_rst_false.ram_memory_reg_i_84_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_85 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(Q[2]), .I2(\g_ram_rst_false.ram_memory_reg_6 [28]), .I3(Q[5]), .I4(\FSM_onehot_curr_state_reg_n_0_[10] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [28]), .O(\g_ram_rst_false.ram_memory_reg_i_85_n_0 )); LUT5 #( .INIT(32'h001F1F1F)) \g_ram_rst_false.ram_memory_reg_i_86 (.I0(\FSM_onehot_curr_state_reg_n_0_[9] ), .I1(Q[2]), .I2(\g_ram_rst_false.ram_memory_reg_6 [27]), .I3(store_data_word[27]), .I4(Q[4]), .O(\g_ram_rst_false.ram_memory_reg_i_86_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_87 (.I0(Q[6]), .I1(\FSM_onehot_curr_state_reg_n_0_[11] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [59]), .I3(Q[5]), .I4(\FSM_onehot_curr_state_reg_n_0_[10] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [27]), .O(\g_ram_rst_false.ram_memory_reg_i_87_n_0 )); LUT6 #( .INIT(64'h0000005757575757)) \g_ram_rst_false.ram_memory_reg_i_88 (.I0(\g_ram_rst_false.ram_memory_reg_4 [58]), .I1(Q[6]), .I2(\FSM_onehot_curr_state_reg_n_0_[11] ), .I3(Q[5]), .I4(\FSM_onehot_curr_state_reg_n_0_[10] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [26]), .O(\g_ram_rst_false.ram_memory_reg_i_88_n_0 )); LUT6 #( .INIT(64'hFFFFF444F444F444)) \g_ram_rst_false.ram_memory_reg_i_89 (.I0(\g_ram_rst_false.ram_memory_reg_i_125_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 [1]), .I2(\g_ram_rst_false.ram_memory_reg_6 [26]), .I3(data_selector[1]), .I4(Q[4]), .I5(store_data_word[26]), .O(\g_ram_rst_false.ram_memory_reg_i_89_n_0 )); LUT6 #( .INIT(64'h0000001F1F1F1F1F)) \g_ram_rst_false.ram_memory_reg_i_90 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [25]), .I3(Q[6]), .I4(\FSM_onehot_curr_state_reg_n_0_[11] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [57]), .O(\g_ram_rst_false.ram_memory_reg_i_90_n_0 )); LUT6 #( .INIT(64'hFFFFF444F444F444)) \g_ram_rst_false.ram_memory_reg_i_91 (.I0(\g_ram_rst_false.ram_memory_reg_i_125_n_0 ), .I1(\g_ram_rst_false.ram_memory_reg_7 [0]), .I2(\g_ram_rst_false.ram_memory_reg_6 [25]), .I3(data_selector[1]), .I4(Q[4]), .I5(store_data_word[25]), .O(\g_ram_rst_false.ram_memory_reg_i_91_n_0 )); LUT5 #( .INIT(32'h00077777)) \g_ram_rst_false.ram_memory_reg_i_92 (.I0(store_data_word[24]), .I1(Q[4]), .I2(Q[6]), .I3(\FSM_onehot_curr_state_reg_n_0_[11] ), .I4(\g_ram_rst_false.ram_memory_reg_4 [56]), .O(\g_ram_rst_false.ram_memory_reg_i_92_n_0 )); LUT6 #( .INIT(64'hFFFFF444F444F444)) \g_ram_rst_false.ram_memory_reg_i_93 (.I0(\g_ram_rst_false.ram_memory_reg_i_53_n_0 ), .I1(rec_ivld), .I2(\g_ram_rst_false.ram_memory_reg_6 [24]), .I3(data_selector[1]), .I4(\g_ram_rst_false.ram_memory_reg_4 [24]), .I5(data_selector[3]), .O(\g_ram_rst_false.ram_memory_reg_i_93_n_0 )); LUT6 #( .INIT(64'h0000001F1F1F1F1F)) \g_ram_rst_false.ram_memory_reg_i_94 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [23]), .I3(Q[6]), .I4(\FSM_onehot_curr_state_reg_n_0_[11] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [55]), .O(\g_ram_rst_false.ram_memory_reg_i_94_n_0 )); LUT6 #( .INIT(64'hFFFFF888F888F888)) \g_ram_rst_false.ram_memory_reg_i_95 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [23]), .I2(Q[4]), .I3(store_data_word[23]), .I4(Q[7]), .I5(\g_ram_rst_false.ram_memory_reg_8 [2]), .O(\g_ram_rst_false.ram_memory_reg_i_95_n_0 )); LUT6 #( .INIT(64'h0000001F1F1F1F1F)) \g_ram_rst_false.ram_memory_reg_i_96 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [22]), .I3(Q[6]), .I4(\FSM_onehot_curr_state_reg_n_0_[11] ), .I5(\g_ram_rst_false.ram_memory_reg_4 [54]), .O(\g_ram_rst_false.ram_memory_reg_i_96_n_0 )); LUT6 #( .INIT(64'hFFFFF888F888F888)) \g_ram_rst_false.ram_memory_reg_i_97 (.I0(data_selector[1]), .I1(\g_ram_rst_false.ram_memory_reg_6 [22]), .I2(Q[4]), .I3(store_data_word[22]), .I4(Q[7]), .I5(\g_ram_rst_false.ram_memory_reg_8 [1]), .O(\g_ram_rst_false.ram_memory_reg_i_97_n_0 )); LUT6 #( .INIT(64'h00000DDD0DDD0DDD)) \g_ram_rst_false.ram_memory_reg_i_98 (.I0(\g_ram_rst_false.ram_memory_reg_4 [53]), .I1(\g_ram_rst_false.ram_memory_reg_i_79_n_0 ), .I2(Q[7]), .I3(\g_ram_rst_false.ram_memory_reg_8 [0]), .I4(Q[4]), .I5(store_data_word[21]), .O(\g_ram_rst_false.ram_memory_reg_i_98_n_0 )); LUT6 #( .INIT(64'hFFFFFFE0E0E0E0E0)) \g_ram_rst_false.ram_memory_reg_i_99 (.I0(Q[5]), .I1(\FSM_onehot_curr_state_reg_n_0_[10] ), .I2(\g_ram_rst_false.ram_memory_reg_4 [21]), .I3(\FSM_onehot_curr_state_reg_n_0_[9] ), .I4(Q[2]), .I5(\g_ram_rst_false.ram_memory_reg_6 [21]), .O(\g_ram_rst_false.ram_memory_reg_i_99_n_0 )); (* SOFT_HLUTNM = "soft_lutpair315" *) LUT5 #( .INIT(32'hFFF9F9F9)) \rx_mem_free_raw[5]_i_1 (.I0(\rx_mem_free_raw_reg[5] ), .I1(data_overrun_i_reg), .I2(\write_pointer_raw_i_reg[0] ), .I3(rec_abort), .I4(ident_valid_q), .O(E)); (* SOFT_HLUTNM = "soft_lutpair315" *) LUT4 #( .INIT(16'hFEEE)) \write_pointer_raw_i[4]_i_1 (.I0(data_overrun_i_reg), .I1(\write_pointer_raw_i_reg[0] ), .I2(rec_abort), .I3(ident_valid_q), .O(commit_overrun_abort_reg)); (* SOFT_HLUTNM = "soft_lutpair327" *) LUT2 #( .INIT(4'hE)) \write_pointer_ts_i[4]_i_1 (.I0(Q[5]), .I1(Q[3]), .O(\FSM_onehot_curr_state_reg[6]_0 )); endmodule module rxb_pointers (D, \adress[7] , Q, rx_full, \adress[4] , \alc_alc_bit_reg[0] , \rx_mem_free_i_i_reg[5]_0 , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \read_pointer_i_reg[0]_0 , \g_bit[0].reg_value_r_reg[0] , ADDRARDADDR, \g_bit[0].reg_value_r_reg[0]_0 , ADDRBWRADDR, \write_pointer_raw_i_reg[4]_0 , sbe_IBUF, adress_IBUF, \r_data_reg[1] , \r_data_reg[20] , \r_data_reg[20]_0 , \r_data_reg[20]_1 , data_overrun_i_reg, \r_data_reg[16] , E, \r_data_reg[1]_0 , \r_data_reg[1]_1 , \r_data_reg[1]_2 , \r_data[1]_i_2__0_0 , rxb_port_b_data_out_i, \r_data_reg[18] , \r_data[3]_i_2 , \r_data_reg[20]_2 , \r_data_reg[20]_3 , \r_data_reg[20]_4 , \r_data_reg[20]_5 , \r_data_reg[20]_6 , \r_data_reg[16]_0 , \r_data_reg[16]_1 , rxb_port_b_data_out, \mr_ctrl_out[rx_settings_rtsop] , ident_valid_q, rec_abort, commit_overrun_abort, \rx_mem_free_raw_reg[1]_0 , commit_rx_frame, \mr_tst_out[tst_dest_tst_addr] , \g_ram_rst_false.ram_memory_reg_2 , data_in_IBUF, \rx_mem_free_i_i_reg[0]_0 , \mr_ctrl_out[mode_rxbam] , \g_ram_rst_false.ram_memory_reg_3 , \write_pointer_raw_i_reg[4]_1 , \write_pointer_raw_i_reg[0]_0 , clk_sys_IBUF_BUFG, \rx_mem_free_i_i_reg[5]_1 , \rx_mem_free_raw_reg[5]_0 , \write_pointer_ts_i_reg[4]_0 ); output [1:0]D; output \adress[7] ; output [2:0]Q; output rx_full; output \adress[4] ; output \alc_alc_bit_reg[0] ; output [0:0]\rx_mem_free_i_i_reg[5]_0 ; output \g_ram_rst_false.ram_memory_reg ; output \g_ram_rst_false.ram_memory_reg_0 ; output \g_ram_rst_false.ram_memory_reg_1 ; output [0:0]\read_pointer_i_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0] ; output [3:0]ADDRARDADDR; output [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; output [4:0]ADDRBWRADDR; output \write_pointer_raw_i_reg[4]_0 ; input [3:0]sbe_IBUF; input [5:0]adress_IBUF; input \r_data_reg[1] ; input \r_data_reg[20] ; input \r_data_reg[20]_0 ; input \r_data_reg[20]_1 ; input data_overrun_i_reg; input \r_data_reg[16] ; input [0:0]E; input \r_data_reg[1]_0 ; input \r_data_reg[1]_1 ; input \r_data_reg[1]_2 ; input \r_data[1]_i_2__0_0 ; input [5:0]rxb_port_b_data_out_i; input \r_data_reg[18] ; input \r_data[3]_i_2 ; input \r_data_reg[20]_2 ; input [1:0]\r_data_reg[20]_3 ; input \r_data_reg[20]_4 ; input [0:0]\r_data_reg[20]_5 ; input \r_data_reg[20]_6 ; input \r_data_reg[16]_0 ; input \r_data_reg[16]_1 ; input [0:0]rxb_port_b_data_out; input \mr_ctrl_out[rx_settings_rtsop] ; input ident_valid_q; input rec_abort; input commit_overrun_abort; input \rx_mem_free_raw_reg[1]_0 ; input commit_rx_frame; input [4:0]\mr_tst_out[tst_dest_tst_addr] ; input \g_ram_rst_false.ram_memory_reg_2 ; input [0:0]data_in_IBUF; input \rx_mem_free_i_i_reg[0]_0 ; input \mr_ctrl_out[mode_rxbam] ; input [2:0]\g_ram_rst_false.ram_memory_reg_3 ; input \write_pointer_raw_i_reg[4]_1 ; input [0:0]\write_pointer_raw_i_reg[0]_0 ; input clk_sys_IBUF_BUFG; input \rx_mem_free_i_i_reg[5]_1 ; input [0:0]\rx_mem_free_raw_reg[5]_0 ; input [0:0]\write_pointer_ts_i_reg[4]_0 ; wire [3:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [1:0]D; wire [0:0]E; wire [2:0]Q; wire \adress[4] ; wire \adress[7] ; wire [5:0]adress_IBUF; wire \alc_alc_bit_reg[0] ; wire clk_sys_IBUF_BUFG; wire commit_overrun_abort; wire commit_rx_frame; wire [0:0]data_in_IBUF; wire data_overrun_i_i_4_n_0; wire data_overrun_i_reg; wire \g_bit[0].reg_value_r_reg[0] ; wire [0:0]\g_bit[0].reg_value_r_reg[0]_0 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire [2:0]\g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_i_128_n_0 ; wire \g_ram_rst_false.ram_memory_reg_i_46_n_0 ; wire ident_valid_q; wire \mr_ctrl_out[mode_rxbam] ; wire \mr_ctrl_out[rx_data_read] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire [4:0]\mr_tst_out[tst_dest_tst_addr] ; wire [5:0]p_1_in; wire [4:0]plusOp; wire \r_data[16]_i_6_n_0 ; wire \r_data[1]_i_2__0_0 ; wire \r_data[1]_i_2__0_n_0 ; wire \r_data[1]_i_9_n_0 ; wire \r_data[20]_i_2_n_0 ; wire \r_data[20]_i_5_n_0 ; wire \r_data[3]_i_2 ; wire \r_data[3]_i_7_n_0 ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[16]_1 ; wire \r_data_reg[18] ; wire \r_data_reg[1] ; wire \r_data_reg[1]_0 ; wire \r_data_reg[1]_1 ; wire \r_data_reg[1]_2 ; wire \r_data_reg[1]_i_4_n_0 ; wire \r_data_reg[20] ; wire \r_data_reg[20]_0 ; wire \r_data_reg[20]_1 ; wire \r_data_reg[20]_2 ; wire [1:0]\r_data_reg[20]_3 ; wire \r_data_reg[20]_4 ; wire [0:0]\r_data_reg[20]_5 ; wire \r_data_reg[20]_6 ; wire \read_pointer_i[3]_i_1_n_0 ; wire [0:0]\read_pointer_i_reg[0]_0 ; wire rec_abort; wire rx_full; wire [4:0]rx_mem_free; wire \rx_mem_free_i_i[2]_i_2_n_0 ; wire \rx_mem_free_i_i[3]_i_2_n_0 ; wire \rx_mem_free_i_i[3]_i_3_n_0 ; wire \rx_mem_free_i_i[5]_i_1_n_0 ; wire \rx_mem_free_i_i_reg[0]_0 ; wire [0:0]\rx_mem_free_i_i_reg[5]_0 ; wire \rx_mem_free_i_i_reg[5]_1 ; wire \rx_mem_free_raw[0]_i_1_n_0 ; wire \rx_mem_free_raw[1]_i_1_n_0 ; wire \rx_mem_free_raw[2]_i_2_n_0 ; wire \rx_mem_free_raw[2]_i_3_n_0 ; wire \rx_mem_free_raw[3]_i_2_n_0 ; wire \rx_mem_free_raw[3]_i_3_n_0 ; wire \rx_mem_free_raw[3]_i_4_n_0 ; wire \rx_mem_free_raw[4]_i_1_n_0 ; wire \rx_mem_free_raw[4]_i_2_n_0 ; wire \rx_mem_free_raw[4]_i_3_n_0 ; wire \rx_mem_free_raw[4]_i_4_n_0 ; wire \rx_mem_free_raw[5]_i_2_n_0 ; wire \rx_mem_free_raw[5]_i_3_n_0 ; wire \rx_mem_free_raw[5]_i_4_n_0 ; wire \rx_mem_free_raw[5]_i_6_n_0 ; wire \rx_mem_free_raw_reg[1]_0 ; wire \rx_mem_free_raw_reg[2]_i_1_n_0 ; wire \rx_mem_free_raw_reg[3]_i_1_n_0 ; wire [0:0]\rx_mem_free_raw_reg[5]_0 ; wire \rx_mem_free_raw_reg_n_0_[0] ; wire \rx_mem_free_raw_reg_n_0_[1] ; wire \rx_mem_free_raw_reg_n_0_[2] ; wire \rx_mem_free_raw_reg_n_0_[3] ; wire \rx_mem_free_raw_reg_n_0_[4] ; wire \rx_mem_free_raw_reg_n_0_[5] ; wire [4:1]rx_read_pointer; wire [3:1]rx_write_pointer; wire [0:0]rxb_port_b_data_out; wire [5:0]rxb_port_b_data_out_i; wire [3:0]sbe_IBUF; wire [4:0]write_pointer_raw; wire [4:0]write_pointer_raw_d; wire \write_pointer_raw_i[4]_i_4_n_0 ; wire [0:0]\write_pointer_raw_i_reg[0]_0 ; wire \write_pointer_raw_i_reg[4]_0 ; wire \write_pointer_raw_i_reg[4]_1 ; wire [4:0]write_pointer_ts_d; wire \write_pointer_ts_i[4]_i_3_n_0 ; wire [4:0]write_pointer_ts_i_reg; wire [0:0]\write_pointer_ts_i_reg[4]_0 ; LUT6 #( .INIT(64'hFFFFFFFFBEFFFFBE)) data_overrun_i_i_3 (.I0(data_overrun_i_i_4_n_0), .I1(write_pointer_raw[4]), .I2(rx_read_pointer[4]), .I3(write_pointer_raw[0]), .I4(\read_pointer_i_reg[0]_0 ), .I5(\r_data_reg[18] ), .O(\write_pointer_raw_i_reg[4]_0 )); LUT6 #( .INIT(64'h6FF6FFFFFFFF6FF6)) data_overrun_i_i_4 (.I0(write_pointer_raw[1]), .I1(rx_read_pointer[1]), .I2(rx_read_pointer[3]), .I3(write_pointer_raw[3]), .I4(rx_read_pointer[2]), .I5(write_pointer_raw[2]), .O(data_overrun_i_i_4_n_0)); LUT6 #( .INIT(64'hB8B8B8B8B88BB8B8)) \g_ram_rst_false.ram_memory_reg_i_1 (.I0(\mr_tst_out[tst_dest_tst_addr] [4]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(rx_read_pointer[4]), .I3(\g_bit[0].reg_value_r_reg[0] ), .I4(rx_read_pointer[3]), .I5(\g_ram_rst_false.ram_memory_reg_i_46_n_0 ), .O(ADDRARDADDR[3])); LUT6 #( .INIT(64'hBBBBBBB8888888B8)) \g_ram_rst_false.ram_memory_reg_i_10 (.I0(\mr_tst_out[tst_dest_tst_addr] [0]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(write_pointer_raw[0]), .I3(\g_ram_rst_false.ram_memory_reg_3 [2]), .I4(\g_ram_rst_false.ram_memory_reg_3 [1]), .I5(write_pointer_ts_i_reg[0]), .O(ADDRBWRADDR[0])); LUT6 #( .INIT(64'h2222222222222220)) \g_ram_rst_false.ram_memory_reg_i_112 (.I0(E), .I1(\g_ram_rst_false.ram_memory_reg_i_128_n_0 ), .I2(sbe_IBUF[3]), .I3(sbe_IBUF[1]), .I4(sbe_IBUF[2]), .I5(sbe_IBUF[0]), .O(\mr_ctrl_out[rx_data_read] )); LUT6 #( .INIT(64'hEFFFFFFFFFFFFFFF)) \g_ram_rst_false.ram_memory_reg_i_128 (.I0(adress_IBUF[5]), .I1(adress_IBUF[2]), .I2(adress_IBUF[3]), .I3(adress_IBUF[4]), .I4(adress_IBUF[0]), .I5(adress_IBUF[1]), .O(\g_ram_rst_false.ram_memory_reg_i_128_n_0 )); LUT5 #( .INIT(32'hB8B8B88B)) \g_ram_rst_false.ram_memory_reg_i_2 (.I0(\mr_tst_out[tst_dest_tst_addr] [3]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(rx_read_pointer[3]), .I3(\g_ram_rst_false.ram_memory_reg_i_46_n_0 ), .I4(\g_bit[0].reg_value_r_reg[0] ), .O(ADDRARDADDR[2])); LUT6 #( .INIT(64'hB8B8B8B88BB8B8B8)) \g_ram_rst_false.ram_memory_reg_i_3 (.I0(\mr_tst_out[tst_dest_tst_addr] [2]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(rx_read_pointer[2]), .I3(\read_pointer_i_reg[0]_0 ), .I4(rx_read_pointer[1]), .I5(\g_bit[0].reg_value_r_reg[0] ), .O(ADDRARDADDR[1])); LUT5 #( .INIT(32'hB88BB8B8)) \g_ram_rst_false.ram_memory_reg_i_4 (.I0(\mr_tst_out[tst_dest_tst_addr] [1]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(rx_read_pointer[1]), .I3(\g_bit[0].reg_value_r_reg[0] ), .I4(\read_pointer_i_reg[0]_0 ), .O(ADDRARDADDR[0])); LUT6 #( .INIT(64'hAAAAFBFFFFFFFBFF)) \g_ram_rst_false.ram_memory_reg_i_45 (.I0(\r_data_reg[18] ), .I1(data_in_IBUF), .I2(\rx_mem_free_i_i_reg[0]_0 ), .I3(\adress[7] ), .I4(\mr_ctrl_out[mode_rxbam] ), .I5(\mr_ctrl_out[rx_data_read] ), .O(\g_bit[0].reg_value_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair337" *) LUT3 #( .INIT(8'h7F)) \g_ram_rst_false.ram_memory_reg_i_46 (.I0(rx_read_pointer[1]), .I1(\read_pointer_i_reg[0]_0 ), .I2(rx_read_pointer[2]), .O(\g_ram_rst_false.ram_memory_reg_i_46_n_0 )); LUT6 #( .INIT(64'hBBBBBBB8888888B8)) \g_ram_rst_false.ram_memory_reg_i_6 (.I0(\mr_tst_out[tst_dest_tst_addr] [4]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(write_pointer_raw[4]), .I3(\g_ram_rst_false.ram_memory_reg_3 [2]), .I4(\g_ram_rst_false.ram_memory_reg_3 [1]), .I5(write_pointer_ts_i_reg[4]), .O(ADDRBWRADDR[4])); LUT6 #( .INIT(64'hBBBBBBB8888888B8)) \g_ram_rst_false.ram_memory_reg_i_7 (.I0(\mr_tst_out[tst_dest_tst_addr] [3]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(write_pointer_raw[3]), .I3(\g_ram_rst_false.ram_memory_reg_3 [2]), .I4(\g_ram_rst_false.ram_memory_reg_3 [1]), .I5(write_pointer_ts_i_reg[3]), .O(ADDRBWRADDR[3])); LUT6 #( .INIT(64'hBBBBBBB8888888B8)) \g_ram_rst_false.ram_memory_reg_i_8 (.I0(\mr_tst_out[tst_dest_tst_addr] [2]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(write_pointer_raw[2]), .I3(\g_ram_rst_false.ram_memory_reg_3 [2]), .I4(\g_ram_rst_false.ram_memory_reg_3 [1]), .I5(write_pointer_ts_i_reg[2]), .O(ADDRBWRADDR[2])); LUT6 #( .INIT(64'hBBBBBBB8888888B8)) \g_ram_rst_false.ram_memory_reg_i_9 (.I0(\mr_tst_out[tst_dest_tst_addr] [1]), .I1(\g_ram_rst_false.ram_memory_reg_2 ), .I2(write_pointer_raw[1]), .I3(\g_ram_rst_false.ram_memory_reg_3 [2]), .I4(\g_ram_rst_false.ram_memory_reg_3 [1]), .I5(write_pointer_ts_i_reg[1]), .O(ADDRBWRADDR[1])); LUT6 #( .INIT(64'h0000000000000001)) int_status_i_2__0 (.I0(rx_mem_free[1]), .I1(rx_mem_free[0]), .I2(rx_mem_free[2]), .I3(rx_mem_free[3]), .I4(rx_mem_free[4]), .I5(\rx_mem_free_i_i_reg[5]_0 ), .O(rx_full)); LUT6 #( .INIT(64'hCCCCCCCCCCEEFCEE)) \r_data[16]_i_3 (.I0(\r_data[16]_i_6_n_0 ), .I1(\r_data_reg[16]_0 ), .I2(\r_data_reg[20]_3 [0]), .I3(adress_IBUF[2]), .I4(\r_data_reg[16] ), .I5(\r_data_reg[16]_1 ), .O(\alc_alc_bit_reg[0] )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \r_data[16]_i_6 (.I0(rxb_port_b_data_out), .I1(\mr_ctrl_out[rx_settings_rtsop] ), .I2(adress_IBUF[1]), .I3(\read_pointer_i_reg[0]_0 ), .I4(adress_IBUF[0]), .I5(rx_mem_free[0]), .O(\r_data[16]_i_6_n_0 )); LUT6 #( .INIT(64'h4F400F0F4F400000)) \r_data[17]_i_6 (.I0(\r_data_reg[18] ), .I1(rxb_port_b_data_out_i[2]), .I2(adress_IBUF[1]), .I3(rx_read_pointer[1]), .I4(adress_IBUF[0]), .I5(rx_mem_free[1]), .O(\g_ram_rst_false.ram_memory_reg_1 )); LUT6 #( .INIT(64'h4F400F0F4F400000)) \r_data[18]_i_5 (.I0(\r_data_reg[18] ), .I1(rxb_port_b_data_out_i[3]), .I2(adress_IBUF[1]), .I3(rx_read_pointer[2]), .I4(adress_IBUF[0]), .I5(rx_mem_free[2]), .O(\g_ram_rst_false.ram_memory_reg_0 )); LUT6 #( .INIT(64'h4F400F0F4F400000)) \r_data[19]_i_6 (.I0(\r_data_reg[18] ), .I1(rxb_port_b_data_out_i[4]), .I2(adress_IBUF[1]), .I3(rx_read_pointer[3]), .I4(adress_IBUF[0]), .I5(rx_mem_free[3]), .O(\g_ram_rst_false.ram_memory_reg )); LUT6 #( .INIT(64'h02020202020202A2)) \r_data[1]_i_1 (.I0(sbe_IBUF[0]), .I1(\r_data[1]_i_2__0_n_0 ), .I2(adress_IBUF[5]), .I3(\r_data_reg[1] ), .I4(adress_IBUF[3]), .I5(adress_IBUF[4]), .O(D[0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \r_data[1]_i_2__0 (.I0(\r_data_reg[1]_i_4_n_0 ), .I1(\r_data_reg[1]_0 ), .I2(adress_IBUF[4]), .I3(\r_data_reg[1]_1 ), .I4(adress_IBUF[3]), .I5(\r_data_reg[1]_2 ), .O(\r_data[1]_i_2__0_n_0 )); LUT6 #( .INIT(64'hDD1D3333DD1DFFFF)) \r_data[1]_i_9 (.I0(rx_write_pointer[1]), .I1(adress_IBUF[1]), .I2(rxb_port_b_data_out_i[0]), .I3(\r_data_reg[18] ), .I4(adress_IBUF[0]), .I5(rx_full), .O(\r_data[1]_i_9_n_0 )); LUT6 #( .INIT(64'h008A008A008AAA8A)) \r_data[20]_i_1 (.I0(sbe_IBUF[2]), .I1(\r_data[20]_i_2_n_0 ), .I2(\r_data_reg[20] ), .I3(adress_IBUF[5]), .I4(\r_data_reg[20]_0 ), .I5(\r_data_reg[20]_1 ), .O(D[1])); LUT6 #( .INIT(64'h88F888F8FFFF88F8)) \r_data[20]_i_2 (.I0(\r_data_reg[20]_2 ), .I1(\r_data[20]_i_5_n_0 ), .I2(\r_data_reg[20]_3 [1]), .I3(\r_data_reg[20]_4 ), .I4(\r_data_reg[20]_5 ), .I5(\r_data_reg[20]_6 ), .O(\r_data[20]_i_2_n_0 )); LUT6 #( .INIT(64'h4F400F0F4F400000)) \r_data[20]_i_5 (.I0(\r_data_reg[18] ), .I1(rxb_port_b_data_out_i[5]), .I2(adress_IBUF[1]), .I3(rx_read_pointer[4]), .I4(adress_IBUF[0]), .I5(rx_mem_free[4]), .O(\r_data[20]_i_5_n_0 )); LUT5 #( .INIT(32'hF7F737F7)) \r_data[3]_i_7 (.I0(rx_write_pointer[3]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(rxb_port_b_data_out_i[1]), .I4(\r_data_reg[18] ), .O(\r_data[3]_i_7_n_0 )); MUXF7 \r_data_reg[1]_i_4 (.I0(\r_data[1]_i_9_n_0 ), .I1(\r_data[1]_i_2__0_0 ), .O(\r_data_reg[1]_i_4_n_0 ), .S(adress_IBUF[2])); MUXF7 \r_data_reg[3]_i_4 (.I0(\r_data[3]_i_7_n_0 ), .I1(\r_data[3]_i_2 ), .O(\adress[4] ), .S(adress_IBUF[2])); (* SOFT_HLUTNM = "soft_lutpair339" *) LUT1 #( .INIT(2'h1)) \read_pointer_i[0]_i_1 (.I0(\read_pointer_i_reg[0]_0 ), .O(plusOp[0])); (* SOFT_HLUTNM = "soft_lutpair339" *) LUT2 #( .INIT(4'h6)) \read_pointer_i[1]_i_1 (.I0(\read_pointer_i_reg[0]_0 ), .I1(rx_read_pointer[1]), .O(plusOp[1])); (* SOFT_HLUTNM = "soft_lutpair337" *) LUT3 #( .INIT(8'h6A)) \read_pointer_i[2]_i_1 (.I0(rx_read_pointer[2]), .I1(\read_pointer_i_reg[0]_0 ), .I2(rx_read_pointer[1]), .O(plusOp[2])); (* SOFT_HLUTNM = "soft_lutpair333" *) LUT4 #( .INIT(16'h6AAA)) \read_pointer_i[3]_i_1 (.I0(rx_read_pointer[3]), .I1(rx_read_pointer[2]), .I2(\read_pointer_i_reg[0]_0 ), .I3(rx_read_pointer[1]), .O(\read_pointer_i[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \read_pointer_i[4]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0] ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair333" *) LUT5 #( .INIT(32'h6AAAAAAA)) \read_pointer_i[4]_i_2 (.I0(rx_read_pointer[4]), .I1(rx_read_pointer[1]), .I2(\read_pointer_i_reg[0]_0 ), .I3(rx_read_pointer[2]), .I4(rx_read_pointer[3]), .O(plusOp[4])); FDCE \read_pointer_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(plusOp[0]), .Q(\read_pointer_i_reg[0]_0 )); FDCE \read_pointer_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(plusOp[1]), .Q(rx_read_pointer[1])); FDCE \read_pointer_i_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(plusOp[2]), .Q(rx_read_pointer[2])); FDCE \read_pointer_i_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(\read_pointer_i[3]_i_1_n_0 ), .Q(rx_read_pointer[3])); FDCE \read_pointer_i_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\g_bit[0].reg_value_r_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(plusOp[4]), .Q(rx_read_pointer[4])); LUT6 #( .INIT(64'h0000000000000001)) reg_q_i_2 (.I0(data_overrun_i_reg), .I1(\r_data_reg[16] ), .I2(adress_IBUF[5]), .I3(adress_IBUF[2]), .I4(adress_IBUF[4]), .I5(adress_IBUF[3]), .O(\adress[7] )); LUT4 #( .INIT(16'hA5B1)) \rx_mem_free_i_i[0]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0] ), .I1(rx_mem_free[0]), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(commit_rx_frame), .O(p_1_in[0])); LUT6 #( .INIT(64'h9C889CDD9CDD9C88)) \rx_mem_free_i_i[1]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0] ), .I1(\rx_mem_free_raw_reg_n_0_[1] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(commit_rx_frame), .I4(rx_mem_free[0]), .I5(rx_mem_free[1]), .O(p_1_in[1])); LUT6 #( .INIT(64'h9CCCDDDD9CCC8888)) \rx_mem_free_i_i[2]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0] ), .I1(\rx_mem_free_raw_reg_n_0_[2] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(\rx_mem_free_raw_reg_n_0_[1] ), .I4(commit_rx_frame), .I5(\rx_mem_free_i_i[2]_i_2_n_0 ), .O(p_1_in[2])); (* SOFT_HLUTNM = "soft_lutpair338" *) LUT3 #( .INIT(8'h78)) \rx_mem_free_i_i[2]_i_2 (.I0(rx_mem_free[0]), .I1(rx_mem_free[1]), .I2(rx_mem_free[2]), .O(\rx_mem_free_i_i[2]_i_2_n_0 )); LUT6 #( .INIT(64'hB888B8BBB8BBB888)) \rx_mem_free_i_i[3]_i_1 (.I0(\rx_mem_free_raw_reg_n_0_[3] ), .I1(\g_bit[0].reg_value_r_reg[0] ), .I2(\rx_mem_free_i_i[3]_i_2_n_0 ), .I3(commit_rx_frame), .I4(rx_mem_free[3]), .I5(\rx_mem_free_i_i[3]_i_3_n_0 ), .O(p_1_in[3])); LUT4 #( .INIT(16'h6AAA)) \rx_mem_free_i_i[3]_i_2 (.I0(\rx_mem_free_raw_reg_n_0_[3] ), .I1(\rx_mem_free_raw_reg_n_0_[1] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(\rx_mem_free_raw_reg_n_0_[2] ), .O(\rx_mem_free_i_i[3]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair338" *) LUT3 #( .INIT(8'h80)) \rx_mem_free_i_i[3]_i_3 (.I0(rx_mem_free[2]), .I1(rx_mem_free[1]), .I2(rx_mem_free[0]), .O(\rx_mem_free_i_i[3]_i_3_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \rx_mem_free_i_i[4]_i_1 (.I0(\rx_mem_free_raw_reg_n_0_[4] ), .I1(\g_bit[0].reg_value_r_reg[0] ), .I2(\rx_mem_free_raw[4]_i_3_n_0 ), .I3(commit_rx_frame), .I4(\rx_mem_free_raw[4]_i_4_n_0 ), .O(p_1_in[4])); LUT2 #( .INIT(4'hB)) \rx_mem_free_i_i[5]_i_1 (.I0(commit_rx_frame), .I1(\g_bit[0].reg_value_r_reg[0] ), .O(\rx_mem_free_i_i[5]_i_1_n_0 )); LUT5 #( .INIT(32'hB8BBB888)) \rx_mem_free_i_i[5]_i_2 (.I0(\rx_mem_free_raw_reg_n_0_[5] ), .I1(\g_bit[0].reg_value_r_reg[0] ), .I2(\rx_mem_free_raw[5]_i_4_n_0 ), .I3(commit_rx_frame), .I4(\rx_mem_free_raw[5]_i_6_n_0 ), .O(p_1_in[5])); FDCE \rx_mem_free_i_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_i_i[5]_i_1_n_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(p_1_in[0]), .Q(rx_mem_free[0])); FDCE \rx_mem_free_i_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_i_i[5]_i_1_n_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(p_1_in[1]), .Q(rx_mem_free[1])); FDCE \rx_mem_free_i_i_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_i_i[5]_i_1_n_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(p_1_in[2]), .Q(rx_mem_free[2])); FDCE \rx_mem_free_i_i_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_i_i[5]_i_1_n_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(p_1_in[3]), .Q(rx_mem_free[3])); FDCE \rx_mem_free_i_i_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_i_i[5]_i_1_n_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(p_1_in[4]), .Q(rx_mem_free[4])); FDPE \rx_mem_free_i_i_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_i_i[5]_i_1_n_0 ), .D(p_1_in[5]), .PRE(\rx_mem_free_i_i_reg[5]_1 ), .Q(\rx_mem_free_i_i_reg[5]_0 )); LUT6 #( .INIT(64'hFFD500150015FFD5)) \rx_mem_free_raw[0]_i_1 (.I0(\rx_mem_free_raw_reg_n_0_[0] ), .I1(ident_valid_q), .I2(rec_abort), .I3(commit_overrun_abort), .I4(rx_mem_free[0]), .I5(\g_bit[0].reg_value_r_reg[0] ), .O(\rx_mem_free_raw[0]_i_1_n_0 )); LUT6 #( .INIT(64'h96AA96FF96559600)) \rx_mem_free_raw[1]_i_1 (.I0(\g_bit[0].reg_value_r_reg[0] ), .I1(\rx_mem_free_raw_reg_n_0_[1] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(\rx_mem_free_raw_reg[1]_0 ), .I4(rx_mem_free[0]), .I5(rx_mem_free[1]), .O(\rx_mem_free_raw[1]_i_1_n_0 )); LUT5 #( .INIT(32'h6AFF6A00)) \rx_mem_free_raw[2]_i_2 (.I0(\rx_mem_free_raw_reg_n_0_[2] ), .I1(\rx_mem_free_raw_reg_n_0_[0] ), .I2(\rx_mem_free_raw_reg_n_0_[1] ), .I3(\rx_mem_free_raw_reg[1]_0 ), .I4(\rx_mem_free_i_i[2]_i_2_n_0 ), .O(\rx_mem_free_raw[2]_i_2_n_0 )); LUT5 #( .INIT(32'hA9FFA900)) \rx_mem_free_raw[2]_i_3 (.I0(\rx_mem_free_raw_reg_n_0_[2] ), .I1(\rx_mem_free_raw_reg_n_0_[0] ), .I2(\rx_mem_free_raw_reg_n_0_[1] ), .I3(\rx_mem_free_raw_reg[1]_0 ), .I4(rx_mem_free[2]), .O(\rx_mem_free_raw[2]_i_3_n_0 )); LUT6 #( .INIT(64'h6AAAFFFF6AAA0000)) \rx_mem_free_raw[3]_i_2 (.I0(\rx_mem_free_raw_reg_n_0_[3] ), .I1(\rx_mem_free_raw_reg_n_0_[1] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(\rx_mem_free_raw_reg_n_0_[2] ), .I4(\rx_mem_free_raw_reg[1]_0 ), .I5(\rx_mem_free_raw[3]_i_4_n_0 ), .O(\rx_mem_free_raw[3]_i_2_n_0 )); LUT6 #( .INIT(64'hAAA9FFFFAAA90000)) \rx_mem_free_raw[3]_i_3 (.I0(\rx_mem_free_raw_reg_n_0_[3] ), .I1(\rx_mem_free_raw_reg_n_0_[1] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(\rx_mem_free_raw_reg_n_0_[2] ), .I4(\rx_mem_free_raw_reg[1]_0 ), .I5(rx_mem_free[3]), .O(\rx_mem_free_raw[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair332" *) LUT4 #( .INIT(16'h6AAA)) \rx_mem_free_raw[3]_i_4 (.I0(rx_mem_free[3]), .I1(rx_mem_free[0]), .I2(rx_mem_free[1]), .I3(rx_mem_free[2]), .O(\rx_mem_free_raw[3]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \rx_mem_free_raw[4]_i_1 (.I0(\rx_mem_free_raw[4]_i_2_n_0 ), .I1(rx_mem_free[4]), .I2(\g_bit[0].reg_value_r_reg[0] ), .I3(\rx_mem_free_raw[4]_i_3_n_0 ), .I4(\rx_mem_free_raw_reg[1]_0 ), .I5(\rx_mem_free_raw[4]_i_4_n_0 ), .O(\rx_mem_free_raw[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair331" *) LUT5 #( .INIT(32'hAAAAAAA9)) \rx_mem_free_raw[4]_i_2 (.I0(\rx_mem_free_raw_reg_n_0_[4] ), .I1(\rx_mem_free_raw_reg_n_0_[3] ), .I2(\rx_mem_free_raw_reg_n_0_[2] ), .I3(\rx_mem_free_raw_reg_n_0_[0] ), .I4(\rx_mem_free_raw_reg_n_0_[1] ), .O(\rx_mem_free_raw[4]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair331" *) LUT5 #( .INIT(32'h6AAAAAAA)) \rx_mem_free_raw[4]_i_3 (.I0(\rx_mem_free_raw_reg_n_0_[4] ), .I1(\rx_mem_free_raw_reg_n_0_[2] ), .I2(\rx_mem_free_raw_reg_n_0_[0] ), .I3(\rx_mem_free_raw_reg_n_0_[1] ), .I4(\rx_mem_free_raw_reg_n_0_[3] ), .O(\rx_mem_free_raw[4]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair332" *) LUT5 #( .INIT(32'h6AAAAAAA)) \rx_mem_free_raw[4]_i_4 (.I0(rx_mem_free[4]), .I1(rx_mem_free[2]), .I2(rx_mem_free[1]), .I3(rx_mem_free[0]), .I4(rx_mem_free[3]), .O(\rx_mem_free_raw[4]_i_4_n_0 )); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \rx_mem_free_raw[5]_i_2 (.I0(\rx_mem_free_raw[5]_i_3_n_0 ), .I1(\rx_mem_free_i_i_reg[5]_0 ), .I2(\g_bit[0].reg_value_r_reg[0] ), .I3(\rx_mem_free_raw[5]_i_4_n_0 ), .I4(\rx_mem_free_raw_reg[1]_0 ), .I5(\rx_mem_free_raw[5]_i_6_n_0 ), .O(\rx_mem_free_raw[5]_i_2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \rx_mem_free_raw[5]_i_3 (.I0(\rx_mem_free_raw_reg_n_0_[5] ), .I1(\rx_mem_free_raw_reg_n_0_[4] ), .I2(\rx_mem_free_raw_reg_n_0_[1] ), .I3(\rx_mem_free_raw_reg_n_0_[0] ), .I4(\rx_mem_free_raw_reg_n_0_[2] ), .I5(\rx_mem_free_raw_reg_n_0_[3] ), .O(\rx_mem_free_raw[5]_i_3_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \rx_mem_free_raw[5]_i_4 (.I0(\rx_mem_free_raw_reg_n_0_[5] ), .I1(\rx_mem_free_raw_reg_n_0_[3] ), .I2(\rx_mem_free_raw_reg_n_0_[1] ), .I3(\rx_mem_free_raw_reg_n_0_[0] ), .I4(\rx_mem_free_raw_reg_n_0_[2] ), .I5(\rx_mem_free_raw_reg_n_0_[4] ), .O(\rx_mem_free_raw[5]_i_4_n_0 )); LUT6 #( .INIT(64'h6AAAAAAAAAAAAAAA)) \rx_mem_free_raw[5]_i_6 (.I0(\rx_mem_free_i_i_reg[5]_0 ), .I1(rx_mem_free[3]), .I2(rx_mem_free[0]), .I3(rx_mem_free[1]), .I4(rx_mem_free[2]), .I5(rx_mem_free[4]), .O(\rx_mem_free_raw[5]_i_6_n_0 )); FDCE \rx_mem_free_raw_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_raw_reg[5]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(\rx_mem_free_raw[0]_i_1_n_0 ), .Q(\rx_mem_free_raw_reg_n_0_[0] )); FDCE \rx_mem_free_raw_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_raw_reg[5]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(\rx_mem_free_raw[1]_i_1_n_0 ), .Q(\rx_mem_free_raw_reg_n_0_[1] )); FDCE \rx_mem_free_raw_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_raw_reg[5]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(\rx_mem_free_raw_reg[2]_i_1_n_0 ), .Q(\rx_mem_free_raw_reg_n_0_[2] )); MUXF7 \rx_mem_free_raw_reg[2]_i_1 (.I0(\rx_mem_free_raw[2]_i_2_n_0 ), .I1(\rx_mem_free_raw[2]_i_3_n_0 ), .O(\rx_mem_free_raw_reg[2]_i_1_n_0 ), .S(\g_bit[0].reg_value_r_reg[0] )); FDCE \rx_mem_free_raw_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_raw_reg[5]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(\rx_mem_free_raw_reg[3]_i_1_n_0 ), .Q(\rx_mem_free_raw_reg_n_0_[3] )); MUXF7 \rx_mem_free_raw_reg[3]_i_1 (.I0(\rx_mem_free_raw[3]_i_2_n_0 ), .I1(\rx_mem_free_raw[3]_i_3_n_0 ), .O(\rx_mem_free_raw_reg[3]_i_1_n_0 ), .S(\g_bit[0].reg_value_r_reg[0] )); FDCE \rx_mem_free_raw_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_raw_reg[5]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(\rx_mem_free_raw[4]_i_1_n_0 ), .Q(\rx_mem_free_raw_reg_n_0_[4] )); FDPE \rx_mem_free_raw_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\rx_mem_free_raw_reg[5]_0 ), .D(\rx_mem_free_raw[5]_i_2_n_0 ), .PRE(\rx_mem_free_i_i_reg[5]_1 ), .Q(\rx_mem_free_raw_reg_n_0_[5] )); FDCE \write_pointer_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(commit_rx_frame), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw[0]), .Q(Q[0])); FDCE \write_pointer_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(commit_rx_frame), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw[1]), .Q(rx_write_pointer[1])); FDCE \write_pointer_i_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(commit_rx_frame), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw[2]), .Q(Q[1])); FDCE \write_pointer_i_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(commit_rx_frame), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw[3]), .Q(rx_write_pointer[3])); FDCE \write_pointer_i_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(commit_rx_frame), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw[4]), .Q(Q[2])); (* SOFT_HLUTNM = "soft_lutpair335" *) LUT3 #( .INIT(8'h2E)) \write_pointer_raw_i[0]_i_1 (.I0(Q[0]), .I1(\write_pointer_raw_i_reg[4]_1 ), .I2(write_pointer_raw[0]), .O(write_pointer_raw_d[0])); (* SOFT_HLUTNM = "soft_lutpair335" *) LUT4 #( .INIT(16'h6F60)) \write_pointer_raw_i[1]_i_1 (.I0(write_pointer_raw[0]), .I1(write_pointer_raw[1]), .I2(\write_pointer_raw_i_reg[4]_1 ), .I3(rx_write_pointer[1]), .O(write_pointer_raw_d[1])); (* SOFT_HLUTNM = "soft_lutpair330" *) LUT5 #( .INIT(32'h6AFF6A00)) \write_pointer_raw_i[2]_i_1 (.I0(write_pointer_raw[2]), .I1(write_pointer_raw[1]), .I2(write_pointer_raw[0]), .I3(\write_pointer_raw_i_reg[4]_1 ), .I4(Q[1]), .O(write_pointer_raw_d[2])); LUT6 #( .INIT(64'h6AAAFFFF6AAA0000)) \write_pointer_raw_i[3]_i_1 (.I0(write_pointer_raw[3]), .I1(write_pointer_raw[0]), .I2(write_pointer_raw[1]), .I3(write_pointer_raw[2]), .I4(\write_pointer_raw_i_reg[4]_1 ), .I5(rx_write_pointer[3]), .O(write_pointer_raw_d[3])); LUT5 #( .INIT(32'h6AFF6A00)) \write_pointer_raw_i[4]_i_2 (.I0(write_pointer_raw[4]), .I1(\write_pointer_raw_i[4]_i_4_n_0 ), .I2(write_pointer_raw[3]), .I3(\write_pointer_raw_i_reg[4]_1 ), .I4(Q[2]), .O(write_pointer_raw_d[4])); (* SOFT_HLUTNM = "soft_lutpair330" *) LUT3 #( .INIT(8'h80)) \write_pointer_raw_i[4]_i_4 (.I0(write_pointer_raw[2]), .I1(write_pointer_raw[1]), .I2(write_pointer_raw[0]), .O(\write_pointer_raw_i[4]_i_4_n_0 )); FDCE \write_pointer_raw_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_raw_i_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw_d[0]), .Q(write_pointer_raw[0])); FDCE \write_pointer_raw_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_raw_i_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw_d[1]), .Q(write_pointer_raw[1])); FDCE \write_pointer_raw_i_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_raw_i_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw_d[2]), .Q(write_pointer_raw[2])); FDCE \write_pointer_raw_i_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_raw_i_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw_d[3]), .Q(write_pointer_raw[3])); FDCE \write_pointer_raw_i_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_raw_i_reg[0]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_raw_d[4]), .Q(write_pointer_raw[4])); (* SOFT_HLUTNM = "soft_lutpair336" *) LUT3 #( .INIT(8'hA3)) \write_pointer_ts_i[0]_i_1 (.I0(write_pointer_raw[0]), .I1(write_pointer_ts_i_reg[0]), .I2(\g_ram_rst_false.ram_memory_reg_3 [0]), .O(write_pointer_ts_d[0])); (* SOFT_HLUTNM = "soft_lutpair336" *) LUT4 #( .INIT(16'h8BB8)) \write_pointer_ts_i[1]_i_1 (.I0(write_pointer_raw[1]), .I1(\g_ram_rst_false.ram_memory_reg_3 [0]), .I2(write_pointer_ts_i_reg[0]), .I3(write_pointer_ts_i_reg[1]), .O(write_pointer_ts_d[1])); (* SOFT_HLUTNM = "soft_lutpair334" *) LUT5 #( .INIT(32'h8BB8B8B8)) \write_pointer_ts_i[2]_i_1 (.I0(write_pointer_raw[2]), .I1(\g_ram_rst_false.ram_memory_reg_3 [0]), .I2(write_pointer_ts_i_reg[2]), .I3(write_pointer_ts_i_reg[1]), .I4(write_pointer_ts_i_reg[0]), .O(write_pointer_ts_d[2])); LUT6 #( .INIT(64'h8BB8B8B8B8B8B8B8)) \write_pointer_ts_i[3]_i_1 (.I0(write_pointer_raw[3]), .I1(\g_ram_rst_false.ram_memory_reg_3 [0]), .I2(write_pointer_ts_i_reg[3]), .I3(write_pointer_ts_i_reg[0]), .I4(write_pointer_ts_i_reg[1]), .I5(write_pointer_ts_i_reg[2]), .O(write_pointer_ts_d[3])); LUT5 #( .INIT(32'h8BB8B8B8)) \write_pointer_ts_i[4]_i_2 (.I0(write_pointer_raw[4]), .I1(\g_ram_rst_false.ram_memory_reg_3 [0]), .I2(write_pointer_ts_i_reg[4]), .I3(\write_pointer_ts_i[4]_i_3_n_0 ), .I4(write_pointer_ts_i_reg[3]), .O(write_pointer_ts_d[4])); (* SOFT_HLUTNM = "soft_lutpair334" *) LUT3 #( .INIT(8'h80)) \write_pointer_ts_i[4]_i_3 (.I0(write_pointer_ts_i_reg[2]), .I1(write_pointer_ts_i_reg[1]), .I2(write_pointer_ts_i_reg[0]), .O(\write_pointer_ts_i[4]_i_3_n_0 )); FDCE \write_pointer_ts_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_ts_i_reg[4]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_ts_d[0]), .Q(write_pointer_ts_i_reg[0])); FDCE \write_pointer_ts_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_ts_i_reg[4]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_ts_d[1]), .Q(write_pointer_ts_i_reg[1])); FDCE \write_pointer_ts_i_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_ts_i_reg[4]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_ts_d[2]), .Q(write_pointer_ts_i_reg[2])); FDCE \write_pointer_ts_i_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_ts_i_reg[4]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_ts_d[3]), .Q(write_pointer_ts_i_reg[3])); FDCE \write_pointer_ts_i_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\write_pointer_ts_i_reg[4]_0 ), .CLR(\rx_mem_free_i_i_reg[5]_1 ), .D(write_pointer_ts_d[4]), .Q(write_pointer_ts_i_reg[4])); endmodule module rxb_ram (rxb_port_b_data_out_i, D, \g_bit[0].reg_value_r_reg[0] , \adress[4] , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_bit[0].reg_value_r_reg[0]_0 , \g_ram_rst_false.ram_memory_reg_4 , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , \g_ram_rst_false.ram_memory_reg_7 , \g_bit[0].reg_value_r_reg[0]_1 , \adress[4]_0 , \frame_count_reg[3] , \g_ram_rst_false.ram_memory_reg_8 , rxb_port_b_data_out, \g_ram_rst_false.ram_memory_reg_9 , clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, rxb_port_a_data_in_i, DIADI, WEBWE, sbe_IBUF, \r_data_reg[11] , \r_data_reg[11]_0 , adress_IBUF, \r_data_reg[11]_1 , \r_data_reg[26] , \r_data_reg[26]_0 , \r_data_reg[26]_1 , \r_data_reg[27] , \r_data_reg[27]_0 , \r_data_reg[28] , \r_data_reg[28]_0 , \r_data_reg[28]_1 , \r_data_reg[28]_2 , \r_data_reg[29] , \r_data_reg[29]_0 , \r_data_reg[30] , \r_data_reg[30]_0 , \r_data_reg[31] , \r_data_reg[31]_0 , \r_data_reg[0] , \r_data_reg[0]_0 , soft_res_d_n, \r_data_reg[0]_1 , \r_data_reg[24] , \r_data_reg[24]_0 , \r_data_reg[24]_1 , \mr_ctrl_out[settings_pex] , \r_data_reg[26]_2 , \r_data_reg[27]_1 , \r_data[6]_i_2 , \r_data[7]_i_2__0 , \r_data[8]_i_2 , \r_data[9]_i_2__0 , \r_data[10]_i_2__0 , \r_data_reg[11]_2 , \r_data_reg[11]_3 , \r_data_reg[11]_4 , \r_data[11]_i_2__0 , \r_data[15]_i_6 , \r_data[0]_i_2 , \r_data[12]_i_2 , \r_data[13]_i_2 , \r_data_reg[14]_i_2 , \r_data[14]_i_5 , \r_data[21]_i_2 , \r_data[21]_i_2_0 , \r_data[23]_i_2 , \r_data[4]_i_2 , \r_data[4]_i_2_0 , \r_data[0]_i_2_0 , \r_data[0]_i_2_1 , \r_data[5]_i_2 , Q, \r_data[6]_i_4 , \r_data[4]_i_5 , rx_mof, \read_counter_q_reg[0] ); output [31:0]rxb_port_b_data_out_i; output [8:0]D; output \g_bit[0].reg_value_r_reg[0] ; output \adress[4] ; output \g_ram_rst_false.ram_memory_reg ; output \g_ram_rst_false.ram_memory_reg_0 ; output \g_ram_rst_false.ram_memory_reg_1 ; output \g_ram_rst_false.ram_memory_reg_2 ; output \g_ram_rst_false.ram_memory_reg_3 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_ram_rst_false.ram_memory_reg_4 ; output \g_ram_rst_false.ram_memory_reg_5 ; output \g_ram_rst_false.ram_memory_reg_6 ; output \g_ram_rst_false.ram_memory_reg_7 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \adress[4]_0 ; output \frame_count_reg[3] ; output \g_ram_rst_false.ram_memory_reg_8 ; output [0:0]rxb_port_b_data_out; output [4:0]\g_ram_rst_false.ram_memory_reg_9 ; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [30:0]rxb_port_a_data_in_i; input [0:0]DIADI; input [0:0]WEBWE; input [2:0]sbe_IBUF; input \r_data_reg[11] ; input \r_data_reg[11]_0 ; input [5:0]adress_IBUF; input \r_data_reg[11]_1 ; input \r_data_reg[26] ; input \r_data_reg[26]_0 ; input \r_data_reg[26]_1 ; input \r_data_reg[27] ; input \r_data_reg[27]_0 ; input \r_data_reg[28] ; input \r_data_reg[28]_0 ; input \r_data_reg[28]_1 ; input \r_data_reg[28]_2 ; input \r_data_reg[29] ; input \r_data_reg[29]_0 ; input \r_data_reg[30] ; input \r_data_reg[30]_0 ; input \r_data_reg[31] ; input \r_data_reg[31]_0 ; input \r_data_reg[0] ; input \r_data_reg[0]_0 ; input soft_res_d_n; input \r_data_reg[0]_1 ; input \r_data_reg[24] ; input \r_data_reg[24]_0 ; input \r_data_reg[24]_1 ; input \mr_ctrl_out[settings_pex] ; input \r_data_reg[26]_2 ; input \r_data_reg[27]_1 ; input \r_data[6]_i_2 ; input \r_data[7]_i_2__0 ; input \r_data[8]_i_2 ; input \r_data[9]_i_2__0 ; input \r_data[10]_i_2__0 ; input \r_data_reg[11]_2 ; input \r_data_reg[11]_3 ; input \r_data_reg[11]_4 ; input \r_data[11]_i_2__0 ; input \r_data[15]_i_6 ; input \r_data[0]_i_2 ; input \r_data[12]_i_2 ; input \r_data[13]_i_2 ; input \r_data_reg[14]_i_2 ; input \r_data[14]_i_5 ; input \r_data[21]_i_2 ; input [0:0]\r_data[21]_i_2_0 ; input [1:0]\r_data[23]_i_2 ; input \r_data[4]_i_2 ; input \r_data[4]_i_2_0 ; input \r_data[0]_i_2_0 ; input \r_data[0]_i_2_1 ; input \r_data[5]_i_2 ; input [3:0]Q; input \r_data[6]_i_4 ; input [2:0]\r_data[4]_i_5 ; input rx_mof; input [4:0]\read_counter_q_reg[0] ; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [8:0]D; wire [0:0]DIADI; wire [3:0]Q; wire [0:0]WEBWE; wire \adress[4] ; wire \adress[4]_0 ; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire \frame_count_reg[3] ; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire \g_ram_rst_false.ram_memory_reg_7 ; wire \g_ram_rst_false.ram_memory_reg_8 ; wire [4:0]\g_ram_rst_false.ram_memory_reg_9 ; wire \mr_ctrl_out[settings_pex] ; wire \r_data[0]_i_2 ; wire \r_data[0]_i_2_0 ; wire \r_data[0]_i_2_1 ; wire \r_data[10]_i_2__0 ; wire \r_data[11]_i_2__0 ; wire \r_data[12]_i_2 ; wire \r_data[13]_i_2 ; wire \r_data[14]_i_5 ; wire \r_data[15]_i_6 ; wire \r_data[21]_i_2 ; wire [0:0]\r_data[21]_i_2_0 ; wire [1:0]\r_data[23]_i_2 ; wire \r_data[4]_i_2 ; wire \r_data[4]_i_2_0 ; wire [2:0]\r_data[4]_i_5 ; wire \r_data[5]_i_2 ; wire \r_data[6]_i_2 ; wire \r_data[6]_i_4 ; wire \r_data[7]_i_2__0 ; wire \r_data[8]_i_2 ; wire \r_data[9]_i_2__0 ; wire \r_data_reg[0] ; wire \r_data_reg[0]_0 ; wire \r_data_reg[0]_1 ; wire \r_data_reg[11] ; wire \r_data_reg[11]_0 ; wire \r_data_reg[11]_1 ; wire \r_data_reg[11]_2 ; wire \r_data_reg[11]_3 ; wire \r_data_reg[11]_4 ; wire \r_data_reg[14]_i_2 ; wire \r_data_reg[24] ; wire \r_data_reg[24]_0 ; wire \r_data_reg[24]_1 ; wire \r_data_reg[26] ; wire \r_data_reg[26]_0 ; wire \r_data_reg[26]_1 ; wire \r_data_reg[26]_2 ; wire \r_data_reg[27] ; wire \r_data_reg[27]_0 ; wire \r_data_reg[27]_1 ; wire \r_data_reg[28] ; wire \r_data_reg[28]_0 ; wire \r_data_reg[28]_1 ; wire \r_data_reg[28]_2 ; wire \r_data_reg[29] ; wire \r_data_reg[29]_0 ; wire \r_data_reg[30] ; wire \r_data_reg[30]_0 ; wire \r_data_reg[31] ; wire \r_data_reg[31]_0 ; wire [4:0]\read_counter_q_reg[0] ; wire rx_mof; wire [30:0]rxb_port_a_data_in_i; wire [0:0]rxb_port_b_data_out; wire [31:0]rxb_port_b_data_out_i; wire [2:0]sbe_IBUF; wire soft_res_d_n; dp_inf_ram i_dp_inf_ram (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .D(D), .DIADI(DIADI), .Q(Q), .WEBWE(WEBWE), .\adress[4] (\adress[4] ), .\adress[4]_0 (\adress[4]_0 ), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\frame_count_reg[3] (\frame_count_reg[3] ), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_1 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_0 ), .\g_ram_rst_false.ram_memory_reg_10 (\g_ram_rst_false.ram_memory_reg_9 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_1 ), .\g_ram_rst_false.ram_memory_reg_3 (\g_ram_rst_false.ram_memory_reg_2 ), .\g_ram_rst_false.ram_memory_reg_4 (\g_ram_rst_false.ram_memory_reg_3 ), .\g_ram_rst_false.ram_memory_reg_5 (\g_ram_rst_false.ram_memory_reg_4 ), .\g_ram_rst_false.ram_memory_reg_6 (\g_ram_rst_false.ram_memory_reg_5 ), .\g_ram_rst_false.ram_memory_reg_7 (\g_ram_rst_false.ram_memory_reg_6 ), .\g_ram_rst_false.ram_memory_reg_8 (\g_ram_rst_false.ram_memory_reg_7 ), .\g_ram_rst_false.ram_memory_reg_9 (\g_ram_rst_false.ram_memory_reg_8 ), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\r_data[0]_i_2_0 (\r_data[0]_i_2 ), .\r_data[0]_i_2_1 (\r_data[0]_i_2_0 ), .\r_data[0]_i_2_2 (\r_data[0]_i_2_1 ), .\r_data[10]_i_2__0 (\r_data[10]_i_2__0 ), .\r_data[11]_i_2__0_0 (\r_data[11]_i_2__0 ), .\r_data[12]_i_2 (\r_data[12]_i_2 ), .\r_data[13]_i_2 (\r_data[13]_i_2 ), .\r_data[14]_i_5_0 (\r_data[14]_i_5 ), .\r_data[15]_i_6 (\r_data[15]_i_6 ), .\r_data[21]_i_2 (\r_data[21]_i_2 ), .\r_data[21]_i_2_0 (\r_data[21]_i_2_0 ), .\r_data[23]_i_2 (\r_data[23]_i_2 ), .\r_data[4]_i_2 (\r_data[4]_i_2 ), .\r_data[4]_i_2_0 (\r_data[4]_i_2_0 ), .\r_data[4]_i_5_0 (\r_data[4]_i_5 ), .\r_data[5]_i_2 (\r_data[5]_i_2 ), .\r_data[6]_i_2 (\r_data[6]_i_2 ), .\r_data[6]_i_4_0 (\r_data[6]_i_4 ), .\r_data[7]_i_2__0 (\r_data[7]_i_2__0 ), .\r_data[8]_i_2 (\r_data[8]_i_2 ), .\r_data[9]_i_2__0 (\r_data[9]_i_2__0 ), .\r_data_reg[0] (\r_data_reg[0] ), .\r_data_reg[0]_0 (\r_data_reg[0]_0 ), .\r_data_reg[0]_1 (\r_data_reg[0]_1 ), .\r_data_reg[11] (\r_data_reg[11] ), .\r_data_reg[11]_0 (\r_data_reg[11]_0 ), .\r_data_reg[11]_1 (\r_data_reg[11]_1 ), .\r_data_reg[11]_2 (\r_data_reg[11]_2 ), .\r_data_reg[11]_3 (\r_data_reg[11]_3 ), .\r_data_reg[11]_4 (\r_data_reg[11]_4 ), .\r_data_reg[14]_i_2 (\r_data_reg[14]_i_2 ), .\r_data_reg[24] (\r_data_reg[24] ), .\r_data_reg[24]_0 (\r_data_reg[24]_0 ), .\r_data_reg[24]_1 (\r_data_reg[24]_1 ), .\r_data_reg[26] (\r_data_reg[26] ), .\r_data_reg[26]_0 (\r_data_reg[26]_0 ), .\r_data_reg[26]_1 (\r_data_reg[26]_1 ), .\r_data_reg[26]_2 (\r_data_reg[26]_2 ), .\r_data_reg[27] (\r_data_reg[27] ), .\r_data_reg[27]_0 (\r_data_reg[27]_0 ), .\r_data_reg[27]_1 (\r_data_reg[27]_1 ), .\r_data_reg[28] (\r_data_reg[28] ), .\r_data_reg[28]_0 (\r_data_reg[28]_0 ), .\r_data_reg[28]_1 (\r_data_reg[28]_1 ), .\r_data_reg[28]_2 (\r_data_reg[28]_2 ), .\r_data_reg[29] (\r_data_reg[29] ), .\r_data_reg[29]_0 (\r_data_reg[29]_0 ), .\r_data_reg[30] (\r_data_reg[30] ), .\r_data_reg[30]_0 (\r_data_reg[30]_0 ), .\r_data_reg[31] (\r_data_reg[31] ), .\r_data_reg[31]_0 (\r_data_reg[31]_0 ), .\read_counter_q_reg[0] (\read_counter_q_reg[0] ), .rx_mof(rx_mof), .rxb_port_a_data_in_i(rxb_port_a_data_in_i), .rxb_port_b_data_out(rxb_port_b_data_out), .rxb_port_b_data_out_i(rxb_port_b_data_out_i), .sbe_IBUF(sbe_IBUF), .soft_res_d_n(soft_res_d_n)); endmodule module rxb_top (rxb_port_b_data_out_i, D, \frame_count_reg[3]_0 , \adress[7] , rx_full, \adress[4] , \g_bit[0].reg_value_r_reg[0] , \adress[4]_0 , \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_bit[0].reg_value_r_reg[0]_0 , \g_ram_rst_false.ram_memory_reg_4 , \alc_alc_bit_reg[0] , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , \g_ram_rst_false.ram_memory_reg_7 , \g_bit[0].reg_value_r_reg[0]_1 , \adress[4]_1 , \frame_count_reg[3]_1 , Q, \g_ram_rst_false.ram_memory_reg_8 , \g_ram_rst_false.ram_memory_reg_9 , \g_ram_rst_false.ram_memory_reg_10 , \g_ram_rst_false.ram_memory_reg_11 , commit_overrun_abort, \g_bit[0].reg_value_r_reg[0]_2 , \FSM_onehot_curr_state_reg[8] , \FSM_onehot_curr_state_reg[1] , \FSM_onehot_curr_state_reg[8]_0 , \g_byte_shift_reg[1].shift_reg_q_reg[1][6] , \FSM_onehot_curr_state_reg[7] , \FSM_onehot_curr_state_reg[1]_0 , rx_data_overrun, clk_sys_IBUF_BUFG, ADDRARDADDR, DIADI, reg_q_reg, \FSM_onehot_curr_state_reg[11] , sbe_IBUF, \r_data_reg[11] , \r_data_reg[11]_0 , adress_IBUF, \r_data_reg[11]_1 , \r_data_reg[26] , \r_data_reg[26]_0 , \r_data_reg[26]_1 , \r_data_reg[27] , \r_data_reg[27]_0 , \r_data_reg[28] , \r_data_reg[28]_0 , \r_data_reg[28]_1 , \r_data_reg[29] , \r_data_reg[29]_0 , \r_data_reg[30] , \r_data_reg[30]_0 , \r_data_reg[31] , \r_data_reg[31]_0 , \r_data_reg[0] , soft_res_d_n, \r_data_reg[0]_0 , \r_data[0]_i_2 , \r_data_reg[1] , \r_data_reg[20] , \r_data_reg[20]_0 , \r_data_reg[24] , \r_data_reg[24]_0 , data_overrun_i_reg_0, \r_data_reg[16] , E, \r_data_reg[1]_0 , \r_data_reg[1]_1 , \r_data_reg[1]_2 , \r_data[1]_i_2__0 , \r_data[3]_i_2 , \r_data_reg[20]_1 , \r_data_reg[20]_2 , \r_data_reg[20]_3 , \r_data_reg[20]_4 , \r_data_reg[24]_1 , \mr_ctrl_out[settings_pex] , \r_data_reg[26]_2 , \r_data_reg[27]_1 , \r_data[6]_i_2 , \r_data[7]_i_2__0 , \r_data[8]_i_2 , \r_data[9]_i_2__0 , \r_data[10]_i_2__0 , \r_data_reg[11]_2 , \r_data_reg[11]_3 , \r_data_reg[11]_4 , \r_data[11]_i_2__0 , \r_data_reg[16]_0 , \r_data[12]_i_2 , \r_data[13]_i_2 , \r_data_reg[14]_i_2 , \r_data[14]_i_5 , \r_data_reg[16]_1 , \r_data[23]_i_2 , \r_data[4]_i_2 , \r_data[4]_i_2_0 , \r_data[0]_i_2_0 , \r_data[0]_i_2_1 , \r_data[5]_i_2 , \r_data[6]_i_4 , \mr_ctrl_out[rx_settings_rtsop] , ident_valid_q, rec_abort, \rx_mem_free_raw_reg[1] , \mr_tst_out[tst_dest_tst_addr] , \g_ram_rst_false.ram_memory_reg_12 , data_in_IBUF, data_overrun_i_reg_1, \mr_ctrl_out[mode_rxbam] , \mr_tst_out[tst_control_twrstb] , \g_ram_rst_false.ram_memory_reg_13 , \g_ram_rst_false.ram_memory_reg_14 , \g_ram_rst_false.ram_memory_reg_15 , \g_ram_rst_false.ram_memory_reg_16 , \FSM_onehot_curr_state_reg[11]_0 , \g_ram_rst_false.ram_memory_reg_i_111 , \FSM_onehot_curr_state_reg[0] , \FSM_onehot_curr_state_reg[8]_1 , store_data_word, \g_ram_rst_false.ram_memory_reg_17 , \g_ram_rst_false.ram_memory_reg_18 , rec_is_rtr, rec_ident_type, rec_frame_type, rec_brs, rec_esi, rec_ivld, rec_lbpf, \g_ram_rst_false.ram_memory_reg_19 , \g_ram_rst_false.ram_memory_reg_20 , \g_ram_rst_false.ram_memory_reg_21 , \mr_ctrl_out[mode_erfm] , rec_abort_f, \FSM_onehot_curr_state_reg[0]_0 , \cc_stat[err_erp] , store_metadata, rec_is_rtr_i, scan_mode_IBUF, rst_n_out_OBUF, rec_valid, \FSM_onehot_curr_state_reg[6] , \timestamp_capture_reg[63]_0 , timestamp_IBUF); output [31:0]rxb_port_b_data_out_i; output [10:0]D; output \frame_count_reg[3]_0 ; output \adress[7] ; output rx_full; output \adress[4] ; output \g_bit[0].reg_value_r_reg[0] ; output \adress[4]_0 ; output \g_ram_rst_false.ram_memory_reg ; output \g_ram_rst_false.ram_memory_reg_0 ; output \g_ram_rst_false.ram_memory_reg_1 ; output \g_ram_rst_false.ram_memory_reg_2 ; output \g_ram_rst_false.ram_memory_reg_3 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_ram_rst_false.ram_memory_reg_4 ; output \alc_alc_bit_reg[0] ; output \g_ram_rst_false.ram_memory_reg_5 ; output \g_ram_rst_false.ram_memory_reg_6 ; output \g_ram_rst_false.ram_memory_reg_7 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \adress[4]_1 ; output \frame_count_reg[3]_1 ; output [0:0]Q; output \g_ram_rst_false.ram_memory_reg_8 ; output \g_ram_rst_false.ram_memory_reg_9 ; output \g_ram_rst_false.ram_memory_reg_10 ; output \g_ram_rst_false.ram_memory_reg_11 ; output commit_overrun_abort; output \g_bit[0].reg_value_r_reg[0]_2 ; output [5:0]\FSM_onehot_curr_state_reg[8] ; output \FSM_onehot_curr_state_reg[1] ; output \FSM_onehot_curr_state_reg[8]_0 ; output \g_byte_shift_reg[1].shift_reg_q_reg[1][6] ; output \FSM_onehot_curr_state_reg[7] ; output \FSM_onehot_curr_state_reg[1]_0 ; output rx_data_overrun; input clk_sys_IBUF_BUFG; input [0:0]ADDRARDADDR; input [0:0]DIADI; input reg_q_reg; input \FSM_onehot_curr_state_reg[11] ; input [3:0]sbe_IBUF; input \r_data_reg[11] ; input \r_data_reg[11]_0 ; input [5:0]adress_IBUF; input \r_data_reg[11]_1 ; input \r_data_reg[26] ; input \r_data_reg[26]_0 ; input \r_data_reg[26]_1 ; input \r_data_reg[27] ; input \r_data_reg[27]_0 ; input \r_data_reg[28] ; input \r_data_reg[28]_0 ; input \r_data_reg[28]_1 ; input \r_data_reg[29] ; input \r_data_reg[29]_0 ; input \r_data_reg[30] ; input \r_data_reg[30]_0 ; input \r_data_reg[31] ; input \r_data_reg[31]_0 ; input \r_data_reg[0] ; input soft_res_d_n; input \r_data_reg[0]_0 ; input \r_data[0]_i_2 ; input \r_data_reg[1] ; input \r_data_reg[20] ; input \r_data_reg[20]_0 ; input \r_data_reg[24] ; input \r_data_reg[24]_0 ; input data_overrun_i_reg_0; input \r_data_reg[16] ; input [0:0]E; input \r_data_reg[1]_0 ; input \r_data_reg[1]_1 ; input \r_data_reg[1]_2 ; input \r_data[1]_i_2__0 ; input \r_data[3]_i_2 ; input \r_data_reg[20]_1 ; input [1:0]\r_data_reg[20]_2 ; input \r_data_reg[20]_3 ; input [0:0]\r_data_reg[20]_4 ; input \r_data_reg[24]_1 ; input \mr_ctrl_out[settings_pex] ; input \r_data_reg[26]_2 ; input \r_data_reg[27]_1 ; input \r_data[6]_i_2 ; input \r_data[7]_i_2__0 ; input \r_data[8]_i_2 ; input \r_data[9]_i_2__0 ; input \r_data[10]_i_2__0 ; input \r_data_reg[11]_2 ; input \r_data_reg[11]_3 ; input \r_data_reg[11]_4 ; input \r_data[11]_i_2__0 ; input \r_data_reg[16]_0 ; input \r_data[12]_i_2 ; input \r_data[13]_i_2 ; input \r_data_reg[14]_i_2 ; input \r_data[14]_i_5 ; input \r_data_reg[16]_1 ; input [1:0]\r_data[23]_i_2 ; input \r_data[4]_i_2 ; input \r_data[4]_i_2_0 ; input \r_data[0]_i_2_0 ; input \r_data[0]_i_2_1 ; input \r_data[5]_i_2 ; input \r_data[6]_i_4 ; input \mr_ctrl_out[rx_settings_rtsop] ; input ident_valid_q; input rec_abort; input \rx_mem_free_raw_reg[1] ; input [4:0]\mr_tst_out[tst_dest_tst_addr] ; input \g_ram_rst_false.ram_memory_reg_12 ; input [2:0]data_in_IBUF; input data_overrun_i_reg_1; input \mr_ctrl_out[mode_rxbam] ; input \mr_tst_out[tst_control_twrstb] ; input [30:0]\g_ram_rst_false.ram_memory_reg_13 ; input \g_ram_rst_false.ram_memory_reg_14 ; input \g_ram_rst_false.ram_memory_reg_15 ; input \g_ram_rst_false.ram_memory_reg_16 ; input \FSM_onehot_curr_state_reg[11]_0 ; input \g_ram_rst_false.ram_memory_reg_i_111 ; input \FSM_onehot_curr_state_reg[0] ; input \FSM_onehot_curr_state_reg[8]_1 ; input [31:0]store_data_word; input [3:0]\g_ram_rst_false.ram_memory_reg_17 ; input [28:0]\g_ram_rst_false.ram_memory_reg_18 ; input rec_is_rtr; input rec_ident_type; input rec_frame_type; input rec_brs; input rec_esi; input rec_ivld; input rec_lbpf; input [1:0]\g_ram_rst_false.ram_memory_reg_19 ; input [2:0]\g_ram_rst_false.ram_memory_reg_20 ; input [3:0]\g_ram_rst_false.ram_memory_reg_21 ; input \mr_ctrl_out[mode_erfm] ; input rec_abort_f; input \FSM_onehot_curr_state_reg[0]_0 ; input \cc_stat[err_erp] ; input store_metadata; input rec_is_rtr_i; input scan_mode_IBUF; input rst_n_out_OBUF; input rec_valid; input [2:0]\FSM_onehot_curr_state_reg[6] ; input [0:0]\timestamp_capture_reg[63]_0 ; input [63:0]timestamp_IBUF; wire [0:0]ADDRARDADDR; wire [10:0]D; wire [0:0]DIADI; wire [0:0]E; wire \FSM_onehot_curr_state_reg[0] ; wire \FSM_onehot_curr_state_reg[0]_0 ; wire \FSM_onehot_curr_state_reg[11] ; wire \FSM_onehot_curr_state_reg[11]_0 ; wire \FSM_onehot_curr_state_reg[1] ; wire \FSM_onehot_curr_state_reg[1]_0 ; wire [2:0]\FSM_onehot_curr_state_reg[6] ; wire \FSM_onehot_curr_state_reg[7] ; wire [5:0]\FSM_onehot_curr_state_reg[8] ; wire \FSM_onehot_curr_state_reg[8]_0 ; wire \FSM_onehot_curr_state_reg[8]_1 ; wire [0:0]Q; wire \adress[4] ; wire \adress[4]_0 ; wire \adress[4]_1 ; wire \adress[7] ; wire [5:0]adress_IBUF; wire \alc_alc_bit_reg[0] ; wire \cc_stat[err_erp] ; wire clk_sys_IBUF_BUFG; wire commit_overrun_abort; wire commit_rx_frame; wire [31:0]data4; wire [2:0]data_in_IBUF; wire data_overrun_i; wire data_overrun_i_reg_0; wire data_overrun_i_reg_1; wire \frame_count[0]_i_1_n_0 ; wire \frame_count[1]_i_1_n_0 ; wire \frame_count[2]_i_1_n_0 ; wire \frame_count[3]_i_1_n_0 ; wire \frame_count[3]_i_2_n_0 ; wire \frame_count[3]_i_3_n_0 ; wire \frame_count_reg[3]_0 ; wire \frame_count_reg[3]_1 ; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_byte_shift_reg[1].shift_reg_q_reg[1][6] ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire \g_ram_rst_false.ram_memory_reg_10 ; wire \g_ram_rst_false.ram_memory_reg_11 ; wire \g_ram_rst_false.ram_memory_reg_12 ; wire [30:0]\g_ram_rst_false.ram_memory_reg_13 ; wire \g_ram_rst_false.ram_memory_reg_14 ; wire \g_ram_rst_false.ram_memory_reg_15 ; wire \g_ram_rst_false.ram_memory_reg_16 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_17 ; wire [28:0]\g_ram_rst_false.ram_memory_reg_18 ; wire [1:0]\g_ram_rst_false.ram_memory_reg_19 ; wire \g_ram_rst_false.ram_memory_reg_2 ; wire [2:0]\g_ram_rst_false.ram_memory_reg_20 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_21 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire \g_ram_rst_false.ram_memory_reg_7 ; wire \g_ram_rst_false.ram_memory_reg_8 ; wire \g_ram_rst_false.ram_memory_reg_9 ; wire \g_ram_rst_false.ram_memory_reg_i_111 ; wire i_rst_reg_n_0; wire i_rxb_fsm_n_0; wire i_rxb_fsm_n_1; wire i_rxb_fsm_n_4; wire i_rxb_fsm_n_48; wire i_rxb_fsm_n_49; wire i_rxb_fsm_n_50; wire i_rxb_fsm_n_51; wire i_rxb_fsm_n_52; wire i_rxb_pointers_n_25; wire i_rxb_ram_n_62; wire ident_valid_q; wire \mr_ctrl_out[mode_erfm] ; wire \mr_ctrl_out[mode_rxbam] ; wire \mr_ctrl_out[rx_settings_rtsop] ; wire \mr_ctrl_out[settings_pex] ; wire \mr_tst_out[tst_control_twrstb] ; wire [4:0]\mr_tst_out[tst_dest_tst_addr] ; wire \r_data[0]_i_2 ; wire \r_data[0]_i_2_0 ; wire \r_data[0]_i_2_1 ; wire \r_data[0]_i_4_n_0 ; wire \r_data[10]_i_2__0 ; wire \r_data[11]_i_2__0 ; wire \r_data[12]_i_2 ; wire \r_data[13]_i_2 ; wire \r_data[14]_i_5 ; wire \r_data[1]_i_2__0 ; wire [1:0]\r_data[23]_i_2 ; wire \r_data[3]_i_2 ; wire \r_data[4]_i_2 ; wire \r_data[4]_i_2_0 ; wire \r_data[5]_i_2 ; wire \r_data[6]_i_2 ; wire \r_data[6]_i_4 ; wire \r_data[7]_i_2__0 ; wire \r_data[8]_i_2 ; wire \r_data[9]_i_2__0 ; wire \r_data_reg[0] ; wire \r_data_reg[0]_0 ; wire \r_data_reg[11] ; wire \r_data_reg[11]_0 ; wire \r_data_reg[11]_1 ; wire \r_data_reg[11]_2 ; wire \r_data_reg[11]_3 ; wire \r_data_reg[11]_4 ; wire \r_data_reg[14]_i_2 ; wire \r_data_reg[16] ; wire \r_data_reg[16]_0 ; wire \r_data_reg[16]_1 ; wire \r_data_reg[1] ; wire \r_data_reg[1]_0 ; wire \r_data_reg[1]_1 ; wire \r_data_reg[1]_2 ; wire \r_data_reg[20] ; wire \r_data_reg[20]_0 ; wire \r_data_reg[20]_1 ; wire [1:0]\r_data_reg[20]_2 ; wire \r_data_reg[20]_3 ; wire [0:0]\r_data_reg[20]_4 ; wire \r_data_reg[24] ; wire \r_data_reg[24]_0 ; wire \r_data_reg[24]_1 ; wire \r_data_reg[26] ; wire \r_data_reg[26]_0 ; wire \r_data_reg[26]_1 ; wire \r_data_reg[26]_2 ; wire \r_data_reg[27] ; wire \r_data_reg[27]_0 ; wire \r_data_reg[27]_1 ; wire \r_data_reg[28] ; wire \r_data_reg[28]_0 ; wire \r_data_reg[28]_1 ; wire \r_data_reg[29] ; wire \r_data_reg[29]_0 ; wire \r_data_reg[30] ; wire \r_data_reg[30]_0 ; wire \r_data_reg[31] ; wire \r_data_reg[31]_0 ; wire [4:1]read_counter_d; wire [4:0]read_counter_q_reg; wire read_increment; wire rec_abort; wire rec_abort_f; wire rec_brs; wire rec_esi; wire rec_frame_type; wire rec_ident_type; wire rec_is_rtr; wire rec_is_rtr_i; wire rec_ivld; wire rec_lbpf; wire rec_valid; wire reg_q_reg; wire rst_n_out_OBUF; wire rx_data_overrun; wire [3:0]rx_frame_count; wire rx_full; wire [5:5]rx_mem_free; wire \rx_mem_free_raw_reg[1] ; wire rx_mof; wire [4:0]rx_write_pointer; wire [4:0]rxb_port_a_address_i; wire [31:0]rxb_port_a_data_in_i; wire rxb_port_a_write_i; wire [4:1]rxb_port_b_address_i; wire [16:16]rxb_port_b_data_out; wire [31:0]rxb_port_b_data_out_i; wire [3:0]sbe_IBUF; wire scan_mode_IBUF; wire soft_res_d_n; wire [31:0]store_data_word; wire store_metadata; wire store_ts_wr_ptr; wire [63:0]timestamp_IBUF; wire [0:0]\timestamp_capture_reg[63]_0 ; wire \timestamp_capture_reg_n_0_[0] ; wire \timestamp_capture_reg_n_0_[10] ; wire \timestamp_capture_reg_n_0_[11] ; wire \timestamp_capture_reg_n_0_[12] ; wire \timestamp_capture_reg_n_0_[13] ; wire \timestamp_capture_reg_n_0_[14] ; wire \timestamp_capture_reg_n_0_[15] ; wire \timestamp_capture_reg_n_0_[16] ; wire \timestamp_capture_reg_n_0_[17] ; wire \timestamp_capture_reg_n_0_[18] ; wire \timestamp_capture_reg_n_0_[19] ; wire \timestamp_capture_reg_n_0_[1] ; wire \timestamp_capture_reg_n_0_[20] ; wire \timestamp_capture_reg_n_0_[21] ; wire \timestamp_capture_reg_n_0_[22] ; wire \timestamp_capture_reg_n_0_[23] ; wire \timestamp_capture_reg_n_0_[24] ; wire \timestamp_capture_reg_n_0_[25] ; wire \timestamp_capture_reg_n_0_[26] ; wire \timestamp_capture_reg_n_0_[27] ; wire \timestamp_capture_reg_n_0_[28] ; wire \timestamp_capture_reg_n_0_[29] ; wire \timestamp_capture_reg_n_0_[2] ; wire \timestamp_capture_reg_n_0_[30] ; wire \timestamp_capture_reg_n_0_[31] ; wire \timestamp_capture_reg_n_0_[3] ; wire \timestamp_capture_reg_n_0_[4] ; wire \timestamp_capture_reg_n_0_[5] ; wire \timestamp_capture_reg_n_0_[6] ; wire \timestamp_capture_reg_n_0_[7] ; wire \timestamp_capture_reg_n_0_[8] ; wire \timestamp_capture_reg_n_0_[9] ; wire write_pointer_ts_ce; FDCE commit_overrun_abort_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rst_reg_n_0), .D(i_rxb_fsm_n_52), .Q(commit_overrun_abort)); FDCE commit_rx_frame_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rst_reg_n_0), .D(i_rxb_fsm_n_50), .Q(commit_rx_frame)); FDCE data_overrun_flg_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(i_rst_reg_n_0), .D(i_rxb_fsm_n_51), .Q(rx_data_overrun)); FDCE data_overrun_i_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(i_rxb_fsm_n_49), .Q(data_overrun_i)); LUT1 #( .INIT(2'h1)) \frame_count[0]_i_1 (.I0(rx_frame_count[0]), .O(\frame_count[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair341" *) LUT3 #( .INIT(8'h69)) \frame_count[1]_i_1 (.I0(rx_frame_count[0]), .I1(\frame_count[3]_i_3_n_0 ), .I2(rx_frame_count[1]), .O(\frame_count[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair341" *) LUT4 #( .INIT(16'h78E1)) \frame_count[2]_i_1 (.I0(\frame_count[3]_i_3_n_0 ), .I1(rx_frame_count[0]), .I2(rx_frame_count[2]), .I3(rx_frame_count[1]), .O(\frame_count[2]_i_1_n_0 )); LUT2 #( .INIT(4'h9)) \frame_count[3]_i_1 (.I0(commit_rx_frame), .I1(\frame_count[3]_i_3_n_0 ), .O(\frame_count[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair340" *) LUT5 #( .INIT(32'h6AAAAAA9)) \frame_count[3]_i_2 (.I0(rx_frame_count[3]), .I1(rx_frame_count[1]), .I2(rx_frame_count[2]), .I3(rx_frame_count[0]), .I4(\frame_count[3]_i_3_n_0 ), .O(\frame_count[3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \frame_count[3]_i_3 (.I0(\g_bit[0].reg_value_r_reg[0]_2 ), .I1(read_counter_q_reg[3]), .I2(read_counter_q_reg[4]), .I3(read_counter_q_reg[2]), .I4(read_counter_q_reg[1]), .I5(read_counter_q_reg[0]), .O(\frame_count[3]_i_3_n_0 )); FDCE \frame_count_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\frame_count[3]_i_1_n_0 ), .CLR(i_rst_reg_n_0), .D(\frame_count[0]_i_1_n_0 ), .Q(rx_frame_count[0])); FDCE \frame_count_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\frame_count[3]_i_1_n_0 ), .CLR(i_rst_reg_n_0), .D(\frame_count[1]_i_1_n_0 ), .Q(rx_frame_count[1])); FDCE \frame_count_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\frame_count[3]_i_1_n_0 ), .CLR(i_rst_reg_n_0), .D(\frame_count[2]_i_1_n_0 ), .Q(rx_frame_count[2])); FDCE \frame_count_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\frame_count[3]_i_1_n_0 ), .CLR(i_rst_reg_n_0), .D(\frame_count[3]_i_2_n_0 ), .Q(rx_frame_count[3])); rst_reg i_rst_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .reg_q_reg(i_rst_reg_n_0), .reg_q_reg_0(reg_q_reg), .reg_q_reg_1(\FSM_onehot_curr_state_reg[11] ), .rst_n_out_OBUF(rst_n_out_OBUF), .scan_mode_IBUF(scan_mode_IBUF)); rxb_fsm i_rxb_fsm (.E(i_rxb_fsm_n_0), .\FSM_onehot_curr_state_reg[0]_0 (i_rxb_fsm_n_49), .\FSM_onehot_curr_state_reg[0]_1 (\FSM_onehot_curr_state_reg[0] ), .\FSM_onehot_curr_state_reg[0]_2 (\FSM_onehot_curr_state_reg[0]_0 ), .\FSM_onehot_curr_state_reg[11]_0 (i_rxb_fsm_n_50), .\FSM_onehot_curr_state_reg[11]_1 (\FSM_onehot_curr_state_reg[11]_0 ), .\FSM_onehot_curr_state_reg[11]_2 (\FSM_onehot_curr_state_reg[11] ), .\FSM_onehot_curr_state_reg[1]_0 (\FSM_onehot_curr_state_reg[1] ), .\FSM_onehot_curr_state_reg[1]_1 (\FSM_onehot_curr_state_reg[1]_0 ), .\FSM_onehot_curr_state_reg[6]_0 (write_pointer_ts_ce), .\FSM_onehot_curr_state_reg[6]_1 (\FSM_onehot_curr_state_reg[6] ), .\FSM_onehot_curr_state_reg[7]_0 (\FSM_onehot_curr_state_reg[7] ), .\FSM_onehot_curr_state_reg[8]_0 (\FSM_onehot_curr_state_reg[8]_0 ), .\FSM_onehot_curr_state_reg[8]_1 (\FSM_onehot_curr_state_reg[8]_1 ), .Q({\FSM_onehot_curr_state_reg[8] [5],i_rxb_fsm_n_4,\FSM_onehot_curr_state_reg[8] [4:3],store_ts_wr_ptr,\FSM_onehot_curr_state_reg[8] [2:0]}), .WEBWE(rxb_port_a_write_i), .\cc_stat[err_erp] (\cc_stat[err_erp] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .commit_overrun_abort_reg(i_rxb_fsm_n_48), .commit_rx_frame(commit_rx_frame), .data_in_IBUF(data_in_IBUF[2:1]), .data_overrun_flg_reg(i_rxb_fsm_n_51), .data_overrun_i(data_overrun_i), .data_overrun_i_reg(i_rxb_fsm_n_1), .data_overrun_i_reg_0(i_rxb_fsm_n_52), .data_overrun_i_reg_1(i_rxb_pointers_n_25), .data_overrun_i_reg_2(data_overrun_i_reg_1), .data_overrun_i_reg_3(\adress[7] ), .\g_byte_shift_reg[1].shift_reg_q_reg[1][6] (\g_byte_shift_reg[1].shift_reg_q_reg[1][6] ), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg_12 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg_13 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_14 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_15 ), .\g_ram_rst_false.ram_memory_reg_3 (\g_ram_rst_false.ram_memory_reg_16 ), .\g_ram_rst_false.ram_memory_reg_4 ({data4,\timestamp_capture_reg_n_0_[31] ,\timestamp_capture_reg_n_0_[30] ,\timestamp_capture_reg_n_0_[29] ,\timestamp_capture_reg_n_0_[28] ,\timestamp_capture_reg_n_0_[27] ,\timestamp_capture_reg_n_0_[26] ,\timestamp_capture_reg_n_0_[25] ,\timestamp_capture_reg_n_0_[24] ,\timestamp_capture_reg_n_0_[23] ,\timestamp_capture_reg_n_0_[22] ,\timestamp_capture_reg_n_0_[21] ,\timestamp_capture_reg_n_0_[20] ,\timestamp_capture_reg_n_0_[19] ,\timestamp_capture_reg_n_0_[18] ,\timestamp_capture_reg_n_0_[17] ,\timestamp_capture_reg_n_0_[16] ,\timestamp_capture_reg_n_0_[15] ,\timestamp_capture_reg_n_0_[14] ,\timestamp_capture_reg_n_0_[13] ,\timestamp_capture_reg_n_0_[12] ,\timestamp_capture_reg_n_0_[11] ,\timestamp_capture_reg_n_0_[10] ,\timestamp_capture_reg_n_0_[9] ,\timestamp_capture_reg_n_0_[8] ,\timestamp_capture_reg_n_0_[7] ,\timestamp_capture_reg_n_0_[6] ,\timestamp_capture_reg_n_0_[5] ,\timestamp_capture_reg_n_0_[4] ,\timestamp_capture_reg_n_0_[3] ,\timestamp_capture_reg_n_0_[2] ,\timestamp_capture_reg_n_0_[1] ,\timestamp_capture_reg_n_0_[0] }), .\g_ram_rst_false.ram_memory_reg_5 (\g_ram_rst_false.ram_memory_reg_17 ), .\g_ram_rst_false.ram_memory_reg_6 (\g_ram_rst_false.ram_memory_reg_18 ), .\g_ram_rst_false.ram_memory_reg_7 (\g_ram_rst_false.ram_memory_reg_19 ), .\g_ram_rst_false.ram_memory_reg_8 (\g_ram_rst_false.ram_memory_reg_20 ), .\g_ram_rst_false.ram_memory_reg_9 (\g_ram_rst_false.ram_memory_reg_21 ), .\g_ram_rst_false.ram_memory_reg_i_111_0 (\g_ram_rst_false.ram_memory_reg_i_111 ), .ident_valid_q(ident_valid_q), .\mr_ctrl_out[mode_erfm] (\mr_ctrl_out[mode_erfm] ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .rec_abort(rec_abort), .rec_abort_f(rec_abort_f), .rec_brs(rec_brs), .rec_esi(rec_esi), .rec_frame_type(rec_frame_type), .rec_ident_type(rec_ident_type), .rec_is_rtr(rec_is_rtr), .rec_is_rtr_i(rec_is_rtr_i), .rec_ivld(rec_ivld), .rec_lbpf(rec_lbpf), .rec_valid(rec_valid), .rx_data_overrun(rx_data_overrun), .\rx_mem_free_raw_reg[5] (\g_bit[0].reg_value_r_reg[0]_2 ), .rxb_port_a_data_in_i({rxb_port_a_data_in_i[31:15],rxb_port_a_data_in_i[13:0]}), .store_data_word(store_data_word), .store_metadata(store_metadata), .\write_pointer_raw_i_reg[0] (commit_overrun_abort)); rxb_pointers i_rxb_pointers (.ADDRARDADDR(rxb_port_b_address_i), .ADDRBWRADDR(rxb_port_a_address_i), .D({D[3],D[1]}), .E(E), .Q({rx_write_pointer[4],rx_write_pointer[2],rx_write_pointer[0]}), .\adress[4] (\adress[4] ), .\adress[7] (\adress[7] ), .adress_IBUF(adress_IBUF), .\alc_alc_bit_reg[0] (\alc_alc_bit_reg[0] ), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .commit_overrun_abort(commit_overrun_abort), .commit_rx_frame(commit_rx_frame), .data_in_IBUF(data_in_IBUF[0]), .data_overrun_i_reg(data_overrun_i_reg_0), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0]_2 ), .\g_bit[0].reg_value_r_reg[0]_0 (read_increment), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg_8 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg_9 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_10 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_12 ), .\g_ram_rst_false.ram_memory_reg_3 ({i_rxb_fsm_n_4,\FSM_onehot_curr_state_reg[8] [4],store_ts_wr_ptr}), .ident_valid_q(ident_valid_q), .\mr_ctrl_out[mode_rxbam] (\mr_ctrl_out[mode_rxbam] ), .\mr_ctrl_out[rx_settings_rtsop] (\mr_ctrl_out[rx_settings_rtsop] ), .\mr_tst_out[tst_dest_tst_addr] (\mr_tst_out[tst_dest_tst_addr] ), .\r_data[1]_i_2__0_0 (\r_data[1]_i_2__0 ), .\r_data[3]_i_2 (\r_data[3]_i_2 ), .\r_data_reg[16] (\r_data_reg[16] ), .\r_data_reg[16]_0 (\r_data_reg[16]_1 ), .\r_data_reg[16]_1 (\r_data_reg[16]_0 ), .\r_data_reg[18] (\frame_count_reg[3]_0 ), .\r_data_reg[1] (\r_data_reg[1] ), .\r_data_reg[1]_0 (\r_data_reg[1]_0 ), .\r_data_reg[1]_1 (\r_data_reg[1]_1 ), .\r_data_reg[1]_2 (\r_data_reg[1]_2 ), .\r_data_reg[20] (\r_data_reg[20] ), .\r_data_reg[20]_0 (\r_data_reg[20]_0 ), .\r_data_reg[20]_1 (\r_data_reg[11] ), .\r_data_reg[20]_2 (\r_data_reg[20]_1 ), .\r_data_reg[20]_3 (\r_data_reg[20]_2 ), .\r_data_reg[20]_4 (\r_data_reg[20]_3 ), .\r_data_reg[20]_5 (\r_data_reg[20]_4 ), .\r_data_reg[20]_6 (\r_data_reg[24]_1 ), .\read_pointer_i_reg[0]_0 (Q), .rec_abort(rec_abort), .rx_full(rx_full), .\rx_mem_free_i_i_reg[0]_0 (data_overrun_i_reg_1), .\rx_mem_free_i_i_reg[5]_0 (rx_mem_free), .\rx_mem_free_i_i_reg[5]_1 (i_rst_reg_n_0), .\rx_mem_free_raw_reg[1]_0 (\rx_mem_free_raw_reg[1] ), .\rx_mem_free_raw_reg[5]_0 (i_rxb_fsm_n_0), .rxb_port_b_data_out(rxb_port_b_data_out), .rxb_port_b_data_out_i({rxb_port_b_data_out_i[20:17],rxb_port_b_data_out_i[3],rxb_port_b_data_out_i[1]}), .sbe_IBUF(sbe_IBUF), .\write_pointer_raw_i_reg[0]_0 (i_rxb_fsm_n_48), .\write_pointer_raw_i_reg[4]_0 (i_rxb_pointers_n_25), .\write_pointer_raw_i_reg[4]_1 (i_rxb_fsm_n_1), .\write_pointer_ts_i_reg[4]_0 (write_pointer_ts_ce)); rxb_ram i_rxb_ram (.ADDRARDADDR({rxb_port_b_address_i,ADDRARDADDR}), .ADDRBWRADDR(rxb_port_a_address_i), .D({D[10:4],D[2],D[0]}), .DIADI(DIADI), .Q(rx_frame_count), .WEBWE(rxb_port_a_write_i), .\adress[4] (\adress[4]_0 ), .\adress[4]_0 (\adress[4]_1 ), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\frame_count_reg[3] (\frame_count_reg[3]_1 ), .\g_bit[0].reg_value_r_reg[0] (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_1 ), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg_0 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_ram_rst_false.ram_memory_reg_1 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_2 ), .\g_ram_rst_false.ram_memory_reg_3 (\g_ram_rst_false.ram_memory_reg_3 ), .\g_ram_rst_false.ram_memory_reg_4 (\g_ram_rst_false.ram_memory_reg_4 ), .\g_ram_rst_false.ram_memory_reg_5 (\g_ram_rst_false.ram_memory_reg_5 ), .\g_ram_rst_false.ram_memory_reg_6 (\g_ram_rst_false.ram_memory_reg_6 ), .\g_ram_rst_false.ram_memory_reg_7 (\g_ram_rst_false.ram_memory_reg_7 ), .\g_ram_rst_false.ram_memory_reg_8 (\g_ram_rst_false.ram_memory_reg_11 ), .\g_ram_rst_false.ram_memory_reg_9 ({read_counter_d,i_rxb_ram_n_62}), .\mr_ctrl_out[settings_pex] (\mr_ctrl_out[settings_pex] ), .\r_data[0]_i_2 (\r_data_reg[16]_0 ), .\r_data[0]_i_2_0 (\r_data[0]_i_2_0 ), .\r_data[0]_i_2_1 (\r_data[0]_i_2_1 ), .\r_data[10]_i_2__0 (\r_data[10]_i_2__0 ), .\r_data[11]_i_2__0 (\r_data[11]_i_2__0 ), .\r_data[12]_i_2 (\r_data[12]_i_2 ), .\r_data[13]_i_2 (\r_data[13]_i_2 ), .\r_data[14]_i_5 (\r_data[14]_i_5 ), .\r_data[15]_i_6 (\r_data_reg[16] ), .\r_data[21]_i_2 (\r_data_reg[20]_1 ), .\r_data[21]_i_2_0 (rx_mem_free), .\r_data[23]_i_2 (\r_data[23]_i_2 ), .\r_data[4]_i_2 (\r_data[4]_i_2 ), .\r_data[4]_i_2_0 (\r_data[4]_i_2_0 ), .\r_data[4]_i_5 ({rx_write_pointer[4],rx_write_pointer[2],rx_write_pointer[0]}), .\r_data[5]_i_2 (\r_data[5]_i_2 ), .\r_data[6]_i_2 (\r_data[6]_i_2 ), .\r_data[6]_i_4 (\r_data[6]_i_4 ), .\r_data[7]_i_2__0 (\r_data[7]_i_2__0 ), .\r_data[8]_i_2 (\r_data[8]_i_2 ), .\r_data[9]_i_2__0 (\r_data[9]_i_2__0 ), .\r_data_reg[0] (\r_data_reg[0] ), .\r_data_reg[0]_0 (\r_data[0]_i_4_n_0 ), .\r_data_reg[0]_1 (\r_data_reg[0]_0 ), .\r_data_reg[11] (\r_data_reg[11] ), .\r_data_reg[11]_0 (\r_data_reg[11]_0 ), .\r_data_reg[11]_1 (\r_data_reg[11]_1 ), .\r_data_reg[11]_2 (\r_data_reg[11]_2 ), .\r_data_reg[11]_3 (\r_data_reg[11]_3 ), .\r_data_reg[11]_4 (\r_data_reg[11]_4 ), .\r_data_reg[14]_i_2 (\r_data_reg[14]_i_2 ), .\r_data_reg[24] (\r_data_reg[24] ), .\r_data_reg[24]_0 (\r_data_reg[24]_0 ), .\r_data_reg[24]_1 (\r_data_reg[24]_1 ), .\r_data_reg[26] (\r_data_reg[26] ), .\r_data_reg[26]_0 (\r_data_reg[26]_0 ), .\r_data_reg[26]_1 (\r_data_reg[26]_1 ), .\r_data_reg[26]_2 (\r_data_reg[26]_2 ), .\r_data_reg[27] (\r_data_reg[27] ), .\r_data_reg[27]_0 (\r_data_reg[27]_0 ), .\r_data_reg[27]_1 (\r_data_reg[27]_1 ), .\r_data_reg[28] (\r_data_reg[28] ), .\r_data_reg[28]_0 (\r_data_reg[28]_0 ), .\r_data_reg[28]_1 (\r_data_reg[28]_1 ), .\r_data_reg[28]_2 (\frame_count_reg[3]_0 ), .\r_data_reg[29] (\r_data_reg[29] ), .\r_data_reg[29]_0 (\r_data_reg[29]_0 ), .\r_data_reg[30] (\r_data_reg[30] ), .\r_data_reg[30]_0 (\r_data_reg[30]_0 ), .\r_data_reg[31] (\r_data_reg[31] ), .\r_data_reg[31]_0 (\r_data_reg[31]_0 ), .\read_counter_q_reg[0] (read_counter_q_reg), .rx_mof(rx_mof), .rxb_port_a_data_in_i({rxb_port_a_data_in_i[31:15],rxb_port_a_data_in_i[13:0]}), .rxb_port_b_data_out(rxb_port_b_data_out), .rxb_port_b_data_out_i(rxb_port_b_data_out_i), .sbe_IBUF({sbe_IBUF[3],sbe_IBUF[1:0]}), .soft_res_d_n(soft_res_d_n)); (* SOFT_HLUTNM = "soft_lutpair340" *) LUT4 #( .INIT(16'h0001)) int_status_i_2__5 (.I0(rx_frame_count[3]), .I1(rx_frame_count[1]), .I2(rx_frame_count[2]), .I3(rx_frame_count[0]), .O(\frame_count_reg[3]_0 )); LUT6 #( .INIT(64'hFEFEFEFAAAAAAAAA)) \r_data[0]_i_4 (.I0(\r_data_reg[11] ), .I1(adress_IBUF[1]), .I2(adress_IBUF[2]), .I3(adress_IBUF[0]), .I4(\frame_count_reg[3]_0 ), .I5(\r_data[0]_i_2 ), .O(\r_data[0]_i_4_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \r_data[2]_i_15 (.I0(read_counter_q_reg[4]), .I1(read_counter_q_reg[2]), .I2(read_counter_q_reg[1]), .I3(read_counter_q_reg[0]), .I4(read_counter_q_reg[3]), .O(rx_mof)); FDCE \read_counter_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(read_increment), .CLR(i_rst_reg_n_0), .D(i_rxb_ram_n_62), .Q(read_counter_q_reg[0])); FDCE \read_counter_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(read_increment), .CLR(i_rst_reg_n_0), .D(read_counter_d[1]), .Q(read_counter_q_reg[1])); FDCE \read_counter_q_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(read_increment), .CLR(i_rst_reg_n_0), .D(read_counter_d[2]), .Q(read_counter_q_reg[2])); FDCE \read_counter_q_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(read_increment), .CLR(i_rst_reg_n_0), .D(read_counter_d[3]), .Q(read_counter_q_reg[3])); FDCE \read_counter_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(read_increment), .CLR(i_rst_reg_n_0), .D(read_counter_d[4]), .Q(read_counter_q_reg[4])); FDCE \timestamp_capture_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[0]), .Q(\timestamp_capture_reg_n_0_[0] )); FDCE \timestamp_capture_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[10]), .Q(\timestamp_capture_reg_n_0_[10] )); FDCE \timestamp_capture_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[11]), .Q(\timestamp_capture_reg_n_0_[11] )); FDCE \timestamp_capture_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[12]), .Q(\timestamp_capture_reg_n_0_[12] )); FDCE \timestamp_capture_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[13]), .Q(\timestamp_capture_reg_n_0_[13] )); FDCE \timestamp_capture_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[14]), .Q(\timestamp_capture_reg_n_0_[14] )); FDCE \timestamp_capture_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[15]), .Q(\timestamp_capture_reg_n_0_[15] )); FDCE \timestamp_capture_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[16]), .Q(\timestamp_capture_reg_n_0_[16] )); FDCE \timestamp_capture_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[17]), .Q(\timestamp_capture_reg_n_0_[17] )); FDCE \timestamp_capture_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[18]), .Q(\timestamp_capture_reg_n_0_[18] )); FDCE \timestamp_capture_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[19]), .Q(\timestamp_capture_reg_n_0_[19] )); FDCE \timestamp_capture_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[1]), .Q(\timestamp_capture_reg_n_0_[1] )); FDCE \timestamp_capture_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[20]), .Q(\timestamp_capture_reg_n_0_[20] )); FDCE \timestamp_capture_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[21]), .Q(\timestamp_capture_reg_n_0_[21] )); FDCE \timestamp_capture_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[22]), .Q(\timestamp_capture_reg_n_0_[22] )); FDCE \timestamp_capture_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[23]), .Q(\timestamp_capture_reg_n_0_[23] )); FDCE \timestamp_capture_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[24]), .Q(\timestamp_capture_reg_n_0_[24] )); FDCE \timestamp_capture_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[25]), .Q(\timestamp_capture_reg_n_0_[25] )); FDCE \timestamp_capture_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[26]), .Q(\timestamp_capture_reg_n_0_[26] )); FDCE \timestamp_capture_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[27]), .Q(\timestamp_capture_reg_n_0_[27] )); FDCE \timestamp_capture_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[28]), .Q(\timestamp_capture_reg_n_0_[28] )); FDCE \timestamp_capture_reg[29] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[29]), .Q(\timestamp_capture_reg_n_0_[29] )); FDCE \timestamp_capture_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[2]), .Q(\timestamp_capture_reg_n_0_[2] )); FDCE \timestamp_capture_reg[30] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[30]), .Q(\timestamp_capture_reg_n_0_[30] )); FDCE \timestamp_capture_reg[31] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[31]), .Q(\timestamp_capture_reg_n_0_[31] )); FDCE \timestamp_capture_reg[32] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[32]), .Q(data4[0])); FDCE \timestamp_capture_reg[33] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[33]), .Q(data4[1])); FDCE \timestamp_capture_reg[34] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[34]), .Q(data4[2])); FDCE \timestamp_capture_reg[35] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[35]), .Q(data4[3])); FDCE \timestamp_capture_reg[36] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[36]), .Q(data4[4])); FDCE \timestamp_capture_reg[37] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[37]), .Q(data4[5])); FDCE \timestamp_capture_reg[38] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[38]), .Q(data4[6])); FDCE \timestamp_capture_reg[39] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[39]), .Q(data4[7])); FDCE \timestamp_capture_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[3]), .Q(\timestamp_capture_reg_n_0_[3] )); FDCE \timestamp_capture_reg[40] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[40]), .Q(data4[8])); FDCE \timestamp_capture_reg[41] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[41]), .Q(data4[9])); FDCE \timestamp_capture_reg[42] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[42]), .Q(data4[10])); FDCE \timestamp_capture_reg[43] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[43]), .Q(data4[11])); FDCE \timestamp_capture_reg[44] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[44]), .Q(data4[12])); FDCE \timestamp_capture_reg[45] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[45]), .Q(data4[13])); FDCE \timestamp_capture_reg[46] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[46]), .Q(data4[14])); FDCE \timestamp_capture_reg[47] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[47]), .Q(data4[15])); FDCE \timestamp_capture_reg[48] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[48]), .Q(data4[16])); FDCE \timestamp_capture_reg[49] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[49]), .Q(data4[17])); FDCE \timestamp_capture_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[4]), .Q(\timestamp_capture_reg_n_0_[4] )); FDCE \timestamp_capture_reg[50] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[50]), .Q(data4[18])); FDCE \timestamp_capture_reg[51] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[51]), .Q(data4[19])); FDCE \timestamp_capture_reg[52] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[52]), .Q(data4[20])); FDCE \timestamp_capture_reg[53] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[53]), .Q(data4[21])); FDCE \timestamp_capture_reg[54] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[54]), .Q(data4[22])); FDCE \timestamp_capture_reg[55] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[55]), .Q(data4[23])); FDCE \timestamp_capture_reg[56] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[56]), .Q(data4[24])); FDCE \timestamp_capture_reg[57] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[57]), .Q(data4[25])); FDCE \timestamp_capture_reg[58] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[58]), .Q(data4[26])); FDCE \timestamp_capture_reg[59] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[59]), .Q(data4[27])); FDCE \timestamp_capture_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[5]), .Q(\timestamp_capture_reg_n_0_[5] )); FDCE \timestamp_capture_reg[60] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[60]), .Q(data4[28])); FDCE \timestamp_capture_reg[61] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[61]), .Q(data4[29])); FDCE \timestamp_capture_reg[62] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[62]), .Q(data4[30])); FDCE \timestamp_capture_reg[63] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[63]), .Q(data4[31])); FDCE \timestamp_capture_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[6]), .Q(\timestamp_capture_reg_n_0_[6] )); FDCE \timestamp_capture_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[7]), .Q(\timestamp_capture_reg_n_0_[7] )); FDCE \timestamp_capture_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[8]), .Q(\timestamp_capture_reg_n_0_[8] )); FDCE \timestamp_capture_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(\timestamp_capture_reg[63]_0 ), .CLR(\FSM_onehot_curr_state_reg[11] ), .D(timestamp_IBUF[9]), .Q(\timestamp_capture_reg_n_0_[9] )); endmodule module shift_reg_byte (\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 , D, reg_q_reg, \FSM_sequential_curr_state_reg[1] , \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 , \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 , \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_1 , S, \g_byte_shift_reg[1].shift_reg_q_reg[1][6]_0 , \g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 , store_data_word, \g_byte_shift_reg[0].shift_reg_q_reg[0][5]_0 , \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_2 , reg_q_reg_0, \cc_stat[is_receiver] , \g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 , rec_is_rtr, \ctrl_ctr_q_reg[8] , \ctrl_ctr_q_reg[5] , \ctrl_ctr_q_reg[8]_0 , \ctrl_ctr_q_reg[8]_1 , \ctrl_ctr_q_reg[5]_0 , \ctrl_ctr_q_reg[5]_1 , \ctrl_ctr_q_reg[5]_2 , \ctrl_ctr_q_reg[5]_3 , crc_match_c6_carry__0, crc_match_c5_carry__0, \crc_match_c6_inferred__0/i__carry , \ctrl_ctr_q_reg[8]_2 , \ctrl_ctr_q_reg[8]_3 , \ctrl_ctr_q_reg[8]_4 , rx_shift_cmd, clk_sys_IBUF_BUFG, \g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 , \g_byte_shift_reg[1].shift_reg_q_reg[1][0]_0 , \g_byte_shift_reg[2].shift_reg_q_reg[2][0]_1 , \g_byte_shift_reg[3].shift_reg_q_reg[3][0]_1 ); output \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 ; output [16:0]D; output reg_q_reg; output \FSM_sequential_curr_state_reg[1] ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_1 ; output [0:0]S; output [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][6]_0 ; output [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 ; output [14:0]store_data_word; output [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][5]_0 ; output \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_2 ; output [0:0]reg_q_reg_0; input \cc_stat[is_receiver] ; input [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ; input rec_is_rtr; input \ctrl_ctr_q_reg[8] ; input \ctrl_ctr_q_reg[5] ; input \ctrl_ctr_q_reg[8]_0 ; input \ctrl_ctr_q_reg[8]_1 ; input \ctrl_ctr_q_reg[5]_0 ; input \ctrl_ctr_q_reg[5]_1 ; input [1:0]\ctrl_ctr_q_reg[5]_2 ; input \ctrl_ctr_q_reg[5]_3 ; input [5:0]crc_match_c6_carry__0; input [2:0]crc_match_c5_carry__0; input [2:0]\crc_match_c6_inferred__0/i__carry ; input \ctrl_ctr_q_reg[8]_2 ; input \ctrl_ctr_q_reg[8]_3 ; input \ctrl_ctr_q_reg[8]_4 ; input [3:0]rx_shift_cmd; input clk_sys_IBUF_BUFG; input \g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ; input [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][0]_0 ; input [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_1 ; input [0:0]\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_1 ; wire [16:0]D; wire \FSM_sequential_curr_state_reg[1] ; wire [0:0]S; wire \cc_stat[is_receiver] ; wire clk_sys_IBUF_BUFG; wire [2:0]crc_match_c5_carry__0; wire [5:0]crc_match_c6_carry__0; wire [2:0]\crc_match_c6_inferred__0/i__carry ; wire \ctrl_ctr_q[8]_i_10_n_0 ; wire \ctrl_ctr_q[8]_i_16_n_0 ; wire \ctrl_ctr_q_reg[5] ; wire \ctrl_ctr_q_reg[5]_0 ; wire \ctrl_ctr_q_reg[5]_1 ; wire [1:0]\ctrl_ctr_q_reg[5]_2 ; wire \ctrl_ctr_q_reg[5]_3 ; wire \ctrl_ctr_q_reg[8] ; wire \ctrl_ctr_q_reg[8]_0 ; wire \ctrl_ctr_q_reg[8]_1 ; wire \ctrl_ctr_q_reg[8]_2 ; wire \ctrl_ctr_q_reg[8]_3 ; wire \ctrl_ctr_q_reg[8]_4 ; wire [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][1]_1 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 ; wire \g_byte_shift_reg[0].shift_reg_q_reg[0][2]_2 ; wire [0:0]\g_byte_shift_reg[0].shift_reg_q_reg[0][5]_0 ; wire [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][0]_0 ; wire [0:0]\g_byte_shift_reg[1].shift_reg_q_reg[1][6]_0 ; wire [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 ; wire [0:0]\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_1 ; wire \g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ; wire [0:0]\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_1 ; wire rec_is_rtr; wire reg_q_reg; wire [0:0]reg_q_reg_0; wire [3:0]rx_shift_cmd; wire [14:0]store_data_word; LUT6 #( .INIT(64'h9009000000009009)) crc_match_c5_carry__0_i_2 (.I0(D[6]), .I1(crc_match_c5_carry__0[1]), .I2(D[5]), .I3(crc_match_c5_carry__0[0]), .I4(crc_match_c5_carry__0[2]), .I5(store_data_word[0]), .O(\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_0 )); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c6_carry__0_i_2 (.I0(D[4]), .I1(crc_match_c6_carry__0[5]), .I2(D[2]), .I3(crc_match_c6_carry__0[3]), .I4(crc_match_c6_carry__0[4]), .I5(D[3]), .O(\g_byte_shift_reg[1].shift_reg_q_reg[1][6]_0 )); LUT6 #( .INIT(64'h9009000000009009)) crc_match_c6_carry_i_4 (.I0(D[8]), .I1(crc_match_c6_carry__0[1]), .I2(D[7]), .I3(crc_match_c6_carry__0[0]), .I4(crc_match_c6_carry__0[2]), .I5(D[9]), .O(S)); LUT6 #( .INIT(64'hB8BBBBBB8B8B8B8B)) \ctrl_ctr_q[5]_i_3 (.I0(\ctrl_ctr_q_reg[5]_0 ), .I1(\ctrl_ctr_q_reg[5] ), .I2(D[8]), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .I4(\ctrl_ctr_q_reg[5]_1 ), .I5(D[9]), .O(\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_1 )); LUT6 #( .INIT(64'h00000000FB0BFBFB)) \ctrl_ctr_q[5]_i_4 (.I0(D[9]), .I1(D[7]), .I2(\ctrl_ctr_q_reg[5] ), .I3(\ctrl_ctr_q_reg[5]_2 [1]), .I4(\ctrl_ctr_q_reg[5]_2 [0]), .I5(\ctrl_ctr_q_reg[5]_3 ), .O(\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 )); LUT2 #( .INIT(4'h8)) \ctrl_ctr_q[6]_i_4 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_1 ), .I1(\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_1 ), .O(\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 )); (* SOFT_HLUTNM = "soft_lutpair285" *) LUT5 #( .INIT(32'h02AA0AAA)) \ctrl_ctr_q[6]_i_6 (.I0(D[9]), .I1(D[8]), .I2(D[7]), .I3(\ctrl_ctr_q_reg[5]_1 ), .I4(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .O(\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_2 )); LUT6 #( .INIT(64'h88B8B88888888888)) \ctrl_ctr_q[8]_i_10 (.I0(\ctrl_ctr_q_reg[8] ), .I1(\ctrl_ctr_q_reg[5] ), .I2(D[8]), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .I4(D[7]), .I5(\ctrl_ctr_q[8]_i_16_n_0 ), .O(\ctrl_ctr_q[8]_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair285" *) LUT2 #( .INIT(4'h8)) \ctrl_ctr_q[8]_i_16 (.I0(\ctrl_ctr_q_reg[5]_1 ), .I1(D[9]), .O(\ctrl_ctr_q[8]_i_16_n_0 )); LUT6 #( .INIT(64'hF0DDF000F022F000)) \ctrl_ctr_q[8]_i_2 (.I0(\FSM_sequential_curr_state_reg[1] ), .I1(reg_q_reg), .I2(\ctrl_ctr_q_reg[8]_2 ), .I3(\ctrl_ctr_q_reg[8]_3 ), .I4(\ctrl_ctr_q_reg[8]_4 ), .I5(\ctrl_ctr_q[8]_i_10_n_0 ), .O(reg_q_reg_0)); LUT6 #( .INIT(64'hAAAAAAAA00000002)) \ctrl_ctr_q[8]_i_27 (.I0(\cc_stat[is_receiver] ), .I1(D[8]), .I2(D[9]), .I3(D[7]), .I4(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .I5(rec_is_rtr), .O(\g_byte_shift_reg[0].shift_reg_q_reg[0][1]_0 )); LUT2 #( .INIT(4'h2)) \ctrl_ctr_q[8]_i_6 (.I0(\g_byte_shift_reg[0].shift_reg_q_reg[0][2]_0 ), .I1(\ctrl_ctr_q_reg[8]_1 ), .O(\FSM_sequential_curr_state_reg[1] )); LUT6 #( .INIT(64'h88B8B8B888B88888)) \ctrl_ctr_q[8]_i_7 (.I0(\ctrl_ctr_q_reg[8]_0 ), .I1(\ctrl_ctr_q_reg[5] ), .I2(\ctrl_ctr_q[8]_i_16_n_0 ), .I3(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .I4(D[8]), .I5(D[7]), .O(reg_q_reg)); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][0] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(\g_byte_shift_reg[0].shift_reg_q_reg[0][0]_0 ), .Q(D[7])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][1] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[7]), .Q(D[8])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][2] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[8]), .Q(D[9])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][3] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[9]), .Q(D[10])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][4] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[10]), .Q(D[11])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][5] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[11]), .Q(D[12])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][6] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[12]), .Q(D[13])); FDCE \g_byte_shift_reg[0].shift_reg_q_reg[0][7] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[0]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[13]), .Q(D[14])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][0] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(\g_byte_shift_reg[1].shift_reg_q_reg[1][0]_0 ), .Q(D[15])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][1] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[15]), .Q(D[16])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][2] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[16]), .Q(D[0])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][3] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[0]), .Q(D[1])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][4] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[1]), .Q(D[2])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][5] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[2]), .Q(D[3])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][6] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[3]), .Q(D[4])); FDCE \g_byte_shift_reg[1].shift_reg_q_reg[1][7] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[1]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[4]), .Q(D[5])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][0] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(\g_byte_shift_reg[2].shift_reg_q_reg[2][0]_1 ), .Q(D[6])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][1] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(D[6]), .Q(store_data_word[0])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][2] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[0]), .Q(store_data_word[1])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][3] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[1]), .Q(store_data_word[2])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][4] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[2]), .Q(store_data_word[3])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][5] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[3]), .Q(store_data_word[4])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][6] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[4]), .Q(store_data_word[5])); FDCE \g_byte_shift_reg[2].shift_reg_q_reg[2][7] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[2]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[5]), .Q(store_data_word[6])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][0] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_1 ), .Q(store_data_word[7])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][1] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[7]), .Q(store_data_word[8])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][2] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[8]), .Q(store_data_word[9])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][3] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[9]), .Q(store_data_word[10])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][4] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[10]), .Q(store_data_word[11])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][5] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[11]), .Q(store_data_word[12])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][6] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[12]), .Q(store_data_word[13])); FDCE \g_byte_shift_reg[3].shift_reg_q_reg[3][7] (.C(clk_sys_IBUF_BUFG), .CE(rx_shift_cmd[3]), .CLR(\g_byte_shift_reg[3].shift_reg_q_reg[3][0]_0 ), .D(store_data_word[13]), .Q(store_data_word[14])); LUT6 #( .INIT(64'h9009000000009009)) i__carry_i_3 (.I0(D[12]), .I1(\crc_match_c6_inferred__0/i__carry [2]), .I2(D[10]), .I3(\crc_match_c6_inferred__0/i__carry [0]), .I4(\crc_match_c6_inferred__0/i__carry [1]), .I5(D[11]), .O(\g_byte_shift_reg[0].shift_reg_q_reg[0][5]_0 )); endmodule module shift_reg_preload (Q, E, D, clk_sys_IBUF_BUFG, \shift_regs_reg[0]_0 ); output [31:0]Q; input [0:0]E; input [31:0]D; input clk_sys_IBUF_BUFG; input \shift_regs_reg[0]_0 ; wire [31:0]D; wire [0:0]E; wire [31:0]Q; wire clk_sys_IBUF_BUFG; wire \shift_regs_reg[0]_0 ; FDCE \shift_regs_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[0]), .Q(Q[0])); FDCE \shift_regs_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[10]), .Q(Q[10])); FDCE \shift_regs_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[11]), .Q(Q[11])); FDCE \shift_regs_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[12]), .Q(Q[12])); FDCE \shift_regs_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[13]), .Q(Q[13])); FDCE \shift_regs_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[14]), .Q(Q[14])); FDCE \shift_regs_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[15]), .Q(Q[15])); FDCE \shift_regs_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[16]), .Q(Q[16])); FDCE \shift_regs_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[17]), .Q(Q[17])); FDCE \shift_regs_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[18]), .Q(Q[18])); FDCE \shift_regs_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[19]), .Q(Q[19])); FDCE \shift_regs_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[1]), .Q(Q[1])); FDCE \shift_regs_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[20]), .Q(Q[20])); FDCE \shift_regs_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[21]), .Q(Q[21])); FDCE \shift_regs_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[22]), .Q(Q[22])); FDCE \shift_regs_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[23]), .Q(Q[23])); FDCE \shift_regs_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[24]), .Q(Q[24])); FDCE \shift_regs_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[25]), .Q(Q[25])); FDCE \shift_regs_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[26]), .Q(Q[26])); FDCE \shift_regs_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[27]), .Q(Q[27])); FDCE \shift_regs_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[28]), .Q(Q[28])); FDCE \shift_regs_reg[29] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[29]), .Q(Q[29])); FDCE \shift_regs_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[2]), .Q(Q[2])); FDCE \shift_regs_reg[30] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[30]), .Q(Q[30])); FDCE \shift_regs_reg[31] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[31]), .Q(Q[31])); FDCE \shift_regs_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[3]), .Q(Q[3])); FDCE \shift_regs_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[4]), .Q(Q[4])); FDCE \shift_regs_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[5]), .Q(Q[5])); FDCE \shift_regs_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[6]), .Q(Q[6])); FDCE \shift_regs_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[7]), .Q(Q[7])); FDCE \shift_regs_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[8]), .Q(Q[8])); FDCE \shift_regs_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(E), .CLR(\shift_regs_reg[0]_0 ), .D(D[9]), .Q(Q[9])); endmodule module sig_sync (sync_reg_0, sync_edge3__0, can_rx_IBUF, clk_sys_IBUF_BUFG, rff_reg_0, rx_data_sync_prev); output sync_reg_0; output sync_edge3__0; input can_rx_IBUF; input clk_sys_IBUF_BUFG; input rff_reg_0; input rx_data_sync_prev; wire can_rx_IBUF; wire clk_sys_IBUF_BUFG; wire rff; wire rff_reg_0; wire rx_data_sync_prev; wire sync_edge3__0; wire sync_reg_0; LUT2 #( .INIT(4'h6)) \exp_seg_length_q[8]_i_8 (.I0(sync_reg_0), .I1(rx_data_sync_prev), .O(sync_edge3__0)); FDPE rff_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(can_rx_IBUF), .PRE(rff_reg_0), .Q(rff)); FDPE sync_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(rff), .PRE(rff_reg_0), .Q(sync_reg_0)); endmodule module test_registers_reg_map (\g_bit[0].reg_value_r_reg[0] , \g_bit[1].reg_value_r_reg[1] , \g_bit[2].reg_value_r_reg[2] , \g_bit[3].reg_value_r_reg[3] , \g_bit[4].reg_value_r_reg[4] , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[1].reg_value_r_reg[1]_0 , \g_bit[2].reg_value_r_reg[2]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[4].reg_value_r_reg[4]_0 , \g_bit[5].reg_value_r_reg[5] , \g_bit[6].reg_value_r_reg[6] , \g_bit[7].reg_value_r_reg[7] , \g_bit[0].reg_value_r_reg[0]_1 , \g_bit[1].reg_value_r_reg[1]_1 , \g_bit[2].reg_value_r_reg[2]_1 , \g_bit[3].reg_value_r_reg[3]_1 , \g_bit[4].reg_value_r_reg[4]_1 , \g_bit[5].reg_value_r_reg[5]_0 , \g_bit[7].reg_value_r_reg[7]_0 , \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[1].reg_value_r_reg[1]_2 , \g_bit[2].reg_value_r_reg[2]_2 , \g_bit[3].reg_value_r_reg[3]_2 , \g_bit[4].reg_value_r_reg[4]_2 , \g_bit[5].reg_value_r_reg[5]_1 , \g_bit[6].reg_value_r_reg[6]_0 , \g_bit[7].reg_value_r_reg[7]_1 , \g_bit[0].reg_value_r_reg[0]_3 , \g_bit[1].reg_value_r_reg[1]_3 , \g_bit[2].reg_value_r_reg[2]_3 , \g_bit[3].reg_value_r_reg[3]_3 , \g_bit[4].reg_value_r_reg[4]_3 , \g_bit[5].reg_value_r_reg[5]_2 , \g_bit[6].reg_value_r_reg[6]_1 , \g_bit[7].reg_value_r_reg[7]_2 , \adress[7] , \adress[10] , \g_bit[0].reg_value_r_reg[0]_4 , \g_bit[0].reg_value_r_reg[0]_5 , \g_bit[0].reg_value_r_reg[0]_6 , \g_bit[0].reg_value_r_reg[0]_7 , \adress[7]_0 , \g_bit[0].reg_value_r_reg[0]_8 , ADDRARDADDR, DIADI, \g_bit[7].reg_value_r_reg[7]_3 , DIBDI, \g_bit[4].reg_value_r_reg[4]_4 , ADDRBWRADDR, \g_bit[7].reg_value_r_reg[7]_4 , \g_bit[7].reg_value_r_reg[7]_5 , \g_bit[4].reg_value_r_reg[4]_5 , \g_bit[4].reg_value_r_reg[4]_6 , \g_bit[7].reg_value_r_reg[7]_6 , \g_bit[7].reg_value_r_reg[7]_7 , \g_bit[4].reg_value_r_reg[4]_7 , \g_bit[4].reg_value_r_reg[4]_8 , \g_bit[7].reg_value_r_reg[7]_8 , \g_bit[7].reg_value_r_reg[7]_9 , \g_bit[4].reg_value_r_reg[4]_9 , \g_bit[4].reg_value_r_reg[4]_10 , \adress[11] , \r_data_reg[31]_0 , wr_en, data_in_IBUF, clk_sys_IBUF_BUFG, \g_bit[7].reg_value_r_reg[7]_10 , wr_en_0, wr_en_1, wr_en_2, wr_en_3, wr_en_4, wr_en_5, wr_en_6, adress_IBUF, sbe_IBUF, \r_data_reg[1]_0 , srd_IBUF, scs_IBUF, txtb_port_b_data_out_i, rxb_port_b_data_out_i, txtb_port_b_data_out_i_6, txtb_port_b_data_out_i_7, txtb_port_b_data_out_i_8, Q, \g_ram_rst_false.ram_memory_reg , \g_ram_rst_false.ram_memory_reg_0 , \g_ram_rst_false.ram_memory_reg_1 , \g_ram_rst_false.ram_memory_reg_2 , \g_ram_rst_false.ram_memory_reg_3 , \g_ram_rst_false.ram_memory_reg_4 , \g_ram_rst_false.ram_memory_reg_5 , \g_ram_rst_false.ram_memory_reg_6 , swr_IBUF); output \g_bit[0].reg_value_r_reg[0] ; output \g_bit[1].reg_value_r_reg[1] ; output \g_bit[2].reg_value_r_reg[2] ; output \g_bit[3].reg_value_r_reg[3] ; output \g_bit[4].reg_value_r_reg[4] ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[1].reg_value_r_reg[1]_0 ; output \g_bit[2].reg_value_r_reg[2]_0 ; output \g_bit[3].reg_value_r_reg[3]_0 ; output \g_bit[4].reg_value_r_reg[4]_0 ; output \g_bit[5].reg_value_r_reg[5] ; output \g_bit[6].reg_value_r_reg[6] ; output \g_bit[7].reg_value_r_reg[7] ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \g_bit[1].reg_value_r_reg[1]_1 ; output \g_bit[2].reg_value_r_reg[2]_1 ; output \g_bit[3].reg_value_r_reg[3]_1 ; output \g_bit[4].reg_value_r_reg[4]_1 ; output \g_bit[5].reg_value_r_reg[5]_0 ; output \g_bit[7].reg_value_r_reg[7]_0 ; output \g_bit[0].reg_value_r_reg[0]_2 ; output \g_bit[1].reg_value_r_reg[1]_2 ; output \g_bit[2].reg_value_r_reg[2]_2 ; output \g_bit[3].reg_value_r_reg[3]_2 ; output \g_bit[4].reg_value_r_reg[4]_2 ; output \g_bit[5].reg_value_r_reg[5]_1 ; output \g_bit[6].reg_value_r_reg[6]_0 ; output \g_bit[7].reg_value_r_reg[7]_1 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \g_bit[1].reg_value_r_reg[1]_3 ; output \g_bit[2].reg_value_r_reg[2]_3 ; output \g_bit[3].reg_value_r_reg[3]_3 ; output \g_bit[4].reg_value_r_reg[4]_3 ; output \g_bit[5].reg_value_r_reg[5]_2 ; output \g_bit[6].reg_value_r_reg[6]_1 ; output \g_bit[7].reg_value_r_reg[7]_2 ; output \adress[7] ; output \adress[10] ; output \g_bit[0].reg_value_r_reg[0]_4 ; output \g_bit[0].reg_value_r_reg[0]_5 ; output \g_bit[0].reg_value_r_reg[0]_6 ; output \g_bit[0].reg_value_r_reg[0]_7 ; output \adress[7]_0 ; output \g_bit[0].reg_value_r_reg[0]_8 ; output [0:0]ADDRARDADDR; output [0:0]DIADI; output [15:0]\g_bit[7].reg_value_r_reg[7]_3 ; output [15:0]DIBDI; output [3:0]\g_bit[4].reg_value_r_reg[4]_4 ; output [4:0]ADDRBWRADDR; output [15:0]\g_bit[7].reg_value_r_reg[7]_4 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_5 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_5 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_6 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_6 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_7 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_7 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_8 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_8 ; output [15:0]\g_bit[7].reg_value_r_reg[7]_9 ; output [3:0]\g_bit[4].reg_value_r_reg[4]_9 ; output [4:0]\g_bit[4].reg_value_r_reg[4]_10 ; output \adress[11] ; output [31:0]\r_data_reg[31]_0 ; input wr_en; input [31:0]data_in_IBUF; input clk_sys_IBUF_BUFG; input \g_bit[7].reg_value_r_reg[7]_10 ; input wr_en_0; input wr_en_1; input wr_en_2; input wr_en_3; input wr_en_4; input wr_en_5; input wr_en_6; input [9:0]adress_IBUF; input [3:0]sbe_IBUF; input \r_data_reg[1]_0 ; input srd_IBUF; input scs_IBUF; input [31:0]txtb_port_b_data_out_i; input [31:0]rxb_port_b_data_out_i; input [31:0]txtb_port_b_data_out_i_6; input [31:0]txtb_port_b_data_out_i_7; input [31:0]txtb_port_b_data_out_i_8; input [0:0]Q; input \g_ram_rst_false.ram_memory_reg ; input \g_ram_rst_false.ram_memory_reg_0 ; input \g_ram_rst_false.ram_memory_reg_1 ; input [3:0]\g_ram_rst_false.ram_memory_reg_2 ; input \g_ram_rst_false.ram_memory_reg_3 ; input \g_ram_rst_false.ram_memory_reg_4 ; input \g_ram_rst_false.ram_memory_reg_5 ; input \g_ram_rst_false.ram_memory_reg_6 ; input swr_IBUF; wire [0:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [0:0]DIADI; wire [15:0]DIBDI; wire [0:0]Q; wire \adress[10] ; wire \adress[11] ; wire \adress[7] ; wire \adress[7]_0 ; wire [9:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [31:0]data_in_IBUF; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire \g_bit[0].reg_value_r_reg[0]_5 ; wire \g_bit[0].reg_value_r_reg[0]_6 ; wire \g_bit[0].reg_value_r_reg[0]_7 ; wire \g_bit[0].reg_value_r_reg[0]_8 ; wire \g_bit[1].reg_value_r_reg[1] ; wire \g_bit[1].reg_value_r_reg[1]_0 ; wire \g_bit[1].reg_value_r_reg[1]_1 ; wire \g_bit[1].reg_value_r_reg[1]_2 ; wire \g_bit[1].reg_value_r_reg[1]_3 ; wire \g_bit[2].reg_value_r_reg[2] ; wire \g_bit[2].reg_value_r_reg[2]_0 ; wire \g_bit[2].reg_value_r_reg[2]_1 ; wire \g_bit[2].reg_value_r_reg[2]_2 ; wire \g_bit[2].reg_value_r_reg[2]_3 ; wire \g_bit[3].reg_value_r_reg[3] ; wire \g_bit[3].reg_value_r_reg[3]_0 ; wire \g_bit[3].reg_value_r_reg[3]_1 ; wire \g_bit[3].reg_value_r_reg[3]_2 ; wire \g_bit[3].reg_value_r_reg[3]_3 ; wire \g_bit[4].reg_value_r_reg[4] ; wire \g_bit[4].reg_value_r_reg[4]_0 ; wire \g_bit[4].reg_value_r_reg[4]_1 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_10 ; wire \g_bit[4].reg_value_r_reg[4]_2 ; wire \g_bit[4].reg_value_r_reg[4]_3 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_4 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_5 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_6 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_7 ; wire [4:0]\g_bit[4].reg_value_r_reg[4]_8 ; wire [3:0]\g_bit[4].reg_value_r_reg[4]_9 ; wire \g_bit[5].reg_value_r_reg[5] ; wire \g_bit[5].reg_value_r_reg[5]_0 ; wire \g_bit[5].reg_value_r_reg[5]_1 ; wire \g_bit[5].reg_value_r_reg[5]_2 ; wire \g_bit[6].reg_value_r_reg[6] ; wire \g_bit[6].reg_value_r_reg[6]_0 ; wire \g_bit[6].reg_value_r_reg[6]_1 ; wire \g_bit[7].reg_value_r_reg[7] ; wire \g_bit[7].reg_value_r_reg[7]_0 ; wire \g_bit[7].reg_value_r_reg[7]_1 ; wire \g_bit[7].reg_value_r_reg[7]_10 ; wire \g_bit[7].reg_value_r_reg[7]_2 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_3 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_4 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_5 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_6 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_7 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_8 ; wire [15:0]\g_bit[7].reg_value_r_reg[7]_9 ; wire \g_ram_rst_false.ram_memory_reg ; wire \g_ram_rst_false.ram_memory_reg_0 ; wire \g_ram_rst_false.ram_memory_reg_1 ; wire [3:0]\g_ram_rst_false.ram_memory_reg_2 ; wire \g_ram_rst_false.ram_memory_reg_3 ; wire \g_ram_rst_false.ram_memory_reg_4 ; wire \g_ram_rst_false.ram_memory_reg_5 ; wire \g_ram_rst_false.ram_memory_reg_6 ; wire i_tst_dest_tst_addr_slice_1_reg_n_5; wire i_tst_dest_tst_addr_slice_1_reg_n_6; wire i_tst_dest_tst_addr_slice_1_reg_n_7; wire i_tst_dest_tst_addr_slice_1_reg_n_8; wire i_tst_dest_tst_addr_slice_2_reg_n_0; wire i_tst_dest_tst_addr_slice_2_reg_n_1; wire i_tst_dest_tst_addr_slice_2_reg_n_2; wire i_tst_dest_tst_addr_slice_2_reg_n_3; wire i_tst_dest_tst_addr_slice_2_reg_n_4; wire i_tst_dest_tst_addr_slice_2_reg_n_5; wire i_tst_dest_tst_addr_slice_2_reg_n_6; wire i_tst_dest_tst_addr_slice_2_reg_n_7; wire i_tst_dest_tst_mtgt_reg_n_0; wire i_tst_dest_tst_mtgt_reg_n_1; wire i_tst_dest_tst_mtgt_reg_n_10; wire i_tst_dest_tst_mtgt_reg_n_11; wire i_tst_dest_tst_mtgt_reg_n_12; wire i_tst_dest_tst_mtgt_reg_n_13; wire i_tst_dest_tst_mtgt_reg_n_14; wire i_tst_dest_tst_mtgt_reg_n_15; wire i_tst_dest_tst_mtgt_reg_n_16; wire i_tst_dest_tst_mtgt_reg_n_18; wire i_tst_dest_tst_mtgt_reg_n_2; wire i_tst_dest_tst_mtgt_reg_n_20; wire i_tst_dest_tst_mtgt_reg_n_21; wire i_tst_dest_tst_mtgt_reg_n_22; wire i_tst_dest_tst_mtgt_reg_n_23; wire i_tst_dest_tst_mtgt_reg_n_24; wire i_tst_dest_tst_mtgt_reg_n_25; wire i_tst_dest_tst_mtgt_reg_n_26; wire i_tst_dest_tst_mtgt_reg_n_27; wire i_tst_dest_tst_mtgt_reg_n_28; wire i_tst_dest_tst_mtgt_reg_n_29; wire i_tst_dest_tst_mtgt_reg_n_3; wire i_tst_dest_tst_mtgt_reg_n_30; wire i_tst_dest_tst_mtgt_reg_n_31; wire i_tst_dest_tst_mtgt_reg_n_32; wire i_tst_dest_tst_mtgt_reg_n_33; wire i_tst_dest_tst_mtgt_reg_n_4; wire i_tst_dest_tst_mtgt_reg_n_5; wire i_tst_dest_tst_mtgt_reg_n_6; wire i_tst_dest_tst_mtgt_reg_n_7; wire i_tst_dest_tst_mtgt_reg_n_8; wire i_tst_dest_tst_mtgt_reg_n_9; wire i_tst_wdata_tst_wdata_slice_1_reg_n_10; wire i_tst_wdata_tst_wdata_slice_1_reg_n_11; wire i_tst_wdata_tst_wdata_slice_1_reg_n_12; wire i_tst_wdata_tst_wdata_slice_1_reg_n_13; wire i_tst_wdata_tst_wdata_slice_1_reg_n_8; wire i_tst_wdata_tst_wdata_slice_1_reg_n_9; wire i_tst_wdata_tst_wdata_slice_2_reg_n_10; wire i_tst_wdata_tst_wdata_slice_2_reg_n_11; wire i_tst_wdata_tst_wdata_slice_2_reg_n_12; wire i_tst_wdata_tst_wdata_slice_2_reg_n_13; wire i_tst_wdata_tst_wdata_slice_2_reg_n_14; wire i_tst_wdata_tst_wdata_slice_2_reg_n_15; wire i_tst_wdata_tst_wdata_slice_2_reg_n_8; wire i_tst_wdata_tst_wdata_slice_2_reg_n_9; wire \mr_tst_out[tst_control_tmaena] ; wire [14:14]\mr_tst_out[tst_wdata_tst_wdata] ; wire r_data0; wire \r_data[15]_i_2__0_n_0 ; wire \r_data[23]_i_2__0_n_0 ; wire \r_data[31]_i_3__0_n_0 ; wire \r_data[7]_i_2_n_0 ; wire \r_data_reg[1]_0 ; wire [31:0]\r_data_reg[31]_0 ; wire [31:0]rxb_port_b_data_out_i; wire [3:0]sbe_IBUF; wire scs_IBUF; wire srd_IBUF; wire swr_IBUF; wire [31:0]txtb_port_b_data_out_i; wire [31:0]txtb_port_b_data_out_i_6; wire [31:0]txtb_port_b_data_out_i_7; wire [31:0]txtb_port_b_data_out_i_8; wire wr_en; wire wr_en_0; wire wr_en_1; wire wr_en_2; wire wr_en_3; wire wr_en_4; wire wr_en_5; wire wr_en_6; memory_reg_rw_lock__parameterized29_50 i_tst_control_tmaena_reg (.\adress[10] (\adress[10] ), .\adress[7] (\adress[7]_0 ), .adress_IBUF(adress_IBUF[9:4]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[7].reg_value_r_reg[7]_10 ), .\mr_tst_out[tst_control_tmaena] (\mr_tst_out[tst_control_tmaena] ), .scs_IBUF(scs_IBUF), .wr_en(wr_en)); memory_reg_rw_lock__parameterized27_51 i_tst_dest_tst_addr_slice_1_reg (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .D(i_tst_dest_tst_addr_slice_1_reg_n_8), .Q(Q), .adress_IBUF(adress_IBUF[5:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7:0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0] ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1] ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2] ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3] ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4] ), .\g_bit[4].reg_value_r_reg[4]_1 (\g_bit[4].reg_value_r_reg[4]_4 ), .\g_bit[4].reg_value_r_reg[4]_2 (\g_bit[4].reg_value_r_reg[4]_5 ), .\g_bit[4].reg_value_r_reg[4]_3 (\g_bit[4].reg_value_r_reg[4]_6 ), .\g_bit[4].reg_value_r_reg[4]_4 (\g_bit[4].reg_value_r_reg[4]_7 ), .\g_bit[4].reg_value_r_reg[4]_5 (\g_bit[4].reg_value_r_reg[4]_8 ), .\g_bit[4].reg_value_r_reg[4]_6 (\g_bit[4].reg_value_r_reg[4]_9 ), .\g_bit[4].reg_value_r_reg[4]_7 (\g_bit[4].reg_value_r_reg[4]_10 ), .\g_bit[5].reg_value_r_reg[5]_0 (i_tst_dest_tst_addr_slice_1_reg_n_5), .\g_bit[6].reg_value_r_reg[6]_0 (i_tst_dest_tst_addr_slice_1_reg_n_6), .\g_bit[7].reg_value_r_reg[7]_0 (i_tst_dest_tst_addr_slice_1_reg_n_7), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_10 ), .\g_ram_rst_false.ram_memory_reg (\g_bit[0].reg_value_r_reg[0]_5 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_ram_rst_false.ram_memory_reg ), .\g_ram_rst_false.ram_memory_reg_1 (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_ram_rst_false.ram_memory_reg_2 ), .\g_ram_rst_false.ram_memory_reg_3 (\g_ram_rst_false.ram_memory_reg_3 ), .\g_ram_rst_false.ram_memory_reg_4 (\g_ram_rst_false.ram_memory_reg_4 ), .\g_ram_rst_false.ram_memory_reg_5 (\g_ram_rst_false.ram_memory_reg_5 ), .\g_ram_rst_false.ram_memory_reg_6 (\g_ram_rst_false.ram_memory_reg_6 ), .\g_ram_rst_false.ram_memory_reg_7 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_ram_rst_false.ram_memory_reg_8 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_ram_rst_false.ram_memory_reg_9 (\g_bit[0].reg_value_r_reg[0]_8 ), .\r_data_reg[1] (\r_data_reg[1]_0 ), .\r_data_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_0 ), .\r_data_reg[1]_1 (i_tst_dest_tst_mtgt_reg_n_18), .sbe_IBUF(sbe_IBUF[0]), .wr_en_0(wr_en_0)); memory_reg_rw_lock__parameterized27_52 i_tst_dest_tst_addr_slice_2_reg (.clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[15:8]), .\g_bit[0].reg_value_r_reg[0]_0 (i_tst_dest_tst_addr_slice_2_reg_n_0), .\g_bit[1].reg_value_r_reg[1]_0 (i_tst_dest_tst_addr_slice_2_reg_n_1), .\g_bit[2].reg_value_r_reg[2]_0 (i_tst_dest_tst_addr_slice_2_reg_n_2), .\g_bit[3].reg_value_r_reg[3]_0 (i_tst_dest_tst_addr_slice_2_reg_n_3), .\g_bit[4].reg_value_r_reg[4]_0 (i_tst_dest_tst_addr_slice_2_reg_n_4), .\g_bit[5].reg_value_r_reg[5]_0 (i_tst_dest_tst_addr_slice_2_reg_n_5), .\g_bit[6].reg_value_r_reg[6]_0 (i_tst_dest_tst_addr_slice_2_reg_n_6), .\g_bit[7].reg_value_r_reg[7]_0 (i_tst_dest_tst_addr_slice_2_reg_n_7), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_10 ), .wr_en_1(wr_en_1)); memory_reg_rw_lock__parameterized33 i_tst_dest_tst_mtgt_reg (.D({i_tst_dest_tst_mtgt_reg_n_0,i_tst_dest_tst_mtgt_reg_n_1,i_tst_dest_tst_mtgt_reg_n_2,i_tst_dest_tst_mtgt_reg_n_3,i_tst_dest_tst_mtgt_reg_n_4,i_tst_dest_tst_mtgt_reg_n_5,i_tst_dest_tst_mtgt_reg_n_6,i_tst_dest_tst_mtgt_reg_n_7,i_tst_dest_tst_mtgt_reg_n_8,i_tst_dest_tst_mtgt_reg_n_9,i_tst_dest_tst_mtgt_reg_n_10,i_tst_dest_tst_mtgt_reg_n_11,i_tst_dest_tst_mtgt_reg_n_12,i_tst_dest_tst_mtgt_reg_n_13,i_tst_dest_tst_mtgt_reg_n_14,i_tst_dest_tst_mtgt_reg_n_15,i_tst_dest_tst_mtgt_reg_n_16}), .DIADI(DIADI), .adress_IBUF(adress_IBUF[5:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[19:16]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_bit[0].reg_value_r_reg[0]_1 (\g_bit[0].reg_value_r_reg[0]_5 ), .\g_bit[0].reg_value_r_reg[0]_2 (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_bit[0].reg_value_r_reg[0]_3 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_bit[0].reg_value_r_reg[0]_4 (\g_bit[0].reg_value_r_reg[0]_8 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[7].reg_value_r_reg[7]_10 ), .\g_ram_rst_false.ram_memory_reg (i_tst_dest_tst_mtgt_reg_n_18), .\g_ram_rst_false.ram_memory_reg_0 (i_tst_dest_tst_mtgt_reg_n_20), .\g_ram_rst_false.ram_memory_reg_1 (i_tst_dest_tst_mtgt_reg_n_21), .\g_ram_rst_false.ram_memory_reg_10 (i_tst_dest_tst_mtgt_reg_n_30), .\g_ram_rst_false.ram_memory_reg_11 (i_tst_dest_tst_mtgt_reg_n_31), .\g_ram_rst_false.ram_memory_reg_12 (i_tst_dest_tst_mtgt_reg_n_32), .\g_ram_rst_false.ram_memory_reg_13 (i_tst_dest_tst_mtgt_reg_n_33), .\g_ram_rst_false.ram_memory_reg_14 (\g_ram_rst_false.ram_memory_reg_0 ), .\g_ram_rst_false.ram_memory_reg_15 (\g_ram_rst_false.ram_memory_reg_1 ), .\g_ram_rst_false.ram_memory_reg_2 (i_tst_dest_tst_mtgt_reg_n_22), .\g_ram_rst_false.ram_memory_reg_3 (i_tst_dest_tst_mtgt_reg_n_23), .\g_ram_rst_false.ram_memory_reg_4 (i_tst_dest_tst_mtgt_reg_n_24), .\g_ram_rst_false.ram_memory_reg_5 (i_tst_dest_tst_mtgt_reg_n_25), .\g_ram_rst_false.ram_memory_reg_6 (i_tst_dest_tst_mtgt_reg_n_26), .\g_ram_rst_false.ram_memory_reg_7 (i_tst_dest_tst_mtgt_reg_n_27), .\g_ram_rst_false.ram_memory_reg_8 (i_tst_dest_tst_mtgt_reg_n_28), .\g_ram_rst_false.ram_memory_reg_9 (i_tst_dest_tst_mtgt_reg_n_29), .\mr_tst_out[tst_control_tmaena] (\mr_tst_out[tst_control_tmaena] ), .\mr_tst_out[tst_wdata_tst_wdata] (\mr_tst_out[tst_wdata_tst_wdata] ), .\r_data_reg[0] (\g_bit[0].reg_value_r_reg[0]_0 ), .\r_data_reg[0]_0 (\g_bit[0].reg_value_r_reg[0] ), .\r_data_reg[16] (\r_data[23]_i_2__0_n_0 ), .\r_data_reg[16]_0 (\g_bit[0].reg_value_r_reg[0]_2 ), .\r_data_reg[17] (\g_bit[1].reg_value_r_reg[1]_2 ), .\r_data_reg[18] (\g_bit[2].reg_value_r_reg[2]_2 ), .\r_data_reg[19] (\g_bit[3].reg_value_r_reg[3]_2 ), .\r_data_reg[20] (\g_bit[4].reg_value_r_reg[4]_2 ), .\r_data_reg[21] (\g_bit[5].reg_value_r_reg[5]_1 ), .\r_data_reg[22] (\g_bit[6].reg_value_r_reg[6]_0 ), .\r_data_reg[23] (\g_bit[7].reg_value_r_reg[7]_1 ), .\r_data_reg[24] (\r_data[31]_i_3__0_n_0 ), .\r_data_reg[24]_0 (\g_bit[0].reg_value_r_reg[0]_3 ), .\r_data_reg[25] (\g_bit[1].reg_value_r_reg[1]_3 ), .\r_data_reg[26] (\g_bit[2].reg_value_r_reg[2]_3 ), .\r_data_reg[27] (\g_bit[3].reg_value_r_reg[3]_3 ), .\r_data_reg[28] (\g_bit[4].reg_value_r_reg[4]_3 ), .\r_data_reg[29] (\g_bit[5].reg_value_r_reg[5]_2 ), .\r_data_reg[30] (\g_bit[6].reg_value_r_reg[6]_1 ), .\r_data_reg[31] (\g_bit[7].reg_value_r_reg[7]_2 ), .rxb_port_b_data_out_i(rxb_port_b_data_out_i), .sbe_IBUF(sbe_IBUF[0]), .txtb_port_b_data_out_i(txtb_port_b_data_out_i), .txtb_port_b_data_out_i_6(txtb_port_b_data_out_i_6), .txtb_port_b_data_out_i_7(txtb_port_b_data_out_i_7), .txtb_port_b_data_out_i_8(txtb_port_b_data_out_i_8), .wr_en_2(wr_en_2)); memory_reg_rw_lock__parameterized27_53 i_tst_wdata_tst_wdata_slice_1_reg (.D({i_tst_wdata_tst_wdata_slice_1_reg_n_8,i_tst_wdata_tst_wdata_slice_1_reg_n_9,i_tst_wdata_tst_wdata_slice_1_reg_n_10,i_tst_wdata_tst_wdata_slice_1_reg_n_11,i_tst_wdata_tst_wdata_slice_1_reg_n_12,i_tst_wdata_tst_wdata_slice_1_reg_n_13}), .\adress[11] (\adress[11] ), .\adress[7] (\adress[7] ), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[7:0]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_0 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_0 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_0 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_0 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_0 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5] ), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[6].reg_value_r_reg[6] ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7] ), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_3 [7:0]), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7]_4 [7:0]), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[7].reg_value_r_reg[7]_6 [7:0]), .\g_bit[7].reg_value_r_reg[7]_4 (\g_bit[7].reg_value_r_reg[7]_8 [7:0]), .\g_bit[7].reg_value_r_reg[7]_5 (\g_bit[7].reg_value_r_reg[7]_10 ), .\g_ram_rst_false.ram_memory_reg (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_bit[0].reg_value_r_reg[0]_8 ), .\r_data_reg[2] (\r_data[7]_i_2_n_0 ), .\r_data_reg[2]_0 (\g_bit[2].reg_value_r_reg[2] ), .\r_data_reg[2]_1 (i_tst_dest_tst_mtgt_reg_n_20), .\r_data_reg[3] (\g_bit[3].reg_value_r_reg[3] ), .\r_data_reg[3]_0 (i_tst_dest_tst_mtgt_reg_n_21), .\r_data_reg[4] (\g_bit[4].reg_value_r_reg[4] ), .\r_data_reg[4]_0 (i_tst_dest_tst_mtgt_reg_n_22), .\r_data_reg[5] (i_tst_dest_tst_addr_slice_1_reg_n_5), .\r_data_reg[5]_0 (i_tst_dest_tst_mtgt_reg_n_23), .\r_data_reg[6] (i_tst_dest_tst_addr_slice_1_reg_n_6), .\r_data_reg[6]_0 (i_tst_dest_tst_mtgt_reg_n_24), .\r_data_reg[7] (i_tst_dest_tst_addr_slice_1_reg_n_7), .\r_data_reg[7]_0 (i_tst_dest_tst_mtgt_reg_n_25), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .wr_en_3(wr_en_3)); memory_reg_rw_lock__parameterized27_54 i_tst_wdata_tst_wdata_slice_2_reg (.D({i_tst_wdata_tst_wdata_slice_2_reg_n_8,i_tst_wdata_tst_wdata_slice_2_reg_n_9,i_tst_wdata_tst_wdata_slice_2_reg_n_10,i_tst_wdata_tst_wdata_slice_2_reg_n_11,i_tst_wdata_tst_wdata_slice_2_reg_n_12,i_tst_wdata_tst_wdata_slice_2_reg_n_13,i_tst_wdata_tst_wdata_slice_2_reg_n_14,i_tst_wdata_tst_wdata_slice_2_reg_n_15}), .adress_IBUF(adress_IBUF[1:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[15:8]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_1 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_1 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_1 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_1 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_1 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5]_0 ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7]_0 ), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_3 [15:8]), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7]_4 [15:8]), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[7].reg_value_r_reg[7]_6 [15:8]), .\g_bit[7].reg_value_r_reg[7]_4 (\g_bit[7].reg_value_r_reg[7]_8 [15:8]), .\g_bit[7].reg_value_r_reg[7]_5 (\g_bit[7].reg_value_r_reg[7]_10 ), .\g_ram_rst_false.ram_memory_reg (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_bit[0].reg_value_r_reg[0]_8 ), .\mr_tst_out[tst_wdata_tst_wdata] (\mr_tst_out[tst_wdata_tst_wdata] ), .\r_data_reg[10] (i_tst_dest_tst_addr_slice_2_reg_n_2), .\r_data_reg[10]_0 (i_tst_dest_tst_mtgt_reg_n_28), .\r_data_reg[11] (i_tst_dest_tst_addr_slice_2_reg_n_3), .\r_data_reg[11]_0 (i_tst_dest_tst_mtgt_reg_n_29), .\r_data_reg[12] (i_tst_dest_tst_addr_slice_2_reg_n_4), .\r_data_reg[12]_0 (i_tst_dest_tst_mtgt_reg_n_30), .\r_data_reg[13] (i_tst_dest_tst_addr_slice_2_reg_n_5), .\r_data_reg[13]_0 (i_tst_dest_tst_mtgt_reg_n_31), .\r_data_reg[14] (i_tst_dest_tst_addr_slice_2_reg_n_6), .\r_data_reg[14]_0 (i_tst_dest_tst_mtgt_reg_n_32), .\r_data_reg[15] (i_tst_dest_tst_addr_slice_2_reg_n_7), .\r_data_reg[15]_0 (i_tst_dest_tst_mtgt_reg_n_33), .\r_data_reg[8] (\r_data[15]_i_2__0_n_0 ), .\r_data_reg[8]_0 (i_tst_dest_tst_addr_slice_2_reg_n_0), .\r_data_reg[8]_1 (i_tst_dest_tst_mtgt_reg_n_26), .\r_data_reg[9] (i_tst_dest_tst_addr_slice_2_reg_n_1), .\r_data_reg[9]_0 (i_tst_dest_tst_mtgt_reg_n_27), .wr_en_4(wr_en_4)); memory_reg_rw_lock__parameterized27_55 i_tst_wdata_tst_wdata_slice_3_reg (.DIBDI(DIBDI[7:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[23:16]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_2 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_2 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_2 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_2 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_2 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5]_1 ), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[6].reg_value_r_reg[6]_0 ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7]_1 ), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_5 [7:0]), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7]_7 [7:0]), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[7].reg_value_r_reg[7]_9 [7:0]), .\g_bit[7].reg_value_r_reg[7]_4 (\g_bit[7].reg_value_r_reg[7]_10 ), .\g_ram_rst_false.ram_memory_reg (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_bit[0].reg_value_r_reg[0]_8 ), .wr_en_5(wr_en_5)); memory_reg_rw_lock__parameterized27_56 i_tst_wdata_tst_wdata_slice_4_reg (.DIBDI(DIBDI[15:8]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .data_in_IBUF(data_in_IBUF[31:24]), .\g_bit[0].reg_value_r_reg[0]_0 (\g_bit[0].reg_value_r_reg[0]_3 ), .\g_bit[1].reg_value_r_reg[1]_0 (\g_bit[1].reg_value_r_reg[1]_3 ), .\g_bit[2].reg_value_r_reg[2]_0 (\g_bit[2].reg_value_r_reg[2]_3 ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_3 ), .\g_bit[4].reg_value_r_reg[4]_0 (\g_bit[4].reg_value_r_reg[4]_3 ), .\g_bit[5].reg_value_r_reg[5]_0 (\g_bit[5].reg_value_r_reg[5]_2 ), .\g_bit[6].reg_value_r_reg[6]_0 (\g_bit[6].reg_value_r_reg[6]_1 ), .\g_bit[7].reg_value_r_reg[7]_0 (\g_bit[7].reg_value_r_reg[7]_2 ), .\g_bit[7].reg_value_r_reg[7]_1 (\g_bit[7].reg_value_r_reg[7]_5 [15:8]), .\g_bit[7].reg_value_r_reg[7]_2 (\g_bit[7].reg_value_r_reg[7]_7 [15:8]), .\g_bit[7].reg_value_r_reg[7]_3 (\g_bit[7].reg_value_r_reg[7]_9 [15:8]), .\g_bit[7].reg_value_r_reg[7]_4 (\g_bit[7].reg_value_r_reg[7]_10 ), .\g_ram_rst_false.ram_memory_reg (\g_bit[0].reg_value_r_reg[0]_6 ), .\g_ram_rst_false.ram_memory_reg_0 (\g_bit[0].reg_value_r_reg[0]_7 ), .\g_ram_rst_false.ram_memory_reg_1 (\g_bit[0].reg_value_r_reg[0]_4 ), .\g_ram_rst_false.ram_memory_reg_2 (\g_bit[0].reg_value_r_reg[0]_8 ), .wr_en_6(wr_en_6)); LUT5 #( .INIT(32'h00000002)) \r_data[15]_i_2__0 (.I0(sbe_IBUF[1]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(adress_IBUF[2]), .I4(adress_IBUF[5]), .O(\r_data[15]_i_2__0_n_0 )); LUT5 #( .INIT(32'h00000002)) \r_data[23]_i_2__0 (.I0(sbe_IBUF[2]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(adress_IBUF[2]), .I4(adress_IBUF[5]), .O(\r_data[23]_i_2__0_n_0 )); LUT6 #( .INIT(64'h0000000000800000)) \r_data[31]_i_1 (.I0(srd_IBUF), .I1(adress_IBUF[9]), .I2(adress_IBUF[6]), .I3(adress_IBUF[7]), .I4(scs_IBUF), .I5(adress_IBUF[8]), .O(r_data0)); LUT5 #( .INIT(32'h00000002)) \r_data[31]_i_3__0 (.I0(sbe_IBUF[3]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(adress_IBUF[2]), .I4(adress_IBUF[5]), .O(\r_data[31]_i_3__0_n_0 )); LUT5 #( .INIT(32'h00000002)) \r_data[7]_i_2 (.I0(sbe_IBUF[0]), .I1(adress_IBUF[3]), .I2(adress_IBUF[4]), .I3(adress_IBUF[2]), .I4(adress_IBUF[5]), .O(\r_data[7]_i_2_n_0 )); FDCE \r_data_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_16), .Q(\r_data_reg[31]_0 [0])); FDCE \r_data_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_13), .Q(\r_data_reg[31]_0 [10])); FDCE \r_data_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_12), .Q(\r_data_reg[31]_0 [11])); FDCE \r_data_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_11), .Q(\r_data_reg[31]_0 [12])); FDCE \r_data_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_10), .Q(\r_data_reg[31]_0 [13])); FDCE \r_data_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_9), .Q(\r_data_reg[31]_0 [14])); FDCE \r_data_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_8), .Q(\r_data_reg[31]_0 [15])); FDCE \r_data_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_15), .Q(\r_data_reg[31]_0 [16])); FDCE \r_data_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_14), .Q(\r_data_reg[31]_0 [17])); FDCE \r_data_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_13), .Q(\r_data_reg[31]_0 [18])); FDCE \r_data_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_12), .Q(\r_data_reg[31]_0 [19])); FDCE \r_data_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_addr_slice_1_reg_n_8), .Q(\r_data_reg[31]_0 [1])); FDCE \r_data_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_11), .Q(\r_data_reg[31]_0 [20])); FDCE \r_data_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_10), .Q(\r_data_reg[31]_0 [21])); FDCE \r_data_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_9), .Q(\r_data_reg[31]_0 [22])); FDCE \r_data_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_8), .Q(\r_data_reg[31]_0 [23])); FDCE \r_data_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_7), .Q(\r_data_reg[31]_0 [24])); FDCE \r_data_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_6), .Q(\r_data_reg[31]_0 [25])); FDCE \r_data_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_5), .Q(\r_data_reg[31]_0 [26])); FDCE \r_data_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_4), .Q(\r_data_reg[31]_0 [27])); FDCE \r_data_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_3), .Q(\r_data_reg[31]_0 [28])); FDCE \r_data_reg[29] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_2), .Q(\r_data_reg[31]_0 [29])); FDCE \r_data_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_1_reg_n_13), .Q(\r_data_reg[31]_0 [2])); FDCE \r_data_reg[30] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_1), .Q(\r_data_reg[31]_0 [30])); FDCE \r_data_reg[31] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_dest_tst_mtgt_reg_n_0), .Q(\r_data_reg[31]_0 [31])); FDCE \r_data_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_1_reg_n_12), .Q(\r_data_reg[31]_0 [3])); FDCE \r_data_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_1_reg_n_11), .Q(\r_data_reg[31]_0 [4])); FDCE \r_data_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_1_reg_n_10), .Q(\r_data_reg[31]_0 [5])); FDCE \r_data_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_1_reg_n_9), .Q(\r_data_reg[31]_0 [6])); FDCE \r_data_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_1_reg_n_8), .Q(\r_data_reg[31]_0 [7])); FDCE \r_data_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_15), .Q(\r_data_reg[31]_0 [8])); FDCE \r_data_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(r_data0), .CLR(\g_bit[7].reg_value_r_reg[7]_10 ), .D(i_tst_wdata_tst_wdata_slice_2_reg_n_14), .Q(\r_data_reg[31]_0 [9])); endmodule module txarb_fsm (fsm_wait_state_q_reg_0, ADDRARDADDR, \FSM_sequential_curr_state_reg[0]_0 , \g_bit[3].reg_value_r_reg[3] , \g_bit[3].reg_value_r_reg[3]_0 , \g_bit[3].reg_value_r_reg[3]_1 , \FSM_sequential_curr_state_reg[1]_0 , D, \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[0]_1 , buffer_md_w, buffer_frame_test_w, tran_frame_valid, \FSM_sequential_curr_state_reg[2]_1 , \curr_state_reg[2] , \last_txtb_index_reg[1] , \FSM_sequential_curr_state_reg[0]_2 , E, \FSM_sequential_curr_state_reg[0]_3 , \txtb_pointer_meta_q_reg[1] , \txtb_pointer_meta_q_reg[4] , \txtb_pointer_meta_q_reg[0] , \curr_txtb_index_i_reg[1] , \curr_txtb_index_i_reg[0] , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[0]_4 , \mr_tst_out[tst_dest_tst_addr] , tst_ena, \g_ram_rst_false.ram_memory_reg , tst_ena_0, tst_ena_2, tst_ena_4, timestamp_IBUF, \tran_frame_test_dbl_buf_reg[fstc] , \tran_frame_test_dbl_buf_reg[fstc]_0 , \tran_frame_test_dbl_buf_reg[fstc]_1 , \tran_frame_test_dbl_buf_reg[fstc]_2 , \ts_low_internal_reg[1] , \ts_low_internal_reg[1]_0 , \ts_low_internal_reg[1]_1 , \ts_low_internal_reg[1]_2 , \ts_low_internal_reg[2] , \ts_low_internal_reg[2]_0 , \ts_low_internal_reg[2]_1 , \ts_low_internal_reg[2]_2 , \tran_identifier_com_reg[3] , \tran_identifier_com_reg[3]_0 , \tran_identifier_com_reg[3]_1 , \tran_identifier_com_reg[3]_2 , \tran_identifier_com_reg[4] , \tran_identifier_com_reg[4]_0 , \tran_identifier_com_reg[4]_1 , \tran_identifier_com_reg[4]_2 , \tran_identifier_com_reg[5] , \tran_identifier_com_reg[5]_0 , \tran_identifier_com_reg[5]_1 , \tran_identifier_com_reg[5]_2 , \tran_identifier_com_reg[6] , \tran_identifier_com_reg[6]_0 , \tran_identifier_com_reg[6]_1 , \tran_identifier_com_reg[6]_2 , \ts_low_internal_reg[7] , \ts_low_internal_reg[7]_0 , \ts_low_internal_reg[7]_1 , \ts_low_internal_reg[7]_2 , \ts_low_internal_reg[8] , \ts_low_internal_reg[8]_0 , \ts_low_internal_reg[8]_1 , \ts_low_internal_reg[8]_2 , \tran_frame_test_dbl_buf_reg[tprm][1] , \tran_frame_test_dbl_buf_reg[tprm][1]_0 , \tran_frame_test_dbl_buf_reg[tprm][1]_1 , \tran_frame_test_dbl_buf_reg[tprm][1]_2 , \tran_frame_test_dbl_buf_reg[tprm][2] , \tran_frame_test_dbl_buf_reg[tprm][2]_0 , \tran_frame_test_dbl_buf_reg[tprm][2]_1 , \tran_frame_test_dbl_buf_reg[tprm][2]_2 , \tran_frame_test_dbl_buf_reg[tprm][3] , \tran_frame_test_dbl_buf_reg[tprm][3]_0 , \tran_frame_test_dbl_buf_reg[tprm][3]_1 , \tran_frame_test_dbl_buf_reg[tprm][3]_2 , \tran_frame_test_dbl_buf_reg[tprm][4] , \tran_frame_test_dbl_buf_reg[tprm][4]_0 , \tran_frame_test_dbl_buf_reg[tprm][4]_1 , \tran_frame_test_dbl_buf_reg[tprm][4]_2 , \ts_low_internal_reg[13] , \ts_low_internal_reg[13]_0 , \ts_low_internal_reg[13]_1 , \ts_low_internal_reg[13]_2 , \ts_low_internal_reg[14] , \ts_low_internal_reg[14]_0 , \ts_low_internal_reg[14]_1 , \ts_low_internal_reg[14]_2 , \tran_identifier_com_reg[15] , \tran_identifier_com_reg[15]_0 , \tran_identifier_com_reg[15]_1 , \tran_identifier_com_reg[15]_2 , \tran_identifier_com_reg[16] , \tran_identifier_com_reg[16]_0 , \tran_identifier_com_reg[16]_1 , \tran_identifier_com_reg[16]_2 , \tran_identifier_com_reg[17] , \tran_identifier_com_reg[17]_0 , \tran_identifier_com_reg[17]_1 , \tran_identifier_com_reg[17]_2 , \tran_identifier_com_reg[18] , \tran_identifier_com_reg[18]_0 , \tran_identifier_com_reg[18]_1 , \tran_identifier_com_reg[18]_2 , \ts_low_internal_reg[19] , \ts_low_internal_reg[19]_0 , \ts_low_internal_reg[19]_1 , \ts_low_internal_reg[19]_2 , \ts_low_internal_reg[20] , \ts_low_internal_reg[20]_0 , \ts_low_internal_reg[20]_1 , \ts_low_internal_reg[20]_2 , \tran_identifier_com_reg[21] , \tran_identifier_com_reg[21]_0 , \tran_identifier_com_reg[21]_1 , \tran_identifier_com_reg[21]_2 , \tran_identifier_com_reg[22] , \tran_identifier_com_reg[22]_0 , \tran_identifier_com_reg[22]_1 , \tran_identifier_com_reg[22]_2 , \tran_identifier_com_reg[23] , \tran_identifier_com_reg[23]_0 , \tran_identifier_com_reg[23]_1 , \tran_identifier_com_reg[23]_2 , \ts_low_internal_reg[24] , \ts_low_internal_reg[24]_0 , \ts_low_internal_reg[24]_1 , \ts_low_internal_reg[24]_2 , \ts_low_internal_reg[25] , \ts_low_internal_reg[25]_0 , \ts_low_internal_reg[25]_1 , \ts_low_internal_reg[25]_2 , \ts_low_internal_reg[26] , \ts_low_internal_reg[26]_0 , \ts_low_internal_reg[26]_1 , \ts_low_internal_reg[26]_2 , \tran_identifier_com_reg[27] , \tran_identifier_com_reg[27]_0 , \tran_identifier_com_reg[27]_1 , \tran_identifier_com_reg[27]_2 , \tran_identifier_com_reg[28] , \tran_identifier_com_reg[28]_0 , \tran_identifier_com_reg[28]_1 , \tran_identifier_com_reg[28]_2 , \ts_low_internal_reg[29] , \ts_low_internal_reg[29]_0 , \ts_low_internal_reg[29]_1 , \ts_low_internal_reg[29]_2 , \ts_low_internal_reg[30] , \ts_low_internal_reg[30]_0 , \ts_low_internal_reg[30]_1 , \ts_low_internal_reg[30]_2 , \ts_low_internal_reg[31] , \ts_low_internal_reg[31]_0 , \ts_low_internal_reg[31]_1 , \ts_low_internal_reg[31]_2 , \ts_low_internal_reg[31]_3 , Q, \FSM_sequential_curr_state_reg[2]_2 , \txtb_pointer_meta_q_reg[0]_0 , fsm_wait_state_q_reg_1, \txtb_hw_cmd[lock] , tran_frame_valid_com_reg, \FSM_sequential_curr_state_reg[2]_3 , tran_frame_valid_com_reg_0, tran_frame_valid_com_reg_1, \FSM_sequential_curr_state[0]_i_2__3_0 , destuff_enable_i_7, tran_frame_valid_com, \mr_ctrl_out[mode_tttm] , \FSM_sequential_curr_state_reg[0]_i_9_0 , \shift_regs_reg[0] , last_txtb_index, \retr_ctr_q_reg[3] , \txtb_pointer_meta_q_reg[1]_0 , \txtb_pointer_meta_q_reg[4]_0 , \txtb_pointer_meta_q_reg[0]_1 ); output fsm_wait_state_q_reg_0; output [0:0]ADDRARDADDR; output \FSM_sequential_curr_state_reg[0]_0 ; output [0:0]\g_bit[3].reg_value_r_reg[3] ; output [0:0]\g_bit[3].reg_value_r_reg[3]_0 ; output [0:0]\g_bit[3].reg_value_r_reg[3]_1 ; output \FSM_sequential_curr_state_reg[1]_0 ; output [28:0]D; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output [2:0]\FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[2]_0 ; output \FSM_sequential_curr_state_reg[0]_1 ; output buffer_md_w; output buffer_frame_test_w; output tran_frame_valid; output \FSM_sequential_curr_state_reg[2]_1 ; output [0:0]\curr_state_reg[2] ; output \last_txtb_index_reg[1] ; output \FSM_sequential_curr_state_reg[0]_2 ; output [0:0]E; output \FSM_sequential_curr_state_reg[0]_3 ; output \txtb_pointer_meta_q_reg[1] ; output \txtb_pointer_meta_q_reg[4] ; output \txtb_pointer_meta_q_reg[0] ; output \curr_txtb_index_i_reg[1] ; output \curr_txtb_index_i_reg[0] ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[0]_4 ; input [0:0]\mr_tst_out[tst_dest_tst_addr] ; input tst_ena; input [0:0]\g_ram_rst_false.ram_memory_reg ; input tst_ena_0; input tst_ena_2; input tst_ena_4; input [63:0]timestamp_IBUF; input \tran_frame_test_dbl_buf_reg[fstc] ; input \tran_frame_test_dbl_buf_reg[fstc]_0 ; input \tran_frame_test_dbl_buf_reg[fstc]_1 ; input \tran_frame_test_dbl_buf_reg[fstc]_2 ; input \ts_low_internal_reg[1] ; input \ts_low_internal_reg[1]_0 ; input \ts_low_internal_reg[1]_1 ; input \ts_low_internal_reg[1]_2 ; input \ts_low_internal_reg[2] ; input \ts_low_internal_reg[2]_0 ; input \ts_low_internal_reg[2]_1 ; input \ts_low_internal_reg[2]_2 ; input \tran_identifier_com_reg[3] ; input \tran_identifier_com_reg[3]_0 ; input \tran_identifier_com_reg[3]_1 ; input \tran_identifier_com_reg[3]_2 ; input \tran_identifier_com_reg[4] ; input \tran_identifier_com_reg[4]_0 ; input \tran_identifier_com_reg[4]_1 ; input \tran_identifier_com_reg[4]_2 ; input \tran_identifier_com_reg[5] ; input \tran_identifier_com_reg[5]_0 ; input \tran_identifier_com_reg[5]_1 ; input \tran_identifier_com_reg[5]_2 ; input \tran_identifier_com_reg[6] ; input \tran_identifier_com_reg[6]_0 ; input \tran_identifier_com_reg[6]_1 ; input \tran_identifier_com_reg[6]_2 ; input \ts_low_internal_reg[7] ; input \ts_low_internal_reg[7]_0 ; input \ts_low_internal_reg[7]_1 ; input \ts_low_internal_reg[7]_2 ; input \ts_low_internal_reg[8] ; input \ts_low_internal_reg[8]_0 ; input \ts_low_internal_reg[8]_1 ; input \ts_low_internal_reg[8]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][1] ; input \tran_frame_test_dbl_buf_reg[tprm][1]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][1]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][1]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][2] ; input \tran_frame_test_dbl_buf_reg[tprm][2]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][2]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][2]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][3] ; input \tran_frame_test_dbl_buf_reg[tprm][3]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][3]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][3]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][4] ; input \tran_frame_test_dbl_buf_reg[tprm][4]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][4]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][4]_2 ; input \ts_low_internal_reg[13] ; input \ts_low_internal_reg[13]_0 ; input \ts_low_internal_reg[13]_1 ; input \ts_low_internal_reg[13]_2 ; input \ts_low_internal_reg[14] ; input \ts_low_internal_reg[14]_0 ; input \ts_low_internal_reg[14]_1 ; input \ts_low_internal_reg[14]_2 ; input \tran_identifier_com_reg[15] ; input \tran_identifier_com_reg[15]_0 ; input \tran_identifier_com_reg[15]_1 ; input \tran_identifier_com_reg[15]_2 ; input \tran_identifier_com_reg[16] ; input \tran_identifier_com_reg[16]_0 ; input \tran_identifier_com_reg[16]_1 ; input \tran_identifier_com_reg[16]_2 ; input \tran_identifier_com_reg[17] ; input \tran_identifier_com_reg[17]_0 ; input \tran_identifier_com_reg[17]_1 ; input \tran_identifier_com_reg[17]_2 ; input \tran_identifier_com_reg[18] ; input \tran_identifier_com_reg[18]_0 ; input \tran_identifier_com_reg[18]_1 ; input \tran_identifier_com_reg[18]_2 ; input \ts_low_internal_reg[19] ; input \ts_low_internal_reg[19]_0 ; input \ts_low_internal_reg[19]_1 ; input \ts_low_internal_reg[19]_2 ; input \ts_low_internal_reg[20] ; input \ts_low_internal_reg[20]_0 ; input \ts_low_internal_reg[20]_1 ; input \ts_low_internal_reg[20]_2 ; input \tran_identifier_com_reg[21] ; input \tran_identifier_com_reg[21]_0 ; input \tran_identifier_com_reg[21]_1 ; input \tran_identifier_com_reg[21]_2 ; input \tran_identifier_com_reg[22] ; input \tran_identifier_com_reg[22]_0 ; input \tran_identifier_com_reg[22]_1 ; input \tran_identifier_com_reg[22]_2 ; input \tran_identifier_com_reg[23] ; input \tran_identifier_com_reg[23]_0 ; input \tran_identifier_com_reg[23]_1 ; input \tran_identifier_com_reg[23]_2 ; input \ts_low_internal_reg[24] ; input \ts_low_internal_reg[24]_0 ; input \ts_low_internal_reg[24]_1 ; input \ts_low_internal_reg[24]_2 ; input \ts_low_internal_reg[25] ; input \ts_low_internal_reg[25]_0 ; input \ts_low_internal_reg[25]_1 ; input \ts_low_internal_reg[25]_2 ; input \ts_low_internal_reg[26] ; input \ts_low_internal_reg[26]_0 ; input \ts_low_internal_reg[26]_1 ; input \ts_low_internal_reg[26]_2 ; input \tran_identifier_com_reg[27] ; input \tran_identifier_com_reg[27]_0 ; input \tran_identifier_com_reg[27]_1 ; input \tran_identifier_com_reg[27]_2 ; input \tran_identifier_com_reg[28] ; input \tran_identifier_com_reg[28]_0 ; input \tran_identifier_com_reg[28]_1 ; input \tran_identifier_com_reg[28]_2 ; input \ts_low_internal_reg[29] ; input \ts_low_internal_reg[29]_0 ; input \ts_low_internal_reg[29]_1 ; input \ts_low_internal_reg[29]_2 ; input \ts_low_internal_reg[30] ; input \ts_low_internal_reg[30]_0 ; input \ts_low_internal_reg[30]_1 ; input \ts_low_internal_reg[30]_2 ; input \ts_low_internal_reg[31] ; input \ts_low_internal_reg[31]_0 ; input \ts_low_internal_reg[31]_1 ; input \ts_low_internal_reg[31]_2 ; input [1:0]\ts_low_internal_reg[31]_3 ; input [1:0]Q; input \FSM_sequential_curr_state_reg[2]_2 ; input \txtb_pointer_meta_q_reg[0]_0 ; input fsm_wait_state_q_reg_1; input \txtb_hw_cmd[lock] ; input tran_frame_valid_com_reg; input \FSM_sequential_curr_state_reg[2]_3 ; input tran_frame_valid_com_reg_0; input tran_frame_valid_com_reg_1; input \FSM_sequential_curr_state[0]_i_2__3_0 ; input destuff_enable_i_7; input tran_frame_valid_com; input \mr_ctrl_out[mode_tttm] ; input [31:0]\FSM_sequential_curr_state_reg[0]_i_9_0 ; input \shift_regs_reg[0] ; input [1:0]last_txtb_index; input \retr_ctr_q_reg[3] ; input \txtb_pointer_meta_q_reg[1]_0 ; input \txtb_pointer_meta_q_reg[4]_0 ; input \txtb_pointer_meta_q_reg[0]_1 ; wire [0:0]ADDRARDADDR; wire [28:0]D; wire [0:0]E; wire \FSM_sequential_curr_state[0]_i_13_n_0 ; wire \FSM_sequential_curr_state[0]_i_14_n_0 ; wire \FSM_sequential_curr_state[0]_i_15_n_0 ; wire \FSM_sequential_curr_state[0]_i_16_n_0 ; wire \FSM_sequential_curr_state[0]_i_17_n_0 ; wire \FSM_sequential_curr_state[0]_i_18_n_0 ; wire \FSM_sequential_curr_state[0]_i_19_n_0 ; wire \FSM_sequential_curr_state[0]_i_1__3_n_0 ; wire \FSM_sequential_curr_state[0]_i_20_n_0 ; wire \FSM_sequential_curr_state[0]_i_22_n_0 ; wire \FSM_sequential_curr_state[0]_i_23_n_0 ; wire \FSM_sequential_curr_state[0]_i_24_n_0 ; wire \FSM_sequential_curr_state[0]_i_25_n_0 ; wire \FSM_sequential_curr_state[0]_i_26_n_0 ; wire \FSM_sequential_curr_state[0]_i_27_n_0 ; wire \FSM_sequential_curr_state[0]_i_28_n_0 ; wire \FSM_sequential_curr_state[0]_i_29_n_0 ; wire \FSM_sequential_curr_state[0]_i_2__3_0 ; wire \FSM_sequential_curr_state[0]_i_2__3_n_0 ; wire \FSM_sequential_curr_state[0]_i_31_n_0 ; wire \FSM_sequential_curr_state[0]_i_32_n_0 ; wire \FSM_sequential_curr_state[0]_i_33_n_0 ; wire \FSM_sequential_curr_state[0]_i_36_n_0 ; wire \FSM_sequential_curr_state[0]_i_37_n_0 ; wire \FSM_sequential_curr_state[0]_i_38_n_0 ; wire \FSM_sequential_curr_state[0]_i_39_n_0 ; wire \FSM_sequential_curr_state[0]_i_40_n_0 ; wire \FSM_sequential_curr_state[0]_i_41_n_0 ; wire \FSM_sequential_curr_state[0]_i_42_n_0 ; wire \FSM_sequential_curr_state[0]_i_43_n_0 ; wire \FSM_sequential_curr_state[0]_i_45_n_0 ; wire \FSM_sequential_curr_state[0]_i_46_n_0 ; wire \FSM_sequential_curr_state[0]_i_47_n_0 ; wire \FSM_sequential_curr_state[0]_i_48_n_0 ; wire \FSM_sequential_curr_state[0]_i_49_n_0 ; wire \FSM_sequential_curr_state[0]_i_4__3_n_0 ; wire \FSM_sequential_curr_state[0]_i_50_n_0 ; wire \FSM_sequential_curr_state[0]_i_51_n_0 ; wire \FSM_sequential_curr_state[0]_i_52_n_0 ; wire \FSM_sequential_curr_state[0]_i_54_n_0 ; wire \FSM_sequential_curr_state[0]_i_55_n_0 ; wire \FSM_sequential_curr_state[0]_i_56_n_0 ; wire \FSM_sequential_curr_state[0]_i_57_n_0 ; wire \FSM_sequential_curr_state[0]_i_59_n_0 ; wire \FSM_sequential_curr_state[0]_i_60_n_0 ; wire \FSM_sequential_curr_state[0]_i_61_n_0 ; wire \FSM_sequential_curr_state[0]_i_62_n_0 ; wire \FSM_sequential_curr_state[0]_i_63_n_0 ; wire \FSM_sequential_curr_state[0]_i_64_n_0 ; wire \FSM_sequential_curr_state[0]_i_65_n_0 ; wire \FSM_sequential_curr_state[0]_i_66_n_0 ; wire \FSM_sequential_curr_state[0]_i_68_n_0 ; wire \FSM_sequential_curr_state[0]_i_69_n_0 ; wire \FSM_sequential_curr_state[0]_i_6__2_n_0 ; wire \FSM_sequential_curr_state[0]_i_70_n_0 ; wire \FSM_sequential_curr_state[0]_i_71_n_0 ; wire \FSM_sequential_curr_state[0]_i_72_n_0 ; wire \FSM_sequential_curr_state[0]_i_73_n_0 ; wire \FSM_sequential_curr_state[0]_i_74_n_0 ; wire \FSM_sequential_curr_state[0]_i_75_n_0 ; wire \FSM_sequential_curr_state[0]_i_76_n_0 ; wire \FSM_sequential_curr_state[0]_i_77_n_0 ; wire \FSM_sequential_curr_state[0]_i_78_n_0 ; wire \FSM_sequential_curr_state[0]_i_79_n_0 ; wire \FSM_sequential_curr_state[0]_i_7_n_0 ; wire \FSM_sequential_curr_state[0]_i_80_n_0 ; wire \FSM_sequential_curr_state[0]_i_81_n_0 ; wire \FSM_sequential_curr_state[0]_i_82_n_0 ; wire \FSM_sequential_curr_state[0]_i_83_n_0 ; wire \FSM_sequential_curr_state[0]_i_84_n_0 ; wire \FSM_sequential_curr_state[0]_i_85_n_0 ; wire \FSM_sequential_curr_state[0]_i_86_n_0 ; wire \FSM_sequential_curr_state[0]_i_87_n_0 ; wire \FSM_sequential_curr_state[0]_i_88_n_0 ; wire \FSM_sequential_curr_state[0]_i_89_n_0 ; wire \FSM_sequential_curr_state[0]_i_90_n_0 ; wire \FSM_sequential_curr_state[0]_i_91_n_0 ; wire \FSM_sequential_curr_state[0]_i_92_n_0 ; wire \FSM_sequential_curr_state[0]_i_93_n_0 ; wire \FSM_sequential_curr_state[0]_i_94_n_0 ; wire \FSM_sequential_curr_state[0]_i_95_n_0 ; wire \FSM_sequential_curr_state[1]_i_1__3_n_0 ; wire \FSM_sequential_curr_state[1]_i_2__3_n_0 ; wire \FSM_sequential_curr_state[2]_i_10__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_12__2_n_0 ; wire \FSM_sequential_curr_state[2]_i_13__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_14_n_0 ; wire \FSM_sequential_curr_state[2]_i_15_n_0 ; wire \FSM_sequential_curr_state[2]_i_16_n_0 ; wire \FSM_sequential_curr_state[2]_i_17_n_0 ; wire \FSM_sequential_curr_state[2]_i_18_n_0 ; wire \FSM_sequential_curr_state[2]_i_19_n_0 ; wire \FSM_sequential_curr_state[2]_i_1__3_n_0 ; wire \FSM_sequential_curr_state[2]_i_2__3_n_0 ; wire \FSM_sequential_curr_state[2]_i_3__3_n_0 ; wire \FSM_sequential_curr_state[2]_i_4__3_n_0 ; wire \FSM_sequential_curr_state[2]_i_5__3_n_0 ; wire \FSM_sequential_curr_state[2]_i_6__1_n_0 ; wire \FSM_sequential_curr_state[2]_i_8__2_n_0 ; wire \FSM_sequential_curr_state[2]_i_9__0_n_0 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_i_12_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_21_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_30_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_35_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_44_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_53_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_58_n_0 ; wire \FSM_sequential_curr_state_reg[0]_i_67_n_0 ; wire [31:0]\FSM_sequential_curr_state_reg[0]_i_9_0 ; wire [2:0]\FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire [1:0]Q; wire buffer_frame_test_w; wire buffer_md_w; wire clk_sys_IBUF_BUFG; wire [2:1]curr_state; wire [0:0]\curr_state_reg[2] ; wire \curr_txtb_index_i_reg[0] ; wire \curr_txtb_index_i_reg[1] ; wire destuff_enable_i_7; wire fsm_wait_state_q_i_1_n_0; wire fsm_wait_state_q_i_2_n_0; wire fsm_wait_state_q_i_3_n_0; wire fsm_wait_state_q_i_6_n_0; wire fsm_wait_state_q_reg_0; wire fsm_wait_state_q_reg_1; wire [0:0]\g_bit[3].reg_value_r_reg[3] ; wire [0:0]\g_bit[3].reg_value_r_reg[3]_0 ; wire [0:0]\g_bit[3].reg_value_r_reg[3]_1 ; wire [0:0]\g_ram_rst_false.ram_memory_reg ; wire [1:0]last_txtb_index; wire \last_txtb_index[1]_i_2_n_0 ; wire \last_txtb_index_reg[1] ; wire less_than00_in; wire less_than1; wire less_than10_in; wire \mr_ctrl_out[mode_tttm] ; wire [0:0]\mr_tst_out[tst_dest_tst_addr] ; wire \retr_ctr_q_reg[3] ; wire \shift_regs_reg[0] ; wire [63:0]timestamp_IBUF; wire \tran_dlc_dbl_buf[3]_i_6_n_0 ; wire \tran_dlc_dbl_buf[3]_i_7_n_0 ; wire \tran_frame_test_dbl_buf_reg[fstc] ; wire \tran_frame_test_dbl_buf_reg[fstc]_0 ; wire \tran_frame_test_dbl_buf_reg[fstc]_1 ; wire \tran_frame_test_dbl_buf_reg[fstc]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][1] ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][2] ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][3] ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][4] ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_2 ; wire tran_frame_valid; wire tran_frame_valid_com; wire tran_frame_valid_com_i_2_n_0; wire tran_frame_valid_com_reg; wire tran_frame_valid_com_reg_0; wire tran_frame_valid_com_reg_1; wire \tran_identifier_com_reg[15] ; wire \tran_identifier_com_reg[15]_0 ; wire \tran_identifier_com_reg[15]_1 ; wire \tran_identifier_com_reg[15]_2 ; wire \tran_identifier_com_reg[16] ; wire \tran_identifier_com_reg[16]_0 ; wire \tran_identifier_com_reg[16]_1 ; wire \tran_identifier_com_reg[16]_2 ; wire \tran_identifier_com_reg[17] ; wire \tran_identifier_com_reg[17]_0 ; wire \tran_identifier_com_reg[17]_1 ; wire \tran_identifier_com_reg[17]_2 ; wire \tran_identifier_com_reg[18] ; wire \tran_identifier_com_reg[18]_0 ; wire \tran_identifier_com_reg[18]_1 ; wire \tran_identifier_com_reg[18]_2 ; wire \tran_identifier_com_reg[21] ; wire \tran_identifier_com_reg[21]_0 ; wire \tran_identifier_com_reg[21]_1 ; wire \tran_identifier_com_reg[21]_2 ; wire \tran_identifier_com_reg[22] ; wire \tran_identifier_com_reg[22]_0 ; wire \tran_identifier_com_reg[22]_1 ; wire \tran_identifier_com_reg[22]_2 ; wire \tran_identifier_com_reg[23] ; wire \tran_identifier_com_reg[23]_0 ; wire \tran_identifier_com_reg[23]_1 ; wire \tran_identifier_com_reg[23]_2 ; wire \tran_identifier_com_reg[27] ; wire \tran_identifier_com_reg[27]_0 ; wire \tran_identifier_com_reg[27]_1 ; wire \tran_identifier_com_reg[27]_2 ; wire \tran_identifier_com_reg[28] ; wire \tran_identifier_com_reg[28]_0 ; wire \tran_identifier_com_reg[28]_1 ; wire \tran_identifier_com_reg[28]_2 ; wire \tran_identifier_com_reg[3] ; wire \tran_identifier_com_reg[3]_0 ; wire \tran_identifier_com_reg[3]_1 ; wire \tran_identifier_com_reg[3]_2 ; wire \tran_identifier_com_reg[4] ; wire \tran_identifier_com_reg[4]_0 ; wire \tran_identifier_com_reg[4]_1 ; wire \tran_identifier_com_reg[4]_2 ; wire \tran_identifier_com_reg[5] ; wire \tran_identifier_com_reg[5]_0 ; wire \tran_identifier_com_reg[5]_1 ; wire \tran_identifier_com_reg[5]_2 ; wire \tran_identifier_com_reg[6] ; wire \tran_identifier_com_reg[6]_0 ; wire \tran_identifier_com_reg[6]_1 ; wire \tran_identifier_com_reg[6]_2 ; wire \ts_low_internal_reg[13] ; wire \ts_low_internal_reg[13]_0 ; wire \ts_low_internal_reg[13]_1 ; wire \ts_low_internal_reg[13]_2 ; wire \ts_low_internal_reg[14] ; wire \ts_low_internal_reg[14]_0 ; wire \ts_low_internal_reg[14]_1 ; wire \ts_low_internal_reg[14]_2 ; wire \ts_low_internal_reg[19] ; wire \ts_low_internal_reg[19]_0 ; wire \ts_low_internal_reg[19]_1 ; wire \ts_low_internal_reg[19]_2 ; wire \ts_low_internal_reg[1] ; wire \ts_low_internal_reg[1]_0 ; wire \ts_low_internal_reg[1]_1 ; wire \ts_low_internal_reg[1]_2 ; wire \ts_low_internal_reg[20] ; wire \ts_low_internal_reg[20]_0 ; wire \ts_low_internal_reg[20]_1 ; wire \ts_low_internal_reg[20]_2 ; wire \ts_low_internal_reg[24] ; wire \ts_low_internal_reg[24]_0 ; wire \ts_low_internal_reg[24]_1 ; wire \ts_low_internal_reg[24]_2 ; wire \ts_low_internal_reg[25] ; wire \ts_low_internal_reg[25]_0 ; wire \ts_low_internal_reg[25]_1 ; wire \ts_low_internal_reg[25]_2 ; wire \ts_low_internal_reg[26] ; wire \ts_low_internal_reg[26]_0 ; wire \ts_low_internal_reg[26]_1 ; wire \ts_low_internal_reg[26]_2 ; wire \ts_low_internal_reg[29] ; wire \ts_low_internal_reg[29]_0 ; wire \ts_low_internal_reg[29]_1 ; wire \ts_low_internal_reg[29]_2 ; wire \ts_low_internal_reg[2] ; wire \ts_low_internal_reg[2]_0 ; wire \ts_low_internal_reg[2]_1 ; wire \ts_low_internal_reg[2]_2 ; wire \ts_low_internal_reg[30] ; wire \ts_low_internal_reg[30]_0 ; wire \ts_low_internal_reg[30]_1 ; wire \ts_low_internal_reg[30]_2 ; wire \ts_low_internal_reg[31] ; wire \ts_low_internal_reg[31]_0 ; wire \ts_low_internal_reg[31]_1 ; wire \ts_low_internal_reg[31]_2 ; wire [1:0]\ts_low_internal_reg[31]_3 ; wire \ts_low_internal_reg[7] ; wire \ts_low_internal_reg[7]_0 ; wire \ts_low_internal_reg[7]_1 ; wire \ts_low_internal_reg[7]_2 ; wire \ts_low_internal_reg[8] ; wire \ts_low_internal_reg[8]_0 ; wire \ts_low_internal_reg[8]_1 ; wire \ts_low_internal_reg[8]_2 ; wire tst_ena; wire tst_ena_0; wire tst_ena_2; wire tst_ena_4; wire \txtb_hw_cmd[lock] ; wire \txtb_pointer_meta_q[4]_i_2_n_0 ; wire \txtb_pointer_meta_q_reg[0] ; wire \txtb_pointer_meta_q_reg[0]_0 ; wire \txtb_pointer_meta_q_reg[0]_1 ; wire \txtb_pointer_meta_q_reg[1] ; wire \txtb_pointer_meta_q_reg[1]_0 ; wire \txtb_pointer_meta_q_reg[4] ; wire \txtb_pointer_meta_q_reg[4]_0 ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_10_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_10_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_12_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_12_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_21_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_21_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_30_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_30_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_35_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_35_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_44_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_44_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_53_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_53_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_58_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_58_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_67_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_67_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_8_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_8_O_UNCONNECTED ; wire [2:0]\NLW_FSM_sequential_curr_state_reg[0]_i_9_CO_UNCONNECTED ; wire [3:0]\NLW_FSM_sequential_curr_state_reg[0]_i_9_O_UNCONNECTED ; assign \FSM_sequential_curr_state_reg[1]_0 = D[2]; assign \FSM_sequential_curr_state_reg[1]_1 = D[1]; assign \FSM_sequential_curr_state_reg[1]_2 = D[8]; assign \FSM_sequential_curr_state_reg[1]_3 = D[7]; assign \FSM_sequential_curr_state_reg[1]_4 = D[14]; assign \FSM_sequential_curr_state_reg[1]_5 = D[13]; assign \FSM_sequential_curr_state_reg[1]_6 = D[20]; assign \FSM_sequential_curr_state_reg[1]_7 = D[19]; assign \FSM_sequential_curr_state_reg[1]_8 = D[26]; assign \FSM_sequential_curr_state_reg[1]_9 = D[25]; LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_13 (.I0(timestamp_IBUF[63]), .I1(\FSM_sequential_curr_state_reg[1]_10 [2]), .I2(timestamp_IBUF[62]), .I3(\FSM_sequential_curr_state_reg[1]_10 [1]), .O(\FSM_sequential_curr_state[0]_i_13_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_14 (.I0(timestamp_IBUF[61]), .I1(\FSM_sequential_curr_state_reg[1]_10 [0]), .I2(timestamp_IBUF[60]), .I3(D[28]), .O(\FSM_sequential_curr_state[0]_i_14_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_15 (.I0(timestamp_IBUF[59]), .I1(D[27]), .I2(timestamp_IBUF[58]), .I3(D[26]), .O(\FSM_sequential_curr_state[0]_i_15_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_16 (.I0(timestamp_IBUF[57]), .I1(D[25]), .I2(timestamp_IBUF[56]), .I3(D[24]), .O(\FSM_sequential_curr_state[0]_i_16_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_17 (.I0(\FSM_sequential_curr_state_reg[1]_10 [2]), .I1(timestamp_IBUF[63]), .I2(\FSM_sequential_curr_state_reg[1]_10 [1]), .I3(timestamp_IBUF[62]), .O(\FSM_sequential_curr_state[0]_i_17_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_18 (.I0(\FSM_sequential_curr_state_reg[1]_10 [0]), .I1(timestamp_IBUF[61]), .I2(D[28]), .I3(timestamp_IBUF[60]), .O(\FSM_sequential_curr_state[0]_i_18_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_19 (.I0(D[26]), .I1(timestamp_IBUF[58]), .I2(D[27]), .I3(timestamp_IBUF[59]), .O(\FSM_sequential_curr_state[0]_i_19_n_0 )); LUT6 #( .INIT(64'hAAAAAAAAAAAAE8B2)) \FSM_sequential_curr_state[0]_i_1__3 (.I0(\FSM_sequential_curr_state[0]_i_2__3_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_3__3_n_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .I4(\FSM_sequential_curr_state[2]_i_5__3_n_0 ), .I5(\FSM_sequential_curr_state[2]_i_6__1_n_0 ), .O(\FSM_sequential_curr_state[0]_i_1__3_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_20 (.I0(D[25]), .I1(timestamp_IBUF[57]), .I2(D[24]), .I3(timestamp_IBUF[56]), .O(\FSM_sequential_curr_state[0]_i_20_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_22 (.I0(timestamp_IBUF[31]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [31]), .I2(timestamp_IBUF[30]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [30]), .O(\FSM_sequential_curr_state[0]_i_22_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_23 (.I0(timestamp_IBUF[29]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [29]), .I2(timestamp_IBUF[28]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [28]), .O(\FSM_sequential_curr_state[0]_i_23_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_24 (.I0(timestamp_IBUF[27]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [27]), .I2(timestamp_IBUF[26]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [26]), .O(\FSM_sequential_curr_state[0]_i_24_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_25 (.I0(timestamp_IBUF[25]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [25]), .I2(timestamp_IBUF[24]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [24]), .O(\FSM_sequential_curr_state[0]_i_25_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_26 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [31]), .I1(timestamp_IBUF[31]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [30]), .I3(timestamp_IBUF[30]), .O(\FSM_sequential_curr_state[0]_i_26_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_27 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [29]), .I1(timestamp_IBUF[29]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [28]), .I3(timestamp_IBUF[28]), .O(\FSM_sequential_curr_state[0]_i_27_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_28 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [27]), .I1(timestamp_IBUF[27]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [26]), .I3(timestamp_IBUF[26]), .O(\FSM_sequential_curr_state[0]_i_28_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_29 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [25]), .I1(timestamp_IBUF[25]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [24]), .I3(timestamp_IBUF[24]), .O(\FSM_sequential_curr_state[0]_i_29_n_0 )); LUT6 #( .INIT(64'h00FF00FB00FF0000)) \FSM_sequential_curr_state[0]_i_2__3 (.I0(\FSM_sequential_curr_state[0]_i_4__3_n_0 ), .I1(\txtb_pointer_meta_q_reg[0]_0 ), .I2(fsm_wait_state_q_reg_0), .I3(\FSM_sequential_curr_state[0]_i_6__2_n_0 ), .I4(fsm_wait_state_q_reg_1), .I5(\FSM_sequential_curr_state[0]_i_7_n_0 ), .O(\FSM_sequential_curr_state[0]_i_2__3_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_31 (.I0(\FSM_sequential_curr_state_reg[1]_10 [2]), .I1(timestamp_IBUF[63]), .I2(\FSM_sequential_curr_state_reg[1]_10 [1]), .I3(timestamp_IBUF[62]), .O(\FSM_sequential_curr_state[0]_i_31_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_32 (.I0(timestamp_IBUF[60]), .I1(D[28]), .I2(timestamp_IBUF[61]), .I3(\FSM_sequential_curr_state_reg[1]_10 [0]), .I4(D[27]), .I5(timestamp_IBUF[59]), .O(\FSM_sequential_curr_state[0]_i_32_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_33 (.I0(D[26]), .I1(timestamp_IBUF[58]), .I2(timestamp_IBUF[56]), .I3(D[24]), .I4(timestamp_IBUF[57]), .I5(D[25]), .O(\FSM_sequential_curr_state[0]_i_33_n_0 )); (* SOFT_HLUTNM = "soft_lutpair348" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[0]_i_34 (.I0(curr_state[2]), .I1(curr_state[1]), .O(\FSM_sequential_curr_state_reg[2]_1 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_36 (.I0(timestamp_IBUF[55]), .I1(D[23]), .I2(timestamp_IBUF[54]), .I3(D[22]), .O(\FSM_sequential_curr_state[0]_i_36_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_37 (.I0(timestamp_IBUF[53]), .I1(D[21]), .I2(timestamp_IBUF[52]), .I3(D[20]), .O(\FSM_sequential_curr_state[0]_i_37_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_38 (.I0(timestamp_IBUF[51]), .I1(D[19]), .I2(timestamp_IBUF[50]), .I3(D[18]), .O(\FSM_sequential_curr_state[0]_i_38_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_39 (.I0(timestamp_IBUF[49]), .I1(D[17]), .I2(timestamp_IBUF[48]), .I3(D[16]), .O(\FSM_sequential_curr_state[0]_i_39_n_0 )); LUT2 #( .INIT(4'h2)) \FSM_sequential_curr_state[0]_i_3__0 (.I0(curr_state[2]), .I1(curr_state[1]), .O(\FSM_sequential_curr_state_reg[2]_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_40 (.I0(D[23]), .I1(timestamp_IBUF[55]), .I2(D[22]), .I3(timestamp_IBUF[54]), .O(\FSM_sequential_curr_state[0]_i_40_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_41 (.I0(D[20]), .I1(timestamp_IBUF[52]), .I2(D[21]), .I3(timestamp_IBUF[53]), .O(\FSM_sequential_curr_state[0]_i_41_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_42 (.I0(D[19]), .I1(timestamp_IBUF[51]), .I2(D[18]), .I3(timestamp_IBUF[50]), .O(\FSM_sequential_curr_state[0]_i_42_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_43 (.I0(D[17]), .I1(timestamp_IBUF[49]), .I2(D[16]), .I3(timestamp_IBUF[48]), .O(\FSM_sequential_curr_state[0]_i_43_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_45 (.I0(timestamp_IBUF[23]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [23]), .I2(timestamp_IBUF[22]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [22]), .O(\FSM_sequential_curr_state[0]_i_45_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_46 (.I0(timestamp_IBUF[21]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [21]), .I2(timestamp_IBUF[20]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [20]), .O(\FSM_sequential_curr_state[0]_i_46_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_47 (.I0(timestamp_IBUF[19]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [19]), .I2(timestamp_IBUF[18]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [18]), .O(\FSM_sequential_curr_state[0]_i_47_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_48 (.I0(timestamp_IBUF[17]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [17]), .I2(timestamp_IBUF[16]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [16]), .O(\FSM_sequential_curr_state[0]_i_48_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_49 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [23]), .I1(timestamp_IBUF[23]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [22]), .I3(timestamp_IBUF[22]), .O(\FSM_sequential_curr_state[0]_i_49_n_0 )); LUT6 #( .INIT(64'hFFFFFBFFFBFFFBFF)) \FSM_sequential_curr_state[0]_i_4__3 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(curr_state[1]), .I2(less_than00_in), .I3(\mr_ctrl_out[mode_tttm] ), .I4(less_than1), .I5(less_than10_in), .O(\FSM_sequential_curr_state[0]_i_4__3_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_50 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [21]), .I1(timestamp_IBUF[21]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [20]), .I3(timestamp_IBUF[20]), .O(\FSM_sequential_curr_state[0]_i_50_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_51 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [19]), .I1(timestamp_IBUF[19]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [18]), .I3(timestamp_IBUF[18]), .O(\FSM_sequential_curr_state[0]_i_51_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_52 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [17]), .I1(timestamp_IBUF[17]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [16]), .I3(timestamp_IBUF[16]), .O(\FSM_sequential_curr_state[0]_i_52_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_54 (.I0(timestamp_IBUF[54]), .I1(D[22]), .I2(timestamp_IBUF[55]), .I3(D[23]), .I4(D[21]), .I5(timestamp_IBUF[53]), .O(\FSM_sequential_curr_state[0]_i_54_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_55 (.I0(D[20]), .I1(timestamp_IBUF[52]), .I2(timestamp_IBUF[50]), .I3(D[18]), .I4(timestamp_IBUF[51]), .I5(D[19]), .O(\FSM_sequential_curr_state[0]_i_55_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_56 (.I0(timestamp_IBUF[48]), .I1(D[16]), .I2(timestamp_IBUF[49]), .I3(D[17]), .I4(D[15]), .I5(timestamp_IBUF[47]), .O(\FSM_sequential_curr_state[0]_i_56_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_57 (.I0(D[14]), .I1(timestamp_IBUF[46]), .I2(timestamp_IBUF[44]), .I3(D[12]), .I4(timestamp_IBUF[45]), .I5(D[13]), .O(\FSM_sequential_curr_state[0]_i_57_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_59 (.I0(timestamp_IBUF[47]), .I1(D[15]), .I2(timestamp_IBUF[46]), .I3(D[14]), .O(\FSM_sequential_curr_state[0]_i_59_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_60 (.I0(timestamp_IBUF[45]), .I1(D[13]), .I2(timestamp_IBUF[44]), .I3(D[12]), .O(\FSM_sequential_curr_state[0]_i_60_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_61 (.I0(timestamp_IBUF[43]), .I1(D[11]), .I2(timestamp_IBUF[42]), .I3(D[10]), .O(\FSM_sequential_curr_state[0]_i_61_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_62 (.I0(timestamp_IBUF[41]), .I1(D[9]), .I2(timestamp_IBUF[40]), .I3(D[8]), .O(\FSM_sequential_curr_state[0]_i_62_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_63 (.I0(D[14]), .I1(timestamp_IBUF[46]), .I2(D[15]), .I3(timestamp_IBUF[47]), .O(\FSM_sequential_curr_state[0]_i_63_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_64 (.I0(D[13]), .I1(timestamp_IBUF[45]), .I2(D[12]), .I3(timestamp_IBUF[44]), .O(\FSM_sequential_curr_state[0]_i_64_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_65 (.I0(D[11]), .I1(timestamp_IBUF[43]), .I2(D[10]), .I3(timestamp_IBUF[42]), .O(\FSM_sequential_curr_state[0]_i_65_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_66 (.I0(D[8]), .I1(timestamp_IBUF[40]), .I2(D[9]), .I3(timestamp_IBUF[41]), .O(\FSM_sequential_curr_state[0]_i_66_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_68 (.I0(timestamp_IBUF[15]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [15]), .I2(timestamp_IBUF[14]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [14]), .O(\FSM_sequential_curr_state[0]_i_68_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_69 (.I0(timestamp_IBUF[13]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [13]), .I2(timestamp_IBUF[12]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [12]), .O(\FSM_sequential_curr_state[0]_i_69_n_0 )); LUT6 #( .INIT(64'h550C0C0C0C0C0CCC)) \FSM_sequential_curr_state[0]_i_6__2 (.I0(tran_frame_valid_com_reg_1), .I1(tran_frame_valid_com_reg), .I2(\txtb_hw_cmd[lock] ), .I3(curr_state[1]), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .I5(curr_state[2]), .O(\FSM_sequential_curr_state[0]_i_6__2_n_0 )); LUT6 #( .INIT(64'hAAABAABFFFABEABF)) \FSM_sequential_curr_state[0]_i_7 (.I0(\txtb_hw_cmd[lock] ), .I1(curr_state[2]), .I2(curr_state[1]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(fsm_wait_state_q_reg_0), .I5(\FSM_sequential_curr_state[0]_i_2__3_0 ), .O(\FSM_sequential_curr_state[0]_i_7_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_70 (.I0(timestamp_IBUF[11]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [11]), .I2(timestamp_IBUF[10]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [10]), .O(\FSM_sequential_curr_state[0]_i_70_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_71 (.I0(timestamp_IBUF[9]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [9]), .I2(timestamp_IBUF[8]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [8]), .O(\FSM_sequential_curr_state[0]_i_71_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_72 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [15]), .I1(timestamp_IBUF[15]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [14]), .I3(timestamp_IBUF[14]), .O(\FSM_sequential_curr_state[0]_i_72_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_73 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [13]), .I1(timestamp_IBUF[13]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [12]), .I3(timestamp_IBUF[12]), .O(\FSM_sequential_curr_state[0]_i_73_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_74 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [11]), .I1(timestamp_IBUF[11]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [10]), .I3(timestamp_IBUF[10]), .O(\FSM_sequential_curr_state[0]_i_74_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_75 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [9]), .I1(timestamp_IBUF[9]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [8]), .I3(timestamp_IBUF[8]), .O(\FSM_sequential_curr_state[0]_i_75_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_76 (.I0(timestamp_IBUF[42]), .I1(D[10]), .I2(timestamp_IBUF[43]), .I3(D[11]), .I4(D[9]), .I5(timestamp_IBUF[41]), .O(\FSM_sequential_curr_state[0]_i_76_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_77 (.I0(D[8]), .I1(timestamp_IBUF[40]), .I2(timestamp_IBUF[38]), .I3(D[6]), .I4(timestamp_IBUF[39]), .I5(D[7]), .O(\FSM_sequential_curr_state[0]_i_77_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_78 (.I0(timestamp_IBUF[36]), .I1(D[4]), .I2(timestamp_IBUF[37]), .I3(D[5]), .I4(D[3]), .I5(timestamp_IBUF[35]), .O(\FSM_sequential_curr_state[0]_i_78_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h9009000000009009)) \FSM_sequential_curr_state[0]_i_79 (.I0(D[2]), .I1(timestamp_IBUF[34]), .I2(timestamp_IBUF[32]), .I3(D[0]), .I4(timestamp_IBUF[33]), .I5(D[1]), .O(\FSM_sequential_curr_state[0]_i_79_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_80 (.I0(timestamp_IBUF[39]), .I1(D[7]), .I2(timestamp_IBUF[38]), .I3(D[6]), .O(\FSM_sequential_curr_state[0]_i_80_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_81 (.I0(timestamp_IBUF[37]), .I1(D[5]), .I2(timestamp_IBUF[36]), .I3(D[4]), .O(\FSM_sequential_curr_state[0]_i_81_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_82 (.I0(timestamp_IBUF[35]), .I1(D[3]), .I2(timestamp_IBUF[34]), .I3(D[2]), .O(\FSM_sequential_curr_state[0]_i_82_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_83 (.I0(timestamp_IBUF[33]), .I1(D[1]), .I2(timestamp_IBUF[32]), .I3(D[0]), .O(\FSM_sequential_curr_state[0]_i_83_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_84 (.I0(D[7]), .I1(timestamp_IBUF[39]), .I2(D[6]), .I3(timestamp_IBUF[38]), .O(\FSM_sequential_curr_state[0]_i_84_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_85 (.I0(D[5]), .I1(timestamp_IBUF[37]), .I2(D[4]), .I3(timestamp_IBUF[36]), .O(\FSM_sequential_curr_state[0]_i_85_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_86 (.I0(D[2]), .I1(timestamp_IBUF[34]), .I2(D[3]), .I3(timestamp_IBUF[35]), .O(\FSM_sequential_curr_state[0]_i_86_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_87 (.I0(D[1]), .I1(timestamp_IBUF[33]), .I2(D[0]), .I3(timestamp_IBUF[32]), .O(\FSM_sequential_curr_state[0]_i_87_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_88 (.I0(timestamp_IBUF[7]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [7]), .I2(timestamp_IBUF[6]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [6]), .O(\FSM_sequential_curr_state[0]_i_88_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_89 (.I0(timestamp_IBUF[5]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [5]), .I2(timestamp_IBUF[4]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [4]), .O(\FSM_sequential_curr_state[0]_i_89_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_90 (.I0(timestamp_IBUF[3]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [3]), .I2(timestamp_IBUF[2]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [2]), .O(\FSM_sequential_curr_state[0]_i_90_n_0 )); LUT4 #( .INIT(16'h22B2)) \FSM_sequential_curr_state[0]_i_91 (.I0(timestamp_IBUF[1]), .I1(\FSM_sequential_curr_state_reg[0]_i_9_0 [1]), .I2(timestamp_IBUF[0]), .I3(\FSM_sequential_curr_state_reg[0]_i_9_0 [0]), .O(\FSM_sequential_curr_state[0]_i_91_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_92 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [7]), .I1(timestamp_IBUF[7]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [6]), .I3(timestamp_IBUF[6]), .O(\FSM_sequential_curr_state[0]_i_92_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_93 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [5]), .I1(timestamp_IBUF[5]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [4]), .I3(timestamp_IBUF[4]), .O(\FSM_sequential_curr_state[0]_i_93_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_94 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [3]), .I1(timestamp_IBUF[3]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [2]), .I3(timestamp_IBUF[2]), .O(\FSM_sequential_curr_state[0]_i_94_n_0 )); LUT4 #( .INIT(16'h9009)) \FSM_sequential_curr_state[0]_i_95 (.I0(\FSM_sequential_curr_state_reg[0]_i_9_0 [1]), .I1(timestamp_IBUF[1]), .I2(\FSM_sequential_curr_state_reg[0]_i_9_0 [0]), .I3(timestamp_IBUF[0]), .O(\FSM_sequential_curr_state[0]_i_95_n_0 )); LUT6 #( .INIT(64'hAAAAAAEBAAAAAA28)) \FSM_sequential_curr_state[1]_i_1__3 (.I0(\FSM_sequential_curr_state[1]_i_2__3_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_3__3_n_0 ), .I2(\FSM_sequential_curr_state[2]_i_4__3_n_0 ), .I3(\FSM_sequential_curr_state[2]_i_5__3_n_0 ), .I4(\FSM_sequential_curr_state[2]_i_6__1_n_0 ), .I5(curr_state[1]), .O(\FSM_sequential_curr_state[1]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF200AA0A0)) \FSM_sequential_curr_state[1]_i_2__3 (.I0(\FSM_sequential_curr_state_reg[2]_2 ), .I1(curr_state[2]), .I2(curr_state[1]), .I3(fsm_wait_state_q_reg_0), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .I5(\FSM_sequential_curr_state[2]_i_8__2_n_0 ), .O(\FSM_sequential_curr_state[1]_i_2__3_n_0 )); LUT6 #( .INIT(64'h00FF00FF000000D7)) \FSM_sequential_curr_state[2]_i_10__0 (.I0(fsm_wait_state_q_reg_0), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(\txtb_hw_cmd[lock] ), .I4(fsm_wait_state_q_reg_1), .I5(tran_frame_valid_com_reg), .O(\FSM_sequential_curr_state[2]_i_10__0_n_0 )); LUT6 #( .INIT(64'h000000000F0F0009)) \FSM_sequential_curr_state[2]_i_12__2 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\txtb_hw_cmd[lock] ), .I3(fsm_wait_state_q_reg_1), .I4(tran_frame_valid_com_reg), .I5(\FSM_sequential_curr_state[2]_i_19_n_0 ), .O(\FSM_sequential_curr_state[2]_i_12__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair343" *) LUT3 #( .INIT(8'h71)) \FSM_sequential_curr_state[2]_i_13__0 (.I0(curr_state[2]), .I1(curr_state[1]), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state[2]_i_13__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair342" *) LUT5 #( .INIT(32'hFFAFC0AF)) \FSM_sequential_curr_state[2]_i_14 (.I0(fsm_wait_state_q_i_6_n_0), .I1(curr_state[2]), .I2(curr_state[1]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(fsm_wait_state_q_reg_0), .O(\FSM_sequential_curr_state[2]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair344" *) LUT5 #( .INIT(32'hB8303000)) \FSM_sequential_curr_state[2]_i_15 (.I0(tran_frame_valid_com_reg_1), .I1(curr_state[2]), .I2(\txtb_hw_cmd[lock] ), .I3(curr_state[1]), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state[2]_i_15_n_0 )); LUT6 #( .INIT(64'hF555F555F454F455)) \FSM_sequential_curr_state[2]_i_16 (.I0(\txtb_hw_cmd[lock] ), .I1(tran_frame_valid_com_reg), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(curr_state[1]), .I4(fsm_wait_state_q_reg_0), .I5(fsm_wait_state_q_reg_1), .O(\FSM_sequential_curr_state[2]_i_16_n_0 )); (* SOFT_HLUTNM = "soft_lutpair347" *) LUT3 #( .INIT(8'h17)) \FSM_sequential_curr_state[2]_i_17 (.I0(curr_state[2]), .I1(curr_state[1]), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state[2]_i_17_n_0 )); LUT6 #( .INIT(64'hC31FC31FC31FF31F)) \FSM_sequential_curr_state[2]_i_18 (.I0(fsm_wait_state_q_i_6_n_0), .I1(curr_state[2]), .I2(curr_state[1]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(fsm_wait_state_q_reg_0), .I5(\txtb_hw_cmd[lock] ), .O(\FSM_sequential_curr_state[2]_i_18_n_0 )); LUT5 #( .INIT(32'h30770044)) \FSM_sequential_curr_state[2]_i_19 (.I0(fsm_wait_state_q_reg_0), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\txtb_hw_cmd[lock] ), .I3(tran_frame_valid_com_reg), .I4(fsm_wait_state_q_i_6_n_0), .O(\FSM_sequential_curr_state[2]_i_19_n_0 )); LUT6 #( .INIT(64'hAAAAAAEBAAAAAA28)) \FSM_sequential_curr_state[2]_i_1__3 (.I0(\FSM_sequential_curr_state[2]_i_2__3_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_3__3_n_0 ), .I2(\FSM_sequential_curr_state[2]_i_4__3_n_0 ), .I3(\FSM_sequential_curr_state[2]_i_5__3_n_0 ), .I4(\FSM_sequential_curr_state[2]_i_6__1_n_0 ), .I5(curr_state[2]), .O(\FSM_sequential_curr_state[2]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF5F200000)) \FSM_sequential_curr_state[2]_i_2__3 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(fsm_wait_state_q_reg_0), .I2(curr_state[1]), .I3(curr_state[2]), .I4(\FSM_sequential_curr_state_reg[2]_2 ), .I5(\FSM_sequential_curr_state[2]_i_8__2_n_0 ), .O(\FSM_sequential_curr_state[2]_i_2__3_n_0 )); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \FSM_sequential_curr_state[2]_i_3__3 (.I0(\FSM_sequential_curr_state[2]_i_9__0_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_10__0_n_0 ), .I2(\FSM_sequential_curr_state_reg[2]_3 ), .I3(curr_state[2]), .I4(curr_state[1]), .I5(\FSM_sequential_curr_state[2]_i_12__2_n_0 ), .O(\FSM_sequential_curr_state[2]_i_3__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair348" *) LUT3 #( .INIT(8'h65)) \FSM_sequential_curr_state[2]_i_4__3 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(curr_state[1]), .I2(curr_state[2]), .O(\FSM_sequential_curr_state[2]_i_4__3_n_0 )); LUT6 #( .INIT(64'hAA65AAAAAA65AA65)) \FSM_sequential_curr_state[2]_i_5__3 (.I0(\FSM_sequential_curr_state[2]_i_13__0_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_14_n_0 ), .I2(\FSM_sequential_curr_state_reg[2]_2 ), .I3(\FSM_sequential_curr_state[2]_i_15_n_0 ), .I4(\FSM_sequential_curr_state[2]_i_16_n_0 ), .I5(curr_state[2]), .O(\FSM_sequential_curr_state[2]_i_5__3_n_0 )); LUT6 #( .INIT(64'h9A99AA999A999A99)) \FSM_sequential_curr_state[2]_i_6__1 (.I0(\FSM_sequential_curr_state[2]_i_17_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_8__2_n_0 ), .I2(\FSM_sequential_curr_state[2]_i_18_n_0 ), .I3(\FSM_sequential_curr_state_reg[2]_2 ), .I4(fsm_wait_state_q_reg_0), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[2]_i_6__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair344" *) LUT5 #( .INIT(32'hEAA82AA8)) \FSM_sequential_curr_state[2]_i_8__2 (.I0(\txtb_hw_cmd[lock] ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(curr_state[1]), .I3(curr_state[2]), .I4(tran_frame_valid_com_reg_1), .O(\FSM_sequential_curr_state[2]_i_8__2_n_0 )); LUT6 #( .INIT(64'h3300030033FF0100)) \FSM_sequential_curr_state[2]_i_9__0 (.I0(fsm_wait_state_q_reg_0), .I1(\txtb_hw_cmd[lock] ), .I2(fsm_wait_state_q_reg_1), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(tran_frame_valid_com_reg), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[2]_i_9__0_n_0 )); (* FSM_ENCODED_STATES = "s_arb_sel_upp_ts:010,s_arb_sel_ftw:011,s_arb_sel_ffw:100,s_arb_sel_idw:101,s_arb_validated:110,s_arb_locked:111,s_arb_sel_low_ts:001,s_arb_idle:000" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_4 ), .D(\FSM_sequential_curr_state[0]_i_1__3_n_0 ), .Q(\FSM_sequential_curr_state_reg[0]_0 )); CARRY4 \FSM_sequential_curr_state_reg[0]_i_10 (.CI(\FSM_sequential_curr_state_reg[0]_i_30_n_0 ), .CO({\NLW_FSM_sequential_curr_state_reg[0]_i_10_CO_UNCONNECTED [3],less_than10_in,\NLW_FSM_sequential_curr_state_reg[0]_i_10_CO_UNCONNECTED [1:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_10_O_UNCONNECTED [3:0]), .S({1'b0,\FSM_sequential_curr_state[0]_i_31_n_0 ,\FSM_sequential_curr_state[0]_i_32_n_0 ,\FSM_sequential_curr_state[0]_i_33_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_12 (.CI(\FSM_sequential_curr_state_reg[0]_i_35_n_0 ), .CO({\FSM_sequential_curr_state_reg[0]_i_12_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_12_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_36_n_0 ,\FSM_sequential_curr_state[0]_i_37_n_0 ,\FSM_sequential_curr_state[0]_i_38_n_0 ,\FSM_sequential_curr_state[0]_i_39_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_12_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_40_n_0 ,\FSM_sequential_curr_state[0]_i_41_n_0 ,\FSM_sequential_curr_state[0]_i_42_n_0 ,\FSM_sequential_curr_state[0]_i_43_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_21 (.CI(\FSM_sequential_curr_state_reg[0]_i_44_n_0 ), .CO({\FSM_sequential_curr_state_reg[0]_i_21_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_21_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_45_n_0 ,\FSM_sequential_curr_state[0]_i_46_n_0 ,\FSM_sequential_curr_state[0]_i_47_n_0 ,\FSM_sequential_curr_state[0]_i_48_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_21_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_49_n_0 ,\FSM_sequential_curr_state[0]_i_50_n_0 ,\FSM_sequential_curr_state[0]_i_51_n_0 ,\FSM_sequential_curr_state[0]_i_52_n_0 })); CARRY4 \FSM_sequential_curr_state_reg[0]_i_30 (.CI(\FSM_sequential_curr_state_reg[0]_i_53_n_0 ), .CO({\FSM_sequential_curr_state_reg[0]_i_30_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_30_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_30_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_54_n_0 ,\FSM_sequential_curr_state[0]_i_55_n_0 ,\FSM_sequential_curr_state[0]_i_56_n_0 ,\FSM_sequential_curr_state[0]_i_57_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_35 (.CI(\FSM_sequential_curr_state_reg[0]_i_58_n_0 ), .CO({\FSM_sequential_curr_state_reg[0]_i_35_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_35_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_59_n_0 ,\FSM_sequential_curr_state[0]_i_60_n_0 ,\FSM_sequential_curr_state[0]_i_61_n_0 ,\FSM_sequential_curr_state[0]_i_62_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_35_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_63_n_0 ,\FSM_sequential_curr_state[0]_i_64_n_0 ,\FSM_sequential_curr_state[0]_i_65_n_0 ,\FSM_sequential_curr_state[0]_i_66_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_44 (.CI(\FSM_sequential_curr_state_reg[0]_i_67_n_0 ), .CO({\FSM_sequential_curr_state_reg[0]_i_44_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_44_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_68_n_0 ,\FSM_sequential_curr_state[0]_i_69_n_0 ,\FSM_sequential_curr_state[0]_i_70_n_0 ,\FSM_sequential_curr_state[0]_i_71_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_44_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_72_n_0 ,\FSM_sequential_curr_state[0]_i_73_n_0 ,\FSM_sequential_curr_state[0]_i_74_n_0 ,\FSM_sequential_curr_state[0]_i_75_n_0 })); CARRY4 \FSM_sequential_curr_state_reg[0]_i_53 (.CI(1'b0), .CO({\FSM_sequential_curr_state_reg[0]_i_53_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_53_CO_UNCONNECTED [2:0]}), .CYINIT(1'b1), .DI({1'b0,1'b0,1'b0,1'b0}), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_53_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_76_n_0 ,\FSM_sequential_curr_state[0]_i_77_n_0 ,\FSM_sequential_curr_state[0]_i_78_n_0 ,\FSM_sequential_curr_state[0]_i_79_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_58 (.CI(1'b0), .CO({\FSM_sequential_curr_state_reg[0]_i_58_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_58_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_80_n_0 ,\FSM_sequential_curr_state[0]_i_81_n_0 ,\FSM_sequential_curr_state[0]_i_82_n_0 ,\FSM_sequential_curr_state[0]_i_83_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_58_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_84_n_0 ,\FSM_sequential_curr_state[0]_i_85_n_0 ,\FSM_sequential_curr_state[0]_i_86_n_0 ,\FSM_sequential_curr_state[0]_i_87_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_67 (.CI(1'b0), .CO({\FSM_sequential_curr_state_reg[0]_i_67_n_0 ,\NLW_FSM_sequential_curr_state_reg[0]_i_67_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_88_n_0 ,\FSM_sequential_curr_state[0]_i_89_n_0 ,\FSM_sequential_curr_state[0]_i_90_n_0 ,\FSM_sequential_curr_state[0]_i_91_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_67_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_92_n_0 ,\FSM_sequential_curr_state[0]_i_93_n_0 ,\FSM_sequential_curr_state[0]_i_94_n_0 ,\FSM_sequential_curr_state[0]_i_95_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_8 (.CI(\FSM_sequential_curr_state_reg[0]_i_12_n_0 ), .CO({less_than00_in,\NLW_FSM_sequential_curr_state_reg[0]_i_8_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_13_n_0 ,\FSM_sequential_curr_state[0]_i_14_n_0 ,\FSM_sequential_curr_state[0]_i_15_n_0 ,\FSM_sequential_curr_state[0]_i_16_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_8_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_17_n_0 ,\FSM_sequential_curr_state[0]_i_18_n_0 ,\FSM_sequential_curr_state[0]_i_19_n_0 ,\FSM_sequential_curr_state[0]_i_20_n_0 })); (* COMPARATOR_THRESHOLD = "11" *) CARRY4 \FSM_sequential_curr_state_reg[0]_i_9 (.CI(\FSM_sequential_curr_state_reg[0]_i_21_n_0 ), .CO({less_than1,\NLW_FSM_sequential_curr_state_reg[0]_i_9_CO_UNCONNECTED [2:0]}), .CYINIT(1'b0), .DI({\FSM_sequential_curr_state[0]_i_22_n_0 ,\FSM_sequential_curr_state[0]_i_23_n_0 ,\FSM_sequential_curr_state[0]_i_24_n_0 ,\FSM_sequential_curr_state[0]_i_25_n_0 }), .O(\NLW_FSM_sequential_curr_state_reg[0]_i_9_O_UNCONNECTED [3:0]), .S({\FSM_sequential_curr_state[0]_i_26_n_0 ,\FSM_sequential_curr_state[0]_i_27_n_0 ,\FSM_sequential_curr_state[0]_i_28_n_0 ,\FSM_sequential_curr_state[0]_i_29_n_0 })); (* FSM_ENCODED_STATES = "s_arb_sel_upp_ts:010,s_arb_sel_ftw:011,s_arb_sel_ffw:100,s_arb_sel_idw:101,s_arb_validated:110,s_arb_locked:111,s_arb_sel_low_ts:001,s_arb_idle:000" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_4 ), .D(\FSM_sequential_curr_state[1]_i_1__3_n_0 ), .Q(curr_state[1])); (* FSM_ENCODED_STATES = "s_arb_sel_upp_ts:010,s_arb_sel_ftw:011,s_arb_sel_ffw:100,s_arb_sel_idw:101,s_arb_validated:110,s_arb_locked:111,s_arb_sel_low_ts:001,s_arb_idle:000" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_4 ), .D(\FSM_sequential_curr_state[2]_i_1__3_n_0 ), .Q(curr_state[2])); (* SOFT_HLUTNM = "soft_lutpair346" *) LUT4 #( .INIT(16'h0200)) \curr_txtb_index_i[1]_i_1 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(tran_frame_valid_com_reg_0), .I2(curr_state[1]), .I3(curr_state[2]), .O(E)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFAB)) fsm_wait_state_q_i_1 (.I0(fsm_wait_state_q_i_2_n_0), .I1(fsm_wait_state_q_i_3_n_0), .I2(fsm_wait_state_q_reg_1), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(buffer_md_w), .I5(buffer_frame_test_w), .O(fsm_wait_state_q_i_1_n_0)); LUT6 #( .INIT(64'h0002020202020233)) fsm_wait_state_q_i_2 (.I0(fsm_wait_state_q_reg_1), .I1(tran_frame_valid_com_reg), .I2(\txtb_hw_cmd[lock] ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(curr_state[1]), .I5(curr_state[2]), .O(fsm_wait_state_q_i_2_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFBFF)) fsm_wait_state_q_i_3 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(curr_state[1]), .I2(curr_state[2]), .I3(fsm_wait_state_q_i_6_n_0), .I4(tran_frame_valid_com_reg), .I5(\txtb_hw_cmd[lock] ), .O(fsm_wait_state_q_i_3_n_0)); LUT5 #( .INIT(32'h55454545)) fsm_wait_state_q_i_6 (.I0(fsm_wait_state_q_reg_0), .I1(less_than00_in), .I2(\mr_ctrl_out[mode_tttm] ), .I3(less_than1), .I4(less_than10_in), .O(fsm_wait_state_q_i_6_n_0)); FDPE fsm_wait_state_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(fsm_wait_state_q_i_1_n_0), .PRE(\FSM_sequential_curr_state_reg[0]_4 ), .Q(fsm_wait_state_q_reg_0)); LUT6 #( .INIT(64'hB888888888888888)) \g_ram_rst_false.ram_memory_reg_i_2__0 (.I0(\mr_tst_out[tst_dest_tst_addr] ), .I1(tst_ena), .I2(\g_ram_rst_false.ram_memory_reg ), .I3(curr_state[2]), .I4(curr_state[1]), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(ADDRARDADDR)); LUT6 #( .INIT(64'hB888888888888888)) \g_ram_rst_false.ram_memory_reg_i_2__1 (.I0(\mr_tst_out[tst_dest_tst_addr] ), .I1(tst_ena_0), .I2(\g_ram_rst_false.ram_memory_reg ), .I3(curr_state[2]), .I4(curr_state[1]), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(\g_bit[3].reg_value_r_reg[3] )); LUT6 #( .INIT(64'hB888888888888888)) \g_ram_rst_false.ram_memory_reg_i_2__2 (.I0(\mr_tst_out[tst_dest_tst_addr] ), .I1(tst_ena_2), .I2(\g_ram_rst_false.ram_memory_reg ), .I3(curr_state[2]), .I4(curr_state[1]), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(\g_bit[3].reg_value_r_reg[3]_0 )); LUT6 #( .INIT(64'hB888888888888888)) \g_ram_rst_false.ram_memory_reg_i_2__3 (.I0(\mr_tst_out[tst_dest_tst_addr] ), .I1(tst_ena_4), .I2(\g_ram_rst_false.ram_memory_reg ), .I3(curr_state[2]), .I4(curr_state[1]), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(\g_bit[3].reg_value_r_reg[3]_1 )); (* SOFT_HLUTNM = "soft_lutpair342" *) LUT3 #( .INIT(8'h80)) \g_ram_rst_false.ram_memory_reg_i_48__2 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(curr_state[1]), .I2(curr_state[2]), .O(\FSM_sequential_curr_state_reg[0]_2 )); (* SOFT_HLUTNM = "soft_lutpair349" *) LUT3 #( .INIT(8'hB8)) \last_txtb_index[0]_i_1 (.I0(Q[0]), .I1(\last_txtb_index[1]_i_2_n_0 ), .I2(last_txtb_index[0]), .O(\curr_txtb_index_i_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair349" *) LUT3 #( .INIT(8'hB8)) \last_txtb_index[1]_i_1 (.I0(Q[1]), .I1(\last_txtb_index[1]_i_2_n_0 ), .I2(last_txtb_index[1]), .O(\curr_txtb_index_i_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair347" *) LUT4 #( .INIT(16'h7E00)) \last_txtb_index[1]_i_2 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(curr_state[2]), .I2(curr_state[1]), .I3(\txtb_hw_cmd[lock] ), .O(\last_txtb_index[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF6FF60000)) \retr_ctr_q[3]_i_3 (.I0(last_txtb_index[1]), .I1(Q[1]), .I2(last_txtb_index[0]), .I3(Q[0]), .I4(\last_txtb_index[1]_i_2_n_0 ), .I5(\retr_ctr_q_reg[3] ), .O(\last_txtb_index_reg[1] )); LUT2 #( .INIT(4'h8)) \shift_regs[0]_i_1 (.I0(D[24]), .I1(\shift_regs_reg[0] ), .O(\curr_state_reg[2] )); LUT6 #( .INIT(64'hAACCF0FFAACCF000)) tran_brs_dbl_buf_i_1 (.I0(\tran_frame_test_dbl_buf_reg[tprm][1] ), .I1(\tran_frame_test_dbl_buf_reg[tprm][1]_0 ), .I2(\tran_frame_test_dbl_buf_reg[tprm][1]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_frame_test_dbl_buf_reg[tprm][1]_2 ), .O(D[9])); LUT6 #( .INIT(64'hAAFFF0CCAA00F0CC)) \tran_dlc_dbl_buf[0]_i_1 (.I0(\tran_frame_test_dbl_buf_reg[fstc] ), .I1(\tran_frame_test_dbl_buf_reg[fstc]_0 ), .I2(\tran_frame_test_dbl_buf_reg[fstc]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_frame_test_dbl_buf_reg[fstc]_2 ), .O(D[0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AACCFFF0AACC00)) \tran_dlc_dbl_buf[1]_i_2 (.I0(\ts_low_internal_reg[1] ), .I1(\ts_low_internal_reg[1]_0 ), .I2(\ts_low_internal_reg[1]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[1]_2 ), .O(D[1])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hAACCFFF0AACC00F0)) \tran_dlc_dbl_buf[2]_i_2 (.I0(\ts_low_internal_reg[2] ), .I1(\ts_low_internal_reg[2]_0 ), .I2(\ts_low_internal_reg[2]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[2]_2 ), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair345" *) LUT4 #( .INIT(16'h0010)) \tran_dlc_dbl_buf[3]_i_1 (.I0(tran_frame_valid_com_reg_0), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(curr_state[2]), .I3(curr_state[1]), .O(buffer_md_w)); LUT6 #( .INIT(64'hAAFFF0CCAA00F0CC)) \tran_dlc_dbl_buf[3]_i_2 (.I0(\tran_identifier_com_reg[3] ), .I1(\tran_identifier_com_reg[3]_0 ), .I2(\tran_identifier_com_reg[3]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_identifier_com_reg[3]_2 ), .O(D[3])); LUT5 #( .INIT(32'hCAAAAAAA)) \tran_dlc_dbl_buf[3]_i_6 (.I0(\ts_low_internal_reg[31]_3 [1]), .I1(Q[1]), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(curr_state[1]), .I4(curr_state[2]), .O(\tran_dlc_dbl_buf[3]_i_6_n_0 )); LUT5 #( .INIT(32'hCAAAAAAA)) \tran_dlc_dbl_buf[3]_i_7 (.I0(\ts_low_internal_reg[31]_3 [0]), .I1(Q[0]), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(curr_state[1]), .I4(curr_state[2]), .O(\tran_dlc_dbl_buf[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair345" *) LUT4 #( .INIT(16'h0400)) \tran_frame_test_dbl_buf[fstc]_i_1 (.I0(tran_frame_valid_com_reg_0), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(curr_state[2]), .I3(curr_state[1]), .O(buffer_frame_test_w)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AACCFFF0AACC00)) tran_frame_type_dbl_buf_i_2 (.I0(\ts_low_internal_reg[7] ), .I1(\ts_low_internal_reg[7]_0 ), .I2(\ts_low_internal_reg[7]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[7]_2 ), .O(D[7])); LUT6 #( .INIT(64'h0020FFFF00200020)) tran_frame_valid_com_i_1 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(tran_frame_valid_com_reg_0), .I2(curr_state[2]), .I3(curr_state[1]), .I4(tran_frame_valid_com_i_2_n_0), .I5(tran_frame_valid_com), .O(\FSM_sequential_curr_state_reg[0]_3 )); LUT6 #( .INIT(64'h40007FFC40004000)) tran_frame_valid_com_i_2 (.I0(tran_frame_valid_com_reg_1), .I1(curr_state[2]), .I2(curr_state[1]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\txtb_hw_cmd[lock] ), .I5(tran_frame_valid_com_reg), .O(tran_frame_valid_com_i_2_n_0)); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) tran_ident_type_dbl_buf_i_1 (.I0(\tran_identifier_com_reg[6] ), .I1(\tran_identifier_com_reg[6]_0 ), .I2(\tran_identifier_com_reg[6]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[6]_2 ), .O(D[6])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \tran_identifier_com[10]_i_1 (.I0(\tran_frame_test_dbl_buf_reg[tprm][2] ), .I1(\tran_frame_test_dbl_buf_reg[tprm][2]_0 ), .I2(\tran_frame_test_dbl_buf_reg[tprm][2]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_frame_test_dbl_buf_reg[tprm][2]_2 ), .O(D[10])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \tran_identifier_com[11]_i_1 (.I0(\tran_frame_test_dbl_buf_reg[tprm][3] ), .I1(\tran_frame_test_dbl_buf_reg[tprm][3]_0 ), .I2(\tran_frame_test_dbl_buf_reg[tprm][3]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_frame_test_dbl_buf_reg[tprm][3]_2 ), .O(D[11])); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \tran_identifier_com[12]_i_1 (.I0(\tran_frame_test_dbl_buf_reg[tprm][4] ), .I1(\tran_frame_test_dbl_buf_reg[tprm][4]_0 ), .I2(\tran_frame_test_dbl_buf_reg[tprm][4]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_frame_test_dbl_buf_reg[tprm][4]_2 ), .O(D[12])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AACCFFF0AACC00)) \tran_identifier_com[13]_i_2 (.I0(\ts_low_internal_reg[13] ), .I1(\ts_low_internal_reg[13]_0 ), .I2(\ts_low_internal_reg[13]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[13]_2 ), .O(D[13])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AAFFCCF0AA00CC)) \tran_identifier_com[14]_i_2 (.I0(\ts_low_internal_reg[14] ), .I1(\ts_low_internal_reg[14]_0 ), .I2(\ts_low_internal_reg[14]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[14]_2 ), .O(D[14])); LUT6 #( .INIT(64'hAAFFF0CCAA00F0CC)) \tran_identifier_com[15]_i_1 (.I0(\tran_identifier_com_reg[15] ), .I1(\tran_identifier_com_reg[15]_0 ), .I2(\tran_identifier_com_reg[15]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_identifier_com_reg[15]_2 ), .O(D[15])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \tran_identifier_com[16]_i_1 (.I0(\tran_identifier_com_reg[16] ), .I1(\tran_identifier_com_reg[16]_0 ), .I2(\tran_identifier_com_reg[16]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[16]_2 ), .O(D[16])); LUT6 #( .INIT(64'hAACCF0FFAACCF000)) \tran_identifier_com[17]_i_1 (.I0(\tran_identifier_com_reg[17] ), .I1(\tran_identifier_com_reg[17]_0 ), .I2(\tran_identifier_com_reg[17]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_identifier_com_reg[17]_2 ), .O(D[17])); LUT6 #( .INIT(64'hAACCF0FFAACCF000)) \tran_identifier_com[18]_i_1 (.I0(\tran_identifier_com_reg[18] ), .I1(\tran_identifier_com_reg[18]_0 ), .I2(\tran_identifier_com_reg[18]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_identifier_com_reg[18]_2 ), .O(D[18])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AACCFFF0AACC00)) \tran_identifier_com[19]_i_2 (.I0(\ts_low_internal_reg[19] ), .I1(\ts_low_internal_reg[19]_0 ), .I2(\ts_low_internal_reg[19]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[19]_2 ), .O(D[19])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AAFFCCF0AA00CC)) \tran_identifier_com[20]_i_2 (.I0(\ts_low_internal_reg[20] ), .I1(\ts_low_internal_reg[20]_0 ), .I2(\ts_low_internal_reg[20]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[20]_2 ), .O(D[20])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \tran_identifier_com[21]_i_1 (.I0(\tran_identifier_com_reg[21] ), .I1(\tran_identifier_com_reg[21]_0 ), .I2(\tran_identifier_com_reg[21]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[21]_2 ), .O(D[21])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \tran_identifier_com[22]_i_1 (.I0(\tran_identifier_com_reg[22] ), .I1(\tran_identifier_com_reg[22]_0 ), .I2(\tran_identifier_com_reg[22]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[22]_2 ), .O(D[22])); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \tran_identifier_com[23]_i_1 (.I0(\tran_identifier_com_reg[23] ), .I1(\tran_identifier_com_reg[23]_0 ), .I2(\tran_identifier_com_reg[23]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[23]_2 ), .O(D[23])); LUT6 #( .INIT(64'hAACCF0FFAACCF000)) \tran_identifier_com[24]_i_1 (.I0(\ts_low_internal_reg[24] ), .I1(\ts_low_internal_reg[24]_0 ), .I2(\ts_low_internal_reg[24]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\ts_low_internal_reg[24]_2 ), .O(D[24])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AACCFFF0AACC00)) \tran_identifier_com[25]_i_2 (.I0(\ts_low_internal_reg[25] ), .I1(\ts_low_internal_reg[25]_0 ), .I2(\ts_low_internal_reg[25]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[25]_2 ), .O(D[25])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hAACCFFF0AACC00F0)) \tran_identifier_com[26]_i_2 (.I0(\ts_low_internal_reg[26] ), .I1(\ts_low_internal_reg[26]_0 ), .I2(\ts_low_internal_reg[26]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[26]_2 ), .O(D[26])); LUT6 #( .INIT(64'hAAFFF0CCAA00F0CC)) \tran_identifier_com[27]_i_1 (.I0(\tran_identifier_com_reg[27] ), .I1(\tran_identifier_com_reg[27]_0 ), .I2(\tran_identifier_com_reg[27]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\tran_identifier_com_reg[27]_2 ), .O(D[27])); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \tran_identifier_com[28]_i_1 (.I0(\tran_identifier_com_reg[28] ), .I1(\tran_identifier_com_reg[28]_0 ), .I2(\tran_identifier_com_reg[28]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[28]_2 ), .O(D[28])); LUT6 #( .INIT(64'hF0FFCCAAF000CCAA)) \tran_identifier_com[4]_i_1 (.I0(\tran_identifier_com_reg[4] ), .I1(\tran_identifier_com_reg[4]_0 ), .I2(\tran_identifier_com_reg[4]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[4]_2 ), .O(D[4])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hF0AAFFCCF0AA00CC)) \tran_identifier_com[8]_i_2 (.I0(\ts_low_internal_reg[8] ), .I1(\ts_low_internal_reg[8]_0 ), .I2(\ts_low_internal_reg[8]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[8]_2 ), .O(D[8])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) tran_is_rtr_dbl_buf_i_1 (.I0(\tran_identifier_com_reg[5] ), .I1(\tran_identifier_com_reg[5]_0 ), .I2(\tran_identifier_com_reg[5]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\tran_identifier_com_reg[5]_2 ), .O(D[5])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \ts_low_internal[29]_i_1 (.I0(\ts_low_internal_reg[29] ), .I1(\ts_low_internal_reg[29]_0 ), .I2(\ts_low_internal_reg[29]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[29]_2 ), .O(\FSM_sequential_curr_state_reg[1]_10 [0])); LUT6 #( .INIT(64'hF0FFAACCF000AACC)) \ts_low_internal[30]_i_1 (.I0(\ts_low_internal_reg[30] ), .I1(\ts_low_internal_reg[30]_0 ), .I2(\ts_low_internal_reg[30]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I5(\ts_low_internal_reg[30]_2 ), .O(\FSM_sequential_curr_state_reg[1]_10 [1])); (* SOFT_HLUTNM = "soft_lutpair346" *) LUT4 #( .INIT(16'h0004)) \ts_low_internal[31]_i_1 (.I0(tran_frame_valid_com_reg_0), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(curr_state[1]), .I3(curr_state[2]), .O(\FSM_sequential_curr_state_reg[0]_1 )); LUT6 #( .INIT(64'hAAFFF0CCAA00F0CC)) \ts_low_internal[31]_i_2 (.I0(\ts_low_internal_reg[31] ), .I1(\ts_low_internal_reg[31]_0 ), .I2(\ts_low_internal_reg[31]_1 ), .I3(\tran_dlc_dbl_buf[3]_i_6_n_0 ), .I4(\tran_dlc_dbl_buf[3]_i_7_n_0 ), .I5(\ts_low_internal_reg[31]_2 ), .O(\FSM_sequential_curr_state_reg[1]_10 [2])); (* SOFT_HLUTNM = "soft_lutpair343" *) LUT5 #( .INIT(32'hFF808080)) \txtb_hw_cmd_q[lock]_i_6 (.I0(curr_state[2]), .I1(curr_state[1]), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(destuff_enable_i_7), .I4(tran_frame_valid_com), .O(tran_frame_valid)); LUT6 #( .INIT(64'hFFF0FFF4FFF0FFF0)) \txtb_pointer_meta_q[0]_i_1 (.I0(fsm_wait_state_q_i_2_n_0), .I1(\txtb_pointer_meta_q[4]_i_2_n_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(buffer_md_w), .I4(buffer_frame_test_w), .I5(\txtb_pointer_meta_q_reg[0]_1 ), .O(\txtb_pointer_meta_q_reg[0] )); LUT6 #( .INIT(64'hFAFAFAFEFAFAFAFA)) \txtb_pointer_meta_q[1]_i_1 (.I0(fsm_wait_state_q_i_2_n_0), .I1(\txtb_pointer_meta_q[4]_i_2_n_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(buffer_md_w), .I4(buffer_frame_test_w), .I5(\txtb_pointer_meta_q_reg[1]_0 ), .O(\txtb_pointer_meta_q_reg[1] )); LUT6 #( .INIT(64'h0000000500000001)) \txtb_pointer_meta_q[4]_i_1 (.I0(fsm_wait_state_q_i_2_n_0), .I1(\txtb_pointer_meta_q[4]_i_2_n_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(buffer_md_w), .I4(buffer_frame_test_w), .I5(\txtb_pointer_meta_q_reg[4]_0 ), .O(\txtb_pointer_meta_q_reg[4] )); LUT6 #( .INIT(64'hFFFFFFFFFFBFFFFF)) \txtb_pointer_meta_q[4]_i_2 (.I0(fsm_wait_state_q_reg_1), .I1(\txtb_pointer_meta_q_reg[0]_0 ), .I2(fsm_wait_state_q_i_6_n_0), .I3(curr_state[2]), .I4(curr_state[1]), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(\txtb_pointer_meta_q[4]_i_2_n_0 )); endmodule module txarb_top (fsm_wait_state_q, \FSM_sequential_curr_state_reg[1] , tran_is_rtr, tran_ident_type, tran_frame_type, tran_brs, \tran_frame_test[fstc] , \tran_frame_test[fcrc] , ADDRARDADDR, \FSM_sequential_curr_state_reg[0] , \curr_txtb_index_i_reg[0]_0 , Q, \g_bit[3].reg_value_r_reg[3] , \curr_txtb_index_i_reg[0]_1 , \curr_txtb_index_i_reg[1]_0 , \g_bit[3].reg_value_r_reg[3]_0 , \curr_txtb_index_i_reg[1]_1 , \g_bit[3].reg_value_r_reg[3]_1 , \curr_txtb_index_i_reg[0]_2 , \curr_txtb_index_i_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[2] , tran_frame_valid, \FSM_sequential_curr_state_reg[2]_0 , txtb_hw_cmd_cs, \curr_state_reg[2] , \tran_identifier_com_reg[25]_0 , \tran_identifier_com_reg[24]_0 , \tran_identifier_com_reg[26]_0 , \tran_identifier_com_reg[27]_0 , \tran_identifier_com_reg[28]_0 , \last_txtb_index_reg[1]_0 , \tran_dlc_com_reg[3]_0 , \tran_frame_test_reg[fstc]_0 , \tran_identifier_com_reg[6]_0 , \tran_identifier_com_reg[5]_0 , \tran_identifier_com_reg[4]_0 , \tran_identifier_com_reg[3]_0 , \tran_identifier_com_reg[2]_0 , \tran_identifier_com_reg[1]_0 , \tran_identifier_com_reg[0]_0 , \crc_q_reg[0] , tran_frame_type_com_reg_0, \crc_q_reg[1] , \tran_frame_test_reg[fcrc]_0 , \tran_frame_test_reg[tprm][1]_0 , \tran_frame_test_reg[tprm][0]_0 , \tran_frame_test_reg[tprm][1]_1 , \tran_frame_test_reg[tprm][4]_0 , \tran_frame_test_reg[tprm][1]_2 , \tran_frame_test_reg[tprm][1]_3 , \tran_frame_test_reg[tprm][0]_1 , \tran_frame_test_reg[tprm][1]_4 , \tran_frame_test_reg[tprm][2]_0 , \tran_dlc_com_reg[3]_1 , \tran_dlc_com_reg[3]_2 , \compl_ctr_q_reg[7] , \tran_dlc_com_reg[3]_3 , \tran_dlc_com_reg[0]_0 , \tran_dlc_com_reg[0]_1 , \tran_dlc_com_reg[3]_4 , \tran_dlc_com_reg[1]_0 , \g_bit[0].reg_value_r_reg[0] , \tran_frame_test_reg[tprm][3]_0 , \tran_frame_test_reg[tprm][3]_1 , \g_bit[0].reg_value_r_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_1 , \tran_frame_test_reg[tprm][2]_1 , \g_bit[0].reg_value_r_reg[0]_2 , \g_bit[0].reg_value_r_reg[0]_3 , \FSM_sequential_curr_state_reg[0]_0 , \g_bit[0].reg_value_r_reg[0]_4 , \tran_frame_test_reg[tprm][0]_2 , \bst_ctr_q_reg[2] , \select_buf_index_reg_reg[1]_0 , \txtb_pointer_meta_q_reg[1]_0 , \txtb_pointer_meta_q_reg[4]_0 , \txtb_pointer_meta_q_reg[0]_0 , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[0]_1 , \mr_tst_out[tst_dest_tst_addr] , tst_ena, \g_ram_rst_false.ram_memory_reg , curr_state, \FSM_sequential_curr_state[0]_i_2 , \txtb_hw_cmd[valid] , \txtb_hw_cmd[failed] , tst_ena_0, \FSM_sequential_curr_state_reg[2]_1 , curr_state_1, tx_command_txce_valid, tx_command_txcr_valid, \txtb_hw_cmd[lock] , tst_ena_2, curr_state_3, \FSM_sequential_curr_state[0]_i_2__1 , tst_ena_4, \txtb_state[3] , curr_state_5, tx_command_txce_valid_6, tx_command_txcr_valid_7, timestamp_IBUF, \tran_frame_test_dbl_buf_reg[fstc]_0 , \tran_frame_test_dbl_buf_reg[fstc]_1 , \tran_frame_test_dbl_buf_reg[fstc]_2 , \tran_frame_test_dbl_buf_reg[fstc]_3 , \ts_low_internal_reg[1]_0 , \ts_low_internal_reg[1]_1 , \ts_low_internal_reg[1]_2 , \ts_low_internal_reg[1]_3 , \ts_low_internal_reg[2]_0 , \ts_low_internal_reg[2]_1 , \ts_low_internal_reg[2]_2 , \ts_low_internal_reg[2]_3 , \tran_identifier_com_reg[3]_1 , \tran_identifier_com_reg[3]_2 , \tran_identifier_com_reg[3]_3 , \tran_identifier_com_reg[3]_4 , \tran_identifier_com_reg[4]_1 , \tran_identifier_com_reg[4]_2 , \tran_identifier_com_reg[4]_3 , \tran_identifier_com_reg[4]_4 , \tran_identifier_com_reg[5]_1 , \tran_identifier_com_reg[5]_2 , \tran_identifier_com_reg[5]_3 , \tran_identifier_com_reg[5]_4 , \tran_identifier_com_reg[6]_1 , \tran_identifier_com_reg[6]_2 , \tran_identifier_com_reg[6]_3 , \tran_identifier_com_reg[6]_4 , \ts_low_internal_reg[7]_0 , \ts_low_internal_reg[7]_1 , \ts_low_internal_reg[7]_2 , \ts_low_internal_reg[7]_3 , \ts_low_internal_reg[8]_0 , \ts_low_internal_reg[8]_1 , \ts_low_internal_reg[8]_2 , \ts_low_internal_reg[8]_3 , \tran_frame_test_dbl_buf_reg[tprm][1]_0 , \tran_frame_test_dbl_buf_reg[tprm][1]_1 , \tran_frame_test_dbl_buf_reg[tprm][1]_2 , \tran_frame_test_dbl_buf_reg[tprm][1]_3 , \tran_frame_test_dbl_buf_reg[tprm][2]_0 , \tran_frame_test_dbl_buf_reg[tprm][2]_1 , \tran_frame_test_dbl_buf_reg[tprm][2]_2 , \tran_frame_test_dbl_buf_reg[tprm][2]_3 , \tran_frame_test_dbl_buf_reg[tprm][3]_0 , \tran_frame_test_dbl_buf_reg[tprm][3]_1 , \tran_frame_test_dbl_buf_reg[tprm][3]_2 , \tran_frame_test_dbl_buf_reg[tprm][3]_3 , \tran_frame_test_dbl_buf_reg[tprm][4]_0 , \tran_frame_test_dbl_buf_reg[tprm][4]_1 , \tran_frame_test_dbl_buf_reg[tprm][4]_2 , \tran_frame_test_dbl_buf_reg[tprm][4]_3 , \ts_low_internal_reg[13]_0 , \ts_low_internal_reg[13]_1 , \ts_low_internal_reg[13]_2 , \ts_low_internal_reg[13]_3 , \ts_low_internal_reg[14]_0 , \ts_low_internal_reg[14]_1 , \ts_low_internal_reg[14]_2 , \ts_low_internal_reg[14]_3 , \tran_identifier_com_reg[15]_0 , \tran_identifier_com_reg[15]_1 , \tran_identifier_com_reg[15]_2 , \tran_identifier_com_reg[15]_3 , \tran_identifier_com_reg[16]_0 , \tran_identifier_com_reg[16]_1 , \tran_identifier_com_reg[16]_2 , \tran_identifier_com_reg[16]_3 , \tran_identifier_com_reg[17]_0 , \tran_identifier_com_reg[17]_1 , \tran_identifier_com_reg[17]_2 , \tran_identifier_com_reg[17]_3 , \tran_identifier_com_reg[18]_0 , \tran_identifier_com_reg[18]_1 , \tran_identifier_com_reg[18]_2 , \tran_identifier_com_reg[18]_3 , \ts_low_internal_reg[19]_0 , \ts_low_internal_reg[19]_1 , \ts_low_internal_reg[19]_2 , \ts_low_internal_reg[19]_3 , \ts_low_internal_reg[20]_0 , \ts_low_internal_reg[20]_1 , \ts_low_internal_reg[20]_2 , \ts_low_internal_reg[20]_3 , \tran_identifier_com_reg[21]_0 , \tran_identifier_com_reg[21]_1 , \tran_identifier_com_reg[21]_2 , \tran_identifier_com_reg[21]_3 , \tran_identifier_com_reg[22]_0 , \tran_identifier_com_reg[22]_1 , \tran_identifier_com_reg[22]_2 , \tran_identifier_com_reg[22]_3 , \tran_identifier_com_reg[23]_0 , \tran_identifier_com_reg[23]_1 , \tran_identifier_com_reg[23]_2 , \tran_identifier_com_reg[23]_3 , \ts_low_internal_reg[24]_0 , \ts_low_internal_reg[24]_1 , \ts_low_internal_reg[24]_2 , \ts_low_internal_reg[24]_3 , \ts_low_internal_reg[25]_0 , \ts_low_internal_reg[25]_1 , \ts_low_internal_reg[25]_2 , \ts_low_internal_reg[25]_3 , \ts_low_internal_reg[26]_0 , \ts_low_internal_reg[26]_1 , \ts_low_internal_reg[26]_2 , \ts_low_internal_reg[26]_3 , \tran_identifier_com_reg[27]_1 , \tran_identifier_com_reg[27]_2 , \tran_identifier_com_reg[27]_3 , \tran_identifier_com_reg[27]_4 , \tran_identifier_com_reg[28]_1 , \tran_identifier_com_reg[28]_2 , \tran_identifier_com_reg[28]_3 , \tran_identifier_com_reg[28]_4 , \ts_low_internal_reg[29]_0 , \ts_low_internal_reg[29]_1 , \ts_low_internal_reg[29]_2 , \ts_low_internal_reg[29]_3 , \ts_low_internal_reg[30]_0 , \ts_low_internal_reg[30]_1 , \ts_low_internal_reg[30]_2 , \ts_low_internal_reg[30]_3 , \ts_low_internal_reg[31]_0 , \ts_low_internal_reg[31]_1 , \ts_low_internal_reg[31]_2 , \ts_low_internal_reg[31]_3 , D, \FSM_sequential_curr_state_reg[2]_2 , \txtb_pointer_meta_q_reg[0]_1 , fsm_wait_state_q_reg, tran_frame_valid_com_reg_0, \FSM_sequential_curr_state_reg[2]_3 , tran_frame_valid_com_reg_1, tran_frame_valid_com_reg_2, \FSM_sequential_curr_state[0]_i_2__3 , txtb_available, \mr_ctrl_out[mode_tttm] , \shift_regs_reg[0] , \shift_regs_reg[28] , \shift_regs_reg[28]_0 , \retr_ctr_q_reg[3] , \shift_regs[31]_i_21_0 , \mr_ctrl_out[mode_tstm] , \shift_regs_reg[28]_1 , \cc_stat[bst_ctr] , \shift_regs_reg[12] , \shift_regs_reg[11] , \shift_regs_reg[17] , \shift_regs_reg[18] , \shift_regs_reg[19] , \shift_regs_reg[24] , \shift_regs_reg[25] , \shift_regs_reg[26] , \shift_regs_reg[27] , \cc_stat[is_transmitter] , \mr_ctrl_out[mode_fde] , \shift_regs[17]_i_4 , \ctrl_ctr_q[4]_i_6 , \txtb_ptr_q_reg[4] , \txtb_ptr_q_reg[4]_0 , \curr_state[0]_i_8 , \mr_ctrl_out[settings_nisofd] ); output fsm_wait_state_q; output [20:0]\FSM_sequential_curr_state_reg[1] ; output tran_is_rtr; output tran_ident_type; output tran_frame_type; output tran_brs; output \tran_frame_test[fstc] ; output \tran_frame_test[fcrc] ; output [0:0]ADDRARDADDR; output [0:0]\FSM_sequential_curr_state_reg[0] ; output \curr_txtb_index_i_reg[0]_0 ; output [1:0]Q; output [0:0]\g_bit[3].reg_value_r_reg[3] ; output \curr_txtb_index_i_reg[0]_1 ; output \curr_txtb_index_i_reg[1]_0 ; output [0:0]\g_bit[3].reg_value_r_reg[3]_0 ; output \curr_txtb_index_i_reg[1]_1 ; output [0:0]\g_bit[3].reg_value_r_reg[3]_1 ; output \curr_txtb_index_i_reg[0]_2 ; output \curr_txtb_index_i_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[2] ; output tran_frame_valid; output \FSM_sequential_curr_state_reg[2]_0 ; output [3:0]txtb_hw_cmd_cs; output [0:0]\curr_state_reg[2] ; output \tran_identifier_com_reg[25]_0 ; output [13:0]\tran_identifier_com_reg[24]_0 ; output \tran_identifier_com_reg[26]_0 ; output \tran_identifier_com_reg[27]_0 ; output \tran_identifier_com_reg[28]_0 ; output \last_txtb_index_reg[1]_0 ; output [2:0]\tran_dlc_com_reg[3]_0 ; output \tran_frame_test_reg[fstc]_0 ; output \tran_identifier_com_reg[6]_0 ; output \tran_identifier_com_reg[5]_0 ; output \tran_identifier_com_reg[4]_0 ; output \tran_identifier_com_reg[3]_0 ; output \tran_identifier_com_reg[2]_0 ; output \tran_identifier_com_reg[1]_0 ; output \tran_identifier_com_reg[0]_0 ; output \crc_q_reg[0] ; output tran_frame_type_com_reg_0; output \crc_q_reg[1] ; output \tran_frame_test_reg[fcrc]_0 ; output \tran_frame_test_reg[tprm][1]_0 ; output \tran_frame_test_reg[tprm][0]_0 ; output \tran_frame_test_reg[tprm][1]_1 ; output \tran_frame_test_reg[tprm][4]_0 ; output \tran_frame_test_reg[tprm][1]_2 ; output \tran_frame_test_reg[tprm][1]_3 ; output \tran_frame_test_reg[tprm][0]_1 ; output \tran_frame_test_reg[tprm][1]_4 ; output \tran_frame_test_reg[tprm][2]_0 ; output \tran_dlc_com_reg[3]_1 ; output \tran_dlc_com_reg[3]_2 ; output \compl_ctr_q_reg[7] ; output \tran_dlc_com_reg[3]_3 ; output \tran_dlc_com_reg[0]_0 ; output \tran_dlc_com_reg[0]_1 ; output \tran_dlc_com_reg[3]_4 ; output \tran_dlc_com_reg[1]_0 ; output \g_bit[0].reg_value_r_reg[0] ; output \tran_frame_test_reg[tprm][3]_0 ; output \tran_frame_test_reg[tprm][3]_1 ; output \g_bit[0].reg_value_r_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_1 ; output \tran_frame_test_reg[tprm][2]_1 ; output \g_bit[0].reg_value_r_reg[0]_2 ; output \g_bit[0].reg_value_r_reg[0]_3 ; output \FSM_sequential_curr_state_reg[0]_0 ; output \g_bit[0].reg_value_r_reg[0]_4 ; output \tran_frame_test_reg[tprm][0]_2 ; output \bst_ctr_q_reg[2] ; output [1:0]\select_buf_index_reg_reg[1]_0 ; output \txtb_pointer_meta_q_reg[1]_0 ; output \txtb_pointer_meta_q_reg[4]_0 ; output \txtb_pointer_meta_q_reg[0]_0 ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[0]_1 ; input [0:0]\mr_tst_out[tst_dest_tst_addr] ; input tst_ena; input [0:0]\g_ram_rst_false.ram_memory_reg ; input [0:0]curr_state; input [0:0]\FSM_sequential_curr_state[0]_i_2 ; input \txtb_hw_cmd[valid] ; input \txtb_hw_cmd[failed] ; input tst_ena_0; input [0:0]\FSM_sequential_curr_state_reg[2]_1 ; input [0:0]curr_state_1; input tx_command_txce_valid; input tx_command_txcr_valid; input \txtb_hw_cmd[lock] ; input tst_ena_2; input [0:0]curr_state_3; input [0:0]\FSM_sequential_curr_state[0]_i_2__1 ; input tst_ena_4; input [0:0]\txtb_state[3] ; input [0:0]curr_state_5; input tx_command_txce_valid_6; input tx_command_txcr_valid_7; input [63:0]timestamp_IBUF; input \tran_frame_test_dbl_buf_reg[fstc]_0 ; input \tran_frame_test_dbl_buf_reg[fstc]_1 ; input \tran_frame_test_dbl_buf_reg[fstc]_2 ; input \tran_frame_test_dbl_buf_reg[fstc]_3 ; input \ts_low_internal_reg[1]_0 ; input \ts_low_internal_reg[1]_1 ; input \ts_low_internal_reg[1]_2 ; input \ts_low_internal_reg[1]_3 ; input \ts_low_internal_reg[2]_0 ; input \ts_low_internal_reg[2]_1 ; input \ts_low_internal_reg[2]_2 ; input \ts_low_internal_reg[2]_3 ; input \tran_identifier_com_reg[3]_1 ; input \tran_identifier_com_reg[3]_2 ; input \tran_identifier_com_reg[3]_3 ; input \tran_identifier_com_reg[3]_4 ; input \tran_identifier_com_reg[4]_1 ; input \tran_identifier_com_reg[4]_2 ; input \tran_identifier_com_reg[4]_3 ; input \tran_identifier_com_reg[4]_4 ; input \tran_identifier_com_reg[5]_1 ; input \tran_identifier_com_reg[5]_2 ; input \tran_identifier_com_reg[5]_3 ; input \tran_identifier_com_reg[5]_4 ; input \tran_identifier_com_reg[6]_1 ; input \tran_identifier_com_reg[6]_2 ; input \tran_identifier_com_reg[6]_3 ; input \tran_identifier_com_reg[6]_4 ; input \ts_low_internal_reg[7]_0 ; input \ts_low_internal_reg[7]_1 ; input \ts_low_internal_reg[7]_2 ; input \ts_low_internal_reg[7]_3 ; input \ts_low_internal_reg[8]_0 ; input \ts_low_internal_reg[8]_1 ; input \ts_low_internal_reg[8]_2 ; input \ts_low_internal_reg[8]_3 ; input \tran_frame_test_dbl_buf_reg[tprm][1]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][1]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][1]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][1]_3 ; input \tran_frame_test_dbl_buf_reg[tprm][2]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][2]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][2]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][2]_3 ; input \tran_frame_test_dbl_buf_reg[tprm][3]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][3]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][3]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][3]_3 ; input \tran_frame_test_dbl_buf_reg[tprm][4]_0 ; input \tran_frame_test_dbl_buf_reg[tprm][4]_1 ; input \tran_frame_test_dbl_buf_reg[tprm][4]_2 ; input \tran_frame_test_dbl_buf_reg[tprm][4]_3 ; input \ts_low_internal_reg[13]_0 ; input \ts_low_internal_reg[13]_1 ; input \ts_low_internal_reg[13]_2 ; input \ts_low_internal_reg[13]_3 ; input \ts_low_internal_reg[14]_0 ; input \ts_low_internal_reg[14]_1 ; input \ts_low_internal_reg[14]_2 ; input \ts_low_internal_reg[14]_3 ; input \tran_identifier_com_reg[15]_0 ; input \tran_identifier_com_reg[15]_1 ; input \tran_identifier_com_reg[15]_2 ; input \tran_identifier_com_reg[15]_3 ; input \tran_identifier_com_reg[16]_0 ; input \tran_identifier_com_reg[16]_1 ; input \tran_identifier_com_reg[16]_2 ; input \tran_identifier_com_reg[16]_3 ; input \tran_identifier_com_reg[17]_0 ; input \tran_identifier_com_reg[17]_1 ; input \tran_identifier_com_reg[17]_2 ; input \tran_identifier_com_reg[17]_3 ; input \tran_identifier_com_reg[18]_0 ; input \tran_identifier_com_reg[18]_1 ; input \tran_identifier_com_reg[18]_2 ; input \tran_identifier_com_reg[18]_3 ; input \ts_low_internal_reg[19]_0 ; input \ts_low_internal_reg[19]_1 ; input \ts_low_internal_reg[19]_2 ; input \ts_low_internal_reg[19]_3 ; input \ts_low_internal_reg[20]_0 ; input \ts_low_internal_reg[20]_1 ; input \ts_low_internal_reg[20]_2 ; input \ts_low_internal_reg[20]_3 ; input \tran_identifier_com_reg[21]_0 ; input \tran_identifier_com_reg[21]_1 ; input \tran_identifier_com_reg[21]_2 ; input \tran_identifier_com_reg[21]_3 ; input \tran_identifier_com_reg[22]_0 ; input \tran_identifier_com_reg[22]_1 ; input \tran_identifier_com_reg[22]_2 ; input \tran_identifier_com_reg[22]_3 ; input \tran_identifier_com_reg[23]_0 ; input \tran_identifier_com_reg[23]_1 ; input \tran_identifier_com_reg[23]_2 ; input \tran_identifier_com_reg[23]_3 ; input \ts_low_internal_reg[24]_0 ; input \ts_low_internal_reg[24]_1 ; input \ts_low_internal_reg[24]_2 ; input \ts_low_internal_reg[24]_3 ; input \ts_low_internal_reg[25]_0 ; input \ts_low_internal_reg[25]_1 ; input \ts_low_internal_reg[25]_2 ; input \ts_low_internal_reg[25]_3 ; input \ts_low_internal_reg[26]_0 ; input \ts_low_internal_reg[26]_1 ; input \ts_low_internal_reg[26]_2 ; input \ts_low_internal_reg[26]_3 ; input \tran_identifier_com_reg[27]_1 ; input \tran_identifier_com_reg[27]_2 ; input \tran_identifier_com_reg[27]_3 ; input \tran_identifier_com_reg[27]_4 ; input \tran_identifier_com_reg[28]_1 ; input \tran_identifier_com_reg[28]_2 ; input \tran_identifier_com_reg[28]_3 ; input \tran_identifier_com_reg[28]_4 ; input \ts_low_internal_reg[29]_0 ; input \ts_low_internal_reg[29]_1 ; input \ts_low_internal_reg[29]_2 ; input \ts_low_internal_reg[29]_3 ; input \ts_low_internal_reg[30]_0 ; input \ts_low_internal_reg[30]_1 ; input \ts_low_internal_reg[30]_2 ; input \ts_low_internal_reg[30]_3 ; input \ts_low_internal_reg[31]_0 ; input \ts_low_internal_reg[31]_1 ; input \ts_low_internal_reg[31]_2 ; input \ts_low_internal_reg[31]_3 ; input [1:0]D; input \FSM_sequential_curr_state_reg[2]_2 ; input \txtb_pointer_meta_q_reg[0]_1 ; input fsm_wait_state_q_reg; input tran_frame_valid_com_reg_0; input \FSM_sequential_curr_state_reg[2]_3 ; input tran_frame_valid_com_reg_1; input tran_frame_valid_com_reg_2; input \FSM_sequential_curr_state[0]_i_2__3 ; input [3:0]txtb_available; input \mr_ctrl_out[mode_tttm] ; input \shift_regs_reg[0] ; input \shift_regs_reg[28] ; input \shift_regs_reg[28]_0 ; input \retr_ctr_q_reg[3] ; input \shift_regs[31]_i_21_0 ; input \mr_ctrl_out[mode_tstm] ; input \shift_regs_reg[28]_1 ; input [1:0]\cc_stat[bst_ctr] ; input [1:0]\shift_regs_reg[12] ; input \shift_regs_reg[11] ; input \shift_regs_reg[17] ; input \shift_regs_reg[18] ; input \shift_regs_reg[19] ; input \shift_regs_reg[24] ; input \shift_regs_reg[25] ; input \shift_regs_reg[26] ; input \shift_regs_reg[27] ; input \cc_stat[is_transmitter] ; input \mr_ctrl_out[mode_fde] ; input \shift_regs[17]_i_4 ; input \ctrl_ctr_q[4]_i_6 ; input \txtb_ptr_q_reg[4] ; input [2:0]\txtb_ptr_q_reg[4]_0 ; input \curr_state[0]_i_8 ; input \mr_ctrl_out[settings_nisofd] ; wire [0:0]ADDRARDADDR; wire [1:0]D; wire [0:0]\FSM_sequential_curr_state[0]_i_2 ; wire [0:0]\FSM_sequential_curr_state[0]_i_2__1 ; wire \FSM_sequential_curr_state[0]_i_2__3 ; wire [0:0]\FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire [20:0]\FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire \FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire [0:0]\FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire [1:0]Q; wire \bst_ctr_q_reg[2] ; wire buffer_frame_test_w; wire buffer_md_w; wire [1:0]\cc_stat[bst_ctr] ; wire \cc_stat[is_transmitter] ; wire clk_sys_IBUF_BUFG; wire \compl_ctr_q_reg[7] ; wire \crc_q_reg[0] ; wire \crc_q_reg[1] ; wire \ctrl_ctr_q[4]_i_6 ; wire \ctrl_ctr_q[8]_i_25_n_0 ; wire \ctrl_ctr_q[8]_i_26_n_0 ; wire [0:0]curr_state; wire \curr_state[0]_i_8 ; wire [0:0]curr_state_1; wire [0:0]curr_state_3; wire [0:0]curr_state_5; wire [0:0]\curr_state_reg[2] ; wire \curr_txtb_index_i_reg[0]_0 ; wire \curr_txtb_index_i_reg[0]_1 ; wire \curr_txtb_index_i_reg[0]_2 ; wire \curr_txtb_index_i_reg[1]_0 ; wire \curr_txtb_index_i_reg[1]_1 ; wire \curr_txtb_index_i_reg[1]_2 ; wire fsm_wait_state_q; wire fsm_wait_state_q_reg; wire \g_bit[0].reg_value_r_reg[0] ; wire \g_bit[0].reg_value_r_reg[0]_0 ; wire \g_bit[0].reg_value_r_reg[0]_1 ; wire \g_bit[0].reg_value_r_reg[0]_2 ; wire \g_bit[0].reg_value_r_reg[0]_3 ; wire \g_bit[0].reg_value_r_reg[0]_4 ; wire [0:0]\g_bit[3].reg_value_r_reg[3] ; wire [0:0]\g_bit[3].reg_value_r_reg[3]_0 ; wire [0:0]\g_bit[3].reg_value_r_reg[3]_1 ; wire [0:0]\g_ram_rst_false.ram_memory_reg ; wire i_txarb_fsm_n_49; wire i_txarb_fsm_n_57; wire i_txarb_fsm_n_58; wire i_txarb_fsm_n_59; wire i_txarb_fsm_n_60; wire i_txarb_fsm_n_61; wire i_txarb_fsm_n_62; wire i_txarb_fsm_n_63; wire [1:0]last_txtb_index; wire \last_txtb_index_reg[1]_0 ; wire \mr_ctrl_out[mode_fde] ; wire \mr_ctrl_out[mode_tstm] ; wire \mr_ctrl_out[mode_tttm] ; wire \mr_ctrl_out[settings_nisofd] ; wire [0:0]\mr_tst_out[tst_dest_tst_addr] ; wire \retr_ctr_q_reg[3] ; wire [1:0]\select_buf_index_reg_reg[1]_0 ; wire \shift_regs[11]_i_3_n_0 ; wire \shift_regs[16]_i_6_n_0 ; wire \shift_regs[17]_i_4 ; wire \shift_regs[18]_i_5_n_0 ; wire \shift_regs[27]_i_5_n_0 ; wire \shift_regs[28]_i_6_n_0 ; wire \shift_regs[28]_i_9_n_0 ; wire \shift_regs[29]_i_10_n_0 ; wire \shift_regs[30]_i_10_n_0 ; wire \shift_regs[31]_i_14_n_0 ; wire \shift_regs[31]_i_21_0 ; wire \shift_regs[31]_i_27_n_0 ; wire \shift_regs_reg[0] ; wire \shift_regs_reg[11] ; wire [1:0]\shift_regs_reg[12] ; wire \shift_regs_reg[17] ; wire \shift_regs_reg[18] ; wire \shift_regs_reg[19] ; wire \shift_regs_reg[24] ; wire \shift_regs_reg[25] ; wire \shift_regs_reg[26] ; wire \shift_regs_reg[27] ; wire \shift_regs_reg[28] ; wire \shift_regs_reg[28]_0 ; wire \shift_regs_reg[28]_1 ; wire [63:0]timestamp_IBUF; wire tran_brs; wire tran_brs_dbl_buf; wire [2:2]tran_dlc; wire \tran_dlc_com_reg[0]_0 ; wire \tran_dlc_com_reg[0]_1 ; wire \tran_dlc_com_reg[1]_0 ; wire [2:0]\tran_dlc_com_reg[3]_0 ; wire \tran_dlc_com_reg[3]_1 ; wire \tran_dlc_com_reg[3]_2 ; wire \tran_dlc_com_reg[3]_3 ; wire \tran_dlc_com_reg[3]_4 ; wire [3:0]tran_dlc_dbl_buf; wire \tran_frame_test[fcrc] ; wire \tran_frame_test[fstc] ; wire \tran_frame_test[sdlc] ; wire [4:0]\tran_frame_test[tprm] ; wire \tran_frame_test_dbl_buf_reg[fcrc]__0 ; wire \tran_frame_test_dbl_buf_reg[fstc]_0 ; wire \tran_frame_test_dbl_buf_reg[fstc]_1 ; wire \tran_frame_test_dbl_buf_reg[fstc]_2 ; wire \tran_frame_test_dbl_buf_reg[fstc]_3 ; wire \tran_frame_test_dbl_buf_reg[fstc]__0 ; wire \tran_frame_test_dbl_buf_reg[sdlc]__0 ; wire [4:0]\tran_frame_test_dbl_buf_reg[tprm] ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][1]_3 ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][2]_3 ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][3]_3 ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_0 ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_1 ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_2 ; wire \tran_frame_test_dbl_buf_reg[tprm][4]_3 ; wire \tran_frame_test_reg[fcrc]_0 ; wire \tran_frame_test_reg[fstc]_0 ; wire \tran_frame_test_reg[tprm][0]_0 ; wire \tran_frame_test_reg[tprm][0]_1 ; wire \tran_frame_test_reg[tprm][0]_2 ; wire \tran_frame_test_reg[tprm][1]_0 ; wire \tran_frame_test_reg[tprm][1]_1 ; wire \tran_frame_test_reg[tprm][1]_2 ; wire \tran_frame_test_reg[tprm][1]_3 ; wire \tran_frame_test_reg[tprm][1]_4 ; wire \tran_frame_test_reg[tprm][2]_0 ; wire \tran_frame_test_reg[tprm][2]_1 ; wire \tran_frame_test_reg[tprm][3]_0 ; wire \tran_frame_test_reg[tprm][3]_1 ; wire \tran_frame_test_reg[tprm][4]_0 ; wire tran_frame_type; wire tran_frame_type_com_reg_0; wire tran_frame_type_dbl_buf; wire tran_frame_valid; wire tran_frame_valid_com; wire tran_frame_valid_com_reg_0; wire tran_frame_valid_com_reg_1; wire tran_frame_valid_com_reg_2; wire tran_ident_type; wire tran_ident_type_dbl_buf; wire [28:0]tran_identifier; wire \tran_identifier_com_reg[0]_0 ; wire \tran_identifier_com_reg[15]_0 ; wire \tran_identifier_com_reg[15]_1 ; wire \tran_identifier_com_reg[15]_2 ; wire \tran_identifier_com_reg[15]_3 ; wire \tran_identifier_com_reg[16]_0 ; wire \tran_identifier_com_reg[16]_1 ; wire \tran_identifier_com_reg[16]_2 ; wire \tran_identifier_com_reg[16]_3 ; wire \tran_identifier_com_reg[17]_0 ; wire \tran_identifier_com_reg[17]_1 ; wire \tran_identifier_com_reg[17]_2 ; wire \tran_identifier_com_reg[17]_3 ; wire \tran_identifier_com_reg[18]_0 ; wire \tran_identifier_com_reg[18]_1 ; wire \tran_identifier_com_reg[18]_2 ; wire \tran_identifier_com_reg[18]_3 ; wire \tran_identifier_com_reg[1]_0 ; wire \tran_identifier_com_reg[21]_0 ; wire \tran_identifier_com_reg[21]_1 ; wire \tran_identifier_com_reg[21]_2 ; wire \tran_identifier_com_reg[21]_3 ; wire \tran_identifier_com_reg[22]_0 ; wire \tran_identifier_com_reg[22]_1 ; wire \tran_identifier_com_reg[22]_2 ; wire \tran_identifier_com_reg[22]_3 ; wire \tran_identifier_com_reg[23]_0 ; wire \tran_identifier_com_reg[23]_1 ; wire \tran_identifier_com_reg[23]_2 ; wire \tran_identifier_com_reg[23]_3 ; wire [13:0]\tran_identifier_com_reg[24]_0 ; wire \tran_identifier_com_reg[25]_0 ; wire \tran_identifier_com_reg[26]_0 ; wire \tran_identifier_com_reg[27]_0 ; wire \tran_identifier_com_reg[27]_1 ; wire \tran_identifier_com_reg[27]_2 ; wire \tran_identifier_com_reg[27]_3 ; wire \tran_identifier_com_reg[27]_4 ; wire \tran_identifier_com_reg[28]_0 ; wire \tran_identifier_com_reg[28]_1 ; wire \tran_identifier_com_reg[28]_2 ; wire \tran_identifier_com_reg[28]_3 ; wire \tran_identifier_com_reg[28]_4 ; wire \tran_identifier_com_reg[2]_0 ; wire \tran_identifier_com_reg[3]_0 ; wire \tran_identifier_com_reg[3]_1 ; wire \tran_identifier_com_reg[3]_2 ; wire \tran_identifier_com_reg[3]_3 ; wire \tran_identifier_com_reg[3]_4 ; wire \tran_identifier_com_reg[4]_0 ; wire \tran_identifier_com_reg[4]_1 ; wire \tran_identifier_com_reg[4]_2 ; wire \tran_identifier_com_reg[4]_3 ; wire \tran_identifier_com_reg[4]_4 ; wire \tran_identifier_com_reg[5]_0 ; wire \tran_identifier_com_reg[5]_1 ; wire \tran_identifier_com_reg[5]_2 ; wire \tran_identifier_com_reg[5]_3 ; wire \tran_identifier_com_reg[5]_4 ; wire \tran_identifier_com_reg[6]_0 ; wire \tran_identifier_com_reg[6]_1 ; wire \tran_identifier_com_reg[6]_2 ; wire \tran_identifier_com_reg[6]_3 ; wire \tran_identifier_com_reg[6]_4 ; wire tran_is_rtr; wire tran_is_rtr_dbl_buf; wire [26:1]tran_word; wire [31:0]ts_low_internal; wire \ts_low_internal_reg[13]_0 ; wire \ts_low_internal_reg[13]_1 ; wire \ts_low_internal_reg[13]_2 ; wire \ts_low_internal_reg[13]_3 ; wire \ts_low_internal_reg[14]_0 ; wire \ts_low_internal_reg[14]_1 ; wire \ts_low_internal_reg[14]_2 ; wire \ts_low_internal_reg[14]_3 ; wire \ts_low_internal_reg[19]_0 ; wire \ts_low_internal_reg[19]_1 ; wire \ts_low_internal_reg[19]_2 ; wire \ts_low_internal_reg[19]_3 ; wire \ts_low_internal_reg[1]_0 ; wire \ts_low_internal_reg[1]_1 ; wire \ts_low_internal_reg[1]_2 ; wire \ts_low_internal_reg[1]_3 ; wire \ts_low_internal_reg[20]_0 ; wire \ts_low_internal_reg[20]_1 ; wire \ts_low_internal_reg[20]_2 ; wire \ts_low_internal_reg[20]_3 ; wire \ts_low_internal_reg[24]_0 ; wire \ts_low_internal_reg[24]_1 ; wire \ts_low_internal_reg[24]_2 ; wire \ts_low_internal_reg[24]_3 ; wire \ts_low_internal_reg[25]_0 ; wire \ts_low_internal_reg[25]_1 ; wire \ts_low_internal_reg[25]_2 ; wire \ts_low_internal_reg[25]_3 ; wire \ts_low_internal_reg[26]_0 ; wire \ts_low_internal_reg[26]_1 ; wire \ts_low_internal_reg[26]_2 ; wire \ts_low_internal_reg[26]_3 ; wire \ts_low_internal_reg[29]_0 ; wire \ts_low_internal_reg[29]_1 ; wire \ts_low_internal_reg[29]_2 ; wire \ts_low_internal_reg[29]_3 ; wire \ts_low_internal_reg[2]_0 ; wire \ts_low_internal_reg[2]_1 ; wire \ts_low_internal_reg[2]_2 ; wire \ts_low_internal_reg[2]_3 ; wire \ts_low_internal_reg[30]_0 ; wire \ts_low_internal_reg[30]_1 ; wire \ts_low_internal_reg[30]_2 ; wire \ts_low_internal_reg[30]_3 ; wire \ts_low_internal_reg[31]_0 ; wire \ts_low_internal_reg[31]_1 ; wire \ts_low_internal_reg[31]_2 ; wire \ts_low_internal_reg[31]_3 ; wire \ts_low_internal_reg[7]_0 ; wire \ts_low_internal_reg[7]_1 ; wire \ts_low_internal_reg[7]_2 ; wire \ts_low_internal_reg[7]_3 ; wire \ts_low_internal_reg[8]_0 ; wire \ts_low_internal_reg[8]_1 ; wire \ts_low_internal_reg[8]_2 ; wire \ts_low_internal_reg[8]_3 ; wire tst_ena; wire tst_ena_0; wire tst_ena_2; wire tst_ena_4; wire tx_command_txce_valid; wire tx_command_txce_valid_6; wire tx_command_txcr_valid; wire tx_command_txcr_valid_7; wire [3:0]txtb_available; wire \txtb_hw_cmd[failed] ; wire \txtb_hw_cmd[lock] ; wire \txtb_hw_cmd[valid] ; wire [3:0]txtb_hw_cmd_cs; wire \txtb_hw_cmd_q[lock]_i_8_n_0 ; wire \txtb_pointer_meta_q_reg[0]_0 ; wire \txtb_pointer_meta_q_reg[0]_1 ; wire \txtb_pointer_meta_q_reg[1]_0 ; wire \txtb_pointer_meta_q_reg[4]_0 ; wire \txtb_ptr_q[4]_i_10_n_0 ; wire \txtb_ptr_q[4]_i_11_n_0 ; wire \txtb_ptr_q[4]_i_12_n_0 ; wire \txtb_ptr_q[4]_i_13_n_0 ; wire \txtb_ptr_q_reg[4] ; wire [2:0]\txtb_ptr_q_reg[4]_0 ; wire [0:0]\txtb_state[3] ; (* SOFT_HLUTNM = "soft_lutpair355" *) LUT3 #( .INIT(8'h7F)) \FSM_sequential_curr_state[0]_i_5__0 (.I0(Q[1]), .I1(Q[0]), .I2(\txtb_hw_cmd[lock] ), .O(\curr_txtb_index_i_reg[1]_2 )); LUT6 #( .INIT(64'h1000100010000000)) \FSM_sequential_curr_state[0]_i_6 (.I0(Q[0]), .I1(Q[1]), .I2(curr_state), .I3(\FSM_sequential_curr_state[0]_i_2 ), .I4(\txtb_hw_cmd[valid] ), .I5(\txtb_hw_cmd[failed] ), .O(\curr_txtb_index_i_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair355" *) LUT3 #( .INIT(8'hBF)) \FSM_sequential_curr_state[0]_i_6__0 (.I0(Q[1]), .I1(Q[0]), .I2(\txtb_hw_cmd[lock] ), .O(\curr_txtb_index_i_reg[1]_0 )); LUT6 #( .INIT(64'h2000200020000000)) \FSM_sequential_curr_state[0]_i_6__1 (.I0(Q[1]), .I1(Q[0]), .I2(curr_state_3), .I3(\FSM_sequential_curr_state[0]_i_2__1 ), .I4(\txtb_hw_cmd[valid] ), .I5(\txtb_hw_cmd[failed] ), .O(\curr_txtb_index_i_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair359" *) LUT2 #( .INIT(4'h1)) \FSM_sequential_curr_state[2]_i_10__1 (.I0(Q[0]), .I1(Q[1]), .O(txtb_hw_cmd_cs[0])); (* SOFT_HLUTNM = "soft_lutpair360" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[2]_i_13 (.I0(Q[0]), .I1(Q[1]), .O(txtb_hw_cmd_cs[3])); (* SOFT_HLUTNM = "soft_lutpair360" *) LUT2 #( .INIT(4'h2)) \FSM_sequential_curr_state[2]_i_14__0 (.I0(Q[0]), .I1(Q[1]), .O(txtb_hw_cmd_cs[1])); LUT6 #( .INIT(64'hD000D000D000D0F0)) \FSM_sequential_curr_state[2]_i_4__0 (.I0(Q[0]), .I1(Q[1]), .I2(\FSM_sequential_curr_state_reg[2]_1 ), .I3(curr_state_1), .I4(tx_command_txce_valid), .I5(tx_command_txcr_valid), .O(\curr_txtb_index_i_reg[0]_1 )); LUT6 #( .INIT(64'h70007000700070F0)) \FSM_sequential_curr_state[2]_i_4__2 (.I0(Q[0]), .I1(Q[1]), .I2(\txtb_state[3] ), .I3(curr_state_5), .I4(tx_command_txce_valid_6), .I5(tx_command_txcr_valid_7), .O(\curr_txtb_index_i_reg[0]_2 )); (* SOFT_HLUTNM = "soft_lutpair359" *) LUT2 #( .INIT(4'h2)) \FSM_sequential_curr_state[2]_i_9__1 (.I0(Q[1]), .I1(Q[0]), .O(txtb_hw_cmd_cs[2])); LUT5 #( .INIT(32'hFF7F00FF)) \ctrl_ctr_q[5]_i_5 (.I0(\tran_dlc_com_reg[3]_0 [0]), .I1(tran_frame_type), .I2(\mr_ctrl_out[mode_fde] ), .I3(tran_dlc), .I4(\tran_dlc_com_reg[3]_0 [2]), .O(\tran_dlc_com_reg[0]_1 )); LUT6 #( .INIT(64'h0070F0F0F0F0F0F0)) \ctrl_ctr_q[6]_i_5 (.I0(\tran_dlc_com_reg[3]_0 [0]), .I1(tran_dlc), .I2(\tran_dlc_com_reg[3]_0 [2]), .I3(\tran_dlc_com_reg[3]_0 [1]), .I4(tran_frame_type), .I5(\mr_ctrl_out[mode_fde] ), .O(\tran_dlc_com_reg[0]_0 )); LUT6 #( .INIT(64'h08A8000000000000)) \ctrl_ctr_q[8]_i_15 (.I0(\tran_dlc_com_reg[3]_0 [2]), .I1(\tran_dlc_com_reg[3]_0 [1]), .I2(tran_dlc), .I3(\tran_dlc_com_reg[3]_0 [0]), .I4(\mr_ctrl_out[mode_fde] ), .I5(tran_frame_type), .O(\tran_dlc_com_reg[3]_4 )); LUT6 #( .INIT(64'h0000000000FDFFFF)) \ctrl_ctr_q[8]_i_17 (.I0(\ctrl_ctr_q[8]_i_25_n_0 ), .I1(\tran_dlc_com_reg[3]_0 [2]), .I2(tran_dlc), .I3(\ctrl_ctr_q[8]_i_26_n_0 ), .I4(\cc_stat[is_transmitter] ), .I5(\ctrl_ctr_q[4]_i_6 ), .O(\tran_dlc_com_reg[3]_2 )); LUT6 #( .INIT(64'h0880000000000000)) \ctrl_ctr_q[8]_i_18 (.I0(\tran_dlc_com_reg[3]_0 [2]), .I1(tran_dlc), .I2(\tran_dlc_com_reg[3]_0 [0]), .I3(\tran_dlc_com_reg[3]_0 [1]), .I4(\mr_ctrl_out[mode_fde] ), .I5(tran_frame_type), .O(\tran_dlc_com_reg[3]_1 )); (* SOFT_HLUTNM = "soft_lutpair354" *) LUT2 #( .INIT(4'h1)) \ctrl_ctr_q[8]_i_25 (.I0(\tran_dlc_com_reg[3]_0 [0]), .I1(\tran_dlc_com_reg[3]_0 [1]), .O(\ctrl_ctr_q[8]_i_25_n_0 )); LUT3 #( .INIT(8'h2A)) \ctrl_ctr_q[8]_i_26 (.I0(tran_is_rtr), .I1(tran_frame_type), .I2(\mr_ctrl_out[mode_fde] ), .O(\ctrl_ctr_q[8]_i_26_n_0 )); LUT3 #( .INIT(8'hFE)) \curr_state[0]_i_12 (.I0(\tran_dlc_com_reg[3]_2 ), .I1(\curr_state[0]_i_8 ), .I2(\mr_ctrl_out[settings_nisofd] ), .O(\g_bit[0].reg_value_r_reg[0]_4 )); FDCE #( .INIT(1'b0)) \curr_txtb_index_i_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(D[0]), .Q(Q[0])); FDCE #( .INIT(1'b0)) \curr_txtb_index_i_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(D[1]), .Q(Q[1])); txarb_fsm i_txarb_fsm (.ADDRARDADDR(ADDRARDADDR), .D({\FSM_sequential_curr_state_reg[1] [17:16],tran_word[26:24],\FSM_sequential_curr_state_reg[1] [15:13],tran_word[20:19],\FSM_sequential_curr_state_reg[1] [12:9],tran_word[14:13],\FSM_sequential_curr_state_reg[1] [8:5],tran_word[8:7],\FSM_sequential_curr_state_reg[1] [4:1],tran_word[2:1],\FSM_sequential_curr_state_reg[1] [0]}), .E(i_txarb_fsm_n_57), .\FSM_sequential_curr_state[0]_i_2__3_0 (\FSM_sequential_curr_state[0]_i_2__3 ), .\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_1 (i_txarb_fsm_n_49), .\FSM_sequential_curr_state_reg[0]_2 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_3 (i_txarb_fsm_n_58), .\FSM_sequential_curr_state_reg[0]_4 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[0]_i_9_0 (ts_low_internal), .\FSM_sequential_curr_state_reg[1]_0 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_1 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_10 (\FSM_sequential_curr_state_reg[1] [20:18]), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_4 ), .\FSM_sequential_curr_state_reg[1]_5 (\FSM_sequential_curr_state_reg[1]_5 ), .\FSM_sequential_curr_state_reg[1]_6 (\FSM_sequential_curr_state_reg[1]_6 ), .\FSM_sequential_curr_state_reg[1]_7 (\FSM_sequential_curr_state_reg[1]_7 ), .\FSM_sequential_curr_state_reg[1]_8 (\FSM_sequential_curr_state_reg[1]_8 ), .\FSM_sequential_curr_state_reg[1]_9 (\FSM_sequential_curr_state_reg[1]_9 ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2] ), .\FSM_sequential_curr_state_reg[2]_1 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_2 ), .\FSM_sequential_curr_state_reg[2]_3 (\FSM_sequential_curr_state_reg[2]_3 ), .Q(Q), .buffer_frame_test_w(buffer_frame_test_w), .buffer_md_w(buffer_md_w), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\curr_state_reg[2] (\curr_state_reg[2] ), .\curr_txtb_index_i_reg[0] (i_txarb_fsm_n_63), .\curr_txtb_index_i_reg[1] (i_txarb_fsm_n_62), .destuff_enable_i_7(\txtb_hw_cmd_q[lock]_i_8_n_0 ), .fsm_wait_state_q_reg_0(fsm_wait_state_q), .fsm_wait_state_q_reg_1(fsm_wait_state_q_reg), .\g_bit[3].reg_value_r_reg[3] (\g_bit[3].reg_value_r_reg[3] ), .\g_bit[3].reg_value_r_reg[3]_0 (\g_bit[3].reg_value_r_reg[3]_0 ), .\g_bit[3].reg_value_r_reg[3]_1 (\g_bit[3].reg_value_r_reg[3]_1 ), .\g_ram_rst_false.ram_memory_reg (\g_ram_rst_false.ram_memory_reg ), .last_txtb_index(last_txtb_index), .\last_txtb_index_reg[1] (\last_txtb_index_reg[1]_0 ), .\mr_ctrl_out[mode_tttm] (\mr_ctrl_out[mode_tttm] ), .\mr_tst_out[tst_dest_tst_addr] (\mr_tst_out[tst_dest_tst_addr] ), .\retr_ctr_q_reg[3] (\retr_ctr_q_reg[3] ), .\shift_regs_reg[0] (\shift_regs_reg[0] ), .timestamp_IBUF(timestamp_IBUF), .\tran_frame_test_dbl_buf_reg[fstc] (\tran_frame_test_dbl_buf_reg[fstc]_0 ), .\tran_frame_test_dbl_buf_reg[fstc]_0 (\tran_frame_test_dbl_buf_reg[fstc]_1 ), .\tran_frame_test_dbl_buf_reg[fstc]_1 (\tran_frame_test_dbl_buf_reg[fstc]_2 ), .\tran_frame_test_dbl_buf_reg[fstc]_2 (\tran_frame_test_dbl_buf_reg[fstc]_3 ), .\tran_frame_test_dbl_buf_reg[tprm][1] (\tran_frame_test_dbl_buf_reg[tprm][1]_0 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_0 (\tran_frame_test_dbl_buf_reg[tprm][1]_1 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_1 (\tran_frame_test_dbl_buf_reg[tprm][1]_2 ), .\tran_frame_test_dbl_buf_reg[tprm][1]_2 (\tran_frame_test_dbl_buf_reg[tprm][1]_3 ), .\tran_frame_test_dbl_buf_reg[tprm][2] (\tran_frame_test_dbl_buf_reg[tprm][2]_0 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_0 (\tran_frame_test_dbl_buf_reg[tprm][2]_1 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_1 (\tran_frame_test_dbl_buf_reg[tprm][2]_2 ), .\tran_frame_test_dbl_buf_reg[tprm][2]_2 (\tran_frame_test_dbl_buf_reg[tprm][2]_3 ), .\tran_frame_test_dbl_buf_reg[tprm][3] (\tran_frame_test_dbl_buf_reg[tprm][3]_0 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_0 (\tran_frame_test_dbl_buf_reg[tprm][3]_1 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_1 (\tran_frame_test_dbl_buf_reg[tprm][3]_2 ), .\tran_frame_test_dbl_buf_reg[tprm][3]_2 (\tran_frame_test_dbl_buf_reg[tprm][3]_3 ), .\tran_frame_test_dbl_buf_reg[tprm][4] (\tran_frame_test_dbl_buf_reg[tprm][4]_0 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_0 (\tran_frame_test_dbl_buf_reg[tprm][4]_1 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_1 (\tran_frame_test_dbl_buf_reg[tprm][4]_2 ), .\tran_frame_test_dbl_buf_reg[tprm][4]_2 (\tran_frame_test_dbl_buf_reg[tprm][4]_3 ), .tran_frame_valid(tran_frame_valid), .tran_frame_valid_com(tran_frame_valid_com), .tran_frame_valid_com_reg(tran_frame_valid_com_reg_0), .tran_frame_valid_com_reg_0(tran_frame_valid_com_reg_1), .tran_frame_valid_com_reg_1(tran_frame_valid_com_reg_2), .\tran_identifier_com_reg[15] (\tran_identifier_com_reg[15]_0 ), .\tran_identifier_com_reg[15]_0 (\tran_identifier_com_reg[15]_1 ), .\tran_identifier_com_reg[15]_1 (\tran_identifier_com_reg[15]_2 ), .\tran_identifier_com_reg[15]_2 (\tran_identifier_com_reg[15]_3 ), .\tran_identifier_com_reg[16] (\tran_identifier_com_reg[16]_0 ), .\tran_identifier_com_reg[16]_0 (\tran_identifier_com_reg[16]_1 ), .\tran_identifier_com_reg[16]_1 (\tran_identifier_com_reg[16]_2 ), .\tran_identifier_com_reg[16]_2 (\tran_identifier_com_reg[16]_3 ), .\tran_identifier_com_reg[17] (\tran_identifier_com_reg[17]_0 ), .\tran_identifier_com_reg[17]_0 (\tran_identifier_com_reg[17]_1 ), .\tran_identifier_com_reg[17]_1 (\tran_identifier_com_reg[17]_2 ), .\tran_identifier_com_reg[17]_2 (\tran_identifier_com_reg[17]_3 ), .\tran_identifier_com_reg[18] (\tran_identifier_com_reg[18]_0 ), .\tran_identifier_com_reg[18]_0 (\tran_identifier_com_reg[18]_1 ), .\tran_identifier_com_reg[18]_1 (\tran_identifier_com_reg[18]_2 ), .\tran_identifier_com_reg[18]_2 (\tran_identifier_com_reg[18]_3 ), .\tran_identifier_com_reg[21] (\tran_identifier_com_reg[21]_0 ), .\tran_identifier_com_reg[21]_0 (\tran_identifier_com_reg[21]_1 ), .\tran_identifier_com_reg[21]_1 (\tran_identifier_com_reg[21]_2 ), .\tran_identifier_com_reg[21]_2 (\tran_identifier_com_reg[21]_3 ), .\tran_identifier_com_reg[22] (\tran_identifier_com_reg[22]_0 ), .\tran_identifier_com_reg[22]_0 (\tran_identifier_com_reg[22]_1 ), .\tran_identifier_com_reg[22]_1 (\tran_identifier_com_reg[22]_2 ), .\tran_identifier_com_reg[22]_2 (\tran_identifier_com_reg[22]_3 ), .\tran_identifier_com_reg[23] (\tran_identifier_com_reg[23]_0 ), .\tran_identifier_com_reg[23]_0 (\tran_identifier_com_reg[23]_1 ), .\tran_identifier_com_reg[23]_1 (\tran_identifier_com_reg[23]_2 ), .\tran_identifier_com_reg[23]_2 (\tran_identifier_com_reg[23]_3 ), .\tran_identifier_com_reg[27] (\tran_identifier_com_reg[27]_1 ), .\tran_identifier_com_reg[27]_0 (\tran_identifier_com_reg[27]_2 ), .\tran_identifier_com_reg[27]_1 (\tran_identifier_com_reg[27]_3 ), .\tran_identifier_com_reg[27]_2 (\tran_identifier_com_reg[27]_4 ), .\tran_identifier_com_reg[28] (\tran_identifier_com_reg[28]_1 ), .\tran_identifier_com_reg[28]_0 (\tran_identifier_com_reg[28]_2 ), .\tran_identifier_com_reg[28]_1 (\tran_identifier_com_reg[28]_3 ), .\tran_identifier_com_reg[28]_2 (\tran_identifier_com_reg[28]_4 ), .\tran_identifier_com_reg[3] (\tran_identifier_com_reg[3]_1 ), .\tran_identifier_com_reg[3]_0 (\tran_identifier_com_reg[3]_2 ), .\tran_identifier_com_reg[3]_1 (\tran_identifier_com_reg[3]_3 ), .\tran_identifier_com_reg[3]_2 (\tran_identifier_com_reg[3]_4 ), .\tran_identifier_com_reg[4] (\tran_identifier_com_reg[4]_1 ), .\tran_identifier_com_reg[4]_0 (\tran_identifier_com_reg[4]_2 ), .\tran_identifier_com_reg[4]_1 (\tran_identifier_com_reg[4]_3 ), .\tran_identifier_com_reg[4]_2 (\tran_identifier_com_reg[4]_4 ), .\tran_identifier_com_reg[5] (\tran_identifier_com_reg[5]_1 ), .\tran_identifier_com_reg[5]_0 (\tran_identifier_com_reg[5]_2 ), .\tran_identifier_com_reg[5]_1 (\tran_identifier_com_reg[5]_3 ), .\tran_identifier_com_reg[5]_2 (\tran_identifier_com_reg[5]_4 ), .\tran_identifier_com_reg[6] (\tran_identifier_com_reg[6]_1 ), .\tran_identifier_com_reg[6]_0 (\tran_identifier_com_reg[6]_2 ), .\tran_identifier_com_reg[6]_1 (\tran_identifier_com_reg[6]_3 ), .\tran_identifier_com_reg[6]_2 (\tran_identifier_com_reg[6]_4 ), .\ts_low_internal_reg[13] (\ts_low_internal_reg[13]_0 ), .\ts_low_internal_reg[13]_0 (\ts_low_internal_reg[13]_1 ), .\ts_low_internal_reg[13]_1 (\ts_low_internal_reg[13]_2 ), .\ts_low_internal_reg[13]_2 (\ts_low_internal_reg[13]_3 ), .\ts_low_internal_reg[14] (\ts_low_internal_reg[14]_0 ), .\ts_low_internal_reg[14]_0 (\ts_low_internal_reg[14]_1 ), .\ts_low_internal_reg[14]_1 (\ts_low_internal_reg[14]_2 ), .\ts_low_internal_reg[14]_2 (\ts_low_internal_reg[14]_3 ), .\ts_low_internal_reg[19] (\ts_low_internal_reg[19]_0 ), .\ts_low_internal_reg[19]_0 (\ts_low_internal_reg[19]_1 ), .\ts_low_internal_reg[19]_1 (\ts_low_internal_reg[19]_2 ), .\ts_low_internal_reg[19]_2 (\ts_low_internal_reg[19]_3 ), .\ts_low_internal_reg[1] (\ts_low_internal_reg[1]_0 ), .\ts_low_internal_reg[1]_0 (\ts_low_internal_reg[1]_1 ), .\ts_low_internal_reg[1]_1 (\ts_low_internal_reg[1]_2 ), .\ts_low_internal_reg[1]_2 (\ts_low_internal_reg[1]_3 ), .\ts_low_internal_reg[20] (\ts_low_internal_reg[20]_0 ), .\ts_low_internal_reg[20]_0 (\ts_low_internal_reg[20]_1 ), .\ts_low_internal_reg[20]_1 (\ts_low_internal_reg[20]_2 ), .\ts_low_internal_reg[20]_2 (\ts_low_internal_reg[20]_3 ), .\ts_low_internal_reg[24] (\ts_low_internal_reg[24]_0 ), .\ts_low_internal_reg[24]_0 (\ts_low_internal_reg[24]_1 ), .\ts_low_internal_reg[24]_1 (\ts_low_internal_reg[24]_2 ), .\ts_low_internal_reg[24]_2 (\ts_low_internal_reg[24]_3 ), .\ts_low_internal_reg[25] (\ts_low_internal_reg[25]_0 ), .\ts_low_internal_reg[25]_0 (\ts_low_internal_reg[25]_1 ), .\ts_low_internal_reg[25]_1 (\ts_low_internal_reg[25]_2 ), .\ts_low_internal_reg[25]_2 (\ts_low_internal_reg[25]_3 ), .\ts_low_internal_reg[26] (\ts_low_internal_reg[26]_0 ), .\ts_low_internal_reg[26]_0 (\ts_low_internal_reg[26]_1 ), .\ts_low_internal_reg[26]_1 (\ts_low_internal_reg[26]_2 ), .\ts_low_internal_reg[26]_2 (\ts_low_internal_reg[26]_3 ), .\ts_low_internal_reg[29] (\ts_low_internal_reg[29]_0 ), .\ts_low_internal_reg[29]_0 (\ts_low_internal_reg[29]_1 ), .\ts_low_internal_reg[29]_1 (\ts_low_internal_reg[29]_2 ), .\ts_low_internal_reg[29]_2 (\ts_low_internal_reg[29]_3 ), .\ts_low_internal_reg[2] (\ts_low_internal_reg[2]_0 ), .\ts_low_internal_reg[2]_0 (\ts_low_internal_reg[2]_1 ), .\ts_low_internal_reg[2]_1 (\ts_low_internal_reg[2]_2 ), .\ts_low_internal_reg[2]_2 (\ts_low_internal_reg[2]_3 ), .\ts_low_internal_reg[30] (\ts_low_internal_reg[30]_0 ), .\ts_low_internal_reg[30]_0 (\ts_low_internal_reg[30]_1 ), .\ts_low_internal_reg[30]_1 (\ts_low_internal_reg[30]_2 ), .\ts_low_internal_reg[30]_2 (\ts_low_internal_reg[30]_3 ), .\ts_low_internal_reg[31] (\ts_low_internal_reg[31]_0 ), .\ts_low_internal_reg[31]_0 (\ts_low_internal_reg[31]_1 ), .\ts_low_internal_reg[31]_1 (\ts_low_internal_reg[31]_2 ), .\ts_low_internal_reg[31]_2 (\ts_low_internal_reg[31]_3 ), .\ts_low_internal_reg[31]_3 (D), .\ts_low_internal_reg[7] (\ts_low_internal_reg[7]_0 ), .\ts_low_internal_reg[7]_0 (\ts_low_internal_reg[7]_1 ), .\ts_low_internal_reg[7]_1 (\ts_low_internal_reg[7]_2 ), .\ts_low_internal_reg[7]_2 (\ts_low_internal_reg[7]_3 ), .\ts_low_internal_reg[8] (\ts_low_internal_reg[8]_0 ), .\ts_low_internal_reg[8]_0 (\ts_low_internal_reg[8]_1 ), .\ts_low_internal_reg[8]_1 (\ts_low_internal_reg[8]_2 ), .\ts_low_internal_reg[8]_2 (\ts_low_internal_reg[8]_3 ), .tst_ena(tst_ena), .tst_ena_0(tst_ena_0), .tst_ena_2(tst_ena_2), .tst_ena_4(tst_ena_4), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .\txtb_pointer_meta_q_reg[0] (i_txarb_fsm_n_61), .\txtb_pointer_meta_q_reg[0]_0 (\txtb_pointer_meta_q_reg[0]_1 ), .\txtb_pointer_meta_q_reg[0]_1 (\txtb_pointer_meta_q_reg[0]_0 ), .\txtb_pointer_meta_q_reg[1] (i_txarb_fsm_n_59), .\txtb_pointer_meta_q_reg[1]_0 (\txtb_pointer_meta_q_reg[1]_0 ), .\txtb_pointer_meta_q_reg[4] (i_txarb_fsm_n_60), .\txtb_pointer_meta_q_reg[4]_0 (\txtb_pointer_meta_q_reg[4]_0 )); FDCE #( .INIT(1'b0)) \last_txtb_index_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(i_txarb_fsm_n_63), .Q(last_txtb_index[0])); FDCE #( .INIT(1'b0)) \last_txtb_index_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(i_txarb_fsm_n_62), .Q(last_txtb_index[1])); FDCE #( .INIT(1'b0)) \select_buf_index_reg_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(D[0]), .Q(\select_buf_index_reg_reg[1]_0 [0])); FDCE #( .INIT(1'b0)) \select_buf_index_reg_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(D[1]), .Q(\select_buf_index_reg_reg[1]_0 [1])); LUT5 #( .INIT(32'h0000222D)) \shift_regs[11]_i_2 (.I0(\shift_regs_reg[12] [0]), .I1(tran_frame_type_com_reg_0), .I2(\shift_regs[18]_i_5_n_0 ), .I3(\shift_regs[11]_i_3_n_0 ), .I4(\shift_regs_reg[11] ), .O(\crc_q_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair351" *) LUT5 #( .INIT(32'hFFFFFF7F)) \shift_regs[11]_i_3 (.I0(\mr_ctrl_out[mode_tstm] ), .I1(\tran_frame_test[fcrc] ), .I2(\tran_frame_test[tprm] [2]), .I3(\tran_frame_test[tprm] [1]), .I4(\tran_frame_test[tprm] [0]), .O(\shift_regs[11]_i_3_n_0 )); LUT5 #( .INIT(32'h00002D22)) \shift_regs[12]_i_2 (.I0(\shift_regs_reg[12] [1]), .I1(tran_frame_type_com_reg_0), .I2(\shift_regs[18]_i_5_n_0 ), .I3(\tran_frame_test_reg[fcrc]_0 ), .I4(\shift_regs_reg[11] ), .O(\crc_q_reg[1] )); LUT6 #( .INIT(64'h0000000000000800)) \shift_regs[13]_i_3 (.I0(\mr_ctrl_out[mode_tstm] ), .I1(\tran_frame_test[fcrc] ), .I2(\tran_frame_test[tprm] [2]), .I3(\tran_frame_test[tprm] [1]), .I4(\tran_frame_test[tprm] [0]), .I5(\shift_regs[18]_i_5_n_0 ), .O(\g_bit[0].reg_value_r_reg[0]_0 )); LUT2 #( .INIT(4'h8)) \shift_regs[14]_i_3 (.I0(tran_identifier[0]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[0]_0 )); LUT6 #( .INIT(64'h0000000000000800)) \shift_regs[14]_i_4 (.I0(\mr_ctrl_out[mode_tstm] ), .I1(\tran_frame_test[fcrc] ), .I2(\tran_frame_test[tprm] [2]), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test[tprm] [1]), .I5(\shift_regs[18]_i_5_n_0 ), .O(\g_bit[0].reg_value_r_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair358" *) LUT2 #( .INIT(4'h8)) \shift_regs[15]_i_3 (.I0(tran_identifier[1]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[1]_0 )); LUT6 #( .INIT(64'h0000000000000008)) \shift_regs[15]_i_4 (.I0(\mr_ctrl_out[mode_tstm] ), .I1(\tran_frame_test[fcrc] ), .I2(\tran_frame_test[tprm] [2]), .I3(\tran_frame_test[tprm] [1]), .I4(\tran_frame_test[tprm] [0]), .I5(\shift_regs[18]_i_5_n_0 ), .O(\g_bit[0].reg_value_r_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair358" *) LUT2 #( .INIT(4'h8)) \shift_regs[16]_i_3 (.I0(tran_identifier[2]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[2]_0 )); LUT6 #( .INIT(64'h000000007F7F7FFF)) \shift_regs[16]_i_4 (.I0(\cc_stat[is_transmitter] ), .I1(tran_frame_type), .I2(\mr_ctrl_out[mode_fde] ), .I3(\tran_dlc_com_reg[3]_1 ), .I4(\shift_regs[16]_i_6_n_0 ), .I5(\shift_regs[17]_i_4 ), .O(tran_frame_type_com_reg_0)); LUT6 #( .INIT(64'h0000000080000000)) \shift_regs[16]_i_5 (.I0(\tran_frame_test[tprm] [2]), .I1(\tran_frame_test[fcrc] ), .I2(\mr_ctrl_out[mode_tstm] ), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test[tprm] [1]), .I5(\shift_regs[18]_i_5_n_0 ), .O(\tran_frame_test_reg[tprm][2]_1 )); LUT6 #( .INIT(64'hC000000000800000)) \shift_regs[16]_i_6 (.I0(tran_dlc), .I1(\mr_ctrl_out[mode_fde] ), .I2(tran_frame_type), .I3(\tran_dlc_com_reg[3]_0 [0]), .I4(\tran_dlc_com_reg[3]_0 [2]), .I5(\tran_dlc_com_reg[3]_0 [1]), .O(\shift_regs[16]_i_6_n_0 )); LUT6 #( .INIT(64'h00000000AAAAAA9A)) \shift_regs[17]_i_2 (.I0(\shift_regs_reg[17] ), .I1(\shift_regs[18]_i_5_n_0 ), .I2(\tran_frame_test[tprm] [1]), .I3(\tran_frame_test[tprm] [0]), .I4(\shift_regs[27]_i_5_n_0 ), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][1]_0 )); (* SOFT_HLUTNM = "soft_lutpair357" *) LUT2 #( .INIT(4'h8)) \shift_regs[17]_i_3 (.I0(tran_identifier[3]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[3]_0 )); LUT6 #( .INIT(64'h00000000AAAAAA9A)) \shift_regs[18]_i_2 (.I0(\shift_regs_reg[18] ), .I1(\shift_regs[18]_i_5_n_0 ), .I2(\tran_frame_test[tprm] [0]), .I3(\tran_frame_test[tprm] [1]), .I4(\shift_regs[27]_i_5_n_0 ), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][0]_0 )); (* SOFT_HLUTNM = "soft_lutpair357" *) LUT2 #( .INIT(4'h8)) \shift_regs[18]_i_3 (.I0(tran_identifier[4]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair350" *) LUT5 #( .INIT(32'hBBBFDDD5)) \shift_regs[18]_i_5 (.I0(\tran_frame_test[tprm] [4]), .I1(\tran_frame_test[tprm] [2]), .I2(\tran_frame_test[tprm] [1]), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test[tprm] [3]), .O(\shift_regs[18]_i_5_n_0 )); LUT6 #( .INIT(64'h00000000AAAAAAA9)) \shift_regs[19]_i_2 (.I0(\shift_regs_reg[19] ), .I1(\tran_frame_test_reg[tprm][4]_0 ), .I2(\shift_regs[27]_i_5_n_0 ), .I3(\tran_frame_test[tprm] [1]), .I4(\tran_frame_test[tprm] [0]), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][1]_1 )); (* SOFT_HLUTNM = "soft_lutpair356" *) LUT2 #( .INIT(4'h8)) \shift_regs[19]_i_3 (.I0(tran_identifier[5]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair356" *) LUT2 #( .INIT(4'h8)) \shift_regs[20]_i_3 (.I0(tran_identifier[6]), .I1(\shift_regs_reg[28]_0 ), .O(\tran_identifier_com_reg[6]_0 )); LUT6 #( .INIT(64'h0000000000400000)) \shift_regs[21]_i_5 (.I0(\tran_frame_test_reg[tprm][4]_0 ), .I1(\mr_ctrl_out[mode_tstm] ), .I2(\tran_frame_test[fcrc] ), .I3(\tran_frame_test[tprm] [2]), .I4(\tran_frame_test[tprm] [1]), .I5(\tran_frame_test[tprm] [0]), .O(\g_bit[0].reg_value_r_reg[0]_2 )); LUT6 #( .INIT(64'h0000000000400000)) \shift_regs[22]_i_5 (.I0(\tran_frame_test_reg[tprm][4]_0 ), .I1(\mr_ctrl_out[mode_tstm] ), .I2(\tran_frame_test[fcrc] ), .I3(\tran_frame_test[tprm] [2]), .I4(\tran_frame_test[tprm] [0]), .I5(\tran_frame_test[tprm] [1]), .O(\g_bit[0].reg_value_r_reg[0]_3 )); LUT6 #( .INIT(64'h00000000AAAAAA6A)) \shift_regs[24]_i_2 (.I0(\shift_regs_reg[24] ), .I1(\tran_frame_test[tprm] [1]), .I2(\tran_frame_test[tprm] [0]), .I3(\shift_regs[27]_i_5_n_0 ), .I4(\tran_frame_test_reg[tprm][4]_0 ), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][1]_2 )); LUT6 #( .INIT(64'h00000000AAAAAAA6)) \shift_regs[25]_i_2 (.I0(\shift_regs_reg[25] ), .I1(\tran_frame_test[tprm] [1]), .I2(\tran_frame_test[tprm] [0]), .I3(\shift_regs[27]_i_5_n_0 ), .I4(\tran_frame_test_reg[tprm][4]_0 ), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][1]_3 )); LUT6 #( .INIT(64'h00000000AAAAAAA6)) \shift_regs[26]_i_2 (.I0(\shift_regs_reg[26] ), .I1(\tran_frame_test[tprm] [0]), .I2(\tran_frame_test[tprm] [1]), .I3(\shift_regs[27]_i_5_n_0 ), .I4(\tran_frame_test_reg[tprm][4]_0 ), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][0]_1 )); (* SOFT_HLUTNM = "soft_lutpair350" *) LUT5 #( .INIT(32'hEEEABBBF)) \shift_regs[26]_i_5 (.I0(\tran_frame_test[tprm] [4]), .I1(\tran_frame_test[tprm] [2]), .I2(\tran_frame_test[tprm] [1]), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test[tprm] [3]), .O(\tran_frame_test_reg[tprm][4]_0 )); LUT6 #( .INIT(64'h00000000AAA9AAAA)) \shift_regs[27]_i_2 (.I0(\shift_regs_reg[27] ), .I1(\shift_regs[27]_i_5_n_0 ), .I2(\tran_frame_test[tprm] [1]), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test_reg[tprm][2]_0 ), .I5(\shift_regs_reg[11] ), .O(\tran_frame_test_reg[tprm][1]_4 )); (* SOFT_HLUTNM = "soft_lutpair353" *) LUT3 #( .INIT(8'h7F)) \shift_regs[27]_i_5 (.I0(\tran_frame_test[tprm] [2]), .I1(\tran_frame_test[fcrc] ), .I2(\mr_ctrl_out[mode_tstm] ), .O(\shift_regs[27]_i_5_n_0 )); LUT5 #( .INIT(32'hA8AA0200)) \shift_regs[28]_i_3 (.I0(\shift_regs_reg[28]_1 ), .I1(\shift_regs[28]_i_6_n_0 ), .I2(\shift_regs[31]_i_14_n_0 ), .I3(\tran_frame_test[fstc] ), .I4(\cc_stat[bst_ctr] [0]), .O(\tran_frame_test_reg[fstc]_0 )); LUT5 #( .INIT(32'hBBB8B8B8)) \shift_regs[28]_i_5 (.I0(tran_identifier[25]), .I1(\shift_regs_reg[28] ), .I2(\shift_regs[28]_i_9_n_0 ), .I3(\shift_regs_reg[28]_0 ), .I4(tran_identifier[14]), .O(\tran_identifier_com_reg[25]_0 )); (* SOFT_HLUTNM = "soft_lutpair352" *) LUT3 #( .INIT(8'hBF)) \shift_regs[28]_i_6 (.I0(\tran_frame_test[tprm] [2]), .I1(\tran_frame_test[tprm] [1]), .I2(\tran_frame_test[tprm] [0]), .O(\shift_regs[28]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair351" *) LUT5 #( .INIT(32'h00008000)) \shift_regs[28]_i_7 (.I0(\tran_frame_test[fcrc] ), .I1(\mr_ctrl_out[mode_tstm] ), .I2(\tran_frame_test[tprm] [0]), .I3(\tran_frame_test[tprm] [1]), .I4(\tran_frame_test[tprm] [2]), .O(\tran_frame_test_reg[fcrc]_0 )); LUT5 #( .INIT(32'hA8880888)) \shift_regs[28]_i_9 (.I0(\shift_regs[31]_i_21_0 ), .I1(\tran_dlc_com_reg[3]_0 [0]), .I2(\tran_frame_test[sdlc] ), .I3(\mr_ctrl_out[mode_tstm] ), .I4(\tran_frame_test[tprm] [0]), .O(\shift_regs[28]_i_9_n_0 )); LUT5 #( .INIT(32'hA8880888)) \shift_regs[29]_i_10 (.I0(\shift_regs[31]_i_21_0 ), .I1(\tran_dlc_com_reg[3]_0 [1]), .I2(\tran_frame_test[sdlc] ), .I3(\mr_ctrl_out[mode_tstm] ), .I4(\tran_frame_test[tprm] [1]), .O(\shift_regs[29]_i_10_n_0 )); LUT5 #( .INIT(32'hBBB8B8B8)) \shift_regs[29]_i_5 (.I0(tran_identifier[26]), .I1(\shift_regs_reg[28] ), .I2(\shift_regs[29]_i_10_n_0 ), .I3(\shift_regs_reg[28]_0 ), .I4(tran_identifier[15]), .O(\tran_identifier_com_reg[26]_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFEFFFFF)) \shift_regs[29]_i_6 (.I0(\tran_frame_test[tprm] [3]), .I1(\tran_frame_test[tprm] [4]), .I2(\mr_ctrl_out[mode_tstm] ), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test[tprm] [1]), .I5(\tran_frame_test[tprm] [2]), .O(\tran_frame_test_reg[tprm][3]_0 )); LUT5 #( .INIT(32'hA8880888)) \shift_regs[30]_i_10 (.I0(\shift_regs[31]_i_21_0 ), .I1(tran_dlc), .I2(\tran_frame_test[sdlc] ), .I3(\mr_ctrl_out[mode_tstm] ), .I4(\tran_frame_test[tprm] [2]), .O(\shift_regs[30]_i_10_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFEFFFFF)) \shift_regs[30]_i_8 (.I0(\tran_frame_test[tprm] [3]), .I1(\tran_frame_test[tprm] [4]), .I2(\mr_ctrl_out[mode_tstm] ), .I3(\tran_frame_test[tprm] [1]), .I4(\tran_frame_test[tprm] [0]), .I5(\tran_frame_test[tprm] [2]), .O(\tran_frame_test_reg[tprm][3]_1 )); LUT5 #( .INIT(32'hBBB8B8B8)) \shift_regs[30]_i_9 (.I0(tran_identifier[27]), .I1(\shift_regs_reg[28] ), .I2(\shift_regs[30]_i_10_n_0 ), .I3(\shift_regs_reg[28]_0 ), .I4(tran_identifier[16]), .O(\tran_identifier_com_reg[27]_0 )); LUT6 #( .INIT(64'hFFFFFFFDFDFDFDFD)) \shift_regs[31]_i_14 (.I0(\mr_ctrl_out[mode_tstm] ), .I1(\tran_frame_test[tprm] [4]), .I2(\tran_frame_test[tprm] [3]), .I3(\tran_frame_test[tprm] [0]), .I4(\tran_frame_test[tprm] [1]), .I5(\tran_frame_test[tprm] [2]), .O(\shift_regs[31]_i_14_n_0 )); (* SOFT_HLUTNM = "soft_lutpair353" *) LUT5 #( .INIT(32'hFEFFFFFF)) \shift_regs[31]_i_19 (.I0(\tran_frame_test[tprm] [0]), .I1(\tran_frame_test[tprm] [1]), .I2(\tran_frame_test[tprm] [2]), .I3(\tran_frame_test[fcrc] ), .I4(\mr_ctrl_out[mode_tstm] ), .O(\tran_frame_test_reg[tprm][0]_2 )); (* SOFT_HLUTNM = "soft_lutpair352" *) LUT5 #( .INIT(32'h00000057)) \shift_regs[31]_i_20 (.I0(\tran_frame_test[tprm] [2]), .I1(\tran_frame_test[tprm] [1]), .I2(\tran_frame_test[tprm] [0]), .I3(\tran_frame_test[tprm] [3]), .I4(\tran_frame_test[tprm] [4]), .O(\tran_frame_test_reg[tprm][2]_0 )); LUT5 #( .INIT(32'hBBB8B8B8)) \shift_regs[31]_i_21 (.I0(tran_identifier[28]), .I1(\shift_regs_reg[28] ), .I2(\shift_regs[31]_i_27_n_0 ), .I3(\shift_regs_reg[28]_0 ), .I4(tran_identifier[17]), .O(\tran_identifier_com_reg[28]_0 )); LUT5 #( .INIT(32'hA8880888)) \shift_regs[31]_i_27 (.I0(\shift_regs[31]_i_21_0 ), .I1(\tran_dlc_com_reg[3]_0 [2]), .I2(\tran_frame_test[sdlc] ), .I3(\mr_ctrl_out[mode_tstm] ), .I4(\tran_frame_test[tprm] [3]), .O(\shift_regs[31]_i_27_n_0 )); LUT6 #( .INIT(64'h5555555655555555)) \shift_regs[31]_i_6 (.I0(\cc_stat[bst_ctr] [1]), .I1(\tran_frame_test[tprm] [0]), .I2(\tran_frame_test[tprm] [1]), .I3(\tran_frame_test[tprm] [2]), .I4(\shift_regs[31]_i_14_n_0 ), .I5(\tran_frame_test[fstc] ), .O(\bst_ctr_q_reg[2] )); FDCE tran_brs_com_reg (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_brs_dbl_buf), .Q(tran_brs)); FDCE tran_brs_dbl_buf_reg (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [5]), .Q(tran_brs_dbl_buf)); FDCE \tran_dlc_com_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_dlc_dbl_buf[0]), .Q(\tran_dlc_com_reg[3]_0 [0])); FDCE \tran_dlc_com_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_dlc_dbl_buf[1]), .Q(\tran_dlc_com_reg[3]_0 [1])); FDCE \tran_dlc_com_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_dlc_dbl_buf[2]), .Q(tran_dlc)); FDCE \tran_dlc_com_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_dlc_dbl_buf[3]), .Q(\tran_dlc_com_reg[3]_0 [2])); FDCE \tran_dlc_dbl_buf_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [0]), .Q(tran_dlc_dbl_buf[0])); FDCE \tran_dlc_dbl_buf_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[1]), .Q(tran_dlc_dbl_buf[1])); FDCE \tran_dlc_dbl_buf_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[2]), .Q(tran_dlc_dbl_buf[2])); FDCE \tran_dlc_dbl_buf_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [1]), .Q(tran_dlc_dbl_buf[3])); FDCE \tran_frame_test_dbl_buf_reg[fcrc] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[1]), .Q(\tran_frame_test_dbl_buf_reg[fcrc]__0 )); FDCE \tran_frame_test_dbl_buf_reg[fstc] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [0]), .Q(\tran_frame_test_dbl_buf_reg[fstc]__0 )); FDCE \tran_frame_test_dbl_buf_reg[sdlc] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[2]), .Q(\tran_frame_test_dbl_buf_reg[sdlc]__0 )); FDCE \tran_frame_test_dbl_buf_reg[tprm][0] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[8]), .Q(\tran_frame_test_dbl_buf_reg[tprm] [0])); FDCE \tran_frame_test_dbl_buf_reg[tprm][1] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [5]), .Q(\tran_frame_test_dbl_buf_reg[tprm] [1])); FDCE \tran_frame_test_dbl_buf_reg[tprm][2] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [6]), .Q(\tran_frame_test_dbl_buf_reg[tprm] [2])); FDCE \tran_frame_test_dbl_buf_reg[tprm][3] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [7]), .Q(\tran_frame_test_dbl_buf_reg[tprm] [3])); FDCE \tran_frame_test_dbl_buf_reg[tprm][4] (.C(clk_sys_IBUF_BUFG), .CE(buffer_frame_test_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [8]), .Q(\tran_frame_test_dbl_buf_reg[tprm] [4])); FDCE \tran_frame_test_reg[fcrc] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[fcrc]__0 ), .Q(\tran_frame_test[fcrc] )); FDCE \tran_frame_test_reg[fstc] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[fstc]__0 ), .Q(\tran_frame_test[fstc] )); FDCE \tran_frame_test_reg[sdlc] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[sdlc]__0 ), .Q(\tran_frame_test[sdlc] )); FDCE \tran_frame_test_reg[tprm][0] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[tprm] [0]), .Q(\tran_frame_test[tprm] [0])); FDCE \tran_frame_test_reg[tprm][1] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[tprm] [1]), .Q(\tran_frame_test[tprm] [1])); FDCE \tran_frame_test_reg[tprm][2] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[tprm] [2]), .Q(\tran_frame_test[tprm] [2])); FDCE \tran_frame_test_reg[tprm][3] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[tprm] [3]), .Q(\tran_frame_test[tprm] [3])); FDCE \tran_frame_test_reg[tprm][4] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\tran_frame_test_dbl_buf_reg[tprm] [4]), .Q(\tran_frame_test[tprm] [4])); FDCE tran_frame_type_com_reg (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_frame_type_dbl_buf), .Q(tran_frame_type)); FDCE tran_frame_type_dbl_buf_reg (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[7]), .Q(tran_frame_type_dbl_buf)); FDCE tran_frame_valid_com_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(i_txarb_fsm_n_58), .Q(tran_frame_valid_com)); FDCE tran_ident_type_com_reg (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_ident_type_dbl_buf), .Q(tran_ident_type)); FDCE tran_ident_type_dbl_buf_reg (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [4]), .Q(tran_ident_type_dbl_buf)); FDCE \tran_identifier_com_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [0]), .Q(tran_identifier[0])); FDCE \tran_identifier_com_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [6]), .Q(\tran_identifier_com_reg[24]_0 [3])); FDCE \tran_identifier_com_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [7]), .Q(\tran_identifier_com_reg[24]_0 [4])); FDCE \tran_identifier_com_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [8]), .Q(\tran_identifier_com_reg[24]_0 [5])); FDCE \tran_identifier_com_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[13]), .Q(\tran_identifier_com_reg[24]_0 [6])); FDCE \tran_identifier_com_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[14]), .Q(tran_identifier[14])); FDCE \tran_identifier_com_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [9]), .Q(tran_identifier[15])); FDCE \tran_identifier_com_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [10]), .Q(tran_identifier[16])); FDCE \tran_identifier_com_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [11]), .Q(tran_identifier[17])); FDCE \tran_identifier_com_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [12]), .Q(\tran_identifier_com_reg[24]_0 [7])); FDCE \tran_identifier_com_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[19]), .Q(\tran_identifier_com_reg[24]_0 [8])); FDCE \tran_identifier_com_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[1]), .Q(tran_identifier[1])); FDCE \tran_identifier_com_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[20]), .Q(\tran_identifier_com_reg[24]_0 [9])); FDCE \tran_identifier_com_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [13]), .Q(\tran_identifier_com_reg[24]_0 [10])); FDCE \tran_identifier_com_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [14]), .Q(\tran_identifier_com_reg[24]_0 [11])); FDCE \tran_identifier_com_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [15]), .Q(\tran_identifier_com_reg[24]_0 [12])); FDCE \tran_identifier_com_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[24]), .Q(\tran_identifier_com_reg[24]_0 [13])); FDCE \tran_identifier_com_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[25]), .Q(tran_identifier[25])); FDCE \tran_identifier_com_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[26]), .Q(tran_identifier[26])); FDCE \tran_identifier_com_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [16]), .Q(tran_identifier[27])); FDCE \tran_identifier_com_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [17]), .Q(tran_identifier[28])); FDCE \tran_identifier_com_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[2]), .Q(tran_identifier[2])); FDCE \tran_identifier_com_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [1]), .Q(tran_identifier[3])); FDCE \tran_identifier_com_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [2]), .Q(tran_identifier[4])); FDCE \tran_identifier_com_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [3]), .Q(tran_identifier[5])); FDCE \tran_identifier_com_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [4]), .Q(tran_identifier[6])); FDCE \tran_identifier_com_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[7]), .Q(\tran_identifier_com_reg[24]_0 [0])); FDCE \tran_identifier_com_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[8]), .Q(\tran_identifier_com_reg[24]_0 [1])); FDCE \tran_identifier_com_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [5]), .Q(\tran_identifier_com_reg[24]_0 [2])); FDCE tran_is_rtr_com_reg (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_57), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_is_rtr_dbl_buf), .Q(tran_is_rtr)); FDCE tran_is_rtr_dbl_buf_reg (.C(clk_sys_IBUF_BUFG), .CE(buffer_md_w), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [3]), .Q(tran_is_rtr_dbl_buf)); FDCE \ts_low_internal_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [0]), .Q(ts_low_internal[0])); FDCE \ts_low_internal_reg[10] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [6]), .Q(ts_low_internal[10])); FDCE \ts_low_internal_reg[11] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [7]), .Q(ts_low_internal[11])); FDCE \ts_low_internal_reg[12] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [8]), .Q(ts_low_internal[12])); FDCE \ts_low_internal_reg[13] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[13]), .Q(ts_low_internal[13])); FDCE \ts_low_internal_reg[14] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[14]), .Q(ts_low_internal[14])); FDCE \ts_low_internal_reg[15] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [9]), .Q(ts_low_internal[15])); FDCE \ts_low_internal_reg[16] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [10]), .Q(ts_low_internal[16])); FDCE \ts_low_internal_reg[17] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [11]), .Q(ts_low_internal[17])); FDCE \ts_low_internal_reg[18] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [12]), .Q(ts_low_internal[18])); FDCE \ts_low_internal_reg[19] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[19]), .Q(ts_low_internal[19])); FDCE \ts_low_internal_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[1]), .Q(ts_low_internal[1])); FDCE \ts_low_internal_reg[20] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[20]), .Q(ts_low_internal[20])); FDCE \ts_low_internal_reg[21] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [13]), .Q(ts_low_internal[21])); FDCE \ts_low_internal_reg[22] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [14]), .Q(ts_low_internal[22])); FDCE \ts_low_internal_reg[23] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [15]), .Q(ts_low_internal[23])); FDCE \ts_low_internal_reg[24] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[24]), .Q(ts_low_internal[24])); FDCE \ts_low_internal_reg[25] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[25]), .Q(ts_low_internal[25])); FDCE \ts_low_internal_reg[26] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[26]), .Q(ts_low_internal[26])); FDCE \ts_low_internal_reg[27] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [16]), .Q(ts_low_internal[27])); FDCE \ts_low_internal_reg[28] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [17]), .Q(ts_low_internal[28])); FDCE \ts_low_internal_reg[29] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [18]), .Q(ts_low_internal[29])); FDCE \ts_low_internal_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[2]), .Q(ts_low_internal[2])); FDCE \ts_low_internal_reg[30] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [19]), .Q(ts_low_internal[30])); FDCE \ts_low_internal_reg[31] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [20]), .Q(ts_low_internal[31])); FDCE \ts_low_internal_reg[3] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [1]), .Q(ts_low_internal[3])); FDCE \ts_low_internal_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [2]), .Q(ts_low_internal[4])); FDCE \ts_low_internal_reg[5] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [3]), .Q(ts_low_internal[5])); FDCE \ts_low_internal_reg[6] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [4]), .Q(ts_low_internal[6])); FDCE \ts_low_internal_reg[7] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[7]), .Q(ts_low_internal[7])); FDCE \ts_low_internal_reg[8] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(tran_word[8]), .Q(ts_low_internal[8])); FDCE \ts_low_internal_reg[9] (.C(clk_sys_IBUF_BUFG), .CE(i_txarb_fsm_n_49), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(\FSM_sequential_curr_state_reg[1] [5]), .Q(ts_low_internal[9])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \txtb_hw_cmd_q[lock]_i_8 (.I0(txtb_available[3]), .I1(txtb_available[2]), .I2(Q[1]), .I3(txtb_available[1]), .I4(Q[0]), .I5(txtb_available[0]), .O(\txtb_hw_cmd_q[lock]_i_8_n_0 )); FDCE #( .INIT(1'b0)) \txtb_pointer_meta_q_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(i_txarb_fsm_n_61), .Q(\txtb_pointer_meta_q_reg[0]_0 )); FDPE #( .INIT(1'b0)) \txtb_pointer_meta_q_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(i_txarb_fsm_n_59), .PRE(\FSM_sequential_curr_state_reg[0]_1 ), .Q(\txtb_pointer_meta_q_reg[1]_0 )); FDCE #( .INIT(1'b0)) \txtb_pointer_meta_q_reg[4] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[0]_1 ), .D(i_txarb_fsm_n_60), .Q(\txtb_pointer_meta_q_reg[4]_0 )); LUT6 #( .INIT(64'hFFFFFFFF000CCFEF)) \txtb_ptr_q[4]_i_10 (.I0(\txtb_ptr_q[4]_i_12_n_0 ), .I1(\tran_dlc_com_reg[0]_0 ), .I2(\txtb_ptr_q_reg[4]_0 [0]), .I3(\tran_dlc_com_reg[0]_1 ), .I4(\txtb_ptr_q_reg[4]_0 [1]), .I5(\txtb_ptr_q[4]_i_13_n_0 ), .O(\txtb_ptr_q[4]_i_10_n_0 )); LUT6 #( .INIT(64'h3BFFFFFF7EFEFEFE)) \txtb_ptr_q[4]_i_11 (.I0(\tran_dlc_com_reg[3]_0 [1]), .I1(\tran_dlc_com_reg[3]_0 [2]), .I2(\tran_dlc_com_reg[3]_0 [0]), .I3(tran_frame_type), .I4(\mr_ctrl_out[mode_fde] ), .I5(tran_dlc), .O(\txtb_ptr_q[4]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair354" *) LUT3 #( .INIT(8'h54)) \txtb_ptr_q[4]_i_12 (.I0(\tran_dlc_com_reg[3]_0 [2]), .I1(\tran_dlc_com_reg[3]_0 [1]), .I2(\tran_dlc_com_reg[3]_0 [0]), .O(\txtb_ptr_q[4]_i_12_n_0 )); LUT6 #( .INIT(64'hE400000000000000)) \txtb_ptr_q[4]_i_13 (.I0(\tran_dlc_com_reg[3]_0 [0]), .I1(\tran_dlc_com_reg[3]_0 [1]), .I2(tran_dlc), .I3(\tran_dlc_com_reg[3]_0 [2]), .I4(\mr_ctrl_out[mode_fde] ), .I5(tran_frame_type), .O(\txtb_ptr_q[4]_i_13_n_0 )); LUT5 #( .INIT(32'h2A3F002A)) \txtb_ptr_q[4]_i_4 (.I0(\txtb_ptr_q[4]_i_10_n_0 ), .I1(\txtb_ptr_q_reg[4] ), .I2(\tran_dlc_com_reg[3]_3 ), .I3(\txtb_ptr_q_reg[4]_0 [2]), .I4(\txtb_ptr_q[4]_i_11_n_0 ), .O(\compl_ctr_q_reg[7] )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \txtb_ptr_q[4]_i_5 (.I0(\tran_dlc_com_reg[3]_0 [1]), .I1(\tran_dlc_com_reg[3]_0 [2]), .I2(\tran_dlc_com_reg[3]_0 [0]), .I3(tran_frame_type), .I4(\mr_ctrl_out[mode_fde] ), .I5(tran_dlc), .O(\tran_dlc_com_reg[1]_0 )); LUT6 #( .INIT(64'hD75FFFFFFFFFFFFF)) \txtb_ptr_q[4]_i_6 (.I0(\tran_dlc_com_reg[3]_0 [2]), .I1(\tran_dlc_com_reg[3]_0 [1]), .I2(tran_dlc), .I3(\tran_dlc_com_reg[3]_0 [0]), .I4(\mr_ctrl_out[mode_fde] ), .I5(tran_frame_type), .O(\tran_dlc_com_reg[3]_3 )); endmodule module txtb_even_top (txtb_port_b_data_out_i, mr_tx_command_txce_q, mr_tx_command_txcr_q, mr_tx_command_txca_q, D, curr_state, \FSM_sequential_curr_state_reg[2] , \adress[3] , \data_in[2] , \err_capt_err_pos_q_reg[3] , \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[0] , \FSM_sequential_curr_state_reg[1] , txtb_allow_bb, abort_or_skipped, txtb_available, tx_command_txce_valid, tx_command_txcr_valid, abort_or_skipped_0, \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, \FSM_sequential_curr_state_reg[2]_1 , sbe_IBUF, \r_data_reg[2] , adress_IBUF, \r_data_reg[2]_0 , \r_data_reg[2]_1 , \r_data_reg[2]_2 , \r_data_reg[2]_3 , \r_data_reg[2]_4 , \r_data_reg[2]_5 , \r_data[2]_i_2 , \r_data[2]_i_2_0 , \r_data[2]_i_2_1 , mr_tx_command_txce_q_reg_0, data_in_IBUF, mr_tx_command_txce_q_reg_1, mr_tx_command_txce_q_reg_2, Q, \mr_tx_priority[0] , \r_data[2]_i_2_2 , swr_IBUF, scs_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, \txtb_hw_cmd[lock] , \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state_reg[0]_0 , txtb_hw_cmd_cs, \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[0]_2 , mr_tx_command_txbi, \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[2]_4 , \FSM_sequential_curr_state_reg[1]_32 ); output [31:0]txtb_port_b_data_out_i; output mr_tx_command_txce_q; output mr_tx_command_txcr_q; output mr_tx_command_txca_q; output [0:0]D; output [1:0]curr_state; output [1:0]\FSM_sequential_curr_state_reg[2] ; output \adress[3] ; output \data_in[2] ; output \err_capt_err_pos_q_reg[3] ; output \FSM_sequential_curr_state_reg[2]_0 ; output \FSM_sequential_curr_state_reg[0] ; output \FSM_sequential_curr_state_reg[1] ; output [0:0]txtb_allow_bb; output abort_or_skipped; output [0:0]txtb_available; output tx_command_txce_valid; output tx_command_txcr_valid; output abort_or_skipped_0; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input \FSM_sequential_curr_state_reg[2]_1 ; input [3:0]sbe_IBUF; input \r_data_reg[2] ; input [9:0]adress_IBUF; input \r_data_reg[2]_0 ; input \r_data_reg[2]_1 ; input \r_data_reg[2]_2 ; input \r_data_reg[2]_3 ; input \r_data_reg[2]_4 ; input \r_data_reg[2]_5 ; input \r_data[2]_i_2 ; input \r_data[2]_i_2_0 ; input \r_data[2]_i_2_1 ; input mr_tx_command_txce_q_reg_0; input [2:0]data_in_IBUF; input mr_tx_command_txce_q_reg_1; input mr_tx_command_txce_q_reg_2; input [2:0]Q; input [1:0]\mr_tx_priority[0] ; input \r_data[2]_i_2_2 ; input swr_IBUF; input scs_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input \txtb_hw_cmd[lock] ; input [1:0]\FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state_reg[0]_0 ; input [0:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state_reg[0]_1 ; input \FSM_sequential_curr_state_reg[0]_2 ; input [1:0]mr_tx_command_txbi; input \FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[2]_4 ; input \FSM_sequential_curr_state_reg[1]_32 ; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [0:0]D; wire [15:0]DIADI; wire [15:0]DIBDI; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire [1:0]\FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire [1:0]\FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire [2:0]Q; wire abort_or_skipped; wire abort_or_skipped_0; wire \adress[3] ; wire [9:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [1:0]curr_state; wire \data_in[2] ; wire [2:0]data_in_IBUF; wire \err_capt_err_pos_q_reg[3] ; wire [0:0]\i_dp_inf_ram_be/g_byte[0].byte_we_reg ; wire \i_dp_inf_ram_be/p_1_in ; wire \i_dp_inf_ram_be/p_2_in ; wire \i_dp_inf_ram_be/p_3_in ; wire \mr_ctrl_out[tx_command_txca] ; wire \mr_ctrl_out[tx_command_txce] ; wire \mr_ctrl_out[tx_command_txcr] ; wire \mr_tst_out[tst_control_twrstb] ; wire [1:0]mr_tx_command_txbi; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txce_q_reg_0; wire mr_tx_command_txce_q_reg_1; wire mr_tx_command_txce_q_reg_2; wire mr_tx_command_txcr_q; wire mr_tx_command_txcr_q_i_2_n_0; wire [1:0]\mr_tx_priority[0] ; wire \r_data[2]_i_2 ; wire \r_data[2]_i_2_0 ; wire \r_data[2]_i_2_1 ; wire \r_data[2]_i_2_2 ; wire \r_data_reg[2] ; wire \r_data_reg[2]_0 ; wire \r_data_reg[2]_1 ; wire \r_data_reg[2]_2 ; wire \r_data_reg[2]_3 ; wire \r_data_reg[2]_4 ; wire \r_data_reg[2]_5 ; wire [3:0]sbe_IBUF; wire scs_IBUF; wire swr_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire [0:0]txtb_allow_bb; wire [0:0]txtb_available; wire \txtb_hw_cmd[lock] ; wire [0:0]txtb_hw_cmd_cs; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; LUT3 #( .INIT(8'hBF)) \g_bit[0].reg_value_r[0]_i_2__7 (.I0(adress_IBUF[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[2]), .O(\adress[3] )); txtb_fsm_90 i_txtb_fsm (.D(D), .\FSM_sequential_curr_state_reg[0]_0 (curr_state[0]), .\FSM_sequential_curr_state_reg[0]_1 (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_2 (\FSM_sequential_curr_state_reg[2] [0]), .\FSM_sequential_curr_state_reg[0]_3 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_4 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[0]_5 (\FSM_sequential_curr_state_reg[0]_2 ), .\FSM_sequential_curr_state_reg[0]_6 (mr_tx_command_txca_q), .\FSM_sequential_curr_state_reg[0]_7 (mr_tx_command_txce_q), .\FSM_sequential_curr_state_reg[1]_0 (curr_state[1]), .\FSM_sequential_curr_state_reg[1]_1 (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_10 (\FSM_sequential_curr_state_reg[1]_8 ), .\FSM_sequential_curr_state_reg[1]_11 (\FSM_sequential_curr_state_reg[1]_9 ), .\FSM_sequential_curr_state_reg[1]_12 (\FSM_sequential_curr_state_reg[1]_10 ), .\FSM_sequential_curr_state_reg[1]_13 (\FSM_sequential_curr_state_reg[1]_11 ), .\FSM_sequential_curr_state_reg[1]_14 (\FSM_sequential_curr_state_reg[1]_12 ), .\FSM_sequential_curr_state_reg[1]_15 (\FSM_sequential_curr_state_reg[1]_13 ), .\FSM_sequential_curr_state_reg[1]_16 (\FSM_sequential_curr_state_reg[1]_14 ), .\FSM_sequential_curr_state_reg[1]_17 (\FSM_sequential_curr_state_reg[1]_15 ), .\FSM_sequential_curr_state_reg[1]_18 (\FSM_sequential_curr_state_reg[1]_16 ), .\FSM_sequential_curr_state_reg[1]_19 (\FSM_sequential_curr_state_reg[1]_17 ), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_20 (\FSM_sequential_curr_state_reg[1]_18 ), .\FSM_sequential_curr_state_reg[1]_21 (\FSM_sequential_curr_state_reg[1]_19 ), .\FSM_sequential_curr_state_reg[1]_22 (\FSM_sequential_curr_state_reg[1]_20 ), .\FSM_sequential_curr_state_reg[1]_23 (\FSM_sequential_curr_state_reg[1]_21 ), .\FSM_sequential_curr_state_reg[1]_24 (\FSM_sequential_curr_state_reg[1]_22 ), .\FSM_sequential_curr_state_reg[1]_25 (\FSM_sequential_curr_state_reg[1]_23 ), .\FSM_sequential_curr_state_reg[1]_26 (\FSM_sequential_curr_state_reg[1]_24 ), .\FSM_sequential_curr_state_reg[1]_27 (\FSM_sequential_curr_state_reg[1]_25 ), .\FSM_sequential_curr_state_reg[1]_28 (\FSM_sequential_curr_state_reg[1]_26 ), .\FSM_sequential_curr_state_reg[1]_29 (\FSM_sequential_curr_state_reg[1]_27 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_30 (\FSM_sequential_curr_state_reg[1]_28 ), .\FSM_sequential_curr_state_reg[1]_31 (\FSM_sequential_curr_state_reg[1]_29 ), .\FSM_sequential_curr_state_reg[1]_32 (\FSM_sequential_curr_state_reg[1]_30 ), .\FSM_sequential_curr_state_reg[1]_33 (\FSM_sequential_curr_state_reg[1]_31 ), .\FSM_sequential_curr_state_reg[1]_34 (mr_tx_command_txcr_q), .\FSM_sequential_curr_state_reg[1]_35 (\FSM_sequential_curr_state_reg[1]_32 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_5 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[1]_6 (\FSM_sequential_curr_state_reg[1]_4 ), .\FSM_sequential_curr_state_reg[1]_7 (\FSM_sequential_curr_state_reg[1]_5 ), .\FSM_sequential_curr_state_reg[1]_8 (\FSM_sequential_curr_state_reg[1]_6 ), .\FSM_sequential_curr_state_reg[1]_9 (\FSM_sequential_curr_state_reg[1]_7 ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2] [1]), .\FSM_sequential_curr_state_reg[2]_1 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_2 ), .\FSM_sequential_curr_state_reg[2]_3 (\FSM_sequential_curr_state_reg[2]_3 ), .\FSM_sequential_curr_state_reg[2]_4 (\FSM_sequential_curr_state_reg[2]_4 ), .\FSM_sequential_curr_state_reg[2]_5 (\FSM_sequential_curr_state_reg[2]_1 ), .Q(Q), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .abort_or_skipped(abort_or_skipped), .abort_or_skipped_0(abort_or_skipped_0), .adress_IBUF({adress_IBUF[5],adress_IBUF[1:0]}), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\err_capt_err_pos_q_reg[3] (\err_capt_err_pos_q_reg[3] ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .mr_tx_command_txbi(mr_tx_command_txbi), .\mr_tx_priority[0] (\mr_tx_priority[0] ), .\r_data[2]_i_2_0 (\r_data[2]_i_2 ), .\r_data[2]_i_2_1 (\r_data[2]_i_2_0 ), .\r_data[2]_i_2_2 (\r_data[2]_i_2_1 ), .\r_data[2]_i_2_3 (\r_data[2]_i_2_2 ), .\r_data_reg[2] (\r_data_reg[2] ), .\r_data_reg[2]_0 (\r_data_reg[2]_0 ), .\r_data_reg[2]_1 (\r_data_reg[2]_1 ), .\r_data_reg[2]_2 (\r_data_reg[2]_2 ), .\r_data_reg[2]_3 (\r_data_reg[2]_3 ), .\r_data_reg[2]_4 (\r_data_reg[2]_4 ), .\r_data_reg[2]_5 (\r_data_reg[2]_5 ), .sbe_IBUF(sbe_IBUF), .tst_ena(tst_ena), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txcr_valid(tx_command_txcr_valid), .txtb_allow_bb(txtb_allow_bb), .txtb_available(txtb_available), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); txtb_ram i_txtb_ram (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .adress_IBUF(adress_IBUF[9:6]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h2)) int_status_i_3__0 (.I0(data_in_IBUF[2]), .I1(mr_tx_command_txce_q_reg_0), .O(\data_in[2] )); LUT6 #( .INIT(64'h0000000000000080)) mr_tx_command_txca_q_i_1 (.I0(\data_in[2] ), .I1(adress_IBUF[4]), .I2(adress_IBUF[3]), .I3(\adress[3] ), .I4(adress_IBUF[5]), .I5(mr_tx_command_txce_q_reg_2), .O(\mr_ctrl_out[tx_command_txca] )); FDCE mr_tx_command_txca_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_1 ), .D(\mr_ctrl_out[tx_command_txca] ), .Q(mr_tx_command_txca_q)); LUT6 #( .INIT(64'h0000000000000004)) mr_tx_command_txce_q_i_1 (.I0(mr_tx_command_txce_q_reg_0), .I1(data_in_IBUF[0]), .I2(mr_tx_command_txce_q_reg_1), .I3(\adress[3] ), .I4(adress_IBUF[5]), .I5(mr_tx_command_txce_q_reg_2), .O(\mr_ctrl_out[tx_command_txce] )); FDCE mr_tx_command_txce_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_1 ), .D(\mr_ctrl_out[tx_command_txce] ), .Q(mr_tx_command_txce_q)); LUT6 #( .INIT(64'h0000000000000080)) mr_tx_command_txcr_q_i_1 (.I0(mr_tx_command_txcr_q_i_2_n_0), .I1(adress_IBUF[4]), .I2(adress_IBUF[3]), .I3(\adress[3] ), .I4(adress_IBUF[5]), .I5(mr_tx_command_txce_q_reg_2), .O(\mr_ctrl_out[tx_command_txcr] )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h2)) mr_tx_command_txcr_q_i_2 (.I0(data_in_IBUF[1]), .I1(mr_tx_command_txce_q_reg_0), .O(mr_tx_command_txcr_q_i_2_n_0)); FDCE mr_tx_command_txcr_q_reg (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_1 ), .D(\mr_ctrl_out[tx_command_txcr] ), .Q(mr_tx_command_txcr_q)); endmodule (* ORIG_REF_NAME = "txtb_even_top" *) module txtb_even_top__parameterized0 (txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[0] , curr_state, \FSM_sequential_curr_state_reg[2] , \retr_ctr_q_reg[0] , \FSM_sequential_curr_state_reg[2]_0 , \retr_ctr_q_reg[2] , \FSM_sequential_curr_state_reg[1] , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[1]_0 , txtb_allow_bb, txtb_available, \FSM_sequential_curr_state_reg[2]_1 , \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , \FSM_sequential_curr_state_reg[1]_32 , clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, adress_IBUF, Q, \mr_tx_priority[2] , curr_state_0, \r_data[2]_i_5 , swr_IBUF, scs_IBUF, sbe_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, \txtb_hw_cmd[lock] , \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state_reg[0]_1 , txtb_hw_cmd_cs, \FSM_sequential_curr_state_reg[0]_2 , tx_command_txcr_valid, \FSM_sequential_curr_state_reg[0]_3 , mr_tx_command_txca_q, mr_tx_command_txbi, mr_tx_command_txce_q, abort_or_skipped, tx_command_txce_valid, mr_tx_command_txcr_q, fsm_wait_state_q_i_5, \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[2]_4 , \FSM_sequential_curr_state_reg[1]_33 , \FSM_sequential_curr_state_reg[2]_5 ); output [31:0]txtb_port_b_data_out_i; output \FSM_sequential_curr_state_reg[0] ; output [1:0]curr_state; output [0:0]\FSM_sequential_curr_state_reg[2] ; output \retr_ctr_q_reg[0] ; output \FSM_sequential_curr_state_reg[2]_0 ; output \retr_ctr_q_reg[2] ; output \FSM_sequential_curr_state_reg[1] ; output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[1]_0 ; output [0:0]txtb_allow_bb; output [0:0]txtb_available; output \FSM_sequential_curr_state_reg[2]_1 ; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; output \FSM_sequential_curr_state_reg[1]_32 ; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [5:0]adress_IBUF; input [3:0]Q; input [2:0]\mr_tx_priority[2] ; input [1:0]curr_state_0; input [0:0]\r_data[2]_i_5 ; input swr_IBUF; input scs_IBUF; input [3:0]sbe_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input \txtb_hw_cmd[lock] ; input [1:0]\FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state_reg[0]_1 ; input [0:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state_reg[0]_2 ; input tx_command_txcr_valid; input \FSM_sequential_curr_state_reg[0]_3 ; input mr_tx_command_txca_q; input [0:0]mr_tx_command_txbi; input mr_tx_command_txce_q; input abort_or_skipped; input tx_command_txce_valid; input mr_tx_command_txcr_q; input [0:0]fsm_wait_state_q_i_5; input \FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[2]_4 ; input \FSM_sequential_curr_state_reg[1]_33 ; input \FSM_sequential_curr_state_reg[2]_5 ; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_33 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire [0:0]\FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire [1:0]\FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire \FSM_sequential_curr_state_reg[2]_5 ; wire [3:0]Q; wire abort_or_skipped; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [1:0]curr_state; wire [1:0]curr_state_0; wire [0:0]fsm_wait_state_q_i_5; wire [0:0]\i_dp_inf_ram_be/g_byte[0].byte_we_reg ; wire \i_dp_inf_ram_be/p_1_in ; wire \i_dp_inf_ram_be/p_2_in ; wire \i_dp_inf_ram_be/p_3_in ; wire \mr_tst_out[tst_control_twrstb] ; wire [0:0]mr_tx_command_txbi; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txcr_q; wire [2:0]\mr_tx_priority[2] ; wire [0:0]\r_data[2]_i_5 ; wire \retr_ctr_q_reg[0] ; wire \retr_ctr_q_reg[2] ; wire [3:0]sbe_IBUF; wire scs_IBUF; wire swr_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire [0:0]txtb_allow_bb; wire [0:0]txtb_available; wire \txtb_hw_cmd[lock] ; wire [0:0]txtb_hw_cmd_cs; wire [2:2]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; txtb_fsm_86 i_txtb_fsm (.\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_1 (curr_state[0]), .\FSM_sequential_curr_state_reg[0]_2 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_3 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[0]_4 (\FSM_sequential_curr_state_reg[0]_2 ), .\FSM_sequential_curr_state_reg[0]_5 (\FSM_sequential_curr_state_reg[0]_3 ), .\FSM_sequential_curr_state_reg[1]_0 (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_1 (curr_state[1]), .\FSM_sequential_curr_state_reg[1]_10 (\FSM_sequential_curr_state_reg[1]_8 ), .\FSM_sequential_curr_state_reg[1]_11 (\FSM_sequential_curr_state_reg[1]_9 ), .\FSM_sequential_curr_state_reg[1]_12 (\FSM_sequential_curr_state_reg[1]_10 ), .\FSM_sequential_curr_state_reg[1]_13 (\FSM_sequential_curr_state_reg[1]_11 ), .\FSM_sequential_curr_state_reg[1]_14 (\FSM_sequential_curr_state_reg[1]_12 ), .\FSM_sequential_curr_state_reg[1]_15 (\FSM_sequential_curr_state_reg[1]_13 ), .\FSM_sequential_curr_state_reg[1]_16 (\FSM_sequential_curr_state_reg[1]_14 ), .\FSM_sequential_curr_state_reg[1]_17 (\FSM_sequential_curr_state_reg[1]_15 ), .\FSM_sequential_curr_state_reg[1]_18 (\FSM_sequential_curr_state_reg[1]_16 ), .\FSM_sequential_curr_state_reg[1]_19 (\FSM_sequential_curr_state_reg[1]_17 ), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_20 (\FSM_sequential_curr_state_reg[1]_18 ), .\FSM_sequential_curr_state_reg[1]_21 (\FSM_sequential_curr_state_reg[1]_19 ), .\FSM_sequential_curr_state_reg[1]_22 (\FSM_sequential_curr_state_reg[1]_20 ), .\FSM_sequential_curr_state_reg[1]_23 (\FSM_sequential_curr_state_reg[1]_21 ), .\FSM_sequential_curr_state_reg[1]_24 (\FSM_sequential_curr_state_reg[1]_22 ), .\FSM_sequential_curr_state_reg[1]_25 (\FSM_sequential_curr_state_reg[1]_23 ), .\FSM_sequential_curr_state_reg[1]_26 (\FSM_sequential_curr_state_reg[1]_24 ), .\FSM_sequential_curr_state_reg[1]_27 (\FSM_sequential_curr_state_reg[1]_25 ), .\FSM_sequential_curr_state_reg[1]_28 (\FSM_sequential_curr_state_reg[1]_26 ), .\FSM_sequential_curr_state_reg[1]_29 (\FSM_sequential_curr_state_reg[1]_27 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_30 (\FSM_sequential_curr_state_reg[1]_28 ), .\FSM_sequential_curr_state_reg[1]_31 (\FSM_sequential_curr_state_reg[1]_29 ), .\FSM_sequential_curr_state_reg[1]_32 (\FSM_sequential_curr_state_reg[1]_30 ), .\FSM_sequential_curr_state_reg[1]_33 (\FSM_sequential_curr_state_reg[1]_31 ), .\FSM_sequential_curr_state_reg[1]_34 (\FSM_sequential_curr_state_reg[1]_32 ), .\FSM_sequential_curr_state_reg[1]_35 (\FSM_sequential_curr_state_reg[1]_33 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_5 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[1]_6 (\FSM_sequential_curr_state_reg[1]_4 ), .\FSM_sequential_curr_state_reg[1]_7 (\FSM_sequential_curr_state_reg[1]_5 ), .\FSM_sequential_curr_state_reg[1]_8 (\FSM_sequential_curr_state_reg[1]_6 ), .\FSM_sequential_curr_state_reg[1]_9 (\FSM_sequential_curr_state_reg[1]_7 ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2] ), .\FSM_sequential_curr_state_reg[2]_1 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_1 ), .\FSM_sequential_curr_state_reg[2]_3 (\FSM_sequential_curr_state_reg[2]_2 ), .\FSM_sequential_curr_state_reg[2]_4 (\FSM_sequential_curr_state_reg[2]_3 ), .\FSM_sequential_curr_state_reg[2]_5 (\FSM_sequential_curr_state_reg[2]_4 ), .\FSM_sequential_curr_state_reg[2]_6 (\FSM_sequential_curr_state_reg[2]_5 ), .Q(Q), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .abort_or_skipped(abort_or_skipped), .adress_IBUF(adress_IBUF[1:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .curr_state_0(curr_state_0), .fsm_wait_state_q_i_5(fsm_wait_state_q_i_5), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .mr_tx_command_txbi(mr_tx_command_txbi), .mr_tx_command_txca_q(mr_tx_command_txca_q), .mr_tx_command_txce_q(mr_tx_command_txce_q), .mr_tx_command_txcr_q(mr_tx_command_txcr_q), .\mr_tx_priority[2] (\mr_tx_priority[2] ), .\r_data[2]_i_5 (\r_data[2]_i_5 ), .\retr_ctr_q_reg[0] (\retr_ctr_q_reg[0] ), .\retr_ctr_q_reg[2] (\retr_ctr_q_reg[2] ), .sbe_IBUF(sbe_IBUF), .tst_ena(tst_ena), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txcr_valid(tx_command_txcr_valid), .txtb_allow_bb(txtb_allow_bb), .txtb_available(txtb_available), .\txtb_hw_cmd[lock] (\txtb_hw_cmd[lock] ), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); txtb_ram__parameterized1 i_txtb_ram (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .adress_IBUF(adress_IBUF[5:2]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule module txtb_fsm (\FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[2]_1 , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state_reg[1]_1 , WEBWE, \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[2]_3 , txtb_allow_bb, \FSM_sequential_curr_state_reg[0]_3 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , \FSM_sequential_curr_state_reg[1]_32 , \FSM_sequential_curr_state_reg[1]_33 , \FSM_sequential_curr_state_reg[1]_34 , adress_IBUF, \r_data[15]_i_2 , \mr_tx_priority[3] , sbe_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, txtb_port_a_cs, \FSM_sequential_curr_state_reg[1]_35 , tx_command_txce_valid, tx_command_txcr_valid, \FSM_sequential_curr_state_reg[2]_4 , \FSM_sequential_curr_state[2]_i_5__2_0 , txtb_hw_cmd_cs, abort_applied, \FSM_sequential_curr_state_reg[0]_4 , \FSM_sequential_curr_state[2]_i_5__2_1 , \FSM_sequential_curr_state_reg[0]_5 , txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[2]_5 , \FSM_sequential_curr_state_reg[2]_6 , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[2]_7 ); output \FSM_sequential_curr_state_reg[2]_0 ; output \FSM_sequential_curr_state_reg[2]_1 ; output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[2]_2 ; output \FSM_sequential_curr_state_reg[0]_2 ; output \FSM_sequential_curr_state_reg[1]_1 ; output [3:0]WEBWE; output \FSM_sequential_curr_state_reg[1]_2 ; output [0:0]\FSM_sequential_curr_state_reg[2]_3 ; output [0:0]txtb_allow_bb; output \FSM_sequential_curr_state_reg[0]_3 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; output \FSM_sequential_curr_state_reg[1]_32 ; output \FSM_sequential_curr_state_reg[1]_33 ; output \FSM_sequential_curr_state_reg[1]_34 ; input [2:0]adress_IBUF; input \r_data[15]_i_2 ; input [2:0]\mr_tx_priority[3] ; input [3:0]sbe_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input [0:0]txtb_port_a_cs; input \FSM_sequential_curr_state_reg[1]_35 ; input tx_command_txce_valid; input tx_command_txcr_valid; input \FSM_sequential_curr_state_reg[2]_4 ; input \FSM_sequential_curr_state[2]_i_5__2_0 ; input [0:0]txtb_hw_cmd_cs; input abort_applied; input \FSM_sequential_curr_state_reg[0]_4 ; input \FSM_sequential_curr_state[2]_i_5__2_1 ; input \FSM_sequential_curr_state_reg[0]_5 ; input [31:0]txtb_port_b_data_out_i; input \FSM_sequential_curr_state_reg[2]_5 ; input \FSM_sequential_curr_state_reg[2]_6 ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[2]_7 ; wire \FSM_sequential_curr_state[0]_i_1__2_n_0 ; wire \FSM_sequential_curr_state[0]_i_2__2_n_0 ; wire \FSM_sequential_curr_state[0]_i_4__2_n_0 ; wire \FSM_sequential_curr_state[1]_i_1__2_n_0 ; wire \FSM_sequential_curr_state[1]_i_2__2_n_0 ; wire \FSM_sequential_curr_state[2]_i_11__2_n_0 ; wire \FSM_sequential_curr_state[2]_i_12__1_n_0 ; wire \FSM_sequential_curr_state[2]_i_1__2_n_0 ; wire \FSM_sequential_curr_state[2]_i_3__2_n_0 ; wire \FSM_sequential_curr_state[2]_i_5__2_0 ; wire \FSM_sequential_curr_state[2]_i_5__2_1 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_33 ; wire \FSM_sequential_curr_state_reg[1]_34 ; wire \FSM_sequential_curr_state_reg[1]_35 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire [0:0]\FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire \FSM_sequential_curr_state_reg[2]_5 ; wire \FSM_sequential_curr_state_reg[2]_6 ; wire \FSM_sequential_curr_state_reg[2]_7 ; wire [3:0]WEBWE; wire abort_applied; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire \i_txtb_ram/txtb_port_a_write_i ; wire \mr_tst_out[tst_control_twrstb] ; wire [2:0]\mr_tx_priority[3] ; wire \r_data[15]_i_2 ; wire [3:0]sbe_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire txt_fsm_ce; wire [0:0]txtb_allow_bb; wire [0:0]txtb_hw_cmd_cs; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \FSM_sequential_curr_state[0]_i_1__2 (.I0(\FSM_sequential_curr_state[0]_i_2__2_n_0 ), .I1(\FSM_sequential_curr_state_reg[0]_5 ), .I2(txtb_allow_bb), .I3(\FSM_sequential_curr_state[0]_i_4__2_n_0 ), .I4(txt_fsm_ce), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state[0]_i_1__2_n_0 )); LUT6 #( .INIT(64'hAAAABBAAAAAAAFAA)) \FSM_sequential_curr_state[0]_i_2__2 (.I0(\FSM_sequential_curr_state[2]_i_12__1_n_0 ), .I1(tx_command_txce_valid), .I2(\FSM_sequential_curr_state_reg[2]_4 ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_1 ), .O(\FSM_sequential_curr_state[0]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT3 #( .INIT(8'hC2)) \FSM_sequential_curr_state[0]_i_3 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(txtb_allow_bb)); LUT6 #( .INIT(64'h500100005F010000)) \FSM_sequential_curr_state[0]_i_4__2 (.I0(abort_applied), .I1(\FSM_sequential_curr_state_reg[0]_4 ), .I2(\FSM_sequential_curr_state_reg[2]_1 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .I5(tx_command_txce_valid), .O(\FSM_sequential_curr_state[0]_i_4__2_n_0 )); LUT3 #( .INIT(8'hB8)) \FSM_sequential_curr_state[1]_i_1__2 (.I0(\FSM_sequential_curr_state[1]_i_2__2_n_0 ), .I1(txt_fsm_ce), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(\FSM_sequential_curr_state[1]_i_1__2_n_0 )); LUT6 #( .INIT(64'hAAAAAAAABEBFAEAE)) \FSM_sequential_curr_state[1]_i_2__2 (.I0(\FSM_sequential_curr_state_reg[1]_35 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_1 ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(tx_command_txce_valid), .I5(tx_command_txcr_valid), .O(\FSM_sequential_curr_state[1]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'h02)) \FSM_sequential_curr_state[1]_i_4__1 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_1 ), .O(\FSM_sequential_curr_state_reg[0]_3 )); LUT6 #( .INIT(64'hFFAAEAAAEAAAEAAA)) \FSM_sequential_curr_state[2]_i_11__2 (.I0(\FSM_sequential_curr_state[2]_i_3__2_n_0 ), .I1(txtb_hw_cmd_cs), .I2(\FSM_sequential_curr_state[2]_i_5__2_1 ), .I3(\FSM_sequential_curr_state_reg[1]_2 ), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .I5(abort_applied), .O(\FSM_sequential_curr_state[2]_i_11__2_n_0 )); LUT6 #( .INIT(64'h88F0F00088F0F0F0)) \FSM_sequential_curr_state[2]_i_12__1 (.I0(\FSM_sequential_curr_state[2]_i_5__2_0 ), .I1(txtb_hw_cmd_cs), .I2(tx_command_txcr_valid), .I3(\FSM_sequential_curr_state_reg[2]_1 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state[2]_i_12__1_n_0 )); LUT5 #( .INIT(32'hFEFFFE00)) \FSM_sequential_curr_state[2]_i_1__2 (.I0(\FSM_sequential_curr_state_reg[2]_5 ), .I1(\FSM_sequential_curr_state[2]_i_3__2_n_0 ), .I2(\FSM_sequential_curr_state_reg[2]_6 ), .I3(txt_fsm_ce), .I4(\FSM_sequential_curr_state_reg[2]_1 ), .O(\FSM_sequential_curr_state[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT5 #( .INIT(32'hF00C0008)) \FSM_sequential_curr_state[2]_i_3__2 (.I0(\FSM_sequential_curr_state_reg[2]_4 ), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_1 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(\FSM_sequential_curr_state_reg[0]_5 ), .O(\FSM_sequential_curr_state[2]_i_3__2_n_0 )); LUT6 #( .INIT(64'hEFEEEFEEFEEEEFEE)) \FSM_sequential_curr_state[2]_i_5__2 (.I0(\FSM_sequential_curr_state[2]_i_11__2_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_12__1_n_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(tx_command_txce_valid), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_1 ), .O(txt_fsm_ce)); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[2]_i_7__2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .O(\FSM_sequential_curr_state_reg[1]_2 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_7 ), .D(\FSM_sequential_curr_state[0]_i_1__2_n_0 ), .Q(\FSM_sequential_curr_state_reg[0]_0 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDPE #( .INIT(1'b1)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\FSM_sequential_curr_state[1]_i_1__2_n_0 ), .PRE(\FSM_sequential_curr_state_reg[2]_7 ), .Q(\FSM_sequential_curr_state_reg[1]_0 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_7 ), .D(\FSM_sequential_curr_state[2]_i_1__2_n_0 ), .Q(\FSM_sequential_curr_state_reg[2]_1 )); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_43__3 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[3]), .O(WEBWE[3])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_44__3 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[2]), .O(WEBWE[2])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_45__3 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[1]), .O(WEBWE[1])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_46__3 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[0]), .O(WEBWE[0])); LUT6 #( .INIT(64'h8888B8B8B8B888B8)) \g_ram_rst_false.ram_memory_reg_i_48__1 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(tst_ena), .I2(txtb_port_a_cs), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_1 ), .O(\i_txtb_ram/txtb_port_a_write_i )); LUT6 #( .INIT(64'h00FF004700000047)) \r_data[12]_i_8 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\mr_tx_priority[3] [0]), .O(\FSM_sequential_curr_state_reg[0]_1 )); LUT4 #( .INIT(16'h3202)) \r_data[13]_i_8 (.I0(\FSM_sequential_curr_state_reg[2]_1 ), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_tx_priority[3] [1]), .O(\FSM_sequential_curr_state_reg[2]_2 )); LUT6 #( .INIT(64'hFF00FFC7FFFFFFC7)) \r_data[14]_i_9 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_1 ), .I3(adress_IBUF[0]), .I4(adress_IBUF[1]), .I5(\mr_tx_priority[3] [2]), .O(\FSM_sequential_curr_state_reg[0]_2 )); LUT6 #( .INIT(64'hFFFFFFFFAAAAAAA8)) \r_data[15]_i_6 (.I0(adress_IBUF[2]), .I1(adress_IBUF[1]), .I2(adress_IBUF[0]), .I3(\FSM_sequential_curr_state_reg[2]_1 ), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .I5(\r_data[15]_i_2 ), .O(\FSM_sequential_curr_state_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT5 #( .INIT(32'hBBBBBBFB)) \r_data[2]_i_11 (.I0(adress_IBUF[2]), .I1(adress_IBUF[1]), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_1 ), .I4(\FSM_sequential_curr_state_reg[0]_0 ), .O(\FSM_sequential_curr_state_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h0010)) \select_buf_index_reg[1]_i_4 (.I0(\FSM_sequential_curr_state_reg[2]_1 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(abort_applied), .O(\FSM_sequential_curr_state_reg[2]_3 )); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT4 #( .INIT(16'h9800)) tran_brs_dbl_buf_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[9]), .O(\FSM_sequential_curr_state_reg[1]_25 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[0]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[0]), .O(\FSM_sequential_curr_state_reg[1]_34 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[1]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[1]), .O(\FSM_sequential_curr_state_reg[1]_33 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[2]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[2]), .O(\FSM_sequential_curr_state_reg[1]_32 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[3]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[3]), .O(\FSM_sequential_curr_state_reg[1]_31 )); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT4 #( .INIT(16'h9800)) tran_frame_type_dbl_buf_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[7]), .O(\FSM_sequential_curr_state_reg[1]_27 )); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT4 #( .INIT(16'h9800)) tran_ident_type_dbl_buf_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[6]), .O(\FSM_sequential_curr_state_reg[1]_28 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[10]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[10]), .O(\FSM_sequential_curr_state_reg[1]_24 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[11]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[11]), .O(\FSM_sequential_curr_state_reg[1]_23 )); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[12]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[12]), .O(\FSM_sequential_curr_state_reg[1]_22 )); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[13]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[13]), .O(\FSM_sequential_curr_state_reg[1]_21 )); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[14]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[14]), .O(\FSM_sequential_curr_state_reg[1]_20 )); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[15]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[15]), .O(\FSM_sequential_curr_state_reg[1]_19 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[16]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[16]), .O(\FSM_sequential_curr_state_reg[1]_18 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[17]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[17]), .O(\FSM_sequential_curr_state_reg[1]_17 )); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[18]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[18]), .O(\FSM_sequential_curr_state_reg[1]_16 )); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[19]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[19]), .O(\FSM_sequential_curr_state_reg[1]_15 )); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[20]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[20]), .O(\FSM_sequential_curr_state_reg[1]_14 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[21]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[21]), .O(\FSM_sequential_curr_state_reg[1]_13 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[22]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[22]), .O(\FSM_sequential_curr_state_reg[1]_12 )); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[23]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[23]), .O(\FSM_sequential_curr_state_reg[1]_11 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[24]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[24]), .O(\FSM_sequential_curr_state_reg[1]_10 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[25]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[25]), .O(\FSM_sequential_curr_state_reg[1]_9 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[26]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[26]), .O(\FSM_sequential_curr_state_reg[1]_8 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[27]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[27]), .O(\FSM_sequential_curr_state_reg[1]_7 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[28]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[28]), .O(\FSM_sequential_curr_state_reg[1]_6 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[4]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[4]), .O(\FSM_sequential_curr_state_reg[1]_30 )); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[8]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[8]), .O(\FSM_sequential_curr_state_reg[1]_26 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT4 #( .INIT(16'h9800)) tran_is_rtr_dbl_buf_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[5]), .O(\FSM_sequential_curr_state_reg[1]_29 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[29]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[29]), .O(\FSM_sequential_curr_state_reg[1]_5 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[30]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[30]), .O(\FSM_sequential_curr_state_reg[1]_4 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[31]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_1 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[31]), .O(\FSM_sequential_curr_state_reg[1]_3 )); endmodule (* ORIG_REF_NAME = "txtb_fsm" *) module txtb_fsm_86 (\FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[2]_0 , \retr_ctr_q_reg[0] , \FSM_sequential_curr_state_reg[2]_1 , \retr_ctr_q_reg[2] , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , WEBWE, \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state_reg[1]_2 , txtb_allow_bb, txtb_available, \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , \FSM_sequential_curr_state_reg[1]_32 , \FSM_sequential_curr_state_reg[1]_33 , \FSM_sequential_curr_state_reg[1]_34 , adress_IBUF, Q, \mr_tx_priority[2] , curr_state_0, \r_data[2]_i_5 , sbe_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, txtb_port_a_cs, \txtb_hw_cmd[lock] , \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[0]_3 , txtb_hw_cmd_cs, \FSM_sequential_curr_state_reg[0]_4 , tx_command_txcr_valid, \FSM_sequential_curr_state_reg[0]_5 , mr_tx_command_txca_q, mr_tx_command_txbi, mr_tx_command_txce_q, abort_or_skipped, tx_command_txce_valid, mr_tx_command_txcr_q, fsm_wait_state_q_i_5, txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[2]_4 , \FSM_sequential_curr_state_reg[2]_5 , \FSM_sequential_curr_state_reg[1]_35 , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[2]_6 ); output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[2]_0 ; output \retr_ctr_q_reg[0] ; output \FSM_sequential_curr_state_reg[2]_1 ; output \retr_ctr_q_reg[2] ; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output [3:0]WEBWE; output \FSM_sequential_curr_state_reg[0]_2 ; output \FSM_sequential_curr_state_reg[1]_2 ; output [0:0]txtb_allow_bb; output [0:0]txtb_available; output \FSM_sequential_curr_state_reg[2]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; output \FSM_sequential_curr_state_reg[1]_32 ; output \FSM_sequential_curr_state_reg[1]_33 ; output \FSM_sequential_curr_state_reg[1]_34 ; input [1:0]adress_IBUF; input [3:0]Q; input [2:0]\mr_tx_priority[2] ; input [1:0]curr_state_0; input [0:0]\r_data[2]_i_5 ; input [3:0]sbe_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input [0:0]txtb_port_a_cs; input \txtb_hw_cmd[lock] ; input [1:0]\FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[0]_3 ; input [0:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state_reg[0]_4 ; input tx_command_txcr_valid; input \FSM_sequential_curr_state_reg[0]_5 ; input mr_tx_command_txca_q; input [0:0]mr_tx_command_txbi; input mr_tx_command_txce_q; input abort_or_skipped; input tx_command_txce_valid; input mr_tx_command_txcr_q; input [0:0]fsm_wait_state_q_i_5; input [31:0]txtb_port_b_data_out_i; input \FSM_sequential_curr_state_reg[2]_4 ; input \FSM_sequential_curr_state_reg[2]_5 ; input \FSM_sequential_curr_state_reg[1]_35 ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[2]_6 ; wire \FSM_sequential_curr_state[0]_i_1__1_n_0 ; wire \FSM_sequential_curr_state[0]_i_2__1_n_0 ; wire \FSM_sequential_curr_state[0]_i_4__1_n_0 ; wire \FSM_sequential_curr_state[1]_i_1__1_n_0 ; wire \FSM_sequential_curr_state[1]_i_4__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_10_n_0 ; wire \FSM_sequential_curr_state[2]_i_11__1_n_0 ; wire \FSM_sequential_curr_state[2]_i_1__1_n_0 ; wire \FSM_sequential_curr_state[2]_i_3__1_n_0 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_33 ; wire \FSM_sequential_curr_state_reg[1]_34 ; wire \FSM_sequential_curr_state_reg[1]_35 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire [1:0]\FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire \FSM_sequential_curr_state_reg[2]_5 ; wire \FSM_sequential_curr_state_reg[2]_6 ; wire [3:0]Q; wire [3:0]WEBWE; wire abort_or_skipped; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [1:0]curr_state_0; wire [0:0]fsm_wait_state_q_i_5; wire \i_txtb_ram/txtb_port_a_write_i ; wire \mr_tst_out[tst_control_twrstb] ; wire [0:0]mr_tx_command_txbi; wire mr_tx_command_txca_q; wire mr_tx_command_txce_q; wire mr_tx_command_txcr_q; wire [2:0]\mr_tx_priority[2] ; wire [0:0]\r_data[2]_i_5 ; wire \retr_ctr_q_reg[0] ; wire \retr_ctr_q_reg[2] ; wire [3:0]sbe_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire txt_fsm_ce; wire [0:0]txtb_allow_bb; wire [0:0]txtb_available; wire \txtb_hw_cmd[lock] ; wire [0:0]txtb_hw_cmd_cs; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [2:0]\txtb_state[2] ; LUT6 #( .INIT(64'hBABFFFFFAAAA0000)) \FSM_sequential_curr_state[0]_i_1__1 (.I0(\FSM_sequential_curr_state[0]_i_2__1_n_0 ), .I1(abort_or_skipped), .I2(\FSM_sequential_curr_state[0]_i_4__1_n_0 ), .I3(tx_command_txce_valid), .I4(txt_fsm_ce), .I5(\FSM_sequential_curr_state_reg[0]_1 ), .O(\FSM_sequential_curr_state[0]_i_1__1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFBEBF8280)) \FSM_sequential_curr_state[0]_i_2__1 (.I0(\FSM_sequential_curr_state_reg[0]_4 ), .I1(\FSM_sequential_curr_state_reg[1]_1 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(tx_command_txcr_valid), .I5(\FSM_sequential_curr_state_reg[0]_5 ), .O(\FSM_sequential_curr_state[0]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h9)) \FSM_sequential_curr_state[0]_i_4__1 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[0]_i_4__1_n_0 )); LUT6 #( .INIT(64'hFFABFFFFFFAA0000)) \FSM_sequential_curr_state[1]_i_1__1 (.I0(\FSM_sequential_curr_state_reg[1]_35 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(tx_command_txcr_valid), .I3(\FSM_sequential_curr_state[1]_i_4__0_n_0 ), .I4(txt_fsm_ce), .I5(\FSM_sequential_curr_state_reg[1]_1 ), .O(\FSM_sequential_curr_state[1]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000004040400040)) \FSM_sequential_curr_state[1]_i_4__0 (.I0(mr_tx_command_txcr_q), .I1(mr_tx_command_txbi), .I2(mr_tx_command_txce_q), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .I5(\FSM_sequential_curr_state_reg[1]_1 ), .O(\FSM_sequential_curr_state[1]_i_4__0_n_0 )); LUT6 #( .INIT(64'h0000000000200000)) \FSM_sequential_curr_state[2]_i_10 (.I0(\FSM_sequential_curr_state_reg[2]_3 [1]), .I1(\FSM_sequential_curr_state_reg[2]_3 [0]), .I2(\txtb_hw_cmd[lock] ), .I3(\FSM_sequential_curr_state_reg[1]_1 ), .I4(\FSM_sequential_curr_state_reg[0]_1 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[2]_i_10_n_0 )); LUT6 #( .INIT(64'hB0008000EF002000)) \FSM_sequential_curr_state[2]_i_11__1 (.I0(mr_tx_command_txca_q), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(mr_tx_command_txbi), .I4(mr_tx_command_txce_q), .I5(\FSM_sequential_curr_state_reg[1]_1 ), .O(\FSM_sequential_curr_state[2]_i_11__1_n_0 )); LUT6 #( .INIT(64'hFFFEFFFFFFFE0000)) \FSM_sequential_curr_state[2]_i_1__1 (.I0(\FSM_sequential_curr_state_reg[0]_2 ), .I1(\FSM_sequential_curr_state[2]_i_3__1_n_0 ), .I2(\FSM_sequential_curr_state_reg[2]_4 ), .I3(\FSM_sequential_curr_state_reg[2]_5 ), .I4(txt_fsm_ce), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[2]_i_1__1_n_0 )); LUT6 #( .INIT(64'hFF0F000000000080)) \FSM_sequential_curr_state[2]_i_2__1 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\txtb_hw_cmd[lock] ), .I2(\FSM_sequential_curr_state_reg[2]_3 [1]), .I3(\FSM_sequential_curr_state_reg[2]_3 [0]), .I4(\FSM_sequential_curr_state_reg[1]_1 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state_reg[0]_2 )); LUT6 #( .INIT(64'h00000808000008F8)) \FSM_sequential_curr_state[2]_i_3__1 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(abort_or_skipped), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(tx_command_txcr_valid), .I4(\FSM_sequential_curr_state_reg[1]_1 ), .I5(tx_command_txce_valid), .O(\FSM_sequential_curr_state[2]_i_3__1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFEAAA)) \FSM_sequential_curr_state[2]_i_6__0 (.I0(\FSM_sequential_curr_state[0]_i_2__1_n_0 ), .I1(\FSM_sequential_curr_state_reg[0]_3 ), .I2(\FSM_sequential_curr_state_reg[1]_2 ), .I3(txtb_hw_cmd_cs), .I4(\FSM_sequential_curr_state[2]_i_10_n_0 ), .I5(\FSM_sequential_curr_state[2]_i_11__1_n_0 ), .O(txt_fsm_ce)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT3 #( .INIT(8'hC2)) \FSM_sequential_curr_state[2]_i_7__1 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_1 ), .O(txtb_allow_bb)); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[2]_i_8__0 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state_reg[1]_2 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_6 ), .D(\FSM_sequential_curr_state[0]_i_1__1_n_0 ), .Q(\FSM_sequential_curr_state_reg[0]_1 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDPE #( .INIT(1'b1)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\FSM_sequential_curr_state[1]_i_1__1_n_0 ), .PRE(\FSM_sequential_curr_state_reg[2]_6 ), .Q(\FSM_sequential_curr_state_reg[1]_1 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_6 ), .D(\FSM_sequential_curr_state[2]_i_1__1_n_0 ), .Q(\FSM_sequential_curr_state_reg[2]_0 )); LUT6 #( .INIT(64'h5555554555455545)) fsm_wait_state_q_i_8 (.I0(fsm_wait_state_q_i_5), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(\FSM_sequential_curr_state_reg[1]_1 ), .I4(mr_tx_command_txbi), .I5(mr_tx_command_txca_q), .O(\FSM_sequential_curr_state_reg[2]_2 )); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_43__2 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[3]), .O(WEBWE[3])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_44__2 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[2]), .O(WEBWE[2])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_45__2 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[1]), .O(WEBWE[1])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_46__2 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[0]), .O(WEBWE[0])); LUT6 #( .INIT(64'h88B8B88888B8B8B8)) \g_ram_rst_false.ram_memory_reg_i_48__0 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(tst_ena), .I2(txtb_port_a_cs), .I3(\FSM_sequential_curr_state_reg[1]_1 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .I5(\FSM_sequential_curr_state_reg[0]_1 ), .O(\i_txtb_ram/txtb_port_a_write_i )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'h38)) \r_data[10]_i_12 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[1]_1 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .O(\txtb_state[2] [2])); LUT5 #( .INIT(32'h3F113FDD)) \r_data[10]_i_9 (.I0(\txtb_state[2] [2]), .I1(adress_IBUF[1]), .I2(Q[2]), .I3(adress_IBUF[0]), .I4(\mr_tx_priority[2] [2]), .O(\retr_ctr_q_reg[2] )); LUT5 #( .INIT(32'h0FFEFFFE)) \r_data[11]_i_9 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(Q[3]), .O(\FSM_sequential_curr_state_reg[0]_0 )); LUT6 #( .INIT(64'h020202020202FF02)) \r_data[2]_i_10 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(curr_state_0[1]), .I4(\r_data[2]_i_5 ), .I5(curr_state_0[0]), .O(\FSM_sequential_curr_state_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'h47)) \r_data[8]_i_11 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_1 ), .O(\txtb_state[2] [0])); LUT5 #( .INIT(32'h3F113FDD)) \r_data[8]_i_8 (.I0(\txtb_state[2] [0]), .I1(adress_IBUF[1]), .I2(Q[0]), .I3(adress_IBUF[0]), .I4(\mr_tx_priority[2] [0]), .O(\retr_ctr_q_reg[0] )); LUT5 #( .INIT(32'h3F113FDD)) \r_data[9]_i_9 (.I0(\FSM_sequential_curr_state_reg[2]_0 ), .I1(adress_IBUF[1]), .I2(Q[1]), .I3(adress_IBUF[0]), .I4(\mr_tx_priority[2] [1]), .O(\FSM_sequential_curr_state_reg[2]_1 )); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'h00000700)) \select_buf_index_reg[1]_i_3 (.I0(mr_tx_command_txca_q), .I1(mr_tx_command_txbi), .I2(\FSM_sequential_curr_state_reg[1]_1 ), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_available)); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( .INIT(16'h9800)) tran_brs_dbl_buf_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[9]), .O(\FSM_sequential_curr_state_reg[1]_25 )); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[0]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[0]), .O(\FSM_sequential_curr_state_reg[1]_34 )); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[1]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[1]), .O(\FSM_sequential_curr_state_reg[1]_33 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[2]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[2]), .O(\FSM_sequential_curr_state_reg[1]_32 )); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[3]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[3]), .O(\FSM_sequential_curr_state_reg[1]_31 )); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'h9800)) tran_frame_type_dbl_buf_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[7]), .O(\FSM_sequential_curr_state_reg[1]_27 )); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'h9800)) tran_ident_type_dbl_buf_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[6]), .O(\FSM_sequential_curr_state_reg[1]_28 )); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[10]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[10]), .O(\FSM_sequential_curr_state_reg[1]_24 )); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[11]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[11]), .O(\FSM_sequential_curr_state_reg[1]_23 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[12]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[12]), .O(\FSM_sequential_curr_state_reg[1]_22 )); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[13]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[13]), .O(\FSM_sequential_curr_state_reg[1]_21 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[14]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[14]), .O(\FSM_sequential_curr_state_reg[1]_20 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[15]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[15]), .O(\FSM_sequential_curr_state_reg[1]_19 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[16]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[16]), .O(\FSM_sequential_curr_state_reg[1]_18 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[17]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[17]), .O(\FSM_sequential_curr_state_reg[1]_17 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[18]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[18]), .O(\FSM_sequential_curr_state_reg[1]_16 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[19]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[19]), .O(\FSM_sequential_curr_state_reg[1]_15 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[20]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[20]), .O(\FSM_sequential_curr_state_reg[1]_14 )); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[21]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[21]), .O(\FSM_sequential_curr_state_reg[1]_13 )); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[22]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[22]), .O(\FSM_sequential_curr_state_reg[1]_12 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[23]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[23]), .O(\FSM_sequential_curr_state_reg[1]_11 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[24]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[24]), .O(\FSM_sequential_curr_state_reg[1]_10 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[25]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[25]), .O(\FSM_sequential_curr_state_reg[1]_9 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[26]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[26]), .O(\FSM_sequential_curr_state_reg[1]_8 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[27]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[27]), .O(\FSM_sequential_curr_state_reg[1]_7 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[28]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[28]), .O(\FSM_sequential_curr_state_reg[1]_6 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[4]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[4]), .O(\FSM_sequential_curr_state_reg[1]_30 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[8]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[8]), .O(\FSM_sequential_curr_state_reg[1]_26 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h9800)) tran_is_rtr_dbl_buf_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[5]), .O(\FSM_sequential_curr_state_reg[1]_29 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[29]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[29]), .O(\FSM_sequential_curr_state_reg[1]_5 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[30]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[30]), .O(\FSM_sequential_curr_state_reg[1]_4 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[31]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[31]), .O(\FSM_sequential_curr_state_reg[1]_3 )); endmodule (* ORIG_REF_NAME = "txtb_fsm" *) module txtb_fsm_88 (\FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[2]_0 , \err_capt_err_type_q_reg[1] , WEBWE, \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , txtb_available, txtb_allow_bb, \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state_reg[0]_3 , \FSM_sequential_curr_state_reg[2]_1 , \FSM_sequential_curr_state_reg[0]_4 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , \FSM_sequential_curr_state_reg[1]_32 , \FSM_sequential_curr_state_reg[1]_33 , adress_IBUF, Q, \mr_tx_priority[1] , sbe_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, txtb_port_a_cs, \FSM_sequential_curr_state_reg[1]_34 , tx_command_txce_valid, tx_command_txcr_valid, \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state[2]_i_5__0_0 , txtb_hw_cmd_cs, abort_applied, \FSM_sequential_curr_state_reg[0]_5 , \FSM_sequential_curr_state[2]_i_5__0_1 , \FSM_sequential_curr_state_reg[0]_6 , \select_buf_index_reg_reg[1] , \FSM_sequential_curr_state[0]_i_11 , txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[2]_4 , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[2]_5 ); output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[2]_0 ; output \err_capt_err_type_q_reg[1] ; output [3:0]WEBWE; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output [0:0]txtb_available; output [0:0]txtb_allow_bb; output \FSM_sequential_curr_state_reg[0]_2 ; output [0:0]\FSM_sequential_curr_state_reg[0]_3 ; output \FSM_sequential_curr_state_reg[2]_1 ; output \FSM_sequential_curr_state_reg[0]_4 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; output \FSM_sequential_curr_state_reg[1]_32 ; output \FSM_sequential_curr_state_reg[1]_33 ; input [1:0]adress_IBUF; input [1:0]Q; input [0:0]\mr_tx_priority[1] ; input [3:0]sbe_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input [0:0]txtb_port_a_cs; input \FSM_sequential_curr_state_reg[1]_34 ; input tx_command_txce_valid; input tx_command_txcr_valid; input \FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state[2]_i_5__0_0 ; input [0:0]txtb_hw_cmd_cs; input abort_applied; input \FSM_sequential_curr_state_reg[0]_5 ; input \FSM_sequential_curr_state[2]_i_5__0_1 ; input \FSM_sequential_curr_state_reg[0]_6 ; input [0:0]\select_buf_index_reg_reg[1] ; input \FSM_sequential_curr_state[0]_i_11 ; input [31:0]txtb_port_b_data_out_i; input \FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[2]_4 ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[2]_5 ; wire \FSM_sequential_curr_state[0]_i_11 ; wire \FSM_sequential_curr_state[0]_i_1__0_n_0 ; wire \FSM_sequential_curr_state[0]_i_2__0_n_0 ; wire \FSM_sequential_curr_state[0]_i_5_n_0 ; wire \FSM_sequential_curr_state[1]_i_1__0_n_0 ; wire \FSM_sequential_curr_state[1]_i_2__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_11__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_12__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_1__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_3__0_n_0 ; wire \FSM_sequential_curr_state[2]_i_5__0_0 ; wire \FSM_sequential_curr_state[2]_i_5__0_1 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire [0:0]\FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[0]_6 ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_33 ; wire \FSM_sequential_curr_state_reg[1]_34 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire \FSM_sequential_curr_state_reg[2]_5 ; wire [1:0]Q; wire [3:0]WEBWE; wire abort_applied; wire [1:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire \err_capt_err_type_q_reg[1] ; wire \i_txtb_ram/txtb_port_a_write_i ; wire \mr_tst_out[tst_control_twrstb] ; wire [0:0]\mr_tx_priority[1] ; wire [3:0]sbe_IBUF; wire [0:0]\select_buf_index_reg_reg[1] ; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire txt_fsm_ce; wire [0:0]txtb_allow_bb; wire [0:0]txtb_available; wire [0:0]txtb_hw_cmd_cs; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [2:2]\txtb_state[1] ; LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \FSM_sequential_curr_state[0]_i_1__0 (.I0(\FSM_sequential_curr_state[0]_i_2__0_n_0 ), .I1(\FSM_sequential_curr_state_reg[0]_6 ), .I2(txtb_allow_bb), .I3(\FSM_sequential_curr_state[0]_i_5_n_0 ), .I4(txt_fsm_ce), .I5(\FSM_sequential_curr_state_reg[0]_1 ), .O(\FSM_sequential_curr_state[0]_i_1__0_n_0 )); LUT6 #( .INIT(64'hAAAABBAAAAAAAFAA)) \FSM_sequential_curr_state[0]_i_2__0 (.I0(\FSM_sequential_curr_state[2]_i_12__0_n_0 ), .I1(tx_command_txce_valid), .I2(\FSM_sequential_curr_state_reg[2]_2 ), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[0]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'hC2)) \FSM_sequential_curr_state[0]_i_4__0 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(txtb_allow_bb)); LUT6 #( .INIT(64'h500100005F010000)) \FSM_sequential_curr_state[0]_i_5 (.I0(abort_applied), .I1(\FSM_sequential_curr_state_reg[0]_5 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(\FSM_sequential_curr_state_reg[0]_1 ), .I5(tx_command_txce_valid), .O(\FSM_sequential_curr_state[0]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT3 #( .INIT(8'hB8)) \FSM_sequential_curr_state[1]_i_1__0 (.I0(\FSM_sequential_curr_state[1]_i_2__0_n_0 ), .I1(txt_fsm_ce), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(\FSM_sequential_curr_state[1]_i_1__0_n_0 )); LUT6 #( .INIT(64'hAAAAAAAABEBFAEAE)) \FSM_sequential_curr_state[1]_i_2__0 (.I0(\FSM_sequential_curr_state_reg[1]_34 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(tx_command_txce_valid), .I5(tx_command_txcr_valid), .O(\FSM_sequential_curr_state[1]_i_2__0_n_0 )); LUT6 #( .INIT(64'hFFAAEAAAEAAAEAAA)) \FSM_sequential_curr_state[2]_i_11__0 (.I0(\FSM_sequential_curr_state[2]_i_3__0_n_0 ), .I1(txtb_hw_cmd_cs), .I2(\FSM_sequential_curr_state[2]_i_5__0_1 ), .I3(\FSM_sequential_curr_state_reg[1]_1 ), .I4(\FSM_sequential_curr_state_reg[0]_1 ), .I5(abort_applied), .O(\FSM_sequential_curr_state[2]_i_11__0_n_0 )); LUT6 #( .INIT(64'h88F0F00088F0F0F0)) \FSM_sequential_curr_state[2]_i_12__0 (.I0(\FSM_sequential_curr_state[2]_i_5__0_0 ), .I1(txtb_hw_cmd_cs), .I2(tx_command_txcr_valid), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[0]_1 ), .O(\FSM_sequential_curr_state[2]_i_12__0_n_0 )); LUT5 #( .INIT(32'hFEFFFE00)) \FSM_sequential_curr_state[2]_i_1__0 (.I0(\FSM_sequential_curr_state_reg[2]_3 ), .I1(\FSM_sequential_curr_state[2]_i_3__0_n_0 ), .I2(\FSM_sequential_curr_state_reg[2]_4 ), .I3(txt_fsm_ce), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'hF00C0008)) \FSM_sequential_curr_state[2]_i_3__0 (.I0(\FSM_sequential_curr_state_reg[2]_2 ), .I1(\FSM_sequential_curr_state_reg[0]_1 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(\FSM_sequential_curr_state_reg[0]_6 ), .O(\FSM_sequential_curr_state[2]_i_3__0_n_0 )); LUT6 #( .INIT(64'hEFEEEFEEFEEEEFEE)) \FSM_sequential_curr_state[2]_i_5__0 (.I0(\FSM_sequential_curr_state[2]_i_11__0_n_0 ), .I1(\FSM_sequential_curr_state[2]_i_12__0_n_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(tx_command_txce_valid), .I4(\FSM_sequential_curr_state_reg[0]_1 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(txt_fsm_ce)); LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[2]_i_7__0 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state_reg[1]_1 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_5 ), .D(\FSM_sequential_curr_state[0]_i_1__0_n_0 ), .Q(\FSM_sequential_curr_state_reg[0]_1 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDPE #( .INIT(1'b1)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\FSM_sequential_curr_state[1]_i_1__0_n_0 ), .PRE(\FSM_sequential_curr_state_reg[2]_5 ), .Q(\FSM_sequential_curr_state_reg[1]_0 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_5 ), .D(\FSM_sequential_curr_state[2]_i_1__0_n_0 ), .Q(\FSM_sequential_curr_state_reg[2]_0 )); LUT6 #( .INIT(64'h5555545500000000)) fsm_wait_state_q_i_5 (.I0(\select_buf_index_reg_reg[1] ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(abort_applied), .I5(\FSM_sequential_curr_state[0]_i_11 ), .O(\FSM_sequential_curr_state_reg[2]_1 )); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_43__1 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[3]), .O(WEBWE[3])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_44__1 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[2]), .O(WEBWE[2])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_45__1 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[1]), .O(WEBWE[1])); LUT2 #( .INIT(4'h8)) \g_ram_rst_false.ram_memory_reg_i_46__1 (.I0(\i_txtb_ram/txtb_port_a_write_i ), .I1(sbe_IBUF[0]), .O(WEBWE[0])); LUT6 #( .INIT(64'h8888B8B8B8B888B8)) \g_ram_rst_false.ram_memory_reg_i_48 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(tst_ena), .I2(txtb_port_a_cs), .I3(\FSM_sequential_curr_state_reg[0]_1 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(\i_txtb_ram/txtb_port_a_write_i )); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'h47)) \r_data[4]_i_13 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(\FSM_sequential_curr_state_reg[0]_3 )); LUT5 #( .INIT(32'h3F113FDD)) \r_data[6]_i_13 (.I0(\txtb_state[1] ), .I1(adress_IBUF[1]), .I2(Q[0]), .I3(adress_IBUF[0]), .I4(\mr_tx_priority[1] ), .O(\err_capt_err_type_q_reg[1] )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT3 #( .INIT(8'h38)) \r_data[6]_i_14 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .O(\txtb_state[1] )); LUT5 #( .INIT(32'h0FFEFFFE)) \r_data[7]_i_9 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(adress_IBUF[0]), .I3(adress_IBUF[1]), .I4(Q[1]), .O(\FSM_sequential_curr_state_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT4 #( .INIT(16'h0010)) \select_buf_index_reg[0]_i_4 (.I0(\FSM_sequential_curr_state_reg[2]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(abort_applied), .O(txtb_available)); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT5 #( .INIT(32'h0000FFFB)) \select_buf_index_reg[1]_i_2 (.I0(abort_applied), .I1(\FSM_sequential_curr_state_reg[0]_1 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .I4(\select_buf_index_reg_reg[1] ), .O(\FSM_sequential_curr_state_reg[0]_4 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h02)) \select_buf_index_reg[1]_i_8 (.I0(\FSM_sequential_curr_state_reg[0]_1 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state_reg[0]_2 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'h9800)) tran_brs_dbl_buf_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[9]), .O(\FSM_sequential_curr_state_reg[1]_24 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[0]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[0]), .O(\FSM_sequential_curr_state_reg[1]_33 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[1]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[1]), .O(\FSM_sequential_curr_state_reg[1]_32 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[2]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[2]), .O(\FSM_sequential_curr_state_reg[1]_31 )); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[3]_i_8 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[3]), .O(\FSM_sequential_curr_state_reg[1]_30 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT4 #( .INIT(16'h9800)) tran_frame_type_dbl_buf_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[7]), .O(\FSM_sequential_curr_state_reg[1]_26 )); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT4 #( .INIT(16'h9800)) tran_ident_type_dbl_buf_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[6]), .O(\FSM_sequential_curr_state_reg[1]_27 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[10]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[10]), .O(\FSM_sequential_curr_state_reg[1]_23 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[11]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[11]), .O(\FSM_sequential_curr_state_reg[1]_22 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[12]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[12]), .O(\FSM_sequential_curr_state_reg[1]_21 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[13]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[13]), .O(\FSM_sequential_curr_state_reg[1]_20 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[14]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[14]), .O(\FSM_sequential_curr_state_reg[1]_19 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[15]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[15]), .O(\FSM_sequential_curr_state_reg[1]_18 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[16]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[16]), .O(\FSM_sequential_curr_state_reg[1]_17 )); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[17]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[17]), .O(\FSM_sequential_curr_state_reg[1]_16 )); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[18]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[18]), .O(\FSM_sequential_curr_state_reg[1]_15 )); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[19]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[19]), .O(\FSM_sequential_curr_state_reg[1]_14 )); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[20]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[20]), .O(\FSM_sequential_curr_state_reg[1]_13 )); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[21]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[21]), .O(\FSM_sequential_curr_state_reg[1]_12 )); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[22]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[22]), .O(\FSM_sequential_curr_state_reg[1]_11 )); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[23]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[23]), .O(\FSM_sequential_curr_state_reg[1]_10 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[24]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[24]), .O(\FSM_sequential_curr_state_reg[1]_9 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[25]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[25]), .O(\FSM_sequential_curr_state_reg[1]_8 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[26]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[26]), .O(\FSM_sequential_curr_state_reg[1]_7 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[27]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[27]), .O(\FSM_sequential_curr_state_reg[1]_6 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[28]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[28]), .O(\FSM_sequential_curr_state_reg[1]_5 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[4]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[4]), .O(\FSM_sequential_curr_state_reg[1]_29 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[8]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[8]), .O(\FSM_sequential_curr_state_reg[1]_25 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT4 #( .INIT(16'h9800)) tran_is_rtr_dbl_buf_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[5]), .O(\FSM_sequential_curr_state_reg[1]_28 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[29]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[29]), .O(\FSM_sequential_curr_state_reg[1]_4 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[30]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[30]), .O(\FSM_sequential_curr_state_reg[1]_3 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[31]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_1 ), .I3(txtb_port_b_data_out_i[31]), .O(\FSM_sequential_curr_state_reg[1]_2 )); endmodule (* ORIG_REF_NAME = "txtb_fsm" *) module txtb_fsm_90 (D, \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[0]_0 , \err_capt_err_pos_q_reg[3] , \FSM_sequential_curr_state_reg[2]_1 , WEBWE, \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[1]_1 , txtb_allow_bb, abort_or_skipped, txtb_available, \FSM_sequential_curr_state_reg[0]_2 , tx_command_txce_valid, tx_command_txcr_valid, abort_or_skipped_0, \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , \FSM_sequential_curr_state_reg[1]_32 , \FSM_sequential_curr_state_reg[1]_33 , sbe_IBUF, \r_data_reg[2] , adress_IBUF, \r_data_reg[2]_0 , \r_data_reg[2]_1 , \r_data_reg[2]_2 , \r_data_reg[2]_3 , \r_data_reg[2]_4 , \r_data_reg[2]_5 , \r_data[2]_i_2_0 , \r_data[2]_i_2_1 , \r_data[2]_i_2_2 , Q, \mr_tx_priority[0] , \r_data[2]_i_2_3 , \mr_tst_out[tst_control_twrstb] , tst_ena, txtb_port_a_cs, \txtb_hw_cmd[lock] , \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state_reg[0]_3 , txtb_hw_cmd_cs, \FSM_sequential_curr_state_reg[0]_4 , \FSM_sequential_curr_state_reg[0]_5 , \FSM_sequential_curr_state_reg[0]_6 , mr_tx_command_txbi, \FSM_sequential_curr_state_reg[0]_7 , \FSM_sequential_curr_state_reg[1]_34 , txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[2]_4 , \FSM_sequential_curr_state_reg[1]_35 , clk_sys_IBUF_BUFG, \FSM_sequential_curr_state_reg[2]_5 ); output [0:0]D; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[2]_0 ; output \FSM_sequential_curr_state_reg[0]_0 ; output \err_capt_err_pos_q_reg[3] ; output \FSM_sequential_curr_state_reg[2]_1 ; output [3:0]WEBWE; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[1]_1 ; output [0:0]txtb_allow_bb; output abort_or_skipped; output [0:0]txtb_available; output [0:0]\FSM_sequential_curr_state_reg[0]_2 ; output tx_command_txce_valid; output tx_command_txcr_valid; output abort_or_skipped_0; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; output \FSM_sequential_curr_state_reg[1]_32 ; output \FSM_sequential_curr_state_reg[1]_33 ; input [3:0]sbe_IBUF; input \r_data_reg[2] ; input [2:0]adress_IBUF; input \r_data_reg[2]_0 ; input \r_data_reg[2]_1 ; input \r_data_reg[2]_2 ; input \r_data_reg[2]_3 ; input \r_data_reg[2]_4 ; input \r_data_reg[2]_5 ; input \r_data[2]_i_2_0 ; input \r_data[2]_i_2_1 ; input \r_data[2]_i_2_2 ; input [2:0]Q; input [1:0]\mr_tx_priority[0] ; input \r_data[2]_i_2_3 ; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input [0:0]txtb_port_a_cs; input \txtb_hw_cmd[lock] ; input [1:0]\FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state_reg[0]_3 ; input [0:0]txtb_hw_cmd_cs; input \FSM_sequential_curr_state_reg[0]_4 ; input \FSM_sequential_curr_state_reg[0]_5 ; input \FSM_sequential_curr_state_reg[0]_6 ; input [1:0]mr_tx_command_txbi; input \FSM_sequential_curr_state_reg[0]_7 ; input \FSM_sequential_curr_state_reg[1]_34 ; input [31:0]txtb_port_b_data_out_i; input \FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[2]_4 ; input \FSM_sequential_curr_state_reg[1]_35 ; input clk_sys_IBUF_BUFG; input \FSM_sequential_curr_state_reg[2]_5 ; wire [0:0]D; wire \FSM_sequential_curr_state[0]_i_1_n_0 ; wire \FSM_sequential_curr_state[0]_i_4_n_0 ; wire \FSM_sequential_curr_state[1]_i_1_n_0 ; wire \FSM_sequential_curr_state[2]_i_1_n_0 ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire [0:0]\FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[0]_4 ; wire \FSM_sequential_curr_state_reg[0]_5 ; wire \FSM_sequential_curr_state_reg[0]_6 ; wire \FSM_sequential_curr_state_reg[0]_7 ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_33 ; wire \FSM_sequential_curr_state_reg[1]_34 ; wire \FSM_sequential_curr_state_reg[1]_35 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire [1:0]\FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire \FSM_sequential_curr_state_reg[2]_5 ; wire [2:0]Q; wire [3:0]WEBWE; wire abort_or_skipped; wire abort_or_skipped_0; wire [2:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire \err_capt_err_pos_q_reg[3] ; wire \mr_tst_out[tst_control_twrstb] ; wire [1:0]mr_tx_command_txbi; wire [1:0]\mr_tx_priority[0] ; wire \r_data[2]_i_2_0 ; wire \r_data[2]_i_2_1 ; wire \r_data[2]_i_2_2 ; wire \r_data[2]_i_2_3 ; wire \r_data_reg[2] ; wire \r_data_reg[2]_0 ; wire \r_data_reg[2]_1 ; wire \r_data_reg[2]_2 ; wire \r_data_reg[2]_3 ; wire \r_data_reg[2]_4 ; wire \r_data_reg[2]_5 ; wire [3:0]sbe_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txce_valid_0; wire tx_command_txcr_valid; wire tx_command_txcr_valid_1; wire [0:0]txtb_allow_bb; wire [0:0]txtb_available; wire txtb_fsm_90_net; wire txtb_fsm_90_net_1; wire txtb_fsm_90_net_10; wire txtb_fsm_90_net_2; wire txtb_fsm_90_net_3; wire txtb_fsm_90_net_4; wire txtb_fsm_90_net_5; wire txtb_fsm_90_net_6; wire txtb_fsm_90_net_7; wire txtb_fsm_90_net_8; wire txtb_fsm_90_net_9; wire \txtb_hw_cmd[lock] ; wire [0:0]txtb_hw_cmd_cs; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [2:2]\txtb_state[0] ; assign \FSM_sequential_curr_state_reg[0]_1 = txtb_fsm_90_net_9; (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[0]_i_3__2 (.I0(\FSM_sequential_curr_state_reg[0]_6 ), .I1(mr_tx_command_txbi[0]), .O(abort_or_skipped)); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[0]_i_3__3 (.I0(\FSM_sequential_curr_state_reg[0]_6 ), .I1(mr_tx_command_txbi[1]), .O(abort_or_skipped_0)); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h9)) \FSM_sequential_curr_state[0]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[0]_i_5__2 (.I0(\FSM_sequential_curr_state_reg[0]_7 ), .I1(mr_tx_command_txbi[0]), .O(tx_command_txce_valid_0)); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[0]_i_5__3 (.I0(\FSM_sequential_curr_state_reg[0]_7 ), .I1(mr_tx_command_txbi[1]), .O(tx_command_txce_valid)); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[1]_i_3__2 (.I0(\FSM_sequential_curr_state_reg[1]_34 ), .I1(mr_tx_command_txbi[0]), .O(tx_command_txcr_valid_1)); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[1]_i_3__3 (.I0(\FSM_sequential_curr_state_reg[1]_34 ), .I1(mr_tx_command_txbi[1]), .O(tx_command_txcr_valid)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT3 #( .INIT(8'hC2)) \FSM_sequential_curr_state[2]_i_7 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(txtb_allow_bb)); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h8)) \FSM_sequential_curr_state[2]_i_9 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state_reg[1]_1 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[0] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_5 ), .D(\FSM_sequential_curr_state[0]_i_1_n_0 ), .Q(\FSM_sequential_curr_state_reg[0]_0 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDPE #( .INIT(1'b1)) \FSM_sequential_curr_state_reg[1] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .D(\FSM_sequential_curr_state[1]_i_1_n_0 ), .PRE(\FSM_sequential_curr_state_reg[2]_5 ), .Q(\FSM_sequential_curr_state_reg[1]_0 )); (* FSM_ENCODED_STATES = "s_txt_tx_prog:111,s_txt_ab_prog:110,s_txt_parity_err:000,s_txt_failed:101,s_txt_ok:011,s_txt_aborted:100,s_txt_ready:001,s_txt_empty:010" *) FDCE #( .INIT(1'b0)) \FSM_sequential_curr_state_reg[2] (.C(clk_sys_IBUF_BUFG), .CE(1'b1), .CLR(\FSM_sequential_curr_state_reg[2]_5 ), .D(\FSM_sequential_curr_state[2]_i_1_n_0 ), .Q(\FSM_sequential_curr_state_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'h47)) \r_data[0]_i_12 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .O(\FSM_sequential_curr_state_reg[0]_2 )); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'h38)) \r_data[2]_i_13 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .O(\txtb_state[0] )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'h00000700)) \select_buf_index_reg[0]_i_3 (.I0(\FSM_sequential_curr_state_reg[0]_6 ), .I1(mr_tx_command_txbi[0]), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_available)); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h9800)) tran_brs_dbl_buf_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[9]), .O(\FSM_sequential_curr_state_reg[1]_24 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[0]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[0]), .O(\FSM_sequential_curr_state_reg[1]_33 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[1]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[1]), .O(\FSM_sequential_curr_state_reg[1]_32 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[2]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[2]), .O(\FSM_sequential_curr_state_reg[1]_31 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT4 #( .INIT(16'h9800)) \tran_dlc_dbl_buf[3]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[3]), .O(\FSM_sequential_curr_state_reg[1]_30 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'h9800)) tran_frame_type_dbl_buf_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[7]), .O(\FSM_sequential_curr_state_reg[1]_26 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'h9800)) tran_ident_type_dbl_buf_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[6]), .O(\FSM_sequential_curr_state_reg[1]_27 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[10]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[10]), .O(\FSM_sequential_curr_state_reg[1]_23 )); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[11]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[11]), .O(\FSM_sequential_curr_state_reg[1]_22 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[12]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[12]), .O(\FSM_sequential_curr_state_reg[1]_21 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[13]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[13]), .O(\FSM_sequential_curr_state_reg[1]_20 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[14]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[14]), .O(\FSM_sequential_curr_state_reg[1]_19 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[15]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[15]), .O(\FSM_sequential_curr_state_reg[1]_18 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[16]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[16]), .O(\FSM_sequential_curr_state_reg[1]_17 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[17]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[17]), .O(\FSM_sequential_curr_state_reg[1]_16 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[18]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[18]), .O(\FSM_sequential_curr_state_reg[1]_15 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[19]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[19]), .O(\FSM_sequential_curr_state_reg[1]_14 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[20]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[20]), .O(\FSM_sequential_curr_state_reg[1]_13 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[21]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[21]), .O(\FSM_sequential_curr_state_reg[1]_12 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[22]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[22]), .O(\FSM_sequential_curr_state_reg[1]_11 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[23]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[23]), .O(\FSM_sequential_curr_state_reg[1]_10 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[24]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[24]), .O(\FSM_sequential_curr_state_reg[1]_9 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[25]_i_6 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[25]), .O(\FSM_sequential_curr_state_reg[1]_8 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[26]_i_5 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[26]), .O(\FSM_sequential_curr_state_reg[1]_7 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[27]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[27]), .O(\FSM_sequential_curr_state_reg[1]_6 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[28]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[28]), .O(\FSM_sequential_curr_state_reg[1]_5 )); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[4]_i_2 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[4]), .O(\FSM_sequential_curr_state_reg[1]_29 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h9800)) \tran_identifier_com[8]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[8]), .O(\FSM_sequential_curr_state_reg[1]_25 )); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'h9800)) tran_is_rtr_dbl_buf_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[5]), .O(\FSM_sequential_curr_state_reg[1]_28 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[29]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[29]), .O(\FSM_sequential_curr_state_reg[1]_4 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[30]_i_3 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[30]), .O(\FSM_sequential_curr_state_reg[1]_3 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'h9800)) \ts_low_internal[31]_i_4 (.I0(\FSM_sequential_curr_state_reg[1]_0 ), .I1(\FSM_sequential_curr_state_reg[2]_0 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(txtb_port_b_data_out_i[31]), .O(\FSM_sequential_curr_state_reg[1]_2 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT4 #( .INIT(16'h5004)) txtb_fsm_90_LUT4 (.I0(tst_ena), .I1(\FSM_sequential_curr_state_reg[0]_0 ), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_fsm_90_net_4)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hFFFFE000)) txtb_fsm_90_LUT5 (.I0(\FSM_sequential_curr_state_reg[2]_2 [0]), .I1(\FSM_sequential_curr_state_reg[2]_2 [1]), .I2(\FSM_sequential_curr_state_reg[1]_0 ), .I3(\FSM_sequential_curr_state_reg[2]_0 ), .I4(txtb_fsm_90_net_3), .O(txtb_fsm_90_net_9)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h4C7C4F7F)) txtb_fsm_90_LUT5_1 (.I0(Q[0]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_tx_priority[0] [0]), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .O(\FSM_sequential_curr_state_reg[2]_1 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00008C80)) txtb_fsm_90_LUT5_2 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(sbe_IBUF[0]), .I2(tst_ena), .I3(txtb_port_a_cs), .I4(txtb_fsm_90_net_4), .O(WEBWE[0])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00008C80)) txtb_fsm_90_LUT5_3 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(sbe_IBUF[1]), .I2(tst_ena), .I3(txtb_port_a_cs), .I4(txtb_fsm_90_net_4), .O(WEBWE[1])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00008C80)) txtb_fsm_90_LUT5_4 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(sbe_IBUF[2]), .I2(tst_ena), .I3(txtb_port_a_cs), .I4(txtb_fsm_90_net_4), .O(WEBWE[2])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h00008C80)) txtb_fsm_90_LUT5_5 (.I0(\mr_tst_out[tst_control_twrstb] ), .I1(sbe_IBUF[3]), .I2(tst_ena), .I3(txtb_port_a_cs), .I4(txtb_fsm_90_net_4), .O(WEBWE[3])); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'h7F7F7F7C)) txtb_fsm_90_LUT5_6 (.I0(Q[2]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .O(\err_capt_err_pos_q_reg[3] )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT5 #( .INIT(32'hAAFF20FF)) txtb_fsm_90_LUT5_7 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(abort_or_skipped), .I2(\FSM_sequential_curr_state[0]_i_4_n_0 ), .I3(txtb_fsm_90_net_5), .I4(txtb_fsm_90_net_7), .O(\FSM_sequential_curr_state[0]_i_1_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0000B3830000B080)) txtb_fsm_90_LUT6 (.I0(Q[1]), .I1(adress_IBUF[0]), .I2(adress_IBUF[1]), .I3(\mr_tx_priority[0] [1]), .I4(\r_data[2]_i_2_3 ), .I5(\txtb_state[0] ), .O(txtb_fsm_90_net_1)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0E0E0E0E0E0F0E0E)) txtb_fsm_90_LUT6_1 (.I0(\r_data[2]_i_2_0 ), .I1(\r_data[2]_i_2_1 ), .I2(\r_data[2]_i_2_2 ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_fsm_90_net)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0200020002003230)) txtb_fsm_90_LUT6_10 (.I0(\FSM_sequential_curr_state_reg[0]_0 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(abort_or_skipped), .I4(tx_command_txcr_valid_1), .I5(tx_command_txce_valid_0), .O(txtb_fsm_90_net_10)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hFFF0FFFFFFF0FFEE)) txtb_fsm_90_LUT6_11 (.I0(\FSM_sequential_curr_state_reg[2]_3 ), .I1(\FSM_sequential_curr_state_reg[2]_4 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(txtb_fsm_90_net_9), .I4(txtb_fsm_90_net_7), .I5(txtb_fsm_90_net_10), .O(\FSM_sequential_curr_state[2]_i_1_n_0 )); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000008A8A8A)) txtb_fsm_90_LUT6_2 (.I0(\r_data_reg[2] ), .I1(\r_data_reg[2]_2 ), .I2(\r_data_reg[2]_3 ), .I3(\r_data_reg[2]_4 ), .I4(\r_data_reg[2]_5 ), .I5(txtb_fsm_90_net), .O(txtb_fsm_90_net_2)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h5700020057005700)) txtb_fsm_90_LUT6_3 (.I0(adress_IBUF[2]), .I1(\r_data_reg[2]_0 ), .I2(\r_data_reg[2]_1 ), .I3(sbe_IBUF[0]), .I4(txtb_fsm_90_net_1), .I5(txtb_fsm_90_net_2), .O(D)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0000000000001000)) txtb_fsm_90_LUT6_4 (.I0(\FSM_sequential_curr_state_reg[2]_2 [0]), .I1(\FSM_sequential_curr_state_reg[2]_2 [1]), .I2(\txtb_hw_cmd[lock] ), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_fsm_90_net_3)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h1100001011333313)) txtb_fsm_90_LUT6_5 (.I0(\FSM_sequential_curr_state_reg[0]_4 ), .I1(\FSM_sequential_curr_state_reg[0]_5 ), .I2(\FSM_sequential_curr_state_reg[0]_0 ), .I3(\FSM_sequential_curr_state_reg[1]_0 ), .I4(\FSM_sequential_curr_state_reg[2]_0 ), .I5(tx_command_txcr_valid_1), .O(txtb_fsm_90_net_5)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hA000C0C0C000A0C0)) txtb_fsm_90_LUT6_6 (.I0(\FSM_sequential_curr_state_reg[0]_6 ), .I1(\FSM_sequential_curr_state_reg[0]_7 ), .I2(mr_tx_command_txbi[0]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_fsm_90_net_6)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h00000000070F0000)) txtb_fsm_90_LUT6_7 (.I0(\FSM_sequential_curr_state_reg[0]_3 ), .I1(txtb_hw_cmd_cs), .I2(txtb_fsm_90_net_3), .I3(\FSM_sequential_curr_state_reg[1]_1 ), .I4(txtb_fsm_90_net_5), .I5(txtb_fsm_90_net_6), .O(txtb_fsm_90_net_7)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'h0000202000200020)) txtb_fsm_90_LUT6_8 (.I0(\FSM_sequential_curr_state_reg[0]_7 ), .I1(\FSM_sequential_curr_state_reg[1]_34 ), .I2(mr_tx_command_txbi[0]), .I3(\FSM_sequential_curr_state_reg[0]_0 ), .I4(\FSM_sequential_curr_state_reg[1]_0 ), .I5(\FSM_sequential_curr_state_reg[2]_0 ), .O(txtb_fsm_90_net_8)); (* OPT_MODIFIED = "RESYNTH_AREA" *) LUT6 #( .INIT(64'hCCCCFFFFCCCCAAAE)) txtb_fsm_90_LUT6_9 (.I0(\FSM_sequential_curr_state_reg[1]_35 ), .I1(\FSM_sequential_curr_state_reg[1]_0 ), .I2(\FSM_sequential_curr_state_reg[2]_0 ), .I3(tx_command_txcr_valid_1), .I4(txtb_fsm_90_net_7), .I5(txtb_fsm_90_net_8), .O(\FSM_sequential_curr_state[1]_i_1_n_0 )); endmodule module txtb_odd_top (txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[0] , curr_state, \FSM_sequential_curr_state_reg[2] , \err_capt_err_type_q_reg[1] , \FSM_sequential_curr_state_reg[1] , txtb_available, txtb_allow_bb, \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, swr_IBUF, scs_IBUF, adress_IBUF, Q, \mr_tx_priority[1] , sbe_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, \FSM_sequential_curr_state_reg[1]_32 , tx_command_txce_valid, tx_command_txcr_valid, \FSM_sequential_curr_state_reg[2]_1 , \FSM_sequential_curr_state[2]_i_5__0 , txtb_hw_cmd_cs, abort_applied, \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state[2]_i_5__0_0 , \FSM_sequential_curr_state_reg[0]_3 , \select_buf_index_reg_reg[1] , \FSM_sequential_curr_state[0]_i_11 , \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[2]_4 ); output [31:0]txtb_port_b_data_out_i; output \FSM_sequential_curr_state_reg[0] ; output [1:0]curr_state; output [1:0]\FSM_sequential_curr_state_reg[2] ; output \err_capt_err_type_q_reg[1] ; output \FSM_sequential_curr_state_reg[1] ; output [0:0]txtb_available; output [0:0]txtb_allow_bb; output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[2]_0 ; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[1]_0 ; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input swr_IBUF; input scs_IBUF; input [5:0]adress_IBUF; input [1:0]Q; input [0:0]\mr_tx_priority[1] ; input [3:0]sbe_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input \FSM_sequential_curr_state_reg[1]_32 ; input tx_command_txce_valid; input tx_command_txcr_valid; input \FSM_sequential_curr_state_reg[2]_1 ; input \FSM_sequential_curr_state[2]_i_5__0 ; input [0:0]txtb_hw_cmd_cs; input abort_applied; input \FSM_sequential_curr_state_reg[0]_2 ; input \FSM_sequential_curr_state[2]_i_5__0_0 ; input \FSM_sequential_curr_state_reg[0]_3 ; input [0:0]\select_buf_index_reg_reg[1] ; input \FSM_sequential_curr_state[0]_i_11 ; input \FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[2]_4 ; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire \FSM_sequential_curr_state[0]_i_11 ; wire \FSM_sequential_curr_state[2]_i_5__0 ; wire \FSM_sequential_curr_state[2]_i_5__0_0 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire [1:0]\FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire \FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire [1:0]Q; wire abort_applied; wire [5:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [1:0]curr_state; wire \err_capt_err_type_q_reg[1] ; wire [0:0]\i_dp_inf_ram_be/g_byte[0].byte_we_reg ; wire \i_dp_inf_ram_be/p_1_in ; wire \i_dp_inf_ram_be/p_2_in ; wire \i_dp_inf_ram_be/p_3_in ; wire \mr_tst_out[tst_control_twrstb] ; wire [0:0]\mr_tx_priority[1] ; wire [3:0]sbe_IBUF; wire scs_IBUF; wire [0:0]\select_buf_index_reg_reg[1] ; wire swr_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire [0:0]txtb_allow_bb; wire [0:0]txtb_available; wire [0:0]txtb_hw_cmd_cs; wire [1:1]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; txtb_fsm_88 i_txtb_fsm (.\FSM_sequential_curr_state[0]_i_11 (\FSM_sequential_curr_state[0]_i_11 ), .\FSM_sequential_curr_state[2]_i_5__0_0 (\FSM_sequential_curr_state[2]_i_5__0 ), .\FSM_sequential_curr_state[2]_i_5__0_1 (\FSM_sequential_curr_state[2]_i_5__0_0 ), .\FSM_sequential_curr_state_reg[0]_0 (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_1 (curr_state[0]), .\FSM_sequential_curr_state_reg[0]_2 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_3 (\FSM_sequential_curr_state_reg[2] [0]), .\FSM_sequential_curr_state_reg[0]_4 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[0]_5 (\FSM_sequential_curr_state_reg[0]_2 ), .\FSM_sequential_curr_state_reg[0]_6 (\FSM_sequential_curr_state_reg[0]_3 ), .\FSM_sequential_curr_state_reg[1]_0 (curr_state[1]), .\FSM_sequential_curr_state_reg[1]_1 (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_10 (\FSM_sequential_curr_state_reg[1]_8 ), .\FSM_sequential_curr_state_reg[1]_11 (\FSM_sequential_curr_state_reg[1]_9 ), .\FSM_sequential_curr_state_reg[1]_12 (\FSM_sequential_curr_state_reg[1]_10 ), .\FSM_sequential_curr_state_reg[1]_13 (\FSM_sequential_curr_state_reg[1]_11 ), .\FSM_sequential_curr_state_reg[1]_14 (\FSM_sequential_curr_state_reg[1]_12 ), .\FSM_sequential_curr_state_reg[1]_15 (\FSM_sequential_curr_state_reg[1]_13 ), .\FSM_sequential_curr_state_reg[1]_16 (\FSM_sequential_curr_state_reg[1]_14 ), .\FSM_sequential_curr_state_reg[1]_17 (\FSM_sequential_curr_state_reg[1]_15 ), .\FSM_sequential_curr_state_reg[1]_18 (\FSM_sequential_curr_state_reg[1]_16 ), .\FSM_sequential_curr_state_reg[1]_19 (\FSM_sequential_curr_state_reg[1]_17 ), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_20 (\FSM_sequential_curr_state_reg[1]_18 ), .\FSM_sequential_curr_state_reg[1]_21 (\FSM_sequential_curr_state_reg[1]_19 ), .\FSM_sequential_curr_state_reg[1]_22 (\FSM_sequential_curr_state_reg[1]_20 ), .\FSM_sequential_curr_state_reg[1]_23 (\FSM_sequential_curr_state_reg[1]_21 ), .\FSM_sequential_curr_state_reg[1]_24 (\FSM_sequential_curr_state_reg[1]_22 ), .\FSM_sequential_curr_state_reg[1]_25 (\FSM_sequential_curr_state_reg[1]_23 ), .\FSM_sequential_curr_state_reg[1]_26 (\FSM_sequential_curr_state_reg[1]_24 ), .\FSM_sequential_curr_state_reg[1]_27 (\FSM_sequential_curr_state_reg[1]_25 ), .\FSM_sequential_curr_state_reg[1]_28 (\FSM_sequential_curr_state_reg[1]_26 ), .\FSM_sequential_curr_state_reg[1]_29 (\FSM_sequential_curr_state_reg[1]_27 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_30 (\FSM_sequential_curr_state_reg[1]_28 ), .\FSM_sequential_curr_state_reg[1]_31 (\FSM_sequential_curr_state_reg[1]_29 ), .\FSM_sequential_curr_state_reg[1]_32 (\FSM_sequential_curr_state_reg[1]_30 ), .\FSM_sequential_curr_state_reg[1]_33 (\FSM_sequential_curr_state_reg[1]_31 ), .\FSM_sequential_curr_state_reg[1]_34 (\FSM_sequential_curr_state_reg[1]_32 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_5 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[1]_6 (\FSM_sequential_curr_state_reg[1]_4 ), .\FSM_sequential_curr_state_reg[1]_7 (\FSM_sequential_curr_state_reg[1]_5 ), .\FSM_sequential_curr_state_reg[1]_8 (\FSM_sequential_curr_state_reg[1]_6 ), .\FSM_sequential_curr_state_reg[1]_9 (\FSM_sequential_curr_state_reg[1]_7 ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2] [1]), .\FSM_sequential_curr_state_reg[2]_1 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_1 ), .\FSM_sequential_curr_state_reg[2]_3 (\FSM_sequential_curr_state_reg[2]_2 ), .\FSM_sequential_curr_state_reg[2]_4 (\FSM_sequential_curr_state_reg[2]_3 ), .\FSM_sequential_curr_state_reg[2]_5 (\FSM_sequential_curr_state_reg[2]_4 ), .Q(Q), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .abort_applied(abort_applied), .adress_IBUF(adress_IBUF[1:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\err_capt_err_type_q_reg[1] (\err_capt_err_type_q_reg[1] ), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .\mr_tx_priority[1] (\mr_tx_priority[1] ), .sbe_IBUF(sbe_IBUF), .\select_buf_index_reg_reg[1] (\select_buf_index_reg_reg[1] ), .tst_ena(tst_ena), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txcr_valid(tx_command_txcr_valid), .txtb_allow_bb(txtb_allow_bb), .txtb_available(txtb_available), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); txtb_ram__parameterized0 i_txtb_ram (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .adress_IBUF(adress_IBUF[5:2]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule (* ORIG_REF_NAME = "txtb_odd_top" *) module txtb_odd_top__parameterized0 (txtb_port_b_data_out_i, \FSM_sequential_curr_state_reg[2] , \txtb_state[3] , curr_state, \FSM_sequential_curr_state_reg[0] , \FSM_sequential_curr_state_reg[2]_0 , \FSM_sequential_curr_state_reg[0]_0 , \FSM_sequential_curr_state_reg[1] , \FSM_sequential_curr_state_reg[1]_0 , \FSM_sequential_curr_state_reg[2]_1 , txtb_allow_bb, \FSM_sequential_curr_state_reg[0]_1 , \FSM_sequential_curr_state_reg[1]_1 , \FSM_sequential_curr_state_reg[1]_2 , \FSM_sequential_curr_state_reg[1]_3 , \FSM_sequential_curr_state_reg[1]_4 , \FSM_sequential_curr_state_reg[1]_5 , \FSM_sequential_curr_state_reg[1]_6 , \FSM_sequential_curr_state_reg[1]_7 , \FSM_sequential_curr_state_reg[1]_8 , \FSM_sequential_curr_state_reg[1]_9 , \FSM_sequential_curr_state_reg[1]_10 , \FSM_sequential_curr_state_reg[1]_11 , \FSM_sequential_curr_state_reg[1]_12 , \FSM_sequential_curr_state_reg[1]_13 , \FSM_sequential_curr_state_reg[1]_14 , \FSM_sequential_curr_state_reg[1]_15 , \FSM_sequential_curr_state_reg[1]_16 , \FSM_sequential_curr_state_reg[1]_17 , \FSM_sequential_curr_state_reg[1]_18 , \FSM_sequential_curr_state_reg[1]_19 , \FSM_sequential_curr_state_reg[1]_20 , \FSM_sequential_curr_state_reg[1]_21 , \FSM_sequential_curr_state_reg[1]_22 , \FSM_sequential_curr_state_reg[1]_23 , \FSM_sequential_curr_state_reg[1]_24 , \FSM_sequential_curr_state_reg[1]_25 , \FSM_sequential_curr_state_reg[1]_26 , \FSM_sequential_curr_state_reg[1]_27 , \FSM_sequential_curr_state_reg[1]_28 , \FSM_sequential_curr_state_reg[1]_29 , \FSM_sequential_curr_state_reg[1]_30 , \FSM_sequential_curr_state_reg[1]_31 , \FSM_sequential_curr_state_reg[1]_32 , clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, swr_IBUF, scs_IBUF, adress_IBUF, \r_data[15]_i_2 , \mr_tx_priority[3] , sbe_IBUF, \mr_tst_out[tst_control_twrstb] , tst_ena, \FSM_sequential_curr_state_reg[1]_33 , tx_command_txce_valid, tx_command_txcr_valid, \FSM_sequential_curr_state_reg[2]_2 , \FSM_sequential_curr_state[2]_i_5__2 , txtb_hw_cmd_cs, abort_applied, \FSM_sequential_curr_state_reg[0]_2 , \FSM_sequential_curr_state[2]_i_5__2_0 , \FSM_sequential_curr_state_reg[0]_3 , \FSM_sequential_curr_state_reg[2]_3 , \FSM_sequential_curr_state_reg[2]_4 , \FSM_sequential_curr_state_reg[2]_5 ); output [31:0]txtb_port_b_data_out_i; output \FSM_sequential_curr_state_reg[2] ; output [0:0]\txtb_state[3] ; output [1:0]curr_state; output \FSM_sequential_curr_state_reg[0] ; output \FSM_sequential_curr_state_reg[2]_0 ; output \FSM_sequential_curr_state_reg[0]_0 ; output \FSM_sequential_curr_state_reg[1] ; output \FSM_sequential_curr_state_reg[1]_0 ; output [0:0]\FSM_sequential_curr_state_reg[2]_1 ; output [0:0]txtb_allow_bb; output \FSM_sequential_curr_state_reg[0]_1 ; output \FSM_sequential_curr_state_reg[1]_1 ; output \FSM_sequential_curr_state_reg[1]_2 ; output \FSM_sequential_curr_state_reg[1]_3 ; output \FSM_sequential_curr_state_reg[1]_4 ; output \FSM_sequential_curr_state_reg[1]_5 ; output \FSM_sequential_curr_state_reg[1]_6 ; output \FSM_sequential_curr_state_reg[1]_7 ; output \FSM_sequential_curr_state_reg[1]_8 ; output \FSM_sequential_curr_state_reg[1]_9 ; output \FSM_sequential_curr_state_reg[1]_10 ; output \FSM_sequential_curr_state_reg[1]_11 ; output \FSM_sequential_curr_state_reg[1]_12 ; output \FSM_sequential_curr_state_reg[1]_13 ; output \FSM_sequential_curr_state_reg[1]_14 ; output \FSM_sequential_curr_state_reg[1]_15 ; output \FSM_sequential_curr_state_reg[1]_16 ; output \FSM_sequential_curr_state_reg[1]_17 ; output \FSM_sequential_curr_state_reg[1]_18 ; output \FSM_sequential_curr_state_reg[1]_19 ; output \FSM_sequential_curr_state_reg[1]_20 ; output \FSM_sequential_curr_state_reg[1]_21 ; output \FSM_sequential_curr_state_reg[1]_22 ; output \FSM_sequential_curr_state_reg[1]_23 ; output \FSM_sequential_curr_state_reg[1]_24 ; output \FSM_sequential_curr_state_reg[1]_25 ; output \FSM_sequential_curr_state_reg[1]_26 ; output \FSM_sequential_curr_state_reg[1]_27 ; output \FSM_sequential_curr_state_reg[1]_28 ; output \FSM_sequential_curr_state_reg[1]_29 ; output \FSM_sequential_curr_state_reg[1]_30 ; output \FSM_sequential_curr_state_reg[1]_31 ; output \FSM_sequential_curr_state_reg[1]_32 ; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input swr_IBUF; input scs_IBUF; input [6:0]adress_IBUF; input \r_data[15]_i_2 ; input [2:0]\mr_tx_priority[3] ; input [3:0]sbe_IBUF; input \mr_tst_out[tst_control_twrstb] ; input tst_ena; input \FSM_sequential_curr_state_reg[1]_33 ; input tx_command_txce_valid; input tx_command_txcr_valid; input \FSM_sequential_curr_state_reg[2]_2 ; input \FSM_sequential_curr_state[2]_i_5__2 ; input [0:0]txtb_hw_cmd_cs; input abort_applied; input \FSM_sequential_curr_state_reg[0]_2 ; input \FSM_sequential_curr_state[2]_i_5__2_0 ; input \FSM_sequential_curr_state_reg[0]_3 ; input \FSM_sequential_curr_state_reg[2]_3 ; input \FSM_sequential_curr_state_reg[2]_4 ; input \FSM_sequential_curr_state_reg[2]_5 ; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire \FSM_sequential_curr_state[2]_i_5__2 ; wire \FSM_sequential_curr_state[2]_i_5__2_0 ; wire \FSM_sequential_curr_state_reg[0] ; wire \FSM_sequential_curr_state_reg[0]_0 ; wire \FSM_sequential_curr_state_reg[0]_1 ; wire \FSM_sequential_curr_state_reg[0]_2 ; wire \FSM_sequential_curr_state_reg[0]_3 ; wire \FSM_sequential_curr_state_reg[1] ; wire \FSM_sequential_curr_state_reg[1]_0 ; wire \FSM_sequential_curr_state_reg[1]_1 ; wire \FSM_sequential_curr_state_reg[1]_10 ; wire \FSM_sequential_curr_state_reg[1]_11 ; wire \FSM_sequential_curr_state_reg[1]_12 ; wire \FSM_sequential_curr_state_reg[1]_13 ; wire \FSM_sequential_curr_state_reg[1]_14 ; wire \FSM_sequential_curr_state_reg[1]_15 ; wire \FSM_sequential_curr_state_reg[1]_16 ; wire \FSM_sequential_curr_state_reg[1]_17 ; wire \FSM_sequential_curr_state_reg[1]_18 ; wire \FSM_sequential_curr_state_reg[1]_19 ; wire \FSM_sequential_curr_state_reg[1]_2 ; wire \FSM_sequential_curr_state_reg[1]_20 ; wire \FSM_sequential_curr_state_reg[1]_21 ; wire \FSM_sequential_curr_state_reg[1]_22 ; wire \FSM_sequential_curr_state_reg[1]_23 ; wire \FSM_sequential_curr_state_reg[1]_24 ; wire \FSM_sequential_curr_state_reg[1]_25 ; wire \FSM_sequential_curr_state_reg[1]_26 ; wire \FSM_sequential_curr_state_reg[1]_27 ; wire \FSM_sequential_curr_state_reg[1]_28 ; wire \FSM_sequential_curr_state_reg[1]_29 ; wire \FSM_sequential_curr_state_reg[1]_3 ; wire \FSM_sequential_curr_state_reg[1]_30 ; wire \FSM_sequential_curr_state_reg[1]_31 ; wire \FSM_sequential_curr_state_reg[1]_32 ; wire \FSM_sequential_curr_state_reg[1]_33 ; wire \FSM_sequential_curr_state_reg[1]_4 ; wire \FSM_sequential_curr_state_reg[1]_5 ; wire \FSM_sequential_curr_state_reg[1]_6 ; wire \FSM_sequential_curr_state_reg[1]_7 ; wire \FSM_sequential_curr_state_reg[1]_8 ; wire \FSM_sequential_curr_state_reg[1]_9 ; wire \FSM_sequential_curr_state_reg[2] ; wire \FSM_sequential_curr_state_reg[2]_0 ; wire [0:0]\FSM_sequential_curr_state_reg[2]_1 ; wire \FSM_sequential_curr_state_reg[2]_2 ; wire \FSM_sequential_curr_state_reg[2]_3 ; wire \FSM_sequential_curr_state_reg[2]_4 ; wire \FSM_sequential_curr_state_reg[2]_5 ; wire abort_applied; wire [6:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire [1:0]curr_state; wire [0:0]\i_dp_inf_ram_be/g_byte[0].byte_we_reg ; wire \i_dp_inf_ram_be/p_1_in ; wire \i_dp_inf_ram_be/p_2_in ; wire \i_dp_inf_ram_be/p_3_in ; wire \mr_tst_out[tst_control_twrstb] ; wire [2:0]\mr_tx_priority[3] ; wire \r_data[15]_i_2 ; wire [3:0]sbe_IBUF; wire scs_IBUF; wire swr_IBUF; wire tst_ena; wire tx_command_txce_valid; wire tx_command_txcr_valid; wire [0:0]txtb_allow_bb; wire [0:0]txtb_hw_cmd_cs; wire [3:3]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; wire [0:0]\txtb_state[3] ; txtb_fsm i_txtb_fsm (.\FSM_sequential_curr_state[2]_i_5__2_0 (\FSM_sequential_curr_state[2]_i_5__2 ), .\FSM_sequential_curr_state[2]_i_5__2_1 (\FSM_sequential_curr_state[2]_i_5__2_0 ), .\FSM_sequential_curr_state_reg[0]_0 (curr_state[0]), .\FSM_sequential_curr_state_reg[0]_1 (\FSM_sequential_curr_state_reg[0] ), .\FSM_sequential_curr_state_reg[0]_2 (\FSM_sequential_curr_state_reg[0]_0 ), .\FSM_sequential_curr_state_reg[0]_3 (\FSM_sequential_curr_state_reg[0]_1 ), .\FSM_sequential_curr_state_reg[0]_4 (\FSM_sequential_curr_state_reg[0]_2 ), .\FSM_sequential_curr_state_reg[0]_5 (\FSM_sequential_curr_state_reg[0]_3 ), .\FSM_sequential_curr_state_reg[1]_0 (curr_state[1]), .\FSM_sequential_curr_state_reg[1]_1 (\FSM_sequential_curr_state_reg[1] ), .\FSM_sequential_curr_state_reg[1]_10 (\FSM_sequential_curr_state_reg[1]_8 ), .\FSM_sequential_curr_state_reg[1]_11 (\FSM_sequential_curr_state_reg[1]_9 ), .\FSM_sequential_curr_state_reg[1]_12 (\FSM_sequential_curr_state_reg[1]_10 ), .\FSM_sequential_curr_state_reg[1]_13 (\FSM_sequential_curr_state_reg[1]_11 ), .\FSM_sequential_curr_state_reg[1]_14 (\FSM_sequential_curr_state_reg[1]_12 ), .\FSM_sequential_curr_state_reg[1]_15 (\FSM_sequential_curr_state_reg[1]_13 ), .\FSM_sequential_curr_state_reg[1]_16 (\FSM_sequential_curr_state_reg[1]_14 ), .\FSM_sequential_curr_state_reg[1]_17 (\FSM_sequential_curr_state_reg[1]_15 ), .\FSM_sequential_curr_state_reg[1]_18 (\FSM_sequential_curr_state_reg[1]_16 ), .\FSM_sequential_curr_state_reg[1]_19 (\FSM_sequential_curr_state_reg[1]_17 ), .\FSM_sequential_curr_state_reg[1]_2 (\FSM_sequential_curr_state_reg[1]_0 ), .\FSM_sequential_curr_state_reg[1]_20 (\FSM_sequential_curr_state_reg[1]_18 ), .\FSM_sequential_curr_state_reg[1]_21 (\FSM_sequential_curr_state_reg[1]_19 ), .\FSM_sequential_curr_state_reg[1]_22 (\FSM_sequential_curr_state_reg[1]_20 ), .\FSM_sequential_curr_state_reg[1]_23 (\FSM_sequential_curr_state_reg[1]_21 ), .\FSM_sequential_curr_state_reg[1]_24 (\FSM_sequential_curr_state_reg[1]_22 ), .\FSM_sequential_curr_state_reg[1]_25 (\FSM_sequential_curr_state_reg[1]_23 ), .\FSM_sequential_curr_state_reg[1]_26 (\FSM_sequential_curr_state_reg[1]_24 ), .\FSM_sequential_curr_state_reg[1]_27 (\FSM_sequential_curr_state_reg[1]_25 ), .\FSM_sequential_curr_state_reg[1]_28 (\FSM_sequential_curr_state_reg[1]_26 ), .\FSM_sequential_curr_state_reg[1]_29 (\FSM_sequential_curr_state_reg[1]_27 ), .\FSM_sequential_curr_state_reg[1]_3 (\FSM_sequential_curr_state_reg[1]_1 ), .\FSM_sequential_curr_state_reg[1]_30 (\FSM_sequential_curr_state_reg[1]_28 ), .\FSM_sequential_curr_state_reg[1]_31 (\FSM_sequential_curr_state_reg[1]_29 ), .\FSM_sequential_curr_state_reg[1]_32 (\FSM_sequential_curr_state_reg[1]_30 ), .\FSM_sequential_curr_state_reg[1]_33 (\FSM_sequential_curr_state_reg[1]_31 ), .\FSM_sequential_curr_state_reg[1]_34 (\FSM_sequential_curr_state_reg[1]_32 ), .\FSM_sequential_curr_state_reg[1]_35 (\FSM_sequential_curr_state_reg[1]_33 ), .\FSM_sequential_curr_state_reg[1]_4 (\FSM_sequential_curr_state_reg[1]_2 ), .\FSM_sequential_curr_state_reg[1]_5 (\FSM_sequential_curr_state_reg[1]_3 ), .\FSM_sequential_curr_state_reg[1]_6 (\FSM_sequential_curr_state_reg[1]_4 ), .\FSM_sequential_curr_state_reg[1]_7 (\FSM_sequential_curr_state_reg[1]_5 ), .\FSM_sequential_curr_state_reg[1]_8 (\FSM_sequential_curr_state_reg[1]_6 ), .\FSM_sequential_curr_state_reg[1]_9 (\FSM_sequential_curr_state_reg[1]_7 ), .\FSM_sequential_curr_state_reg[2]_0 (\FSM_sequential_curr_state_reg[2] ), .\FSM_sequential_curr_state_reg[2]_1 (\txtb_state[3] ), .\FSM_sequential_curr_state_reg[2]_2 (\FSM_sequential_curr_state_reg[2]_0 ), .\FSM_sequential_curr_state_reg[2]_3 (\FSM_sequential_curr_state_reg[2]_1 ), .\FSM_sequential_curr_state_reg[2]_4 (\FSM_sequential_curr_state_reg[2]_2 ), .\FSM_sequential_curr_state_reg[2]_5 (\FSM_sequential_curr_state_reg[2]_3 ), .\FSM_sequential_curr_state_reg[2]_6 (\FSM_sequential_curr_state_reg[2]_4 ), .\FSM_sequential_curr_state_reg[2]_7 (\FSM_sequential_curr_state_reg[2]_5 ), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .abort_applied(abort_applied), .adress_IBUF(adress_IBUF[2:0]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .\mr_tst_out[tst_control_twrstb] (\mr_tst_out[tst_control_twrstb] ), .\mr_tx_priority[3] (\mr_tx_priority[3] ), .\r_data[15]_i_2 (\r_data[15]_i_2 ), .sbe_IBUF(sbe_IBUF), .tst_ena(tst_ena), .tx_command_txce_valid(tx_command_txce_valid), .tx_command_txcr_valid(tx_command_txcr_valid), .txtb_allow_bb(txtb_allow_bb), .txtb_hw_cmd_cs(txtb_hw_cmd_cs), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); txtb_ram__parameterized2 i_txtb_ram (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE({\i_dp_inf_ram_be/p_3_in ,\i_dp_inf_ram_be/p_2_in ,\i_dp_inf_ram_be/p_1_in ,\i_dp_inf_ram_be/g_byte[0].byte_we_reg }), .adress_IBUF(adress_IBUF[6:3]), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule module txtb_ram (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, swr_IBUF, scs_IBUF, adress_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input swr_IBUF; input scs_IBUF; input [3:0]adress_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; dp_inf_ram_be_91 i_dp_inf_ram_be (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE(WEBWE), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule (* ORIG_REF_NAME = "txtb_ram" *) module txtb_ram__parameterized0 (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, swr_IBUF, scs_IBUF, adress_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input swr_IBUF; input scs_IBUF; input [3:0]adress_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; dp_inf_ram_be_89 i_dp_inf_ram_be (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE(WEBWE), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule (* ORIG_REF_NAME = "txtb_ram" *) module txtb_ram__parameterized1 (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, adress_IBUF, swr_IBUF, scs_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input [3:0]adress_IBUF; input swr_IBUF; input scs_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; dp_inf_ram_be_87 i_dp_inf_ram_be (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE(WEBWE), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule (* ORIG_REF_NAME = "txtb_ram" *) module txtb_ram__parameterized2 (txtb_port_b_data_out_i, txtb_port_a_cs, clk_sys_IBUF_BUFG, ADDRARDADDR, ADDRBWRADDR, DIADI, DIBDI, WEBWE, swr_IBUF, scs_IBUF, adress_IBUF); output [31:0]txtb_port_b_data_out_i; output [0:0]txtb_port_a_cs; input clk_sys_IBUF_BUFG; input [4:0]ADDRARDADDR; input [4:0]ADDRBWRADDR; input [15:0]DIADI; input [15:0]DIBDI; input [3:0]WEBWE; input swr_IBUF; input scs_IBUF; input [3:0]adress_IBUF; wire [4:0]ADDRARDADDR; wire [4:0]ADDRBWRADDR; wire [15:0]DIADI; wire [15:0]DIBDI; wire [3:0]WEBWE; wire [3:0]adress_IBUF; wire clk_sys_IBUF_BUFG; wire scs_IBUF; wire swr_IBUF; wire [0:0]txtb_port_a_cs; wire [31:0]txtb_port_b_data_out_i; dp_inf_ram_be i_dp_inf_ram_be (.ADDRARDADDR(ADDRARDADDR), .ADDRBWRADDR(ADDRBWRADDR), .DIADI(DIADI), .DIBDI(DIBDI), .WEBWE(WEBWE), .adress_IBUF(adress_IBUF), .clk_sys_IBUF_BUFG(clk_sys_IBUF_BUFG), .scs_IBUF(scs_IBUF), .swr_IBUF(swr_IBUF), .txtb_port_a_cs(txtb_port_a_cs), .txtb_port_b_data_out_i(txtb_port_b_data_out_i)); endmodule /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2018 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2018.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / Fast Carry Logic with Look Ahead // /___/ /\ Filename : CARRY4.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 04/11/05 - Initial version. // 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752) // 05/31/05 - Change pin order, remove connection check for CYINIT and CI. // 12/21/05 - Add timing path. // 04/13/06 - Add full timing path for DI to O (CR228786) // 06/04/07 - Add wire definition. // 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). // 04/13/12 - CR655410 - add pulldown, CI, CYINIT, sync uni/sim/unp // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps `celldefine module CARRY4 `ifdef XIL_TIMING #( parameter LOC = "UNPLACED" ) `endif ( output [3:0] CO, output [3:0] O, input CI, input CYINIT, input [3:0] DI, input [3:0] S ); // define constants localparam MODULE_NAME = "CARRY4"; `ifdef XIL_XECLIB reg glblGSR = 1'b0; `else tri0 glblGSR = glbl.GSR; `endif wire CI_in; wire CYINIT_in; wire [3:0] DI_in; wire [3:0] S_in; assign CI_in = (CI !== 1'bz) && CI; // rv 0 assign CYINIT_in = (CYINIT !== 1'bz) && CYINIT; // rv 0 assign DI_in = DI; assign S_in = S; // begin behavioral model wire [3:0] CO_fb; assign CO_fb = {CO[2:0], CI_in || CYINIT_in}; assign O = S_in ^ CO_fb; assign CO = (S_in & CO_fb) | (~S_in & DI_in); // end behavioral model `ifndef XIL_XECLIB `ifdef XIL_TIMING specify (CI => CO[0]) = (0:0:0, 0:0:0); (CI => CO[1]) = (0:0:0, 0:0:0); (CI => CO[2]) = (0:0:0, 0:0:0); (CI => CO[3]) = (0:0:0, 0:0:0); (CI => O[0]) = (0:0:0, 0:0:0); (CI => O[1]) = (0:0:0, 0:0:0); (CI => O[2]) = (0:0:0, 0:0:0); (CI => O[3]) = (0:0:0, 0:0:0); (CYINIT => CO[0]) = (0:0:0, 0:0:0); (CYINIT => CO[1]) = (0:0:0, 0:0:0); (CYINIT => CO[2]) = (0:0:0, 0:0:0); (CYINIT => CO[3]) = (0:0:0, 0:0:0); (CYINIT => O[0]) = (0:0:0, 0:0:0); (CYINIT => O[1]) = (0:0:0, 0:0:0); (CYINIT => O[2]) = (0:0:0, 0:0:0); (CYINIT => O[3]) = (0:0:0, 0:0:0); (DI[0] => CO[0]) = (0:0:0, 0:0:0); (DI[0] => CO[1]) = (0:0:0, 0:0:0); (DI[0] => CO[2]) = (0:0:0, 0:0:0); (DI[0] => CO[3]) = (0:0:0, 0:0:0); (DI[0] => O[0]) = (0:0:0, 0:0:0); (DI[0] => O[1]) = (0:0:0, 0:0:0); (DI[0] => O[2]) = (0:0:0, 0:0:0); (DI[0] => O[3]) = (0:0:0, 0:0:0); (DI[1] => CO[0]) = (0:0:0, 0:0:0); (DI[1] => CO[1]) = (0:0:0, 0:0:0); (DI[1] => CO[2]) = (0:0:0, 0:0:0); (DI[1] => CO[3]) = (0:0:0, 0:0:0); (DI[1] => O[0]) = (0:0:0, 0:0:0); (DI[1] => O[1]) = (0:0:0, 0:0:0); (DI[1] => O[2]) = (0:0:0, 0:0:0); (DI[1] => O[3]) = (0:0:0, 0:0:0); (DI[2] => CO[0]) = (0:0:0, 0:0:0); (DI[2] => CO[1]) = (0:0:0, 0:0:0); (DI[2] => CO[2]) = (0:0:0, 0:0:0); (DI[2] => CO[3]) = (0:0:0, 0:0:0); (DI[2] => O[0]) = (0:0:0, 0:0:0); (DI[2] => O[1]) = (0:0:0, 0:0:0); (DI[2] => O[2]) = (0:0:0, 0:0:0); (DI[2] => O[3]) = (0:0:0, 0:0:0); (DI[3] => CO[0]) = (0:0:0, 0:0:0); (DI[3] => CO[1]) = (0:0:0, 0:0:0); (DI[3] => CO[2]) = (0:0:0, 0:0:0); (DI[3] => CO[3]) = (0:0:0, 0:0:0); (DI[3] => O[0]) = (0:0:0, 0:0:0); (DI[3] => O[1]) = (0:0:0, 0:0:0); (DI[3] => O[2]) = (0:0:0, 0:0:0); (DI[3] => O[3]) = (0:0:0, 0:0:0); (S[0] => CO[0]) = (0:0:0, 0:0:0); (S[0] => CO[1]) = (0:0:0, 0:0:0); (S[0] => CO[2]) = (0:0:0, 0:0:0); (S[0] => CO[3]) = (0:0:0, 0:0:0); (S[0] => O[0]) = (0:0:0, 0:0:0); (S[0] => O[1]) = (0:0:0, 0:0:0); (S[0] => O[2]) = (0:0:0, 0:0:0); (S[0] => O[3]) = (0:0:0, 0:0:0); (S[1] => CO[0]) = (0:0:0, 0:0:0); (S[1] => CO[1]) = (0:0:0, 0:0:0); (S[1] => CO[2]) = (0:0:0, 0:0:0); (S[1] => CO[3]) = (0:0:0, 0:0:0); (S[1] => O[0]) = (0:0:0, 0:0:0); (S[1] => O[1]) = (0:0:0, 0:0:0); (S[1] => O[2]) = (0:0:0, 0:0:0); (S[1] => O[3]) = (0:0:0, 0:0:0); (S[2] => CO[0]) = (0:0:0, 0:0:0); (S[2] => CO[1]) = (0:0:0, 0:0:0); (S[2] => CO[2]) = (0:0:0, 0:0:0); (S[2] => CO[3]) = (0:0:0, 0:0:0); (S[2] => O[0]) = (0:0:0, 0:0:0); (S[2] => O[1]) = (0:0:0, 0:0:0); (S[2] => O[2]) = (0:0:0, 0:0:0); (S[2] => O[3]) = (0:0:0, 0:0:0); (S[3] => CO[0]) = (0:0:0, 0:0:0); (S[3] => CO[1]) = (0:0:0, 0:0:0); (S[3] => CO[2]) = (0:0:0, 0:0:0); (S[3] => CO[3]) = (0:0:0, 0:0:0); (S[3] => O[0]) = (0:0:0, 0:0:0); (S[3] => O[1]) = (0:0:0, 0:0:0); (S[3] => O[2]) = (0:0:0, 0:0:0); (S[3] => O[3]) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2009 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 10.1 // \ \ Description : Xilinx Functional Simulation Library Component // / / 2-to-1 Lookup Table Multiplexer with General Output // /___/ /\ Filename : MUXF7.v // \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 // \___\/\___\ // // Revision: // 03/23/04 - Initial version. // 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; // 05/10/07 - When input same, output same for any sel value. (CR434611). // 08/23/07 - User block statement (CR446704). // 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). // End Revision `timescale 1 ps / 1 ps `celldefine module MUXF7 (O, I0, I1, S); `ifdef XIL_TIMING parameter LOC = "UNPLACED"; `endif output O; input I0, I1, S; reg O_out; always @(I0 or I1 or S) if (S) O_out = I1; else O_out = I0; assign O = O_out; `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); (I1 => O) = (0:0:0, 0:0:0); (S => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / 1-Bit Look-Up Table // /___/ /\ Filename : LUT1.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 05/12/11 - Initial version. // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // 09/12/16 - ANSI ports, speed improvements // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `celldefine module LUT1 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter [1:0] INIT = 2'h0 )( output O, input I0 ); // define constants localparam MODULE_NAME = "LUT1"; reg trig_attr = 1'b0; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "LUT1_dr.v" `else reg [1:0] INIT_REG = INIT; `endif x_lut1_mux2 (O, INIT_REG[1], INIT_REG[0], I0); `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine primitive x_lut1_mux2 (o, d1, d0, s0); output o; input d1, d0; input s0; table // d1 d0 s0 : o; ? 1 0 : 1; ? 0 0 : 0; 1 ? 1 : 1; 0 ? 1 : 0; 0 0 x : 0; 1 1 x : 1; endtable endprimitive /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / 5-Bit Look-Up Table // /___/ /\ Filename : LUT5.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 03/23/04 - Initial version. // 02/04/05 - Replace primitive with function; Remove buf. // 01/07/06 - 222733 - Add LOC Parameter // 06/04/07 - Add wire declaration to internal signal. // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // 09/12/16 - ANSI ports, speed improvements // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `celldefine module LUT5 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter [31:0] INIT = 32'h00000000 )( output O, input I0, input I1, input I2, input I3, input I4 ); // define constants localparam MODULE_NAME = "LUT5"; reg trig_attr = 1'b0; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "LUT5_dr.v" `else reg [31:0] INIT_REG = INIT; `endif // begin behavioral model reg O_out; assign O = O_out; function lut_mux4_f; input [3:0] d; input [1:0] s; begin if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) lut_mux4_f = d[s]; else if ( ~(|d) || &d) lut_mux4_f = d[0]; else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}])) lut_mux4_f = d[{1'b0,s[0]}]; else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}])) lut_mux4_f = d[{s[1],1'b0}]; else lut_mux4_f = 1'bx; end endfunction function lut_mux8_f; input [7:0] d; input [2:0] s; begin if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0)) lut_mux8_f = d[s]; else if ( ~(|d) || &d) lut_mux8_f = d[0]; else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) && (d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}])) lut_mux8_f = d[{1'b0,s[1:0]}]; else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) && (d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}])) lut_mux8_f = d[{s[2],1'b0,s[0]}]; else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) && (d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}])) lut_mux8_f = d[{s[2:1],1'b0}]; else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) && (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}])) lut_mux8_f = d[{1'b0,1'b0,s[0]}]; else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) && (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}])) lut_mux8_f = d[{1'b0,s[1],1'b0}]; else if (((s[2] === 1'b1) || (s[2] === 1'b0)) && (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) && (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}])) lut_mux8_f = d[{s[2],1'b0,1'b0}]; else lut_mux8_f = 1'bx; end endfunction always @(I0 or I1 or I2 or I3 or I4) begin if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4) === 1'b1) O_out = INIT_REG[{I4, I3, I2, I1, I0}]; else if ( ~(|INIT_REG) || &INIT_REG ) O_out = INIT_REG[0]; else O_out = lut_mux4_f ({lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}), lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}), lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}), lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I4, I3}); end // end behavioral model `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); (I1 => O) = (0:0:0, 0:0:0); (I2 => O) = (0:0:0, 0:0:0); (I3 => O) = (0:0:0, 0:0:0); (I4 => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / D Flip-Flop with Clock Enable and Asynchronous Preset // /___/ /\ Filename : FDPE.v // \ \ / \ // \___\/\___\ // // Revision: // 08/25/10 - Initial version. // 10/20/10 - remove unused pin line from table. // 11/01/11 - Disable timing check when set reset active (CR632017) // 12/08/11 - add MSGON and XON attributes (CR636891) // 01/16/12 - 640813 - add MSGON and XON functionality // 04/16/13 - PR683925 - add invertible pin support. // End Revision `timescale 1 ps / 1 ps `celldefine module FDPE #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", parameter MSGON = "TRUE", parameter XON = "TRUE", `endif parameter [0:0] INIT = 1'b1, parameter [0:0] IS_C_INVERTED = 1'b0, parameter [0:0] IS_D_INVERTED = 1'b0, parameter [0:0] IS_PRE_INVERTED = 1'b0 )( output Q, input C, input CE, input D, input PRE ); reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; reg [0:0] IS_PRE_INVERTED_REG = IS_PRE_INVERTED; tri0 glblGSR = glbl.GSR; `ifdef XIL_TIMING wire D_dly, C_dly, CE_dly; wire PRE_dly; `endif wire PRE_in; `ifdef XIL_TIMING assign PRE_in = (PRE_dly ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz); `else assign PRE_in = (PRE ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz); `endif // begin behavioral model reg Q_out; assign #100 Q = Q_out; always @(glblGSR or PRE_in) if (glblGSR) assign Q_out = INIT; else if (PRE_in === 1'b1) assign Q_out = 1'b1; else if (PRE_in === 1'bx) assign Q_out = 1'bx; else deassign Q_out; `ifdef XIL_TIMING generate if (IS_C_INVERTED == 1'b0) begin : generate_block1 always @(posedge C_dly or posedge PRE_in) if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) Q_out <= 1'b1; else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) Q_out <= D_dly ^ IS_D_INVERTED_REG; end else begin : generate_block1 always @(negedge C_dly or posedge PRE_in) if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) Q_out <= 1'b1; else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) Q_out <= D_dly ^ IS_D_INVERTED_REG; end endgenerate `else generate if (IS_C_INVERTED == 1'b0) begin : generate_block1 always @(posedge C or posedge PRE_in) if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) Q_out <= 1'b1; else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) Q_out <= D ^ IS_D_INVERTED_REG; end else begin : generate_block1 always @(negedge C or posedge PRE_in) if (PRE_in || (PRE === 1'bx && Q_out == 1'b1)) Q_out <= 1'b1; else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) Q_out <= D ^ IS_D_INVERTED_REG; end endgenerate `endif `ifdef XIL_TIMING reg notifier; wire notifier1; `endif `ifdef XIL_TIMING wire ngsr, in_out; wire nset; wire in_clk_enable, in_clk_enable_p, in_clk_enable_n; wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n; reg init_enable = 1'b1; wire set_clk_enable, set_clk_enable_p, set_clk_enable_n; `endif `ifdef XIL_TIMING not (ngsr, glblGSR); xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out); not (nset, (PRE_dly ^ IS_PRE_INVERTED_REG) && (PRE !== 1'bz)); and (in_clk_enable, ngsr, nset, CE || (CE === 1'bz)); and (ce_clk_enable, ngsr, nset, in_out); and (set_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG); always @(negedge nset) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT); assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1); assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1); assign set_clk_enable_n = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b1); assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0); assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0); assign set_clk_enable_p = (MSGON =="TRUE") && set_clk_enable && (IS_C_INVERTED == 1'b0); `endif // end behavioral model `ifdef XIL_TIMING specify (C => Q) = (100:100:100, 100:100:100); (negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0); (posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0); (PRE => Q) = (0:0:0, 0:0:0); $period (negedge C &&& CE, 0:0:0, notifier); $period (posedge C &&& CE, 0:0:0, notifier); $recrem (negedge PRE, negedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,PRE_dly, C_dly); $recrem (negedge PRE, posedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,PRE_dly, C_dly); $recrem (posedge PRE, negedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_n,set_clk_enable_n,PRE_dly, C_dly); $recrem (posedge PRE, posedge C, 0:0:0, 0:0:0, notifier,set_clk_enable_p,set_clk_enable_p,PRE_dly, C_dly); $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); $width (negedge C &&& CE, 0:0:0, 0, notifier); $width (negedge PRE &&& init_enable, 0:0:0, 0, notifier); $width (posedge C &&& CE, 0:0:0, 0, notifier); $width (posedge PRE &&& init_enable, 0:0:0, 0, notifier); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / 4-Bit Look-Up Table // /___/ /\ Filename : LUT4.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 03/23/04 - Initial version. // 02/04/05 - Replace primitive with function; Remove buf. // 03/11/05 - Add LOC Parameter // 06/04/07 - Add wire declaration to internal signal. // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // 09/12/16 - ANSI ports, speed improvements // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `celldefine module LUT4 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter [15:0] INIT = 16'h0000 )( output O, input I0, input I1, input I2, input I3 ); // define constants localparam MODULE_NAME = "LUT4"; reg trig_attr = 1'b0; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "LUT4_dr.v" `else reg [15:0] INIT_REG = INIT; `endif // begin behavioral model reg O_out; assign O = O_out; function lut_mux4_f; input [3:0] d; input [1:0] s; begin if (((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) lut_mux4_f = d[s]; else if ( ~(|d) || &d) lut_mux4_f = d[0]; else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,s[0]}] === d[{1'b1,s[0]}])) lut_mux4_f = d[{1'b0,s[0]}]; else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{s[1],1'b0}] === d[{s[1],1'b1}])) lut_mux4_f = d[{s[1],1'b0}]; else lut_mux4_f = 1'bx; end endfunction always @(I0 or I1 or I2 or I3) begin if ( (I0 ^ I1 ^ I2 ^ I3) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3) === 1'b1) O_out = INIT_REG[{I3, I2, I1, I0}]; else if ( ~(|INIT_REG) || &INIT_REG ) O_out = INIT_REG[0]; else O_out = lut_mux4_f ({lut_mux4_f (INIT_REG[15:12], {I1, I0}), lut_mux4_f ( INIT_REG[11:8], {I1, I0}), lut_mux4_f ( INIT_REG[7:4], {I1, I0}), lut_mux4_f ( INIT_REG[3:0], {I1, I0})}, {I3, I2}); end // end behavioral model `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); (I1 => O) = (0:0:0, 0:0:0); (I2 => O) = (0:0:0, 0:0:0); (I3 => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2018 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2018.3 // \ \ Description : Xilinx Unified Simulation Library Component // / / General Clock Buffer // /___/ /\ Filename : BUFG.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 03/23/04 - Initial version. // 05/23/07 - Changed timescale to 1 ps / 1 ps. // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps `celldefine module BUFG `ifdef XIL_TIMING #( parameter LOC = "UNPLACED" ) `endif ( output O, input I ); // define constants localparam MODULE_NAME = "BUFG"; `ifdef XIL_TIMING reg notifier; `endif // begin behavioral model buf B1 (O, I); // end behavioral model `ifndef XIL_XECLIB `ifdef XIL_TIMING specify (I => O) = (0:0:0, 0:0:0); $period (negedge I, 0:0:0, notifier); $period (posedge I, 0:0:0, notifier); specparam PATHPULSE$ = 0; endspecify `endif `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2009 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 10.1 // \ \ Description : Xilinx Functional Simulation Library Component // / / GND Connection // /___/ /\ Filename : GND.v // \ \ / \ Timestamp : Thu Mar 25 16:42:19 PST 2004 // \___\/\___\ // // Revision: // 03/23/04 - Initial version. // 05/23/07 - Changed timescale to 1 ps / 1 ps. `timescale 1 ps / 1 ps `celldefine module GND(G); `ifdef XIL_TIMING parameter LOC = "UNPLACED"; `endif output G; assign G = 1'b0; endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / D Flip-Flop with Clock Enable and Asynchronous Clear // /___/ /\ Filename : FDCE.v // \ \ / \ // \___\/\___\ // // Revision: // 08/24/10 - Initial version. // 10/20/10 - remove unused pin line from table. // 11/01/11 - Disable timing check when set reset active (CR632017) // 12/08/11 - add MSGON and XON attributes (CR636891) // 01/16/12 - 640813 - add MSGON and XON functionality // 04/16/13 - PR683925 - add invertible pin support. // End Revision `timescale 1 ps / 1 ps `celldefine module FDCE #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", parameter MSGON = "TRUE", parameter XON = "TRUE", `endif parameter [0:0] INIT = 1'b0, parameter [0:0] IS_CLR_INVERTED = 1'b0, parameter [0:0] IS_C_INVERTED = 1'b0, parameter [0:0] IS_D_INVERTED = 1'b0 )( output Q, input C, input CE, input CLR, input D ); reg [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED; reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED; reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED; tri0 glblGSR = glbl.GSR; `ifdef XIL_TIMING wire D_dly, C_dly, CE_dly; wire CLR_dly; `endif wire CLR_in; `ifdef XIL_TIMING assign CLR_in = (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz); `else assign CLR_in = (CLR ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz); `endif // begin behavioral model reg Q_out; assign #100 Q = Q_out; always @(glblGSR or CLR_in) if (glblGSR) assign Q_out = INIT; else if (CLR_in === 1'b1) assign Q_out = 1'b0; else if (CLR_in === 1'bx) assign Q_out = 1'bx; else deassign Q_out; `ifdef XIL_TIMING generate if (IS_C_INVERTED == 1'b0) begin : generate_block1 always @(posedge C_dly or posedge CLR_in) if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) Q_out <= 1'b0; else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) Q_out <= D_dly ^ IS_D_INVERTED_REG; end else begin : generate_block1 always @(negedge C_dly or posedge CLR_in) if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) Q_out <= 1'b0; else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG)))) Q_out <= D_dly ^ IS_D_INVERTED_REG; end endgenerate `else generate if (IS_C_INVERTED == 1'b0) begin : generate_block1 always @(posedge C or posedge CLR_in) if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) Q_out <= 1'b0; else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) Q_out <= D ^ IS_D_INVERTED_REG; end else begin : generate_block1 always @(negedge C or posedge CLR_in) if (CLR_in || (CLR === 1'bx && Q_out == 1'b0)) Q_out <= 1'b0; else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG)))) Q_out <= D ^ IS_D_INVERTED_REG; end endgenerate `endif `ifdef XIL_TIMING reg notifier; wire notifier1; `endif `ifdef XIL_TIMING wire ngsr, in_out; wire nrst; wire in_clk_enable, in_clk_enable_p, in_clk_enable_n; wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n; reg init_enable = 1'b1; wire rst_clk_enable, rst_clk_enable_p, rst_clk_enable_n; `endif `ifdef XIL_TIMING not (ngsr, glblGSR); xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out); not (nrst, (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz)); and (in_clk_enable, ngsr, nrst, CE || (CE === 1'bz)); and (ce_clk_enable, ngsr, nrst, in_out); and (rst_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG); always @(negedge nrst) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT); assign notifier1 = (XON == "FALSE") ? 1'bx : notifier; assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1); assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1); assign rst_clk_enable_n = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b1); assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0); assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0); assign rst_clk_enable_p = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b0); `endif // end behavioral model `ifdef XIL_TIMING specify (C => Q) = (100:100:100, 100:100:100); (negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0); (posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0); (CLR => Q) = (0:0:0, 0:0:0); $period (negedge C &&& CE, 0:0:0, notifier); $period (posedge C &&& CE, 0:0:0, notifier); $recrem (negedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly); $recrem (negedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly); $recrem (posedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly); $recrem (posedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly); $setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); $setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); $setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly); $setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly); $setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); $setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); $setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly); $setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly); $width (negedge C &&& CE, 0:0:0, 0, notifier); $width (negedge CLR &&& init_enable, 0:0:0, 0, notifier); $width (posedge C &&& CE, 0:0:0, 0, notifier); $width (posedge CLR &&& init_enable, 0:0:0, 0, notifier); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2004 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 10.1 // \ \ Description : Xilinx Functional Simulation Library Component // / / Output Buffer // /___/ /\ Filename : OBUF.v // \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 // \___\/\___\ // // Revision: // 03/23/04 - Initial version. // 02/22/06 - CR#226003 - Added integer, real parameter type // 05/23/07 - Changed timescale to 1 ps / 1 ps. `timescale 1 ps / 1 ps `celldefine module OBUF (O, I); parameter CAPACITANCE = "DONT_CARE"; parameter integer DRIVE = 12; parameter IOSTANDARD = "DEFAULT"; `ifdef XIL_TIMING parameter LOC = " UNPLACED"; `endif parameter SLEW = "SLOW"; output O; input I; tri0 GTS = glbl.GTS; bufif0 B1 (O, I, GTS); initial begin case (CAPACITANCE) "LOW", "NORMAL", "DONT_CARE" : ; default : begin $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); #1 $finish; end endcase end `ifdef XIL_TIMING specify (I => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2017 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.3 // \ \ Description : Xilinx Unified Simulation Library Component // / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM // /___/ /\ Filename : RAMB18E1.v // \ \ / \ // \___\/\___\ // // Revision: // 02/26/08 - Initial version. // 07/25/08 - Fixed ECC in register mode. (IR 477257) // 07/30/08 - Updated to support SDP mode with smaller port width <= 18. (IR 477258) // 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964) // 03/11/09 - X's the unused bits of outputs (CR 511363). // 03/12/09 - Removed parameter from specify block (CR 503821). // 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167). // 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450). // 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327). // 08/12/09 - Updated collision address check for none in phase clocks (CR 527010). // 11/18/09 - Define tasks and functions before calling (CR 532610). // 12/16/09 - Enhanced memory initialization (CR 540764). // 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010). // 04/01/10 - Fixed clocks detection for collision (CR 552123). // 05/11/10 - Updated clocks detection for collision (CR 557624). // - Added attribute RDADDR_COLLISION_HWCONFIG. (CR 557971). // 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807). // 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971). // 07/08/10 - Added SIM_DEVICE attribute (CR 567633). // 07/09/10 - Initialized memory to zero for INIT_FILE (CR 560672). // 08/09/10 - Updated the model according to new address collision/overlap tables (CR 566507). // 09/16/10 - Updated from bit to bus timing (CR 575523). // 10/14/10 - Removed NO_CHANGE support in SDP mode (CR 575924). // 10/15/10 - Updated 7SERIES address overlap and address collision (CR 575953). // 12/10/10 - Converted parameter to wire in specify block (CR 574534). // 03/16/11 - Changed synchronous clock skew to 50ps for 7 series(CR 588053). // 08/04/11 - Fixed address overlap when clocks are within 100ps (CR 611004). // 09/12/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap (CR 621942). // 09/28/11 - Fixed ECC error when clocks are within 100ps with address collision/overlap, part 2 (CR 621942). // 10/11/11 - Fixed collision with clocks rise at the same time (CR 628129). // 10/17/11 - Fixed collision with clocks within 100ps in SDP mode (CR 620844). // 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190). // 11/04/11 - Fixed collision with clock within 100ps in TDP mode (CR 627670). // 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). // 02/05/12 - Fixed read width function when READ_WIDTH_A/B = 0 (CR 643482). // 02/22/12 - Fixed mem/memp out of bounds warning messages (CR 584399). // 03/06/12 - Fixed hierarchical error from CR 584399 (CR 648454). // 03/15/12 - Reverted CR 584399 (CR 651279). // 02/15/13 - Updated collision check to use clock period or 3ns (CR 694934). // 07/25/13 - Added invertible pins support (CR 715417). // 09/04/13 - Removed warning for memp (CR 728988). // 03/24/14 - Balanced all iniputs with xor (CR778933). // 08/29/14 - Added negative timing check (CR 821138). // 09/05/14 - Fixed timing check (CR 822107) // 10/01/14 - Updated conditional timing check for IS_INVERTED parameter. // 10/22/14 - Added #1 to $finish (CR 808642). // 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966). // End Revision `timescale 1 ps / 1 ps `celldefine module RAMB18E1 (DOADO, DOBDO, DOPADOP, DOPBDOP, ADDRARDADDR, ADDRBWRADDR, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE); parameter integer DOA_REG = 0; parameter integer DOB_REG = 0; parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter [17:0] INIT_A = 18'h0; parameter [17:0] INIT_B = 18'h0; parameter INIT_FILE = "NONE"; parameter IS_CLKARDCLK_INVERTED = 1'b0; parameter IS_CLKBWRCLK_INVERTED = 1'b0; parameter IS_ENARDEN_INVERTED = 1'b0; parameter IS_ENBWREN_INVERTED = 1'b0; parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; parameter IS_RSTRAMB_INVERTED = 1'b0; parameter IS_RSTREGARSTREG_INVERTED = 1'b0; parameter IS_RSTREGB_INVERTED = 1'b0; `ifdef XIL_TIMING parameter LOC = "UNPLACED"; `endif parameter RAM_MODE = "TDP"; parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; parameter integer READ_WIDTH_A = 0; parameter integer READ_WIDTH_B = 0; parameter RSTREG_PRIORITY_A = "RSTREG"; parameter RSTREG_PRIORITY_B = "RSTREG"; parameter SIM_COLLISION_CHECK = "ALL"; parameter SIM_DEVICE = "7SERIES"; parameter [17:0] SRVAL_A = 18'h0; parameter [17:0] SRVAL_B = 18'h0; parameter WRITE_MODE_A = "WRITE_FIRST"; parameter WRITE_MODE_B = "WRITE_FIRST"; parameter integer WRITE_WIDTH_A = 0; parameter integer WRITE_WIDTH_B = 0; localparam SETUP_ALL = 1000; localparam SETUP_READ_FIRST = 3000; output [15:0] DOADO; output [15:0] DOBDO; output [1:0] DOPADOP; output [1:0] DOPBDOP; input CLKARDCLK; input CLKBWRCLK; input ENARDEN; input ENBWREN; input REGCEAREGCE; input REGCEB; input RSTRAMARSTRAM; input RSTRAMB; input RSTREGARSTREG; input RSTREGB; input [13:0] ADDRARDADDR; input [13:0] ADDRBWRADDR; input [15:0] DIADI; input [15:0] DIBDI; input [1:0] DIPADIP; input [1:0] DIPBDIP; input [1:0] WEA; input [3:0] WEBWE; tri0 GSR = glbl.GSR; wire [7:0] dangle_out8; wire dangle_out; wire [1:0] dangle_out2; wire [3:0] dangle_out4; wire [5:0] dangle_out6; wire [8:0] dangle_out9; wire [15:0] dangle_out16; wire [31:0] dangle_out32; wire [47:0] dangle_out48; wire [15:0] doado_wire, dobdo_wire; wire [1:0] dopadop_wire, dopbdop_wire; reg [15:0] doado_out, dobdo_out; reg [1:0] dopadop_out, dopbdop_out; reg notifier, notifier_a, notifier_b; reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4; reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9; reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13; reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4; reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9; reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13; reg attr_err = 1'b0; wire regcearegce_in; wire regceb_in; wire [13:0] addrardaddr_in; wire [13:0] addrbwraddr_in; wire [15:0] diadi_in; wire [15:0] dibdi_in; wire [1:0] dipadip_in; wire [1:0] dipbdip_in; wire [1:0] wea_in; wire [3:0] webwe_in; wire clkardclk_in; wire clkbwrclk_in; wire enarden_in; wire enbwren_in; wire rstramarstram_in; wire rstramb_in; wire rstregarstreg_in; wire rstregb_in; `ifdef XIL_TIMING wire CLKARDCLK_delay; wire CLKBWRCLK_delay; wire ENARDEN_delay; wire ENBWREN_delay; wire REGCEAREGCE_delay; wire REGCEB_delay; wire RSTRAMARSTRAM_delay; wire RSTRAMB_delay; wire RSTREGARSTREG_delay; wire RSTREGB_delay; wire [13:0] ADDRARDADDR_delay; wire [13:0] ADDRBWRADDR_delay; wire [15:0] DIADI_delay; wire [15:0] DIBDI_delay; wire [1:0] DIPADIP_delay; wire [1:0] DIPBDIP_delay; wire [1:0] WEA_delay; wire [3:0] WEBWE_delay; `endif `ifdef XIL_TIMING assign regcearegce_in = REGCEAREGCE_delay; assign regceb_in = REGCEB_delay; assign addrardaddr_in = ADDRARDADDR_delay; assign addrbwraddr_in = ADDRBWRADDR_delay; assign diadi_in = DIADI_delay; assign dibdi_in = DIBDI_delay; assign dipadip_in = DIPADIP_delay; assign dipbdip_in = DIPBDIP_delay; assign wea_in = WEA_delay; assign webwe_in = WEBWE_delay; assign clkardclk_in = CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED; assign clkbwrclk_in = CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED; assign enarden_in = ENARDEN_delay ^ IS_ENARDEN_INVERTED; assign enbwren_in = ENBWREN_delay ^ IS_ENBWREN_INVERTED; assign rstramarstram_in = RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED; assign rstramb_in = RSTRAMB_delay ^ IS_RSTRAMB_INVERTED; assign rstregarstreg_in = RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED; assign rstregb_in = RSTREGB_delay ^ IS_RSTREGB_INVERTED; `else assign regcearegce_in = REGCEAREGCE; assign regceb_in = REGCEB; assign addrardaddr_in = ADDRARDADDR; assign addrbwraddr_in = ADDRBWRADDR; assign diadi_in = DIADI; assign dibdi_in = DIBDI; assign dipadip_in = DIPADIP; assign dipbdip_in = DIPBDIP; assign wea_in = WEA; assign webwe_in = WEBWE; assign clkardclk_in = CLKARDCLK ^ IS_CLKARDCLK_INVERTED; assign clkbwrclk_in = CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED; assign enarden_in = ENARDEN ^ IS_ENARDEN_INVERTED; assign enbwren_in = ENBWREN ^ IS_ENBWREN_INVERTED; assign rstramarstram_in = RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED; assign rstramb_in = RSTRAMB ^ IS_RSTRAMB_INVERTED; assign rstregarstreg_in = RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED; assign rstregb_in = RSTREGB ^ IS_RSTREGB_INVERTED; `endif initial begin if (!((IS_CLKARDCLK_INVERTED >= 1'b0) && (IS_CLKARDCLK_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_CLKARDCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKARDCLK_INVERTED); attr_err = 1'b1; end if (!((IS_CLKBWRCLK_INVERTED >= 1'b0) && (IS_CLKBWRCLK_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_CLKBWRCLK_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_CLKBWRCLK_INVERTED); attr_err = 1'b1; end if (!((IS_ENARDEN_INVERTED >= 1'b0) && (IS_ENARDEN_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_ENARDEN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENARDEN_INVERTED); attr_err = 1'b1; end if (!((IS_ENBWREN_INVERTED >= 1'b0) && (IS_ENBWREN_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_ENBWREN_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_ENBWREN_INVERTED); attr_err = 1'b1; end if (!((IS_RSTRAMARSTRAM_INVERTED >= 1'b0) && (IS_RSTRAMARSTRAM_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_RSTRAMARSTRAM_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMARSTRAM_INVERTED); attr_err = 1'b1; end if (!((IS_RSTRAMB_INVERTED >= 1'b0) && (IS_RSTRAMB_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_RSTRAMB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTRAMB_INVERTED); attr_err = 1'b1; end if (!((IS_RSTREGARSTREG_INVERTED >= 1'b0) && (IS_RSTREGARSTREG_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_RSTREGARSTREG_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGARSTREG_INVERTED); attr_err = 1'b1; end if (!((IS_RSTREGB_INVERTED >= 1'b0) && (IS_RSTREGB_INVERTED <= 1'b1))) begin $display("Attribute Syntax Error : The attribute IS_RSTREGB_INVERTED on RAMB18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREGB_INVERTED); attr_err = 1'b1; end if (attr_err == 1'b1) #1 $finish; end // initial begin // special handle for sdp width = 36 localparam [35:0] init_sdp = (READ_WIDTH_A == 36) ? {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : {INIT_B, INIT_A}; localparam [35:0] srval_sdp = (READ_WIDTH_A == 36) ? {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : {SRVAL_B, SRVAL_A}; generate case (RAM_MODE) "TDP" : begin : gen_tdp RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_FILE(INIT_FILE), .SRVAL_A(SRVAL_A), .SRVAL_B(SRVAL_B), .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), .READ_WIDTH_A(READ_WIDTH_A), .READ_WIDTH_B(READ_WIDTH_B), .WRITE_WIDTH_A(WRITE_WIDTH_A), .WRITE_WIDTH_B(WRITE_WIDTH_B), .WRITE_MODE_A(WRITE_MODE_A), .WRITE_MODE_B(WRITE_MODE_B), .SETUP_ALL(SETUP_ALL), .SETUP_READ_FIRST(SETUP_READ_FIRST), .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), .SIM_DEVICE(SIM_DEVICE), .DOA_REG(DOA_REG), .DOB_REG(DOB_REG), .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), .BRAM_SIZE(18), .INIT_00(INIT_00), .INIT_01(INIT_01), .INIT_02(INIT_02), .INIT_03(INIT_03), .INIT_04(INIT_04), .INIT_05(INIT_05), .INIT_06(INIT_06), .INIT_07(INIT_07), .INIT_08(INIT_08), .INIT_09(INIT_09), .INIT_0A(INIT_0A), .INIT_0B(INIT_0B), .INIT_0C(INIT_0C), .INIT_0D(INIT_0D), .INIT_0E(INIT_0E), .INIT_0F(INIT_0F), .INIT_10(INIT_10), .INIT_11(INIT_11), .INIT_12(INIT_12), .INIT_13(INIT_13), .INIT_14(INIT_14), .INIT_15(INIT_15), .INIT_16(INIT_16), .INIT_17(INIT_17), .INIT_18(INIT_18), .INIT_19(INIT_19), .INIT_1A(INIT_1A), .INIT_1B(INIT_1B), .INIT_1C(INIT_1C), .INIT_1D(INIT_1D), .INIT_1E(INIT_1E), .INIT_1F(INIT_1F), .INIT_20(INIT_20), .INIT_21(INIT_21), .INIT_22(INIT_22), .INIT_23(INIT_23), .INIT_24(INIT_24), .INIT_25(INIT_25), .INIT_26(INIT_26), .INIT_27(INIT_27), .INIT_28(INIT_28), .INIT_29(INIT_29), .INIT_2A(INIT_2A), .INIT_2B(INIT_2B), .INIT_2C(INIT_2C), .INIT_2D(INIT_2D), .INIT_2E(INIT_2E), .INIT_2F(INIT_2F), .INIT_30(INIT_30), .INIT_31(INIT_31), .INIT_32(INIT_32), .INIT_33(INIT_33), .INIT_34(INIT_34), .INIT_35(INIT_35), .INIT_36(INIT_36), .INIT_37(INIT_37), .INIT_38(INIT_38), .INIT_39(INIT_39), .INIT_3A(INIT_3A), .INIT_3B(INIT_3B), .INIT_3C(INIT_3C), .INIT_3D(INIT_3D), .INIT_3E(INIT_3E), .INIT_3F(INIT_3F), .INITP_00(INITP_00), .INITP_01(INITP_01), .INITP_02(INITP_02), .INITP_03(INITP_03), .INITP_04(INITP_04), .INITP_05(INITP_05), .INITP_06(INITP_06), .INITP_07(INITP_07)) INT_RAMB_TDP (.ADDRA({2'b0,addrardaddr_in}), .ADDRB({2'b0,addrbwraddr_in}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(dangle_out), .CASCADEOUTB(dangle_out), .CLKA(clkardclk_in), .CLKB(clkbwrclk_in), .DBITERR(dangle_out), .DIA({48'b0,diadi_in}), .DIB({48'b0,dibdi_in}), .DIPA({2'b0,dipadip_in}), .DIPB({6'b0,dipbdip_in}), .DOA({dangle_out48,doado_wire}), .DOB({dangle_out16,dobdo_wire}), .DOPA({dangle_out6,dopadop_wire}), .DOPB({dangle_out2,dopbdop_wire}), .ECCPARITY(dangle_out8), .ENA(enarden_in), .ENB(enbwren_in), .GSR(GSR), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(dangle_out9), .REGCEA(regcearegce_in), .REGCEB(regceb_in), .RSTRAMA(rstramarstram_in), .RSTRAMB(rstramb_in), .RSTREGA(rstregarstreg_in), .RSTREGB(rstregb_in), .SBITERR(dangle_out), .WEA({4{wea_in}}), .WEB({2{webwe_in}})); end // case: "TDP" "SDP" : begin : gen_sdp if (WRITE_WIDTH_B == 36) begin : gen_wide RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), .INIT_A({36'b0,init_sdp}), .INIT_B({36'b0,init_sdp}), .INIT_FILE(INIT_FILE), .SRVAL_A({36'b0,{srval_sdp}}), .SRVAL_B({36'b0,{srval_sdp}}), .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), .READ_WIDTH_A(READ_WIDTH_A), .READ_WIDTH_B(READ_WIDTH_A), .WRITE_WIDTH_A(WRITE_WIDTH_B), .WRITE_WIDTH_B(WRITE_WIDTH_B), .WRITE_MODE_A(WRITE_MODE_A), .WRITE_MODE_B(WRITE_MODE_B), .SETUP_ALL(SETUP_ALL), .SETUP_READ_FIRST(SETUP_READ_FIRST), .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), .SIM_DEVICE(SIM_DEVICE), .DOA_REG(DOA_REG), .DOB_REG(DOB_REG), .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), .BRAM_SIZE(18), .INIT_00(INIT_00), .INIT_01(INIT_01), .INIT_02(INIT_02), .INIT_03(INIT_03), .INIT_04(INIT_04), .INIT_05(INIT_05), .INIT_06(INIT_06), .INIT_07(INIT_07), .INIT_08(INIT_08), .INIT_09(INIT_09), .INIT_0A(INIT_0A), .INIT_0B(INIT_0B), .INIT_0C(INIT_0C), .INIT_0D(INIT_0D), .INIT_0E(INIT_0E), .INIT_0F(INIT_0F), .INIT_10(INIT_10), .INIT_11(INIT_11), .INIT_12(INIT_12), .INIT_13(INIT_13), .INIT_14(INIT_14), .INIT_15(INIT_15), .INIT_16(INIT_16), .INIT_17(INIT_17), .INIT_18(INIT_18), .INIT_19(INIT_19), .INIT_1A(INIT_1A), .INIT_1B(INIT_1B), .INIT_1C(INIT_1C), .INIT_1D(INIT_1D), .INIT_1E(INIT_1E), .INIT_1F(INIT_1F), .INIT_20(INIT_20), .INIT_21(INIT_21), .INIT_22(INIT_22), .INIT_23(INIT_23), .INIT_24(INIT_24), .INIT_25(INIT_25), .INIT_26(INIT_26), .INIT_27(INIT_27), .INIT_28(INIT_28), .INIT_29(INIT_29), .INIT_2A(INIT_2A), .INIT_2B(INIT_2B), .INIT_2C(INIT_2C), .INIT_2D(INIT_2D), .INIT_2E(INIT_2E), .INIT_2F(INIT_2F), .INIT_30(INIT_30), .INIT_31(INIT_31), .INIT_32(INIT_32), .INIT_33(INIT_33), .INIT_34(INIT_34), .INIT_35(INIT_35), .INIT_36(INIT_36), .INIT_37(INIT_37), .INIT_38(INIT_38), .INIT_39(INIT_39), .INIT_3A(INIT_3A), .INIT_3B(INIT_3B), .INIT_3C(INIT_3C), .INIT_3D(INIT_3D), .INIT_3E(INIT_3E), .INIT_3F(INIT_3F), .INITP_00(INITP_00), .INITP_01(INITP_01), .INITP_02(INITP_02), .INITP_03(INITP_03), .INITP_04(INITP_04), .INITP_05(INITP_05), .INITP_06(INITP_06), .INITP_07(INITP_07)) INT_RAMB_SDP (.ADDRA({2'b0,addrardaddr_in}), .ADDRB({2'b0,addrbwraddr_in}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(dangle_out), .CASCADEOUTB(dangle_out), .CLKA(clkardclk_in), .CLKB(clkbwrclk_in), .DBITERR(dangle_out), .DIA(64'b0), .DIB({32'b0,dibdi_in,diadi_in}), .DIPA(4'b0), .DIPB({4'b0,dipbdip_in,dipadip_in}), .DOA({dangle_out32,dobdo_wire,doado_wire}), .DOB(dangle_out32), .DOPA({dangle_out4,dopbdop_wire,dopadop_wire}), .DOPB(dangle_out4), .ECCPARITY(dangle_out8), .ENA(enarden_in), .ENB(enbwren_in), .GSR(GSR), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(dangle_out9), .REGCEA(regcearegce_in), .REGCEB(regceb_in), .RSTRAMA(rstramarstram_in), .RSTRAMB(rstramb_in), .RSTREGA(rstregarstreg_in), .RSTREGB(rstregb_in), .SBITERR(dangle_out), .WEA(8'b0), .WEB({2{webwe_in}})); end // if (WRITE_WIDTH_B == 36) else begin : gen_narrow RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), .INIT_A({36'b0,init_sdp}), .INIT_B({36'b0,init_sdp}), .INIT_FILE(INIT_FILE), .SRVAL_A({36'b0,{srval_sdp}}), .SRVAL_B({36'b0,{srval_sdp}}), .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), .READ_WIDTH_A(READ_WIDTH_A), .READ_WIDTH_B(READ_WIDTH_A), .WRITE_WIDTH_A(WRITE_WIDTH_B), .WRITE_WIDTH_B(WRITE_WIDTH_B), .WRITE_MODE_A(WRITE_MODE_A), .WRITE_MODE_B(WRITE_MODE_B), .SETUP_ALL(SETUP_ALL), .SETUP_READ_FIRST(SETUP_READ_FIRST), .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), .SIM_DEVICE(SIM_DEVICE), .DOA_REG(DOA_REG), .DOB_REG(DOB_REG), .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), .BRAM_SIZE(18), .INIT_00(INIT_00), .INIT_01(INIT_01), .INIT_02(INIT_02), .INIT_03(INIT_03), .INIT_04(INIT_04), .INIT_05(INIT_05), .INIT_06(INIT_06), .INIT_07(INIT_07), .INIT_08(INIT_08), .INIT_09(INIT_09), .INIT_0A(INIT_0A), .INIT_0B(INIT_0B), .INIT_0C(INIT_0C), .INIT_0D(INIT_0D), .INIT_0E(INIT_0E), .INIT_0F(INIT_0F), .INIT_10(INIT_10), .INIT_11(INIT_11), .INIT_12(INIT_12), .INIT_13(INIT_13), .INIT_14(INIT_14), .INIT_15(INIT_15), .INIT_16(INIT_16), .INIT_17(INIT_17), .INIT_18(INIT_18), .INIT_19(INIT_19), .INIT_1A(INIT_1A), .INIT_1B(INIT_1B), .INIT_1C(INIT_1C), .INIT_1D(INIT_1D), .INIT_1E(INIT_1E), .INIT_1F(INIT_1F), .INIT_20(INIT_20), .INIT_21(INIT_21), .INIT_22(INIT_22), .INIT_23(INIT_23), .INIT_24(INIT_24), .INIT_25(INIT_25), .INIT_26(INIT_26), .INIT_27(INIT_27), .INIT_28(INIT_28), .INIT_29(INIT_29), .INIT_2A(INIT_2A), .INIT_2B(INIT_2B), .INIT_2C(INIT_2C), .INIT_2D(INIT_2D), .INIT_2E(INIT_2E), .INIT_2F(INIT_2F), .INIT_30(INIT_30), .INIT_31(INIT_31), .INIT_32(INIT_32), .INIT_33(INIT_33), .INIT_34(INIT_34), .INIT_35(INIT_35), .INIT_36(INIT_36), .INIT_37(INIT_37), .INIT_38(INIT_38), .INIT_39(INIT_39), .INIT_3A(INIT_3A), .INIT_3B(INIT_3B), .INIT_3C(INIT_3C), .INIT_3D(INIT_3D), .INIT_3E(INIT_3E), .INIT_3F(INIT_3F), .INITP_00(INITP_00), .INITP_01(INITP_01), .INITP_02(INITP_02), .INITP_03(INITP_03), .INITP_04(INITP_04), .INITP_05(INITP_05), .INITP_06(INITP_06), .INITP_07(INITP_07)) INT_RAMB_SDP (.ADDRA({2'b0,addrardaddr_in}), .ADDRB({2'b0,addrbwraddr_in}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CASCADEOUTA(dangle_out), .CASCADEOUTB(dangle_out), .CLKA(clkardclk_in), .CLKB(clkbwrclk_in), .DBITERR(dangle_out), .DIA(64'b0), .DIB({48'b0,dibdi_in}), .DIPA(4'b0), .DIPB({6'b0,dipbdip_in}), .DOA({dangle_out32,dobdo_wire,doado_wire}), .DOB(dangle_out32), .DOPA({dangle_out4,dopbdop_wire,dopadop_wire}), .DOPB(dangle_out4), .ECCPARITY(dangle_out8), .ENA(enarden_in), .ENB(enbwren_in), .GSR(GSR), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(dangle_out9), .REGCEA(regcearegce_in), .REGCEB(regceb_in), .RSTRAMA(rstramarstram_in), .RSTRAMB(rstramb_in), .RSTREGA(rstregarstreg_in), .RSTREGB(rstregb_in), .SBITERR(dangle_out), .WEA(8'b0), .WEB({2{webwe_in}})); end // else: !if(WRITE_WIDTH_B == 36) end // case: "SDP" endcase // case(RAM_MODE) endgenerate //*** Timing Checks Start here reg [15:0] DOADO_out; reg [15:0] DOBDO_out; reg [1:0] DOPADOP_out; reg [1:0] DOPBDOP_out; assign DOADO = DOADO_out; assign DOBDO = DOBDO_out; assign DOPADOP = DOPADOP_out; assign DOPBDOP = DOPBDOP_out; always @(doado_wire or rstramb_in or GSR) DOADO_out = doado_wire; always @(dobdo_wire or rstramb_in or GSR) DOBDO_out = dobdo_wire; always @(dopadop_wire or rstramb_in or GSR) DOPADOP_out = dopadop_wire; always @(dopbdop_wire or rstramb_in or GSR) DOPBDOP_out = dopbdop_wire; `ifdef XIL_TIMING wire clkardclk_en_n; wire clkardclk_en_p; wire clkbwrclk_en_n; wire clkbwrclk_en_p; assign clkardclk_en_n = IS_CLKARDCLK_INVERTED; assign clkardclk_en_p = ~IS_CLKARDCLK_INVERTED; assign clkbwrclk_en_n = IS_CLKBWRCLK_INVERTED; assign clkbwrclk_en_p = ~IS_CLKBWRCLK_INVERTED; wire enarden_clka_n = enarden_in && clkardclk_en_n; wire enarden_clka_p = enarden_in && clkardclk_en_p; wire enbwren_clkb_n = enbwren_in && clkbwrclk_en_n; wire enbwren_clkb_p = enbwren_in && clkbwrclk_en_p; wire diadi0_enable_n = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_n; wire diadi0_enable_p = (RAM_MODE == "TDP") && enarden_in && wea_in[0] && clkardclk_en_p; wire dibdi0_enable_n = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_n) : (enbwren_in && webwe_in[2] && clkbwrclk_en_n) ; wire dibdi0_enable_p = (RAM_MODE == "TDP") ? (enbwren_in && webwe_in[0] && clkbwrclk_en_p) : (enbwren_in && webwe_in[2] && clkbwrclk_en_p) ; wire sdp_dia0_clkwr_n = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_n; wire sdp_dia0_clkwr_p = (RAM_MODE == "SDP") && enbwren_in && webwe_in[0] && clkbwrclk_en_p; always @(notifier or notifier_a or notifier_addra0 or notifier_addra1 or notifier_addra2 or notifier_addra3 or notifier_addra4 or notifier_addra5 or notifier_addra6 or notifier_addra7 or notifier_addra8 or notifier_addra9 or notifier_addra10 or notifier_addra11 or notifier_addra12 or notifier_addra13) begin doado_out <= 16'hxxxx; dopadop_out <= 2'bxx; end always @(notifier or notifier_b or notifier_addrb0 or notifier_addrb1 or notifier_addrb2 or notifier_addrb3 or notifier_addrb4 or notifier_addrb5 or notifier_addrb6 or notifier_addrb7 or notifier_addrb8 or notifier_addrb9 or notifier_addrb10 or notifier_addrb11 or notifier_addrb12 or notifier_addrb13) begin dobdo_out <= 16'hxxxx; dopbdop_out <= 2'bxx; if (RAM_MODE == "SDP") begin doado_out <= 16'hxxxx; dopadop_out <= 2'bxx; end end always @(notifier_addra0) begin task_warn_msg ("ADDRARDADDR[0]", "CLKARDCLK"); end always @(notifier_addra1) begin task_warn_msg ("ADDRARDADDR[1]", "CLKARDCLK"); end always @(notifier_addra2) begin task_warn_msg ("ADDRARDADDR[2]", "CLKARDCLK"); end always @(notifier_addra3) begin task_warn_msg ("ADDRARDADDR[3]", "CLKARDCLK"); end always @(notifier_addra4) begin task_warn_msg ("ADDRARDADDR[4]", "CLKARDCLK"); end always @(notifier_addra5) begin task_warn_msg ("ADDRARDADDR[5]", "CLKARDCLK"); end always @(notifier_addra6) begin task_warn_msg ("ADDRARDADDR[6]", "CLKARDCLK"); end always @(notifier_addra7) begin task_warn_msg ("ADDRARDADDR[7]", "CLKARDCLK"); end always @(notifier_addra8) begin task_warn_msg ("ADDRARDADDR[8]", "CLKARDCLK"); end always @(notifier_addra9) begin task_warn_msg ("ADDRARDADDR[9]", "CLKARDCLK"); end always @(notifier_addra10) begin task_warn_msg ("ADDRARDADDR[10]", "CLKARDCLK"); end always @(notifier_addra11) begin task_warn_msg ("ADDRARDADDR[11]", "CLKARDCLK"); end always @(notifier_addra12) begin task_warn_msg ("ADDRARDADDR[12]", "CLKARDCLK"); end always @(notifier_addra13) begin task_warn_msg ("ADDRARDADDR[13]", "CLKARDCLK"); end always @(notifier_addrb0) begin task_warn_msg ("ADDRBWRADDR[0]", "CLKBWRCLK"); end always @(notifier_addrb1) begin task_warn_msg ("ADDRBWRADDR[1]", "CLKBWRCLK"); end always @(notifier_addrb2) begin task_warn_msg ("ADDRBWRADDR[2]", "CLKBWRCLK"); end always @(notifier_addrb3) begin task_warn_msg ("ADDRBWRADDR[3]", "CLKBWRCLK"); end always @(notifier_addrb4) begin task_warn_msg ("ADDRBWRADDR[4]", "CLKBWRCLK"); end always @(notifier_addrb5) begin task_warn_msg ("ADDRBWRADDR[5]", "CLKBWRCLK"); end always @(notifier_addrb6) begin task_warn_msg ("ADDRBWRADDR[6]", "CLKBWRCLK"); end always @(notifier_addrb7) begin task_warn_msg ("ADDRBWRADDR[7]", "CLKBWRCLK"); end always @(notifier_addrb8) begin task_warn_msg ("ADDRBWRADDR[8]", "CLKBWRCLK"); end always @(notifier_addrb9) begin task_warn_msg ("ADDRBWRADDR[9]", "CLKBWRCLK"); end always @(notifier_addrb10) begin task_warn_msg ("ADDRBWRADDR[10]", "CLKBWRCLK"); end always @(notifier_addrb11) begin task_warn_msg ("ADDRBWRADDR[11]", "CLKBWRCLK"); end always @(notifier_addrb12) begin task_warn_msg ("ADDRBWRADDR[12]", "CLKBWRCLK"); end always @(notifier_addrb13) begin task_warn_msg ("ADDRBWRADDR[13]", "CLKBWRCLK"); end task task_warn_msg; input [8*15:1] addr_str; input [8*9:1] clk_str; begin $display("Error: Setup/Hold Violation on %s with respect to %s when memory has been enabled. The memory contents at %s of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.", addr_str, clk_str, addr_str); end endtask // task_warn_msg `endif // `ifdef XIL_TIMING wire ram_mode_wire = (RAM_MODE == "TDP") ? 1 : 0; specify (CLKARDCLK *> DOADO) = (100:100:100, 100:100:100); (CLKARDCLK *> DOPADOP) = (100:100:100, 100:100:100); if (ram_mode_wire == 0) (CLKARDCLK *> DOBDO) = (100:100:100, 100:100:100); if (ram_mode_wire == 0) (CLKARDCLK *> DOPBDOP) = (100:100:100, 100:100:100); if (ram_mode_wire == 1) (CLKBWRCLK *> DOBDO) = (100:100:100, 100:100:100); if (ram_mode_wire == 1) (CLKBWRCLK *> DOPBDOP) = (100:100:100, 100:100:100); `ifdef XIL_TIMING $setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay); $setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, ADDRARDADDR_delay); $setuphold (posedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay); $setuphold (posedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIADI_delay); $setuphold (posedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay); $setuphold (posedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_p, diadi0_enable_p, CLKARDCLK_delay, DIPADIP_delay); $setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); $setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, ENARDEN_delay); $setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); $setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, RSTRAMARSTRAM_delay); $setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); $setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, RSTREGARSTREG_delay); $setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); $setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_p, clkardclk_en_p, CLKARDCLK_delay, REGCEAREGCE_delay); $setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay); $setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_p, enarden_clka_p, CLKARDCLK_delay, WEA_delay); $setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); $setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, ADDRBWRADDR_delay); $setuphold (posedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay); $setuphold (posedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIADI_delay); $setuphold (posedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay); $setuphold (posedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_p, sdp_dia0_clkwr_p, CLKBWRCLK_delay, DIPADIP_delay); $setuphold (posedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay); $setuphold (posedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIBDI_delay); $setuphold (posedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay); $setuphold (posedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_p, dibdi0_enable_p, CLKBWRCLK_delay, DIPBDIP_delay); $setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); $setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, ENBWREN_delay); $setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); $setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, REGCEB_delay); $setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay); $setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, RSTRAMB_delay); $setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); $setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_p, clkbwrclk_en_p, CLKBWRCLK_delay, RSTREGB_delay); $setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay); $setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_p, enbwren_clkb_p, CLKBWRCLK_delay, WEBWE_delay); $setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay); $setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier_addra0, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, ADDRARDADDR_delay); $setuphold (negedge CLKARDCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay); $setuphold (negedge CLKARDCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIADI_delay); $setuphold (negedge CLKARDCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay); $setuphold (negedge CLKARDCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_a, diadi0_enable_n, diadi0_enable_n, CLKARDCLK_delay, DIPADIP_delay); $setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); $setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, ENARDEN_delay); $setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); $setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, RSTRAMARSTRAM_delay); $setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); $setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, RSTREGARSTREG_delay); $setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); $setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier_a, clkardclk_en_n, clkardclk_en_n, CLKARDCLK_delay, REGCEAREGCE_delay); $setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay); $setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier_a, enarden_clka_n, enarden_clka_n, CLKARDCLK_delay, WEA_delay); $setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); $setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier_addrb0, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, ADDRBWRADDR_delay); $setuphold (negedge CLKBWRCLK, posedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay); $setuphold (negedge CLKBWRCLK, negedge DIADI, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIADI_delay); $setuphold (negedge CLKBWRCLK, posedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay); $setuphold (negedge CLKBWRCLK, negedge DIPADIP, 0:0:0, 0:0:0, notifier_b, sdp_dia0_clkwr_n, sdp_dia0_clkwr_n, CLKBWRCLK_delay, DIPADIP_delay); $setuphold (negedge CLKBWRCLK, posedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay); $setuphold (negedge CLKBWRCLK, negedge DIBDI, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIBDI_delay); $setuphold (negedge CLKBWRCLK, posedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay); $setuphold (negedge CLKBWRCLK, negedge DIPBDIP, 0:0:0, 0:0:0, notifier_b, dibdi0_enable_n, dibdi0_enable_n, CLKBWRCLK_delay, DIPBDIP_delay); $setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); $setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, ENBWREN_delay); $setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); $setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, REGCEB_delay); $setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay); $setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, RSTRAMB_delay); $setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); $setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier_b, clkbwrclk_en_n, clkbwrclk_en_n, CLKBWRCLK_delay, RSTREGB_delay); $setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay); $setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier_b, enbwren_clkb_n, enbwren_clkb_n, CLKBWRCLK_delay, WEBWE_delay); $period (negedge CLKARDCLK, 0:0:0, notifier_a); $period (negedge CLKBWRCLK, 0:0:0, notifier_b); $period (posedge CLKARDCLK, 0:0:0, notifier_a); $period (posedge CLKBWRCLK, 0:0:0, notifier_b); $width (posedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a); $width (negedge CLKARDCLK &&& ENARDEN, 0:0:0, 0, notifier_a); $width (posedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b); $width (negedge CLKBWRCLK &&& ENBWREN, 0:0:0, 0, notifier_b); `endif // `ifdef XIL_TIMING specparam PATHPULSE$ = 0; endspecify endmodule // RAMB18E1 // WARNING !!!: The following model is not an user primitive. // Please do not modify any part of it. RAMB18E1 may not work properly if do so. // `timescale 1 ps/1 ps module RB18_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR, ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB); output CASCADEOUTA; output CASCADEOUTB; output DBITERR; output SBITERR; output [8:0] RDADDRECC; output reg [63:0] DOA; output reg [31:0] DOB; output reg [7:0] DOPA; output reg [3:0] DOPB; output [7:0] ECCPARITY; input ENA, CLKA, CASCADEINA, REGCEA; input ENB, CLKB, CASCADEINB, REGCEB; input GSR; input RSTRAMA, RSTRAMB; input RSTREGA, RSTREGB; input INJECTDBITERR, INJECTSBITERR; input [15:0] ADDRA; input [15:0] ADDRB; input [63:0] DIA; input [63:0] DIB; input [3:0] DIPA; input [7:0] DIPB; input [7:0] WEA; input [7:0] WEB; parameter DOA_REG = 0; parameter DOB_REG = 0; parameter EN_ECC_READ = "FALSE"; parameter EN_ECC_WRITE = "FALSE"; parameter [71:0] INIT_A = 72'h0; parameter [71:0] INIT_B = 72'h0; parameter RAM_EXTENSION_A = "NONE"; parameter RAM_EXTENSION_B = "NONE"; parameter RAM_MODE = "TDP"; parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; parameter READ_WIDTH_A = 0; parameter READ_WIDTH_B = 0; parameter RSTREG_PRIORITY_A = "RSTREG"; parameter RSTREG_PRIORITY_B = "RSTREG"; parameter SETUP_ALL = 1000; parameter SETUP_READ_FIRST = 3000; parameter SIM_COLLISION_CHECK = "ALL"; parameter SIM_DEVICE = "7SERIES"; parameter [71:0] SRVAL_A = 72'h0; parameter [71:0] SRVAL_B = 72'h0; parameter WRITE_MODE_A = "WRITE_FIRST"; parameter WRITE_MODE_B = "WRITE_FIRST"; parameter WRITE_WIDTH_A = 0; parameter WRITE_WIDTH_B = 0; parameter INIT_FILE = "NONE"; parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; // xilinx_internal_parameter on // WARNING !!!: This model may not work properly if the following parameters are changed. parameter BRAM_SIZE = 36; // xilinx_internal_parameter off integer count, countp, init_mult, initp_mult, large_width; integer count1, countp1, i, i1, j, j1, i_p, i_mem, init_offset, initp_offset; integer viol_time = 0; integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int; integer ram_mode_int, en_ecc_write_int, en_ecc_read_int; integer chk_ox_same_clk = 0, chk_ox_msg = 0, chk_col_same_clk = 0; reg addra_in_15_reg_bram, addrb_in_15_reg_bram; reg addra_in_15_reg, addrb_in_15_reg; reg addra_in_15_reg1, addrb_in_15_reg1; reg junk1; reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b; reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0; reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0; reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0; reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0; reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0; reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0; reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0; reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0; reg [7:0] eccparity_out = 8'b0; reg [7:0] dopr_ecc, syndrome = 8'b0; reg [7:0] dipb_in_ecc; reg [71:0] ecc_bit_position; reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected; reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx; reg dbiterr_out = 0, sbiterr_out = 0; reg dbiterr_outreg = 0, sbiterr_outreg = 0; reg dbiterr_out_out = 0, sbiterr_out_out = 0; reg [7:0] wea_reg; reg enb_reg; reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg; reg outp_a = 1'b0, outp_b = 1'b0, junkp; reg rising_clka = 1'b0, rising_clkb = 1'b0; reg [15:0] addra_reg, addrb_reg; reg [63:0] dia_reg, dib_reg; reg [3:0] dipa_reg; reg [7:0] dipb_reg; reg [1:0] viol_type = 2'b00; reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0; reg [8:0] rdaddrecc_out_out = 9'b0; reg finish_error = 0; time time_port_a, time_port_b; wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in; wire [7:0] wea_in; wire [7:0] web_in; wire cascadeina_in, cascadeinb_in; wire injectdbiterr_in, injectsbiterr_in; wire rstrega_in, rstregb_in; reg [15:0] ox_addra_reconstruct, ox_addrb_reconstruct; reg [15:0] ox_addra_reconstruct_reg, ox_addrb_reconstruct_reg; wire temp_wire; // trigger NCsim at initial time assign temp_wire = 1; time time_clka_period, time_clkb_period, time_period; reg time_skew_a_flag = 0; reg time_skew_b_flag = 0; assign CASCADEOUTA = DOA[0]; assign CASCADEOUTB = DOB[0]; assign SBITERR = sbiterr_out_out; assign DBITERR = dbiterr_out_out; assign ECCPARITY = eccparity_out; assign RDADDRECC = rdaddrecc_out_out; assign injectdbiterr_in = INJECTDBITERR; assign injectsbiterr_in = INJECTSBITERR; assign rstrega_in = RSTREGA; assign rstregb_in = RSTREGB; localparam sync_clk_skew = (SIM_DEVICE == "7SERIES") ? 50 : 100; // Determine memory size localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A && WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A : (WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B : (READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B && READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : (READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B && READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 72; localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 : (WRITE_WIDTH_A == 72) ? 64 : 64; localparam wa_width_0 = 0; localparam wa_width_1 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 : (WRITE_WIDTH_A == 72) ? 8 : 0; localparam wa_width_2 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 16 : (WRITE_WIDTH_A == 72) ? 16 : 0; localparam wa_width_3 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 24 : (WRITE_WIDTH_A == 72) ? 24 : 0; localparam wa_width_4 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : (WRITE_WIDTH_A == 72) ? 32 : 0; localparam wa_width_5 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : (WRITE_WIDTH_A == 72) ? 40 : 0; localparam wa_width_6 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : (WRITE_WIDTH_A == 72) ? 48 : 0; localparam wa_width_7 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 0 : (WRITE_WIDTH_A == 4) ? 0 : (WRITE_WIDTH_A == 9) ? 0 : (WRITE_WIDTH_A == 18) ? 0 : (WRITE_WIDTH_A == 36) ? 0 : (WRITE_WIDTH_A == 72) ? 56 : 0; localparam wa_width_n = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 : (WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 8 : (WRITE_WIDTH_A == 36) ? 8 : (WRITE_WIDTH_A == 72) ? 8 : 8; localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 : (WRITE_WIDTH_B == 72) ? 64 : 64; localparam wb_width_0 = 0; localparam wb_width_1 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 : (WRITE_WIDTH_B == 72) ? 8 : 0; localparam wb_width_2 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 16 : (WRITE_WIDTH_B == 72) ? 16 : 0; localparam wb_width_3 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 24 : (WRITE_WIDTH_B == 72) ? 24 : 0; localparam wb_width_4 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : (WRITE_WIDTH_B == 72) ? 32 : 0; localparam wb_width_5 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : (WRITE_WIDTH_B == 72) ? 40 : 0; localparam wb_width_6 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : (WRITE_WIDTH_B == 72) ? 48 : 0; localparam wb_width_7 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 0 : (WRITE_WIDTH_B == 4) ? 0 : (WRITE_WIDTH_B == 9) ? 0 : (WRITE_WIDTH_B == 18) ? 0 : (WRITE_WIDTH_B == 36) ? 0 : (WRITE_WIDTH_B == 72) ? 56 : 0; localparam wb_width_n = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 : (WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 8 : (WRITE_WIDTH_B == 36) ? 8 : (WRITE_WIDTH_B == 72) ? 8 : 8; localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : (WRITE_WIDTH_A == 36) ? 4 : (WRITE_WIDTH_A == 72) ? 8 : 8; localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : (WRITE_WIDTH_B == 36) ? 4 : (WRITE_WIDTH_B == 72) ? 8 : 8; localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : (READ_WIDTH_A == 72) ? 64 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : (READ_WIDTH_B == 72) ? 64 : 64) : 64; localparam ra_width_n = (ra_width == 1) ? 1 : (ra_width == 2) ? 2 : (ra_width == 4) ? 4 : (ra_width == 8) ? 8 : (ra_width == 16) ? 8 : (ra_width == 32) ? 8 : (ra_width == 64) ? 8 : 8; localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : (READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : (READ_WIDTH_B == 72) ? 32 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : (READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : (READ_WIDTH_A == 72) ? 32 : 32) : 32; localparam rb_width_0 = 0; localparam rb_width_1 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 8 : (rb_width == 32) ? 8 : (rb_width == 64) ? 8 : 8; localparam rb_width_2 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 0 : (rb_width == 32) ? 16 : (rb_width == 64) ? 16 : 16; localparam rb_width_3 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 0 : (rb_width == 32) ? 24 : (rb_width == 64) ? 24 : 24; localparam rb_width_4 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : (rb_width == 64) ? 32 : 32; localparam rb_width_5 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : (rb_width == 64) ? 40 : 40; localparam rb_width_6 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : (rb_width == 64) ? 48 : 48; localparam rb_width_7 = (rb_width == 1) ? 0 : (rb_width == 2) ? 0 : (rb_width == 4) ? 0 : (rb_width == 8) ? 0 : (rb_width == 16) ? 0 : (rb_width == 32) ? 0 : (rb_width == 64) ? 56 : 56; localparam rb_width_n = (rb_width == 1) ? 1 : (rb_width == 2) ? 2 : (rb_width == 4) ? 4 : (rb_width == 8) ? 8 : (rb_width == 16) ? 8 : (rb_width == 32) ? 8 : (rb_width == 64) ? 8 : 8; localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : (READ_WIDTH_A == 36) ? 4 : (READ_WIDTH_A == 72) ? 8 : 1; localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : (READ_WIDTH_B == 36) ? 4 : (READ_WIDTH_B == 72) ? 4 : 1; localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : (widest_width == 72) ? 6 : 0; always @(*) begin if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin if (BRAM_SIZE == 36) ox_addra_reconstruct[15:0] = {1'b0,ADDRA[14:8],8'b0}; else if (BRAM_SIZE == 18) ox_addra_reconstruct[15:0] = {2'b0,ADDRA[13:7],7'b0}; else ox_addra_reconstruct[15:0] = ADDRA; end else ox_addra_reconstruct[15:0] = ADDRA; end always @(*) begin if (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") begin if (BRAM_SIZE == 36) ox_addrb_reconstruct[15:0] = {1'b0,ADDRB[14:8],8'b0}; else if (BRAM_SIZE == 18) ox_addrb_reconstruct[15:0] = {2'b0,ADDRB[13:7],7'b0}; else ox_addrb_reconstruct[15:0] = ADDRB; end else ox_addrb_reconstruct[15:0] = ADDRB; end localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : (widest_width == 72) ? 64 : 64; localparam width_0 = 0; localparam width_1 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 8 : (widest_width == 36) ? 8 : (widest_width == 72) ? 8 : 0; localparam width_2 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 0 : (widest_width == 36) ? 16 : (widest_width == 72) ? 16 : 0; localparam width_3 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 0 : (widest_width == 36) ? 24 : (widest_width == 72) ? 24 : 0; localparam width_4 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : (widest_width == 72) ? 32 : 0; localparam width_5 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : (widest_width == 72) ? 40 : 0; localparam width_6 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : (widest_width == 72) ? 48 : 0; localparam width_7 = (widest_width == 1) ? 0 : (widest_width == 2) ? 0 : (widest_width == 4) ? 0 : (widest_width == 9) ? 0 : (widest_width == 18) ? 0 : (widest_width == 36) ? 0 : (widest_width == 72) ? 56 : 0; localparam width_n = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : (widest_width == 9) ? 8 : (widest_width == 18) ? 8 : (widest_width == 36) ? 8 : (widest_width == 72) ? 8 : 8; localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : (widest_width == 72) ? 8 : 1; localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : (READ_WIDTH_A == 72) ? 6 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : (READ_WIDTH_B == 72) ? 6 : 10) : 10; localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : (READ_WIDTH_B == 72) ? 6 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : (READ_WIDTH_A == 72) ? 6 : 10) : 10; localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 : (WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 : (WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 : (WRITE_WIDTH_A == 72) ? 6 : 10; localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 : (WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 : (WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 : (WRITE_WIDTH_B == 72) ? 6 : 10; localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10) : 10; localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10) : 10; localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10) : 10; localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10) : 10; localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 : (READ_WIDTH_A == 0) ? ((READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10) : 10; localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10) : 10; localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10) : 10; localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 : (READ_WIDTH_B == 0) ? ((READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10) : 10; localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768; localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384; localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192; localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096; localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048; localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024; localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512; localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 : (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : (widest_width == 72) ? mem_size72 : 32768; localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : (widest_width == 72) ? mem_size72 : 4096; reg [width+widthp-1:0] tmp_mem [0 : mem_depth-1]; reg [width-1:0] mem [mem_depth-1:0]; reg [widthp-1:0] memp [memp_depth-1:0]; integer index = 0; /******************************************** task and function **************************************/ task task_ram; input ram_we; input [7:0] ram_di; input ram_dip; inout [7:0] mem_task; inout memp_task; begin if (ram_we == 1'b1) begin mem_task = ram_di; if (width >= 8) memp_task = ram_dip; end end endtask // task_ram task task_ram_col; input ram_col_we_o; input ram_col_we; input [7:0] ram_col_di; input ram_col_dip; inout [7:0] ram_col_mem_task; inout ram_col_memp_task; integer ram_col_i; begin if (ram_col_we == 1'b1) begin for (ram_col_i = 0; ram_col_i < 8; ram_col_i = ram_col_i + 1) if (ram_col_mem_task[ram_col_i] !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1)) ram_col_mem_task[ram_col_i] = ram_col_di[ram_col_i]; if (width >= 8 && (ram_col_memp_task !== 1'bx || !(ram_col_we === ram_col_we_o && ram_col_we === 1'b1))) ram_col_memp_task = ram_col_dip; end end endtask // task_ram_col task task_ram_ox; input ram_ox_we_o; input ram_ox_we; input [7:0] ram_ox_di; input ram_ox_dip; inout [7:0] ram_ox_mem_task; inout ram_ox_memp_task; integer ram_ox_i; begin if (ram_ox_we == 1'b1) begin for (ram_ox_i = 0; ram_ox_i < 8; ram_ox_i = ram_ox_i + 1) ram_ox_mem_task[ram_ox_i] = ram_ox_di[ram_ox_i]; if (width >= 8) ram_ox_memp_task = ram_ox_dip; end end endtask // task_ram_ox task task_x_buf; input [1:0] wr_rd_mode; input integer do_uindex; input integer do_lindex; input integer dop_index; input [63:0] do_ltmp; inout [63:0] x_buf_do_tmp; input [7:0] dop_ltmp; inout [7:0] x_buf_dop_tmp; integer i; begin if (wr_rd_mode == 2'b01) begin for (i = do_lindex; i <= do_uindex; i = i + 1) begin if (do_ltmp[i] === 1'bx) x_buf_do_tmp[i] = 1'bx; end if (dop_ltmp[dop_index] === 1'bx) x_buf_dop_tmp[dop_index] = 1'bx; end // if (wr_rd_mode == 2'b01) else begin x_buf_do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; x_buf_dop_tmp[dop_index] = dop_ltmp[dop_index]; end // else: !if(wr_rd_mode == 2'b01) end endtask // task_x_buf task task_col_wr_ram_a; input [1:0] col_wr_ram_a_seq; input [7:0] col_wr_ram_a_web_tmp; input [7:0] col_wr_ram_a_wea_tmp; input [63:0] col_wr_ram_a_dia_tmp; input [7:0] col_wr_ram_a_dipa_tmp; input [15:0] col_wr_ram_a_addrb_tmp; input [15:0] col_wr_ram_a_addra_tmp; begin case (wa_width) 1, 2, 4 : begin if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); else task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[col_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(col_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); end // if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) end // case: 1, 2, 4 8 : if (width >= 8) begin if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:3]], memp[col_wr_ram_a_addra_tmp[14:3]]); else task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width], memp[col_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(col_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); end // if (wa_width <= wb_width) end // case: 8 16 : if (width >= 16) begin if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((col_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); end // if (wa_width <= wb_width) end // case: 16 32 : if (width >= 32) begin if (!(col_wr_ram_a_wea_tmp[0] === 1'b1 && col_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || col_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]); else if (wa_width < width) begin task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index)+:1]); end if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); else if (wa_width < width) task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); else if (wa_width < width) task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); else if (wa_width < width) task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); end // if (wa_width <= wb_width) end // case: 32 64 : if (width >= 64) begin if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][width_0 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[0], col_wr_ram_a_wea_tmp[0], col_wr_ram_a_dia_tmp[7:0], col_wr_ram_a_dipa_tmp[0], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[0], col_wr_ram_a_web_tmp[0], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][width_1 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[1], col_wr_ram_a_wea_tmp[1], col_wr_ram_a_dia_tmp[15:8], col_wr_ram_a_dipa_tmp[1], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[1], col_wr_ram_a_web_tmp[1], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][width_2 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[2], col_wr_ram_a_wea_tmp[2], col_wr_ram_a_dia_tmp[23:16], col_wr_ram_a_dipa_tmp[2], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[2], col_wr_ram_a_web_tmp[2], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][width_3 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[3], col_wr_ram_a_wea_tmp[3], col_wr_ram_a_dia_tmp[31:24], col_wr_ram_a_dipa_tmp[3], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[3], col_wr_ram_a_web_tmp[3], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][width_4 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[4], col_wr_ram_a_wea_tmp[4], col_wr_ram_a_dia_tmp[39:32], col_wr_ram_a_dipa_tmp[4], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[4], col_wr_ram_a_web_tmp[4], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][width_5 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[5], col_wr_ram_a_wea_tmp[5], col_wr_ram_a_dia_tmp[47:40], col_wr_ram_a_dipa_tmp[5], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[5], col_wr_ram_a_web_tmp[5], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][width_6 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[6], col_wr_ram_a_wea_tmp[6], col_wr_ram_a_dia_tmp[55:48], col_wr_ram_a_dipa_tmp[6], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[6], col_wr_ram_a_web_tmp[6], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][width_7 +: width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); else task_ram_col (col_wr_ram_a_web_tmp[7], col_wr_ram_a_wea_tmp[7], col_wr_ram_a_dia_tmp[63:56], col_wr_ram_a_dipa_tmp[7], mem[col_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[col_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); if (col_wr_ram_a_seq == 2'b00) chk_for_col_msg (col_wr_ram_a_wea_tmp[7], col_wr_ram_a_web_tmp[7], col_wr_ram_a_addra_tmp, col_wr_ram_a_addrb_tmp); end // case: 64 endcase // case(wa_width) end endtask // task_col_wr_ram_a task task_ox_wr_ram_a; input [1:0] ox_wr_ram_a_seq; input [7:0] ox_wr_ram_a_web_tmp; input [7:0] ox_wr_ram_a_wea_tmp; input [63:0] ox_wr_ram_a_dia_tmp; input [7:0] ox_wr_ram_a_dipa_tmp; input [15:0] ox_wr_ram_a_addrb_tmp; input [15:0] ox_wr_ram_a_addra_tmp; begin case (wa_width) 1, 2, 4 : begin if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); else task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[wa_width-1:0], 1'b0, mem[ox_wr_ram_a_addra_tmp[14:addra_bit_124+1]][(ox_wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); end // if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) end // case: 1, 2, 4 8 : if (width >= 8) begin if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:3]], memp[ox_wr_ram_a_addra_tmp[14:3]]); else task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 8) +: 8], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_8+1]][(ox_wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); end // if (wa_width <= wb_width) end // case: 8 16 : if (width >= 16) begin if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin if (wa_width >= width) task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index)+:1]); else task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][(ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); if (wa_width >= width) task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); else task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 16) + wa_width_1) +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:addra_bit_16+1]][((ox_wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); end // if (wa_width <= wb_width) end // case: 16 32 : if ( width >= 32) begin if (!(ox_wr_ram_a_wea_tmp[0] === 1'b1 && ox_wr_ram_a_web_tmp[0] === 1'b1 && wa_width > wb_width) || ox_wr_ram_a_seq == 2'b10) begin task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); end // if (wa_width <= wb_width) end // case: 32 64 : if (width >= 64) begin task_ram_ox (ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_dia_tmp[7:0], ox_wr_ram_a_dipa_tmp[0], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_0 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[0], ox_wr_ram_a_web_tmp[0], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_dia_tmp[15:8], ox_wr_ram_a_dipa_tmp[1], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_1 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+1)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[1], ox_wr_ram_a_web_tmp[1], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_dia_tmp[23:16], ox_wr_ram_a_dipa_tmp[2], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_2 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+2)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[2], ox_wr_ram_a_web_tmp[2], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_dia_tmp[31:24], ox_wr_ram_a_dipa_tmp[3], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_3 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+3)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[3], ox_wr_ram_a_web_tmp[3], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_dia_tmp[39:32], ox_wr_ram_a_dipa_tmp[4], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_4 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+4)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[4], ox_wr_ram_a_web_tmp[4], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_dia_tmp[47:40], ox_wr_ram_a_dipa_tmp[5], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_5 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+5)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[5], ox_wr_ram_a_web_tmp[5], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_dia_tmp[55:48], ox_wr_ram_a_dipa_tmp[6], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_6 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+6)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[6], ox_wr_ram_a_web_tmp[6], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); task_ram_ox (ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_dia_tmp[63:56], ox_wr_ram_a_dipa_tmp[7], mem[ox_wr_ram_a_addra_tmp[14:6]][wa_width_7 +: wa_width_n], memp[ox_wr_ram_a_addra_tmp[14:6]][(index+7)+:1]); if (ox_wr_ram_a_seq == 2'b00) chk_for_col_msg (ox_wr_ram_a_wea_tmp[7], ox_wr_ram_a_web_tmp[7], ox_wr_ram_a_addra_tmp, ox_wr_ram_a_addrb_tmp); end // case: 64 endcase // case(wa_width) end endtask // task_ox_wr_ram_a task task_col_wr_ram_b; input [1:0] col_wr_ram_b_seq; input [7:0] col_wr_ram_b_wea_tmp; input [7:0] col_wr_ram_b_web_tmp; input [63:0] col_wr_ram_b_dib_tmp; input [7:0] col_wr_ram_b_dipb_tmp; input [15:0] col_wr_ram_b_addra_tmp; input [15:0] col_wr_ram_b_addrb_tmp; begin case (wb_width) 1, 2, 4 : begin if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); else task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); end // if (wb_width <= wa_width) end // case: 1, 2, 4 8 : if (width >= 8) begin if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:3]], memp[col_wr_ram_b_addrb_tmp[14:3]]); else task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); end // if (wb_width <= wa_width) end // case: 8 16 : if (width >= 16) begin if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index)+:1]); else task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); else task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_n) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) end // case: 16 32 : if (width >= 32) begin if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index)+:1]); else task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); else task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); else task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[col_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); else task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((col_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); end // if (!(col_wr_ram_b_wea_tmp[0] === 1'b1 && col_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || col_wr_ram_b_seq == 2'b10) end // case: 32 64 : if (width >= 64) begin task_ram_col (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_dib_tmp[7:0], col_wr_ram_b_dipb_tmp[0], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[0], col_wr_ram_b_web_tmp[0], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_dib_tmp[15:8], col_wr_ram_b_dipb_tmp[1], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[1], col_wr_ram_b_web_tmp[1], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_dib_tmp[23:16], col_wr_ram_b_dipb_tmp[2], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[2], col_wr_ram_b_web_tmp[2], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_dib_tmp[31:24], col_wr_ram_b_dipb_tmp[3], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[3], col_wr_ram_b_web_tmp[3], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_dib_tmp[39:32], col_wr_ram_b_dipb_tmp[4], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[4], col_wr_ram_b_web_tmp[4], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_dib_tmp[47:40], col_wr_ram_b_dipb_tmp[5], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[5], col_wr_ram_b_web_tmp[5], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_dib_tmp[55:48], col_wr_ram_b_dipb_tmp[6], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[6], col_wr_ram_b_web_tmp[6], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); task_ram_col (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_dib_tmp[63:56], col_wr_ram_b_dipb_tmp[7], mem[col_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[col_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); if (col_wr_ram_b_seq == 2'b00) chk_for_col_msg (col_wr_ram_b_wea_tmp[7], col_wr_ram_b_web_tmp[7], col_wr_ram_b_addra_tmp, col_wr_ram_b_addrb_tmp); end // case: 64 endcase // case(wb_width) end endtask // task_col_wr_ram_b task task_ox_wr_ram_b; input [1:0] ox_wr_ram_b_seq; input [7:0] ox_wr_ram_b_wea_tmp; input [7:0] ox_wr_ram_b_web_tmp; input [63:0] ox_wr_ram_b_dib_tmp; input [7:0] ox_wr_ram_b_dipb_tmp; input [15:0] ox_wr_ram_b_addra_tmp; input [15:0] ox_wr_ram_b_addrb_tmp; begin case (wb_width) 1, 2, 4 : begin if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); else task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[wb_width-1:0], 1'b0, mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); end // if (wb_width <= wa_width) end // case: 1, 2, 4 8 : if (width >= 8) begin if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:3]], memp[ox_wr_ram_b_addrb_tmp[14:3]]); else task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); end // if (wb_width <= wa_width) end // case: 8 16 : if (width >= 16) begin if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index)+:1]); else task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); else task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) end // case: 16 32 : if (width >= 32) begin if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) begin if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index)+:1]); else task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); else task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); else task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); if (wb_width >= width) task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[ox_wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); else task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((ox_wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); end // if (!(ox_wr_ram_b_wea_tmp[0] === 1'b1 && ox_wr_ram_b_web_tmp[0] === 1'b1 && wb_width > wa_width) || ox_wr_ram_b_seq == 2'b10) end // case: 32 64 : if (width >= 64) begin task_ram_ox (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_dib_tmp[7:0], ox_wr_ram_b_dipb_tmp[0], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[0], ox_wr_ram_b_web_tmp[0], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_dib_tmp[15:8], ox_wr_ram_b_dipb_tmp[1], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[1], ox_wr_ram_b_web_tmp[1], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_dib_tmp[23:16], ox_wr_ram_b_dipb_tmp[2], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[2], ox_wr_ram_b_web_tmp[2], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_dib_tmp[31:24], ox_wr_ram_b_dipb_tmp[3], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[3], ox_wr_ram_b_web_tmp[3], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_dib_tmp[39:32], ox_wr_ram_b_dipb_tmp[4], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[4], ox_wr_ram_b_web_tmp[4], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_dib_tmp[47:40], ox_wr_ram_b_dipb_tmp[5], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[5], ox_wr_ram_b_web_tmp[5], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_dib_tmp[55:48], ox_wr_ram_b_dipb_tmp[6], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[6], ox_wr_ram_b_web_tmp[6], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); task_ram_ox (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_dib_tmp[63:56], ox_wr_ram_b_dipb_tmp[7], mem[ox_wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[ox_wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); if (ox_wr_ram_b_seq == 2'b00) chk_for_col_msg (ox_wr_ram_b_wea_tmp[7], ox_wr_ram_b_web_tmp[7], ox_wr_ram_b_addra_tmp, ox_wr_ram_b_addrb_tmp); end // case: 64 endcase // case(wb_width) end endtask // task_ox_wr_ram_b task task_wr_ram_a; input [7:0] wr_ram_a_wea_tmp; input [63:0] dia_tmp; input [7:0] dipa_tmp; input [15:0] wr_ram_a_addra_tmp; begin case (wa_width) 1, 2, 4 : begin if (wa_width >= width) task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_lbit_124]], junk1); else task_ram (wr_ram_a_wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[wr_ram_a_addra_tmp[14:addra_bit_124+1]][(wr_ram_a_addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width_n], junk1); end 8 : if (width >= 8) begin if (wa_width >= width) task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:3]], memp[wr_ram_a_addra_tmp[14:3]]); else task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_8+1]][(wr_ram_a_addra_tmp[addra_bit_8:3] * 1) +: 1]); end 16 : if (width >= 16) begin if (wa_width >= width) begin task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:4]][width_0 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index)+:1]); task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:4]][width_1 +: width_n], memp[wr_ram_a_addra_tmp[14:4]][(index+1)+:1]); end else begin task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][(wr_ram_a_addra_tmp[addra_bit_16:4] * 2) +: 1]); task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * wa_width) + wa_width_1) +: wa_width_n], memp[wr_ram_a_addra_tmp[14:addra_bit_16+1]][((wr_ram_a_addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); end // else: !if(wa_width >= wb_width) end // case: 16 32 : if (width >= 32) begin task_ram (wr_ram_a_wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[wr_ram_a_addra_tmp[14:5]][wa_width_0 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index)+:1]); task_ram (wr_ram_a_wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[wr_ram_a_addra_tmp[14:5]][wa_width_1 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+1)+:1]); task_ram (wr_ram_a_wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[wr_ram_a_addra_tmp[14:5]][wa_width_2 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+2)+:1]); task_ram (wr_ram_a_wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[wr_ram_a_addra_tmp[14:5]][wa_width_3 +: wa_width_n], memp[wr_ram_a_addra_tmp[14:5]][(index+3)+:1]); end // case: 32 endcase // case(wa_width) end endtask // task_wr_ram_a task task_wr_ram_b; input [7:0] wr_ram_b_web_tmp; input [63:0] dib_tmp; input [7:0] dipb_tmp; input [15:0] wr_ram_b_addrb_tmp; begin case (wb_width) 1, 2, 4 : begin if (wb_width >= width) task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_lbit_124]], junk1); else task_ram (wr_ram_b_web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[wr_ram_b_addrb_tmp[14:addrb_bit_124+1]][(wr_ram_b_addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width_n], junk1); end 8 : if (width >= 8) begin if (wb_width >= width) task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:3]], memp[wr_ram_b_addrb_tmp[14:3]]); else task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_8+1]][(wr_ram_b_addrb_tmp[addrb_bit_8:3] * 1) +: 1]); end 16 : if (width >= 16) begin if (wb_width >= width) begin task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:4]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index)+:1]); task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:4]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:4]][(index+1)+:1]); end else begin task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][(wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) +: 1]); task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_16+1]][((wr_ram_b_addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); end end // case: 16 32 : if (width >= 32) begin if (wb_width >= width) begin task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:5]][width_0 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index)+:1]); task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:5]][width_1 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+1)+:1]); task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:5]][width_2 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+2)+:1]); task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:5]][width_3 +: width_n], memp[wr_ram_b_addrb_tmp[14:5]][(index+3)+:1]); end else begin task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][(wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) +: 1]); task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_1) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_2) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * wb_width) + wb_width_3) +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:addrb_bit_32+1]][((wr_ram_b_addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); end // else: !if(wb_width >= width) end // case: 32 64 : if (width >= 64) begin // only valid with ECC single bit correction for 64 bits task_ram (wr_ram_b_web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_0 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index)+:1]); task_ram (wr_ram_b_web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_1 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+1)+:1]); task_ram (wr_ram_b_web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_2 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+2)+:1]); task_ram (wr_ram_b_web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_3 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+3)+:1]); task_ram (wr_ram_b_web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_4 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+4)+:1]); task_ram (wr_ram_b_web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_5 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+5)+:1]); task_ram (wr_ram_b_web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_6 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+6)+:1]); task_ram (wr_ram_b_web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[wr_ram_b_addrb_tmp[14:6]][wb_width_7 +: wb_width_n], memp[wr_ram_b_addrb_tmp[14:6]][(index+7)+:1]); end // case: 64 endcase // case(wb_width) end endtask // task_wr_ram_b task task_col_rd_ram_a; input [1:0] col_rd_ram_a_seq; // 1 is bypass input [7:0] col_rd_ram_a_web_tmp; input [7:0] col_rd_ram_a_wea_tmp; input [15:0] col_rd_ram_a_addra_tmp; inout [63:0] col_rd_ram_a_doa_tmp; inout [7:0] col_rd_ram_a_dopa_tmp; reg [63:0] doa_ltmp; reg [7:0] dopa_ltmp; begin doa_ltmp= 64'b0; dopa_ltmp= 8'b0; case (ra_width) 1, 2, 4 : begin if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin if (ra_width >= width) doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_lbit_124]]; else doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end end // case: 1, 2, 4 8 : if (width >= 8) begin if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin if (ra_width >= width) begin doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:3]]; dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:3]]; end else begin doa_ltmp = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width_n]; dopa_ltmp = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_8:3] * 1) +: 1]; end task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end end // case: 8 16 : if (width >= 16) begin if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin if (ra_width >= width) begin doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:4]][width_0 +: width_n]; dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:4]][(index)+:1]; end else begin doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width_n]; dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) +: 1]; end task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin if (ra_width >= width) begin doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:4]][width_1 +: width_n]; dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:4]][(index+1)+:1]; end else begin doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) + ra_width_n) +: ra_width_n]; dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][((col_rd_ram_a_addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1]; end task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end end 32 : if (width >= 32) begin if (ra_width >= width) begin if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:5]][width_0 +: width_n]; dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:5]][(index)+:1]; task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:5]][width_1 +: width_n]; dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+1)+:1]; task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:5]][width_2 +: width_n]; dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+2)+:1]; task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:5]][width_3 +: width_n]; dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:5]][(index+3)+:1]; task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end end // if (ra_width >= width) end 64 : if (width >= 64) begin if ((col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1 && col_rd_ram_a_wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[0] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[0] !== 1'b1)) begin doa_ltmp[7:0] = mem[col_rd_ram_a_addra_tmp[14:6]][width_0 +: width_n]; dopa_ltmp[0:0] = memp[col_rd_ram_a_addra_tmp[14:6]][(index)+:1]; task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1 && col_rd_ram_a_wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[1] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[1] !== 1'b1)) begin doa_ltmp[15:8] = mem[col_rd_ram_a_addra_tmp[14:6]][width_1 +: width_n]; dopa_ltmp[1:1] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+1)+:1]; task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1 && col_rd_ram_a_wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[2] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[2] !== 1'b1)) begin doa_ltmp[23:16] = mem[col_rd_ram_a_addra_tmp[14:6]][width_2 +: width_n]; dopa_ltmp[2:2] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+2)+:1]; task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1 && col_rd_ram_a_wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[3] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[3] !== 1'b1)) begin doa_ltmp[31:24] = mem[col_rd_ram_a_addra_tmp[14:6]][width_3 +: width_n]; dopa_ltmp[3:3] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+3)+:1]; task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1 && col_rd_ram_a_wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[4] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[4] !== 1'b1)) begin doa_ltmp[39:32] = mem[col_rd_ram_a_addra_tmp[14:6]][width_4 +: width_n]; dopa_ltmp[4:4] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+4)+:1]; task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1 && col_rd_ram_a_wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[5] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[5] !== 1'b1)) begin doa_ltmp[47:40] = mem[col_rd_ram_a_addra_tmp[14:6]][width_5 +: width_n]; dopa_ltmp[5:5] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+5)+:1]; task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1 && col_rd_ram_a_wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[6] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[6] !== 1'b1)) begin doa_ltmp[55:48] = mem[col_rd_ram_a_addra_tmp[14:6]][width_6 +: width_n]; dopa_ltmp[6:6] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+6)+:1]; task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end if ((col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1 && col_rd_ram_a_wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (col_rd_ram_a_seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && col_rd_ram_a_web_tmp[7] === 1'b1) || (col_rd_ram_a_seq == 2'b11 && wr_mode_a == 2'b00 && col_rd_ram_a_web_tmp[7] !== 1'b1)) begin doa_ltmp[63:56] = mem[col_rd_ram_a_addra_tmp[14:6]][width_7 +: width_n]; dopa_ltmp[7:7] = memp[col_rd_ram_a_addra_tmp[14:6]][(index+7)+:1]; task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, col_rd_ram_a_doa_tmp, dopa_ltmp, col_rd_ram_a_dopa_tmp); end end endcase // case(ra_width) end endtask // task_col_rd_ram_a task task_col_rd_ram_b; input [1:0] col_rd_ram_b_seq; // 1 is bypass input [7:0] col_rd_ram_b_wea_tmp; input [7:0] col_rd_ram_b_web_tmp; input [15:0] col_rd_ram_b_addrb_tmp; inout [63:0] col_rd_ram_b_dob_tmp; inout [7:0] col_rd_ram_b_dopb_tmp; reg [63:0] col_rd_ram_b_dob_ltmp; reg [7:0] col_rd_ram_b_dopb_ltmp; begin col_rd_ram_b_dob_ltmp= 64'b0; col_rd_ram_b_dopb_ltmp= 8'b0; case (rb_width) 1, 2, 4 : begin if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin if (rb_width >= width) col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]]; else col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width_n]; task_x_buf (wr_mode_b, 3, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end end // case: 1, 2, 4 8 : if (width >= 8) begin if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:3]]; col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:3]]; end else begin col_rd_ram_b_dob_ltmp = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * rb_width) +: rb_width_n]; col_rd_ram_b_dopb_ltmp = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; end task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end end // case: 8 16 : if (width >= 16) begin if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_0 +: width_n]; col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index)+:1]; end else begin col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) +: rb_width_n]; col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 1]; end task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:4]][width_1 +: width_n]; col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:4]][(index+1)+:1]; end else begin col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * rb_width) + rb_width_n) +: rb_width_n]; col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1]; end task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end end 32 : if (width >= 32) begin if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_0 +: width_n]; col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index)+:1]; end else begin col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) +: rb_width_n]; col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][(col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) +: 1]; end task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_1 +: width_n]; col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+1)+:1]; end else begin col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_1) +: rb_width_n]; col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1]; end task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_2 +: width_n]; col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+2)+:1]; end else begin col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_2) +: rb_width_n]; col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1]; end task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin if (rb_width >= width) begin col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:5]][width_3 +: width_n]; col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:5]][(index+3)+:1]; end else begin col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * rb_width) + rb_width_3) +: rb_width_n]; col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:r_addrb_bit_32+1]][((col_rd_ram_b_addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1]; end task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end end 64 : if (width >= 64) begin if ((col_rd_ram_b_web_tmp[0] === 1'b1 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1 && col_rd_ram_b_web_tmp[0] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[0] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[0] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[7:0] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_0 +: width_n]; col_rd_ram_b_dopb_ltmp[0:0] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index)+:1]; task_x_buf (wr_mode_b, 7, 0, 0, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[1] === 1'b1 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1 && col_rd_ram_b_web_tmp[1] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[1] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[1] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[15:8] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_1 +: width_n]; col_rd_ram_b_dopb_ltmp[1:1] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+1)+:1]; task_x_buf (wr_mode_b, 15, 8, 1, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[2] === 1'b1 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1 && col_rd_ram_b_web_tmp[2] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[2] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[2] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[23:16] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_2 +: width_n]; col_rd_ram_b_dopb_ltmp[2:2] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+2)+:1]; task_x_buf (wr_mode_b, 23, 16, 2, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[3] === 1'b1 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1 && col_rd_ram_b_web_tmp[3] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[3] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[3] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[31:24] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_3 +: width_n]; col_rd_ram_b_dopb_ltmp[3:3] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+3)+:1]; task_x_buf (wr_mode_b, 31, 24, 3, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[4] === 1'b1 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1 && col_rd_ram_b_web_tmp[4] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[4] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[4] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[39:32] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_4 +: width_n]; col_rd_ram_b_dopb_ltmp[4:4] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+4)+:1]; task_x_buf (wr_mode_b, 39, 32, 4, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[5] === 1'b1 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1 && col_rd_ram_b_web_tmp[5] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[5] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[5] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[47:40] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_5 +: width_n]; col_rd_ram_b_dopb_ltmp[5:5] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+5)+:1]; task_x_buf (wr_mode_b, 47, 40, 5, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[6] === 1'b1 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1 && col_rd_ram_b_web_tmp[6] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[6] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[6] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[55:48] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_6 +: width_n]; col_rd_ram_b_dopb_ltmp[6:6] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+6)+:1]; task_x_buf (wr_mode_b, 55, 48, 6, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end if ((col_rd_ram_b_web_tmp[7] === 1'b1 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1 && col_rd_ram_b_web_tmp[7] === 1'b0 && viol_type == 2'b11) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (col_rd_ram_b_seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && col_rd_ram_b_wea_tmp[7] === 1'b1) || (col_rd_ram_b_seq == 2'b11 && wr_mode_b == 2'b00 && col_rd_ram_b_wea_tmp[7] !== 1'b1)) begin col_rd_ram_b_dob_ltmp[63:56] = mem[col_rd_ram_b_addrb_tmp[14:6]][width_7 +: width_n]; col_rd_ram_b_dopb_ltmp[7:7] = memp[col_rd_ram_b_addrb_tmp[14:6]][(index+7)+:1]; task_x_buf (wr_mode_b, 63, 56, 7, col_rd_ram_b_dob_ltmp, col_rd_ram_b_dob_tmp, col_rd_ram_b_dopb_ltmp, col_rd_ram_b_dopb_tmp); end end endcase // case(rb_width) end endtask // task_col_rd_ram_b task task_rd_ram_a; input [15:0] rd_ram_a_addra_tmp; inout [63:0] doa_tmp; inout [7:0] dopa_tmp; begin case (ra_width) 1, 2, 4 : begin if (ra_width >= width) doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_lbit_124]]; else doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_124+1]][(rd_ram_a_addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; end 8 : begin if (ra_width >= width) begin doa_tmp = mem[rd_ram_a_addra_tmp[14:3]]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:3]]; end else begin doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_width) +: ra_width]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_8+1]][(rd_ram_a_addra_tmp[r_addra_bit_8:3] * ra_widthp) +: ra_widthp]; end end 16 : begin if (ra_width >= width) begin doa_tmp = mem[rd_ram_a_addra_tmp[14:4]]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:4]]; end else begin doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_width) +: ra_width]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_16+1]][(rd_ram_a_addra_tmp[r_addra_bit_16:4] * ra_widthp) +: ra_widthp]; end end 32 : begin if (ra_width >= width) begin doa_tmp = mem[rd_ram_a_addra_tmp[14:5]]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:5]]; end else begin doa_tmp = mem[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_width) +: ra_width]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:r_addra_bit_32+1]][(rd_ram_a_addra_tmp[r_addra_bit_32:5] * ra_widthp) +: ra_widthp]; end end 64 : begin if (ra_width >= width) begin doa_tmp = mem[rd_ram_a_addra_tmp[14:6]]; dopa_tmp = memp[rd_ram_a_addra_tmp[14:6]]; end end endcase // case(ra_width) end endtask // task_rd_ram_a task task_rd_ram_b; input [15:0] rd_ram_b_addrb_tmp; inout [31:0] dob_tmp; inout [3:0] dopb_tmp; begin case (rb_width) 1, 2, 4 : begin if (rb_width >= width) dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_lbit_124]]; else dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_124+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; end 8 : begin if (rb_width >= width) begin dob_tmp = mem[rd_ram_b_addrb_tmp[14:3]]; dopb_tmp = memp[rd_ram_b_addrb_tmp[14:3]]; end else begin dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_8+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; end end 16 : begin if (rb_width >= width) begin dob_tmp = mem[rd_ram_b_addrb_tmp[14:4]]; dopb_tmp = memp[rd_ram_b_addrb_tmp[14:4]]; end else begin dob_tmp = mem[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; dopb_tmp = memp[rd_ram_b_addrb_tmp[14:r_addrb_bit_16+1]][(rd_ram_b_addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; end end 32 : begin dob_tmp = mem[rd_ram_b_addrb_tmp[14:5]]; dopb_tmp = memp[rd_ram_b_addrb_tmp[14:5]]; end 64 : begin if (rb_width >= width) begin dob_tmp = mem[rd_ram_b_addrb_tmp[14:6]]; dopb_tmp = memp[rd_ram_b_addrb_tmp[14:6]]; end end endcase end endtask // task_rd_ram_b task chk_for_col_msg; input wea_tmp; input web_tmp; input [15:0] addra_tmp; input [15:0] addrb_tmp; begin if (SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin if (chk_ox_msg == 1) begin if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) $display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the overlapped address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); end else $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); col_wr_wr_msg = 0; end // if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin if (chk_ox_msg == 1) begin if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) $display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the overlapped address %h (hex) of port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp, addra_tmp); end else begin if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6")) $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp); else if (wr_mode_a != 2'b01 || (viol_type == 2'b11 && wr_mode_a == 2'b01)) $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp); end // else: !if(chk_ox_msg == 1) col_wra_rdb_msg = 0; end else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin if (chk_ox_msg == 1) begin if (!(rdaddr_collision_hwconfig_int == 0 && chk_ox_same_clk == 1)) $display("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the overlapped address %h (hex) of port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addra_tmp, addrb_tmp); end else begin if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (!(chk_col_same_clk == 1 && rdaddr_collision_hwconfig_int == 0) && SIM_DEVICE == "VIRTEX6")) $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown.", $time/1000.0, addrb_tmp); else if (wr_mode_b != 2'b01 || (viol_type == 2'b10 && wr_mode_b == 2'b01)) $display("Memory Collision Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp); end // else: !if(chk_ox_msg == 1) col_wrb_rda_msg = 0; end // if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) end endtask // chk_for_col_msg task task_col_ecc_read; inout [63:0] do_tmp; inout [7:0] dop_tmp; input [15:0] addr_tmp; reg [71:0] task_ecc_bit_position; reg [7:0] task_dopr_ecc, task_syndrome; reg [63:0] task_di_in_ecc_corrected; reg [7:0] task_dip_in_ecc_corrected; begin if (|do_tmp === 1'bx) begin // if there is collision dbiterr_out <= 1'bx; sbiterr_out <= 1'bx; end else begin task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp); task_syndrome = task_dopr_ecc ^ dop_tmp; if (task_syndrome !== 0) begin if (task_syndrome[7]) begin // dectect single bit error task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]}; if (task_syndrome[6:0] > 71) begin $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); $finish; end task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory do_tmp = task_di_in_ecc_corrected; task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory dop_tmp = task_dip_in_ecc_corrected; dbiterr_out <= 0; sbiterr_out <= 1; end else if (!task_syndrome[7]) begin // double bit error sbiterr_out <= 0; dbiterr_out <= 1; end end // if (task_syndrome !== 0) else begin dbiterr_out <= 0; sbiterr_out <= 0; end // else: !if(task_syndrome !== 0) end end endtask // task_col_ecc_read function [7:0] fn_dip_ecc; input encode; input [63:0] di_in; input [7:0] dip_in; begin fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] ^di_in[61]^di_in[63]; fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] ^di_in[62]^di_in[63]; fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] ^di_in[53]^di_in[54]^di_in[55]^di_in[56] ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] ^di_in[10]^di_in[18]^di_in[19] ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] ^di_in[40]^di_in[49] ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; if (encode == 1'b1) fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6] ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; else fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6] ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; end endfunction // fn_dip_ecc /******************************************** END task and function **************************************/ initial begin if (INIT_FILE == "NONE") begin // memory initialization from attributes init_mult = 256/width; for (count = 0; count < init_mult; count = count + 1) begin init_offset = count * width; mem[count] = INIT_00[init_offset +:width]; mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; if (BRAM_SIZE == 36) begin mem[count + (init_mult * 64)] = INIT_40[init_offset +:width]; mem[count + (init_mult * 65)] = INIT_41[init_offset +:width]; mem[count + (init_mult * 66)] = INIT_42[init_offset +:width]; mem[count + (init_mult * 67)] = INIT_43[init_offset +:width]; mem[count + (init_mult * 68)] = INIT_44[init_offset +:width]; mem[count + (init_mult * 69)] = INIT_45[init_offset +:width]; mem[count + (init_mult * 70)] = INIT_46[init_offset +:width]; mem[count + (init_mult * 71)] = INIT_47[init_offset +:width]; mem[count + (init_mult * 72)] = INIT_48[init_offset +:width]; mem[count + (init_mult * 73)] = INIT_49[init_offset +:width]; mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width]; mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width]; mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width]; mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width]; mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width]; mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width]; mem[count + (init_mult * 80)] = INIT_50[init_offset +:width]; mem[count + (init_mult * 81)] = INIT_51[init_offset +:width]; mem[count + (init_mult * 82)] = INIT_52[init_offset +:width]; mem[count + (init_mult * 83)] = INIT_53[init_offset +:width]; mem[count + (init_mult * 84)] = INIT_54[init_offset +:width]; mem[count + (init_mult * 85)] = INIT_55[init_offset +:width]; mem[count + (init_mult * 86)] = INIT_56[init_offset +:width]; mem[count + (init_mult * 87)] = INIT_57[init_offset +:width]; mem[count + (init_mult * 88)] = INIT_58[init_offset +:width]; mem[count + (init_mult * 89)] = INIT_59[init_offset +:width]; mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width]; mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width]; mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width]; mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width]; mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width]; mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width]; mem[count + (init_mult * 96)] = INIT_60[init_offset +:width]; mem[count + (init_mult * 97)] = INIT_61[init_offset +:width]; mem[count + (init_mult * 98)] = INIT_62[init_offset +:width]; mem[count + (init_mult * 99)] = INIT_63[init_offset +:width]; mem[count + (init_mult * 100)] = INIT_64[init_offset +:width]; mem[count + (init_mult * 101)] = INIT_65[init_offset +:width]; mem[count + (init_mult * 102)] = INIT_66[init_offset +:width]; mem[count + (init_mult * 103)] = INIT_67[init_offset +:width]; mem[count + (init_mult * 104)] = INIT_68[init_offset +:width]; mem[count + (init_mult * 105)] = INIT_69[init_offset +:width]; mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width]; mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width]; mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width]; mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width]; mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width]; mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width]; mem[count + (init_mult * 112)] = INIT_70[init_offset +:width]; mem[count + (init_mult * 113)] = INIT_71[init_offset +:width]; mem[count + (init_mult * 114)] = INIT_72[init_offset +:width]; mem[count + (init_mult * 115)] = INIT_73[init_offset +:width]; mem[count + (init_mult * 116)] = INIT_74[init_offset +:width]; mem[count + (init_mult * 117)] = INIT_75[init_offset +:width]; mem[count + (init_mult * 118)] = INIT_76[init_offset +:width]; mem[count + (init_mult * 119)] = INIT_77[init_offset +:width]; mem[count + (init_mult * 120)] = INIT_78[init_offset +:width]; mem[count + (init_mult * 121)] = INIT_79[init_offset +:width]; mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width]; mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width]; mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width]; mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width]; mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width]; mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width]; end // if (BRAM_SIZE == 36) end // for (count = 0; count < init_mult; count = count + 1) if (width >= 8) begin initp_mult = 256/widthp; for (countp = 0; countp < initp_mult; countp = countp + 1) begin initp_offset = countp * widthp; memp[countp] = INITP_00[initp_offset +:widthp]; memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; if (BRAM_SIZE == 36) begin memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp]; memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp]; memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp]; memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp]; memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp]; memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp]; memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp]; memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp]; end end // for (countp = 0; countp < initp_mult; countp = countp + 1) end // if (width >= 8) end // if (INIT_FILE == "NONE") else begin // memory initialization from memory file for (j = 0; j < mem_depth; j = j + 1) begin for (j1 = 0; j1 < widest_width; j1 = j1 + 1) begin tmp_mem[j][j1] = 1'b0; end end $readmemh (INIT_FILE, tmp_mem); case (widest_width) 1, 2, 4 : begin for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) mem[i_mem] = tmp_mem [i_mem]; end 9 : if ((width == 8) && (widthp == 1)) begin for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin mem[i_mem] = tmp_mem[i_mem][0 +: width]; memp[i_mem] = tmp_mem[i_mem][width +: widthp]; end end 18 : if ((width == 16) && (widthp == 2)) begin for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin mem[i_mem] = tmp_mem[i_mem][0 +: width]; memp[i_mem] = tmp_mem[i_mem][width +: widthp]; end end 36 : if ((width == 32) && (widthp == 4)) begin for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin mem[i_mem] = tmp_mem[i_mem][0 +: width]; memp[i_mem] = tmp_mem[i_mem][width +: widthp]; end end 72 : if ((width == 64) && (widthp == 8)) begin for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin mem[i_mem] = tmp_mem[i_mem][0 +: width]; memp[i_mem] = tmp_mem[i_mem][width +: widthp]; end end endcase // case(widest_width) end // else: !if(INIT_FILE == "NONE") case (EN_ECC_WRITE) "TRUE" : en_ecc_write_int = 1; "FALSE" : en_ecc_write_int = 0; default : begin $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); finish_error = 1; end endcase case (EN_ECC_READ) "TRUE" : en_ecc_read_int = 1; "FALSE" : en_ecc_read_int = 0; default : begin $display("Attribute Syntax Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); finish_error = 1; end endcase case (RAM_MODE) "TDP" : begin ram_mode_int = 1; if (en_ecc_write_int == 1) begin $display("DRC Error : The attribute EN_ECC_WRITE on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE); finish_error = 1; end if (en_ecc_read_int == 1) begin $display("DRC Error : The attribute EN_ECC_READ on RAMB18E1 instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ); finish_error = 1; end end // case: "TDP" "SDP" : begin ram_mode_int = 0; if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_B == "NO_CHANGE") begin $display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RAMB18E1 instance %m."); finish_error = 1; end if (BRAM_SIZE == 18) begin if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP."); finish_error = 1; end end else begin if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP."); finish_error = 1; end end // else: !if(BRAM_SIZE == 18) end // case: "SDP" default : begin $display("Attribute Syntax Error : The attribute RAM_MODE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE); finish_error = 1; end endcase case (WRITE_WIDTH_A) 0, 1, 2, 4, 9, 18 : ; 36 : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); finish_error = 1; end end 72 : begin if (BRAM_SIZE == 18) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); finish_error = 1; end else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); finish_error = 1; end end default : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); finish_error = 1; end else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); finish_error = 1; end end endcase // case(WRITE_WIDTH_A) case (WRITE_WIDTH_B) 0, 1, 2, 4, 9, 18 : ; 36 : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); finish_error = 1; end end 72 : begin if (BRAM_SIZE == 18) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); finish_error = 1; end else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); finish_error = 1; end end default : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); finish_error = 1; end else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); finish_error = 1; end end endcase // case(WRITE_WIDTH_B) case (READ_WIDTH_A) 0, 1, 2, 4, 9, 18 : ; 36 : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); finish_error = 1; end end 72 : begin if (BRAM_SIZE == 18) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); finish_error = 1; end else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); finish_error = 1; end end default : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); finish_error = 1; end else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); finish_error = 1; end end endcase // case(READ_WIDTH_A) case (READ_WIDTH_B) 0, 1, 2, 4, 9, 18 : ; 36 : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); finish_error = 1; end end 72 : begin if (BRAM_SIZE == 18) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); finish_error = 1; end else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); finish_error = 1; end end default : begin if (BRAM_SIZE == 18 && ram_mode_int == 1) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); finish_error = 1; end else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RAMB18E1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); finish_error = 1; end end endcase // case(READ_WIDTH_B) if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."); finish_error = 1; end if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."); finish_error = 1; end if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."); finish_error = 1; end if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."); finish_error = 1; end if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin $display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RAMB18E1 instance %m, both can not be 0."); finish_error = 1; end case (WRITE_MODE_A) "WRITE_FIRST" : wr_mode_a = 2'b00; "READ_FIRST" : wr_mode_a = 2'b01; "NO_CHANGE" : wr_mode_a = 2'b10; default : begin $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); finish_error = 1; end endcase case (WRITE_MODE_B) "WRITE_FIRST" : wr_mode_b = 2'b00; "READ_FIRST" : wr_mode_b = 2'b01; "NO_CHANGE" : wr_mode_b = 2'b10; default : begin $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); finish_error = 1; end endcase case (RAM_EXTENSION_A) "UPPER" : cascade_a = 2'b11; "LOWER" : cascade_a = 2'b01; "NONE" : cascade_a = 2'b00; default : begin $display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A); finish_error = 1; end endcase case (RAM_EXTENSION_B) "UPPER" : cascade_b = 2'b11; "LOWER" : cascade_b = 2'b01; "NONE" : cascade_b = 2'b00; default : begin $display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B); finish_error = 1; end endcase if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB18E1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); finish_error = 1; end case (RSTREG_PRIORITY_A) "RSTREG" : rstreg_priority_a_int = 1; "REGCE" : rstreg_priority_a_int = 0; default : begin $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A); finish_error = 1; end endcase case (RSTREG_PRIORITY_B) "RSTREG" : rstreg_priority_b_int = 1; "REGCE" : rstreg_priority_b_int = 0; default : begin $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RAMB18E1 instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B); finish_error = 1; end endcase if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin $display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RAMB18E1 instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE."); finish_error = 1; end case (RDADDR_COLLISION_HWCONFIG) "DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0; "PERFORMANCE" : rdaddr_collision_hwconfig_int = 1; default : begin $display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RAMB18E1 instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG); finish_error = 1; end endcase if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin $display("Attribute Syntax Error : The Attribute SIM_DEVICE on RAMB18E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE); finish_error = 1; end if (finish_error == 1) #1 $finish; end // initial begin // GSR always @(GSR) if (GSR) begin assign doa_out = INIT_A[0 +: ra_width]; if (ra_width >= 8) begin assign dopa_out = INIT_A[ra_width +: ra_widthp]; end assign dob_out = INIT_B[0 +: rb_width]; if (rb_width >= 8) begin assign dopb_out = INIT_B[rb_width +: rb_widthp]; end assign dbiterr_out = 0; assign sbiterr_out = 0; assign rdaddrecc_out = 9'b0; end else begin deassign doa_out; deassign dopa_out; deassign dob_out; deassign dopb_out; deassign dbiterr_out; deassign sbiterr_out; deassign rdaddrecc_out; end always @(time_clka_period or time_clkb_period) begin if (time_clka_period != 0 && time_clkb_period != 0) begin if (time_clka_period <= time_clkb_period) begin if (time_clka_period <= SETUP_READ_FIRST) begin time_period = time_clka_period; end else begin time_period = SETUP_READ_FIRST; end end else if (time_clkb_period <= SETUP_READ_FIRST) time_period = time_clkb_period; else time_period = SETUP_READ_FIRST; end end // registering signals always @(posedge CLKA) begin `ifdef MODEL_TECH #0 rising_clka = 1; // mentor race condition check `else rising_clka = 1; `endif if (time_skew_a_flag == 0) begin if ($time > 110000) begin time_clka_period = $time - time_port_a; time_skew_a_flag = 1; end end if (ENA === 1'b1) begin time_port_a = $time; addra_reg = ADDRA; wea_reg = WEA; dia_reg = DIA; dipa_reg = DIPA; ox_addra_reconstruct_reg = ox_addra_reconstruct; end end always @(posedge CLKB) begin `ifdef MODEL_TECH #0 rising_clkb = 1; // mentor race condition check `else rising_clkb = 1; `endif if (time_skew_b_flag == 0) begin if ($time > 110000) begin time_clkb_period = $time - time_port_b; time_skew_b_flag = 1; end end if (ENB === 1'b1) begin time_port_b = $time; addrb_reg = ADDRB; web_reg = WEB; enb_reg = ENB; dib_reg = DIB; dipb_reg = DIPB; ox_addrb_reconstruct_reg = ox_addrb_reconstruct; end end // always @ (posedge CLKB) // CLKA and CLKB always @(posedge rising_clka or posedge rising_clkb) begin // Registering addr[15] for cascade mode if (rising_clka) if (cascade_a[1]) addra_in_15_reg_bram = ~ADDRA[15]; else addra_in_15_reg_bram = ADDRA[15]; if (rising_clkb) if (cascade_b[1]) addrb_in_15_reg_bram = ~ADDRB[15]; else addrb_in_15_reg_bram = ADDRB[15]; if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin /************************************* Collision starts *****************************************/ if (SIM_COLLISION_CHECK != "NONE") begin if (GSR === 1'b0) begin if (time_port_a > time_port_b) begin if (time_port_a - time_port_b <= sync_clk_skew) begin viol_time = 1; end else if (time_port_a - time_port_b <= time_period) begin viol_time = 2; end end else begin if (time_port_b - time_port_a <= sync_clk_skew) begin viol_time = 1; end else if (time_port_b - time_port_a <= time_period) begin viol_time = 2; end end // else: !if(time_port_a > time_port_b) if (ENA === 1'b0 || ENB === 1'b0) viol_time = 0; if ((WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000)) if ((WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00)) viol_time = 0; if (viol_time != 0) begin if (SIM_DEVICE == "VIRTEX6") begin // Clka and clkb rise at the same time if ((rising_clka && rising_clkb) || viol_time == 1) begin if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin viol_type = 2'b01; chk_col_same_clk = 1; if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin doa_buf = dob_buf; dopa_buf = dopb_buf; end else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin dob_buf = doa_buf; dopb_buf = dopa_buf; end else begin task_rd_ram_a (ADDRA, doa_buf, dopa_buf); task_rd_ram_b (ADDRB, dob_buf, dopb_buf); end task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); chk_col_same_clk = 0; task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf); task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); dib_ecc_col = DIB; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc_col; task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); end else task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && rdaddr_collision_hwconfig_int == 1) begin task_col_wr_ram_a (2'b10, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); task_col_wr_ram_b (2'b10, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); end if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) task_col_ecc_read (doa_buf, dopa_buf, ADDRA); end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin viol_type = 2'b01; chk_ox_msg = 1; chk_ox_same_clk = 1; if (time_port_a > time_port_b) task_rd_ram_a (ADDRA, doa_buf, dopa_buf); else if (time_port_b > time_port_a) task_rd_ram_b (ADDRB, dob_buf, dopb_buf); else begin task_rd_ram_a (ADDRA, doa_buf, dopa_buf); task_rd_ram_b (ADDRB, dob_buf, dopb_buf); end task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); chk_ox_msg = 0; chk_ox_same_clk = 0; task_ox_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); dib_ecc_col = DIB; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc_col; task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); end else task_ox_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); if (rdaddr_collision_hwconfig_int == 1) begin task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, ADDRA); task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, ADDRB); end if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) task_col_ecc_read (doa_buf, dopa_buf, ADDRA); end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) else viol_time = 0; end // if (rising_clka && rising_clkb) // Clkb before clka else if (rising_clka && !rising_clkb) begin if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin viol_type = 2'b10; task_rd_ram_a (ADDRA, doa_buf, dopa_buf); task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf); task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); dib_ecc_col = dib_reg; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); eccparity_out = dip_ecc_col; task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); end else task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin task_col_wr_ram_a (2'b10, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); task_col_wr_ram_b (2'b10, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); end if (ram_mode_int == 0 && en_ecc_read_int == 1) task_col_ecc_read (doa_buf, dopa_buf, ADDRA); end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) begin viol_type = 2'b10; chk_ox_msg = 1; task_rd_ram_a (ADDRA, doa_buf, dopa_buf); // get msg task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); chk_ox_msg = 0; task_ox_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); dib_ecc_col = dib_reg; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); eccparity_out = dip_ecc_col; task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); end else task_ox_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, web_reg, 8'hff, di_x, di_x[7:0], addrb_reg, ADDRA); task_col_wr_ram_b (2'b10, WEA, 8'hff, di_x, di_x[7:0], ADDRA, addrb_reg); if (ram_mode_int == 0 && en_ecc_read_int == 1) task_col_ecc_read (doa_buf, dopa_buf, ADDRA); end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb])) else viol_time = 0; end // if (rising_clka && !rising_clkb) // Clka before clkb else if (!rising_clka && rising_clkb) begin if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin viol_type = 2'b11; task_rd_ram_b (ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); dib_ecc_col = DIB; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc_col; task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); end else task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin task_col_wr_ram_a (2'b10, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); task_col_wr_ram_b (2'b10, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); end if (ram_mode_int == 0 && en_ecc_read_int == 1) task_col_ecc_read (doa_buf, dopa_buf, addra_reg); end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) begin viol_type = 2'b11; chk_ox_msg = 1; task_rd_ram_b (ADDRB, dob_buf, dopb_buf); // get msg task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); chk_ox_msg = 0; task_ox_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); dib_ecc_col = DIB; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc_col; task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); end else task_ox_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, WEB, 8'hff, di_x, di_x[7:0], ADDRB, addra_reg); task_col_wr_ram_b (2'b10, wea_reg, 8'hff, di_x, di_x[7:0], addra_reg, ADDRB); if (ram_mode_int == 0 && en_ecc_read_int == 1) task_col_ecc_read (doa_buf, dopa_buf, addra_reg); end // if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb])) else viol_time = 0; end // if (!rising_clka && rising_clkb) end // if (SIM_DEVICE == "VIRTEX6") else begin // 7series // Clka and clkb rise at the same time if ((rising_clka && rising_clkb) || viol_time == 1) begin if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin viol_type = 2'b01; chk_col_same_clk = 1; if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_a > time_port_b)) begin doa_buf = dob_buf; dopa_buf = dopb_buf; end else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (time_port_b > time_port_a)) begin dob_buf = doa_buf; dopb_buf = dopa_buf; end else begin task_rd_ram_a (ADDRA, doa_buf, dopa_buf); task_rd_ram_b (ADDRB, dob_buf, dopb_buf); end task_col_wr_ram_a (2'b00, WEB, WEA, di_x, di_x[7:0], ADDRB, ADDRA); task_col_wr_ram_b (2'b00, WEA, WEB, di_x, di_x[7:0], ADDRA, ADDRB); chk_col_same_clk = 0; task_col_rd_ram_a (2'b01, WEB, WEA, ADDRA, doa_buf, dopa_buf); task_col_rd_ram_b (2'b01, WEA, WEB, ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, WEB, WEA, DIA, DIPA, ADDRB, ADDRA); dib_ecc_col = DIB; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc_col; task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, dip_ecc_col, ADDRA, ADDRB); end else task_col_wr_ram_b (2'b10, WEA, WEB, dib_ecc_col, DIPB, ADDRA, ADDRB); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, WEB, WEA, ADDRA, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, WEA, WEB, ADDRB, dob_buf, dopb_buf); if ((ram_mode_int == 0 && en_ecc_read_int == 1) && ((time_port_a > time_port_b) || (rising_clka && rising_clkb))) task_col_ecc_read (doa_buf, dopa_buf, ADDRA); end // if (ADDRA[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin $display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); $finish; end else viol_time = 0; end // if ((rising_clka && rising_clkb) || viol_time == 1) // Clkb before clka else if (rising_clka && !rising_clkb) begin if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin viol_type = 2'b10; task_rd_ram_a (ADDRA, doa_buf, dopa_buf); task_col_wr_ram_a (2'b00, web_reg, WEA, di_x, di_x[7:0], addrb_reg, ADDRA); task_col_wr_ram_b (2'b00, WEA, web_reg, di_x, di_x[7:0], ADDRA, addrb_reg); task_col_rd_ram_a (2'b01, web_reg, WEA, ADDRA, doa_buf, dopa_buf); task_col_rd_ram_b (2'b01, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, web_reg, WEA, DIA, DIPA, addrb_reg, ADDRA); dib_ecc_col = dib_reg; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); eccparity_out = dip_ecc_col; task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dip_ecc_col, ADDRA, addrb_reg); end else task_col_wr_ram_b (2'b10, WEA, web_reg, dib_ecc_col, dipb_reg, ADDRA, addrb_reg); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, web_reg, WEA, ADDRA, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, WEA, web_reg, addrb_reg, dob_buf, dopb_buf); if (ram_mode_int == 0 && en_ecc_read_int == 1) task_col_ecc_read (doa_buf, dopa_buf, ADDRA); end // if (ADDRA[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct[15:col_addr_lsb] === ox_addrb_reconstruct_reg[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin $display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, ADDRA, addrb_reg, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); $finish; end else viol_time = 0; end // if (rising_clka && !rising_clkb) // Clka before clkb else if (!rising_clka && rising_clkb) begin if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) begin viol_type = 2'b11; task_rd_ram_b (ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b00, WEB, wea_reg, di_x, di_x[7:0], ADDRB, addra_reg); task_col_wr_ram_b (2'b00, wea_reg, WEB, di_x, di_x[7:0], addra_reg, ADDRB); task_col_rd_ram_a (2'b01, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); task_col_rd_ram_b (2'b01, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); task_col_wr_ram_a (2'b10, WEB, wea_reg, dia_reg, dipa_reg, ADDRB, addra_reg); dib_ecc_col = DIB; if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; dib_ecc_col[62] = ~dib_ecc_col[62]; end else if (injectsbiterr_in === 1) begin dib_ecc_col[30] = ~dib_ecc_col[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) if (ram_mode_int == 0 && en_ecc_write_int == 1 && ENB === 1'b1) begin dip_ecc_col = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc_col; task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, dip_ecc_col, addra_reg, ADDRB); end else task_col_wr_ram_b (2'b10, wea_reg, WEB, dib_ecc_col, DIPB, addra_reg, ADDRB); if (wr_mode_a != 2'b01) task_col_rd_ram_a (2'b11, WEB, wea_reg, addra_reg, doa_buf, dopa_buf); if (wr_mode_b != 2'b01) task_col_rd_ram_b (2'b11, wea_reg, WEB, ADDRB, dob_buf, dopb_buf); if (ram_mode_int == 0 && en_ecc_read_int == 1) task_col_ecc_read (doa_buf, dopa_buf, addra_reg); end // if (addra_reg[15:col_addr_lsb] === ADDRB[15:col_addr_lsb]) else if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && (ox_addra_reconstruct_reg[15:col_addr_lsb] === ox_addrb_reconstruct[15:col_addr_lsb]) && rdaddr_collision_hwconfig_int == 1) begin $display ("Address Overlap Error on RAMB18E1 : %m at simulation time %.3f ns.\nA read/write/write was performed on address %h (hex) of port A while a write/read/write was requested to the overlapped address %h (hex) of port B with RDADDR_COLLISION_HWCONFIG set to %s and WRITE_MODE_A set %s and WRITE_MODE_B set to %s . The write will be unsuccessful and the contents of the RAM at both address locations of port A and B became unknown. To correct this issue, either evaluate changing RDADDR_COLLISION_HWCONFIG to DELAYED_WRITE, change both WITRE_MODEs to something other than READ_FIRST or control addressing to not incur address overlap.", $time/1000.0, addra_reg, ADDRB, RDADDR_COLLISION_HWCONFIG, WRITE_MODE_A, WRITE_MODE_B ); $finish; end else viol_time = 0; end // if (!rising_clka && rising_clkb) end // else: !if(SIM_DEVICE == "VIRTEX6") end // if (viol_time != 0) end // if (GSR === 1'b0) if (SIM_COLLISION_CHECK == "WARNING_ONLY") viol_time = 0; end // if (SIM_COLLISION_CHECK != "NONE") /*************************************** end collision ********************************/ end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) /**************************** Port A ****************************************/ if (rising_clka) begin // DRC if (RSTRAMA === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m."); // end DRC // registering ADDRA[15] the second time if (REGCEA) addra_in_15_reg1 = addra_in_15_reg; if (ENA && (wr_mode_a != 2'b10 || WEA[0] == 0 || RSTRAMA == 1'b1)) if (cascade_a[1]) addra_in_15_reg = ~ADDRA[15]; else addra_in_15_reg = ADDRA[15]; if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin // SRVAL if (RSTRAMA === 1'b1) begin doa_buf = SRVAL_A[0 +: ra_width]; doa_out = SRVAL_A[0 +: ra_width]; if (ra_width >= 8) begin dopa_buf = SRVAL_A[ra_width +: ra_widthp]; dopa_out = SRVAL_A[ra_width +: ra_widthp]; end end if (viol_time == 0) begin // Read first if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin task_rd_ram_a (ADDRA, doa_buf, dopa_buf); // ECC decode if (ram_mode_int == 0 && en_ecc_read_int == 1) begin dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf); syndrome = dopr_ecc ^ dopa_buf; if (syndrome !== 0) begin if (syndrome[7]) begin // dectect single bit error ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]}; if (syndrome[6:0] > 71) begin $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); $finish; end ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory doa_buf = dia_in_ecc_corrected; dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory dopa_buf = dipa_in_ecc_corrected; dbiterr_out <= 0; sbiterr_out <= 1; end else if (!syndrome[7]) begin // double bit error sbiterr_out <= 0; dbiterr_out <= 1; end end // if (syndrome !== 0) else begin dbiterr_out <= 0; sbiterr_out <= 0; end // else: !if(syndrome !== 0) // output of rdaddrecc rdaddrecc_out[8:0] <= ADDRA[14:6]; end // if (ram_mode_int == 0 && en_ecc_read_int == 1) end // if (wr_mode_a == 2'b01) // Write task_wr_ram_a (WEA, DIA, DIPA, ADDRA); // Read if not read first if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1)) task_rd_ram_a (ADDRA, doa_buf, dopa_buf); end // if (viol_time == 0) end // if (GSR == 1'b0 && ENA == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) end // if (rising_clka) // end of port A /************************************** port B ***************************************************************/ if (rising_clkb) begin // DRC if (RSTRAMB === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RAMB18E1 instance %m."); if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin if (injectsbiterr_in === 1) $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m."); if (injectdbiterr_in === 1) $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RAMB18E1 instance %m."); end // End DRC if (REGCEB) addrb_in_15_reg1 = addrb_in_15_reg; if (ENB && (wr_mode_b != 2'b10 || WEB[0] == 0 || RSTRAMB == 1'b1)) if (cascade_b[1]) addrb_in_15_reg = ~ADDRB[15]; else addrb_in_15_reg = ADDRB[15]; if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin // SRVAL if (RSTRAMB === 1'b1) begin dob_buf = SRVAL_B[0 +: rb_width]; dob_out = SRVAL_B[0 +: rb_width]; if (rb_width >= 8) begin dopb_buf = SRVAL_B[rb_width +: rb_widthp]; dopb_out = SRVAL_B[rb_width +: rb_widthp]; end end if (viol_time == 0) begin // ECC encode if (ram_mode_int == 0 && en_ecc_write_int == 1) begin dip_ecc = fn_dip_ecc(1'b1, DIB, DIPB); eccparity_out = dip_ecc; dipb_in_ecc = dip_ecc; end else dipb_in_ecc = DIPB; dib_in_ecc = DIB; // injecting error if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin if (injectdbiterr_in === 1) begin // double bit dib_in_ecc[30] = ~dib_in_ecc[30]; dib_in_ecc[62] = ~dib_in_ecc[62]; end else if (injectsbiterr_in === 1) begin // single bit dib_in_ecc[30] = ~dib_in_ecc[30]; end end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1) // Read first if (wr_mode_b == 2'b01 && RSTRAMB === 1'b0) task_rd_ram_b (ADDRB, dob_buf, dopb_buf); // Write task_wr_ram_b (WEB, dib_in_ecc, dipb_in_ecc, ADDRB); // Read if not read first if (wr_mode_b != 2'b01 && RSTRAMB === 1'b0) task_rd_ram_b (ADDRB, dob_buf, dopb_buf); end // if (viol_time == 0) end // if (GSR == 1'b0 && ENB == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0)) end // if (rising_clkb) // end of port B if (GSR == 1'b0) begin // writing outputs of port A if (ENA && (rising_clka || viol_time != 0)) begin if (RSTRAMA === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000))) begin doa_out <= doa_buf; if (ra_width >= 8) dopa_out <= dopa_buf; end end // writing outputs of port B if (ENB && (rising_clkb || viol_time != 0)) begin if (RSTRAMB === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))) begin dob_out <= dob_buf; if (rb_width >= 8) dopb_out <= dopb_buf; end end end // if (GSR == 1'b0) viol_time = 0; `ifdef MODEL_TECH #0 rising_clka = 0; // mentor race condition check #0 rising_clkb = 0; // mentor race condition check `else rising_clka = 0; rising_clkb = 0; `endif viol_type = 2'b00; col_wr_wr_msg = 1; col_wra_rdb_msg = 1; col_wrb_rda_msg = 1; end // always @ (posedge rising_clka or posedge rising_clkb) // ********* Cascade Port A ******** always @(posedge CLKA or CASCADEINA or addra_in_15_reg or doa_out or dopa_out) begin if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin doa_out_mux[0] = CASCADEINA; end else begin doa_out_mux = doa_out; if (ra_width >= 8) dopa_out_mux = dopa_out; end end // output register mode always @(posedge CLKA or CASCADEINA or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin doa_outreg_mux[0] = CASCADEINA; end else begin doa_outreg_mux = doa_outreg; if (ra_width >= 8) dopa_outreg_mux = dopa_outreg; end end // ********* Cascade Port B ******** always @(posedge CLKB or CASCADEINB or addrb_in_15_reg or dob_out or dopb_out) begin if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin dob_out_mux[0] = CASCADEINB; end else begin dob_out_mux = dob_out; if (rb_width >= 8) dopb_out_mux = dopb_out; end end // output register mode always @(posedge CLKB or CASCADEINB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin dob_outreg_mux[0] = CASCADEINB; end else begin dob_outreg_mux = dob_outreg; if (rb_width >= 8) dopb_outreg_mux = dopb_outreg; end end // always @ (posedge REGCLKB or CASCADEINREGB or addrb_in_15_reg1 or dob_outreg or dopb_outreg) // ***** Output Registers **** Port A ***** always @(posedge CLKA or posedge GSR) begin if (DOA_REG == 1) begin if (GSR == 1'b1) begin rdaddrecc_outreg <= 9'b0; dbiterr_outreg <= 0; sbiterr_outreg <= 0; doa_outreg <= INIT_A[0 +: ra_width]; if (ra_width >= 8) dopa_outreg <= INIT_A[ra_width +: ra_widthp]; end else if (GSR == 1'b0) begin if (REGCEA === 1'b1) begin dbiterr_outreg <= dbiterr_out; sbiterr_outreg <= sbiterr_out; rdaddrecc_outreg <= rdaddrecc_out; end if (rstreg_priority_a_int == 0) begin // Virtex5 behavior if (REGCEA == 1'b1) begin if (RSTREGA == 1'b1) begin doa_outreg <= SRVAL_A[0 +: ra_width]; if (ra_width >= 8) dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; end else if (RSTREGA == 1'b0) begin doa_outreg <= doa_out; if (ra_width >= 8) dopa_outreg <= dopa_out; end end // if (REGCEA == 1'b1) end // if (rstreg_priority_a_int == 1'b0) else begin if (RSTREGA == 1'b1) begin doa_outreg <= SRVAL_A[0 +: ra_width]; if (ra_width >= 8) dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; end else if (RSTREGA == 1'b0) begin if (REGCEA == 1'b1) begin doa_outreg <= doa_out; if (ra_width >= 8) dopa_outreg <= dopa_out; end end end // else: !if(rstreg_priority_a_int == 1'b0) end // if (GSR == 1'b0) end // if (DOA_REG == 1) end // always @ (posedge CLKA or posedge GSR) always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin case (DOA_REG) 0 : begin dbiterr_out_out = dbiterr_out; sbiterr_out_out = sbiterr_out; rdaddrecc_out_out = rdaddrecc_out; DOA[0 +: ra_width] = doa_out_mux[0 +: ra_width]; if (ra_width >= 8) DOPA[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp]; end 1 : begin dbiterr_out_out = dbiterr_outreg; sbiterr_out_out = sbiterr_outreg; DOA[0 +: ra_width] = doa_outreg_mux[0 +: ra_width]; rdaddrecc_out_out = rdaddrecc_outreg; if (ra_width >= 8) DOPA[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp]; end default : begin $display("Attribute Syntax Error : The attribute DOA_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); $finish; end endcase end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) // ***** Output Registers **** Port B ***** always @(posedge CLKB or posedge GSR) begin if (DOB_REG == 1) begin if (GSR == 1'b1) begin dob_outreg <= INIT_B[0 +: rb_width]; if (rb_width >= 8) dopb_outreg <= INIT_B[rb_width +: rb_widthp]; end else if (GSR == 1'b0) begin if (rstreg_priority_b_int == 0) begin // Virtex5 behavior if (REGCEB == 1'b1) begin if (RSTREGB == 1'b1) begin dob_outreg <= SRVAL_B[0 +: rb_width]; if (rb_width >= 8) dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; end else if (RSTREGB == 1'b0) begin dob_outreg <= dob_out; if (rb_width >= 8) dopb_outreg <= dopb_out; end end // if (REGCEB == 1'b1) end // if (rstreg_priority_b_int == 1'b0) else begin if (RSTREGB == 1'b1) begin dob_outreg <= SRVAL_B[0 +: rb_width]; if (rb_width >= 8) dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; end else if (RSTREGB == 1'b0) begin if (REGCEB == 1'b1) begin dob_outreg <= dob_out; if (rb_width >= 8) dopb_outreg <= dopb_out; end end end // else: !if(rstreg_priority_b_int == 1'b0) end // if (GSR == 1'b0) end // if (DOB_REG == 1) end // always @ (posedge CLKB or posedge GSR) always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin case (DOB_REG) 0 : begin DOB[0 +: rb_width] = dob_out_mux[0 +: rb_width]; if (rb_width >= 8) DOPB[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp]; end 1 : begin DOB[0 +: rb_width] = dob_outreg_mux[0 +: rb_width]; if (rb_width >= 8) DOPB[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp]; end default : begin $display("Attribute Syntax Error : The attribute DOB_REG on RAMB18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); $finish; end endcase end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) endmodule // RB18_INTERNAL_VLOG `endcelldefine // end of RB18_INTERNAL_VLOG - Note: Not an user primitive /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2009 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 10.1 // \ \ Description : Xilinx Functional Simulation Library Component // / / VCC Connection // /___/ /\ Filename : VCC.v // \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 // \___\/\___\ // // Revision: // 03/23/04 - Initial version. // 05/23/07 - Changed timescale to 1 ps / 1 ps. // 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). // End Revision `timescale 1 ps / 1 ps `celldefine module VCC(P); `ifdef XIL_TIMING parameter LOC = "UNPLACED"; `endif output P; assign P = 1'b1; endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / 6-Bit Look-Up Table // /___/ /\ Filename : LUT6.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 03/23/04 - Initial version. // 02/04/05 - Replace primitive with function; Remove buf. // 01/07/06 - 222733 - Add LOC Parameter // 06/04/07 - Add wire declaration to internal signal. // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // 09/12/16 - ANSI ports, speed improvements // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `celldefine module LUT6 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter [63:0] INIT = 64'h0000000000000000 )( output O, input I0, input I1, input I2, input I3, input I4, input I5 ); // define constants localparam MODULE_NAME = "LUT6"; reg trig_attr = 1'b0; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "LUT6_dr.v" `else reg [63:0] INIT_REG = INIT; `endif // begin behavioral model reg O_out; assign O = O_out; function lut_mux8_f; input [7:0] d; input [2:0] s; begin if (((s[2]^s[1]^s[0]) === 1'b1) || ((s[2]^s[1]^s[0]) === 1'b0)) lut_mux8_f = d[s]; else if ( ~(|d) || &d) lut_mux8_f = d[0]; else if ((((s[1]^s[0]) === 1'b1) || ((s[1]^s[0]) === 1'b0)) && (d[{1'b0,s[1:0]}] === d[{1'b1,s[1:0]}])) lut_mux8_f = d[{1'b0,s[1:0]}]; else if ((((s[2]^s[0]) === 1'b1) || ((s[2]^s[0]) === 1'b0)) && (d[{s[2],1'b0,s[0]}] === d[{s[2],1'b1,s[0]}])) lut_mux8_f = d[{s[2],1'b0,s[0]}]; else if ((((s[2]^s[1]) === 1'b1) || ((s[2]^s[1]) === 1'b0)) && (d[{s[2],s[1],1'b0}] === d[{s[2],s[1],1'b1}])) lut_mux8_f = d[{s[2:1],1'b0}]; else if (((s[0] === 1'b1) || (s[0] === 1'b0)) && (d[{1'b0,1'b0,s[0]}] === d[{1'b0,1'b1,s[0]}]) && (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}] === d[{1'b1,1'b1,s[0]}])) lut_mux8_f = d[{1'b0,1'b0,s[0]}]; else if (((s[1] === 1'b1) || (s[1] === 1'b0)) && (d[{1'b0,s[1],1'b0}] === d[{1'b0,s[1],1'b1}]) && (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}] === d[{1'b1,s[1],1'b1}])) lut_mux8_f = d[{1'b0,s[1],1'b0}]; else if (((s[2] === 1'b1) || (s[2] === 1'b0)) && (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b0,1'b1}]) && (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}] === d[{s[2],1'b1,1'b1}])) lut_mux8_f = d[{s[2],1'b0,1'b0}]; else lut_mux8_f = 1'bx; end endfunction always @(I0 or I1 or I2 or I3 or I4 or I5) begin if ( (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b0 || (I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5) === 1'b1) O_out = INIT_REG[{I5, I4, I3, I2, I1, I0}]; else if ( ~(|INIT_REG) || &INIT_REG ) O_out = INIT_REG[0]; else O_out = lut_mux8_f ({lut_mux8_f (INIT_REG[63:56], {I2, I1, I0}), lut_mux8_f (INIT_REG[55:48], {I2, I1, I0}), lut_mux8_f (INIT_REG[47:40], {I2, I1, I0}), lut_mux8_f (INIT_REG[39:32], {I2, I1, I0}), lut_mux8_f (INIT_REG[31:24], {I2, I1, I0}), lut_mux8_f (INIT_REG[23:16], {I2, I1, I0}), lut_mux8_f ( INIT_REG[15:8], {I2, I1, I0}), lut_mux8_f ( INIT_REG[7:0], {I2, I1, I0})}, {I5, I4, I3}); end // end behavioral model `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); (I1 => O) = (0:0:0, 0:0:0); (I2 => O) = (0:0:0, 0:0:0); (I3 => O) = (0:0:0, 0:0:0); (I4 => O) = (0:0:0, 0:0:0); (I5 => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / 3-Bit Look-Up Table // /___/ /\ Filename : LUT3.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 03/23/04 - Initial version. // 03/11/05 - Add LOC Parameter // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // 09/12/16 - ANSI ports, speed improvements // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `celldefine module LUT3 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter [7:0] INIT = 8'h00 )( output O, input I0, input I1, input I2 ); // define constants localparam MODULE_NAME = "LUT3"; reg trig_attr = 1'b0; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "LUT3_dr.v" `else reg [7:0] INIT_REG = INIT; `endif x_lut3_mux8 (O, INIT_REG[7], INIT_REG[6], INIT_REG[5], INIT_REG[4], INIT_REG[3], INIT_REG[2], INIT_REG[1], INIT_REG[0], I2, I1, I0); `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); (I1 => O) = (0:0:0, 0:0:0); (I2 => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine primitive x_lut3_mux8 (o, d7, d6, d5, d4, d3, d2, d1, d0, s2, s1, s0); output o; input d7, d6, d5, d4, d3, d2, d1, d0; input s2, s1, s0; table // d7 d6 d5 d4 d3 d2 d1 d0 s2 s1 s0 : o; ? ? ? ? ? ? ? 1 0 0 0 : 1; ? ? ? ? ? ? ? 0 0 0 0 : 0; ? ? ? ? ? ? 1 ? 0 0 1 : 1; ? ? ? ? ? ? 0 ? 0 0 1 : 0; ? ? ? ? ? 1 ? ? 0 1 0 : 1; ? ? ? ? ? 0 ? ? 0 1 0 : 0; ? ? ? ? 1 ? ? ? 0 1 1 : 1; ? ? ? ? 0 ? ? ? 0 1 1 : 0; ? ? ? 1 ? ? ? ? 1 0 0 : 1; ? ? ? 0 ? ? ? ? 1 0 0 : 0; ? ? 1 ? ? ? ? ? 1 0 1 : 1; ? ? 0 ? ? ? ? ? 1 0 1 : 0; ? 1 ? ? ? ? ? ? 1 1 0 : 1; ? 0 ? ? ? ? ? ? 1 1 0 : 0; 1 ? ? ? ? ? ? ? 1 1 1 : 1; 0 ? ? ? ? ? ? ? 1 1 1 : 0; ? ? ? ? ? ? 0 0 0 0 x : 0; ? ? ? ? ? ? 1 1 0 0 x : 1; ? ? ? ? 0 0 ? ? 0 1 x : 0; ? ? ? ? 1 1 ? ? 0 1 x : 1; ? ? 0 0 ? ? ? ? 1 0 x : 0; ? ? 1 1 ? ? ? ? 1 0 x : 1; 0 0 ? ? ? ? ? ? 1 1 x : 0; 1 1 ? ? ? ? ? ? 1 1 x : 1; ? ? ? ? ? 0 ? 0 0 x 0 : 0; ? ? ? ? ? 1 ? 1 0 x 0 : 1; ? ? ? ? 0 ? 0 ? 0 x 1 : 0; ? ? ? ? 1 ? 1 ? 0 x 1 : 1; ? 0 ? 0 ? ? ? ? 1 x 0 : 0; ? 1 ? 1 ? ? ? ? 1 x 0 : 1; 0 ? 0 ? ? ? ? ? 1 x 1 : 0; 1 ? 1 ? ? ? ? ? 1 x 1 : 1; ? ? ? 0 ? ? ? 0 x 0 0 : 0; ? ? ? 1 ? ? ? 1 x 0 0 : 1; ? ? 0 ? ? ? 0 ? x 0 1 : 0; ? ? 1 ? ? ? 1 ? x 0 1 : 1; ? 0 ? ? ? 0 ? ? x 1 0 : 0; ? 1 ? ? ? 1 ? ? x 1 0 : 1; 0 ? ? ? 0 ? ? ? x 1 1 : 0; 1 ? ? ? 1 ? ? ? x 1 1 : 1; ? ? ? ? 0 0 0 0 0 x x : 0; ? ? ? ? 1 1 1 1 0 x x : 1; 0 0 0 0 ? ? ? ? 1 x x : 0; 1 1 1 1 ? ? ? ? 1 x x : 1; ? ? 0 0 ? ? 0 0 x 0 x : 0; ? ? 1 1 ? ? 1 1 x 0 x : 1; 0 0 ? ? 0 0 ? ? x 1 x : 0; 1 1 ? ? 1 1 ? ? x 1 x : 1; ? 0 ? 0 ? 0 ? 0 x x 0 : 0; ? 1 ? 1 ? 1 ? 1 x x 0 : 1; 0 ? 0 ? 0 ? 0 ? x x 1 : 0; 1 ? 1 ? 1 ? 1 ? x x 1 : 1; 0 0 0 0 0 0 0 0 x x x : 0; 1 1 1 1 1 1 1 1 x x x : 1; endtable endprimitive /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2004 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 10.1 // \ \ Description : Xilinx Functional Simulation Library Component // / / Input Buffer // /___/ /\ Filename : IBUF.v // \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 // \___\/\___\ // // Revision: // 03/23/04 - Initial version. // 05/23/07 - Changed timescale to 1 ps / 1 ps. // 07/16/08 - Added IBUF_LOW_PWR attribute. // 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. // 12/13/11 - Added `celldefine and `endcelldefine (CR 524859). // 10/22/14 - Added #1 to $finish (CR 808642). // End Revision `timescale 1 ps / 1 ps `celldefine module IBUF (O, I); parameter CAPACITANCE = "DONT_CARE"; parameter IBUF_DELAY_VALUE = "0"; parameter IBUF_LOW_PWR = "TRUE"; parameter IFD_DELAY_VALUE = "AUTO"; parameter IOSTANDARD = "DEFAULT"; `ifdef XIL_TIMING parameter LOC = " UNPLACED"; `endif output O; input I; //begin behavioral model buf B1 (O, I); initial begin case (CAPACITANCE) "LOW", "NORMAL", "DONT_CARE" : ; default : begin $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); #1 $finish; end endcase case (IBUF_DELAY_VALUE) "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; default : begin $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); #1 $finish; end endcase case (IBUF_LOW_PWR) "FALSE", "TRUE" : ; default : begin $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); #1 $finish; end endcase case (IFD_DELAY_VALUE) "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; default : begin $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); #1 $finish; end endcase end //end behavioral model `ifdef XIL_TIMING specify (I => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine /////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995/2016 Xilinx, Inc. // All Right Reserved. /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2017.1 // \ \ Description : Xilinx Unified Simulation Library Component // / / 2-Bit Look-Up Table // /___/ /\ Filename : LUT2.v // \ \ / \ // \___\/\___\ // /////////////////////////////////////////////////////////////////////////////// // Revision: // 03/23/04 - Initial version. // 03/11/05 - Add LOC Parameter // 12/13/11 - 524859 - Added `celldefine and `endcelldefine // 09/12/16 - ANSI ports, speed improvements // End Revision: /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `celldefine module LUT2 #( `ifdef XIL_TIMING parameter LOC = "UNPLACED", `endif parameter [3:0] INIT = 4'h0 )( output O, input I0, input I1 ); // define constants localparam MODULE_NAME = "LUT2"; reg trig_attr = 1'b0; // include dynamic registers - XILINX test only `ifdef XIL_DR `include "LUT2_dr.v" `else reg [3:0] INIT_REG = INIT; `endif x_lut2_mux4 (O, INIT_REG[3], INIT_REG[2], INIT_REG[1], INIT_REG[0], I1, I0); `ifdef XIL_TIMING specify (I0 => O) = (0:0:0, 0:0:0); (I1 => O) = (0:0:0, 0:0:0); specparam PATHPULSE$ = 0; endspecify `endif endmodule `endcelldefine primitive x_lut2_mux4 (o, d3, d2, d1, d0, s1, s0); output o; input d3, d2, d1, d0; input s1, s0; table // d3 d2 d1 d0 s1 s0 : o; ? ? ? 1 0 0 : 1; ? ? ? 0 0 0 : 0; ? ? 1 ? 0 1 : 1; ? ? 0 ? 0 1 : 0; ? 1 ? ? 1 0 : 1; ? 0 ? ? 1 0 : 0; 1 ? ? ? 1 1 : 1; 0 ? ? ? 1 1 : 0; ? ? 0 0 0 x : 0; ? ? 1 1 0 x : 1; 0 0 ? ? 1 x : 0; 1 1 ? ? 1 x : 1; ? 0 ? 0 x 0 : 0; ? 1 ? 1 x 0 : 1; 0 ? 0 ? x 1 : 0; 1 ? 1 ? x 1 : 1; 0 0 0 0 x x : 0; 1 1 1 1 x x : 1; endtable endprimitive `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; parameter GRES_WIDTH = 10000; parameter GRES_START = 10000; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; wire GRESTORE; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; reg GRESTORE_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; assign (strong1, weak0) GRESTORE = GRESTORE_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end initial begin GRESTORE_int = 1'b0; #(GRES_START); GRESTORE_int = 1'b1; #(GRES_WIDTH); GRESTORE_int = 1'b0; end endmodule `endif