Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
| Date         : Mon Jul 20 14:12:55 2026
| Host         : fedora running 64-bit unknown
| Command      : report_utilization -hierarchical -hierarchical_percentages
| Design       : ctu_can_fd_top
| Device       : xc7k70tfbv676-1
| Speed File   : -1
| Design State : Optimized
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Utilization Design Information

Table of Contents
-----------------
1. Utilization by Hierarchy

1. Utilization by Hierarchy
---------------------------

+----------------------------------------------------+-------------------------------------+-------------+-------------+----------+----------+-------------+----------+----------+------------+
|                      Instance                      |                Module               |  Total LUTs |  Logic LUTs |  LUTRAMs |   SRLs   |     FFs     |  RAMB36  |  RAMB18  | DSP Blocks |
+----------------------------------------------------+-------------------------------------+-------------+-------------+----------+----------+-------------+----------+----------+------------+
| ctu_can_fd_top                                     |                               (top) | 2279(5.56%) | 2279(5.56%) | 0(0.00%) | 0(0.00%) | 1044(1.27%) | 0(0.00%) | 5(1.85%) |   0(0.00%) |
|   (ctu_can_fd_top)                                 |                               (top) |    0(0.00%) |    0(0.00%) | 0(0.00%) | 0(0.00%) |    0(0.00%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_bm_top                                         |                              bm_top |  111(0.27%) |  111(0.27%) | 0(0.00%) | 0(0.00%) |   84(0.10%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_bm_ssp_generator                             |                    bm_ssp_generator |   61(0.15%) |   61(0.15%) | 0(0.00%) | 0(0.00%) |   33(0.04%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_btl_top                                        |                             btl_top |  146(0.36%) |  146(0.36%) | 0(0.00%) | 0(0.00%) |   74(0.09%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_btl_fsm                                      |                             btl_fsm |   56(0.14%) |   56(0.14%) | 0(0.00%) | 0(0.00%) |    3(0.01%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_im_top                                         |                              im_top |   73(0.18%) |   73(0.18%) | 0(0.00%) | 0(0.00%) |   37(0.05%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_mac_top                                        |                             mac_top |  788(1.92%) |  788(1.92%) | 0(0.00%) | 0(0.00%) |  327(0.40%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_mac_crc_top                                  |                         mac_crc_top |   63(0.15%) |   63(0.15%) | 0(0.00%) | 0(0.00%) |   53(0.06%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_mac_fc_top                                   |                          mac_fc_top |  143(0.35%) |  143(0.35%) | 0(0.00%) | 0(0.00%) |   58(0.07%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (i_mac_fc_err_counters)                      |                 mac_fc_err_counters |  127(0.31%) |  127(0.31%) | 0(0.00%) | 0(0.00%) |   54(0.07%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_mac_pc_top                                   |                          mac_pc_top |  524(1.28%) |  524(1.28%) | 0(0.00%) | 0(0.00%) |  190(0.23%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|       i_mac_pc_fsm                                 |                          mac_pc_fsm |  436(1.06%) |  436(1.06%) | 0(0.00%) | 0(0.00%) |   35(0.04%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|       i_mac_pc_rx_shift_reg                        |                 mac_pc_rx_shift_reg |   26(0.06%) |   26(0.06%) | 0(0.00%) | 0(0.00%) |   75(0.09%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_mr_top                                         |                              mr_top |  595(1.45%) |  595(1.45%) | 0(0.00%) | 0(0.00%) |  274(0.33%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_control_registers_reg_map                    |           control_registers_reg_map |  233(0.57%) |  233(0.57%) | 0(0.00%) | 0(0.00%) |  185(0.23%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     g_test_registers_true.i_test_registers_reg_map |              test_registers_reg_map |  326(0.80%) |  326(0.80%) | 0(0.00%) | 0(0.00%) |   85(0.10%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|       i_tst_dest_tst_mtgt_reg                      | memory_reg_rw_lock__parameterized33 |  136(0.33%) |  136(0.33%) | 0(0.00%) | 0(0.00%) |    4(0.01%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_rxb_top                                        |                             rxb_top |  237(0.58%) |  237(0.58%) | 0(0.00%) | 0(0.00%) |  122(0.15%) | 0(0.00%) | 1(0.37%) |   0(0.00%) |
|     (i_rxb_top)                                    |                             rxb_top |    7(0.02%) |    7(0.02%) | 0(0.00%) | 0(0.00%) |   77(0.09%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_rxb_fsm                                      |                             rxb_fsm |  121(0.30%) |  121(0.30%) | 0(0.00%) | 0(0.00%) |   12(0.01%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_rxb_pointers                                 |                        rxb_pointers |   62(0.15%) |   62(0.15%) | 0(0.00%) | 0(0.00%) |   32(0.04%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|   i_txarb_top                                      |                           txarb_top |  180(0.44%) |  180(0.44%) | 0(0.00%) | 0(0.00%) |  107(0.13%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     (i_txarb_top)                                  |                           txarb_top |   60(0.15%) |   60(0.15%) | 0(0.00%) | 0(0.00%) |  103(0.13%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
|     i_txarb_fsm                                    |                           txarb_fsm |  120(0.29%) |  120(0.29%) | 0(0.00%) | 0(0.00%) |    4(0.01%) | 0(0.00%) | 0(0.00%) |   0(0.00%) |
+----------------------------------------------------+-------------------------------------+-------------+-------------+----------+----------+-------------+----------+----------+------------+


