File: /__w/CTU-CAN-FD/CTU-CAN-FD/test/main_tb/agents/feature_test_agent/feature_test_agent.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- Feature test agent. Executes feature tests.
71: --
72: -- Feature test agent is started by test controller agent, when test_type
73: -- is configured to "feature". Feature test agent resets DUT, configures it,
74: -- enables it, runs test sequence.
75: --
76: --------------------------------------------------------------------------------
77: -- Revision History:
78: -- 11.3.2021 Created file
79: --------------------------------------------------------------------------------
80:
81: Library ctu_can_fd_tb;
82: context ctu_can_fd_tb.ieee_context;
83: context ctu_can_fd_tb.tb_common_context;
84: context ctu_can_fd_tb.rtl_context;
85: context ctu_can_fd_tb.tb_agents_context;
86:
87: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
88:
89: entity feature_test_agent is
90: generic(
91: -- Test details
92: test_name : string;
93: test_type : string;
94:
95: -- DUT config
96: cfg_sys_clk_period : string;
97:
98: -- Bit timing cofnig used in; compliance tests
99: cfg_brp : natural;
100: cfg_prop : natural;
101: cfg_ph_1 : natural;
102: cfg_ph_2 : natural;
103: cfg_sjw : natural;
104: cfg_brp_fd : natural;
105: cfg_prop_fd : natural;
106: cfg_ph_1_fd : natural;
107: cfg_ph_2_fd : natural;
108: cfg_sjw_fd : natural;
109:
110: -- Secondary sample point config
111: cfg_ssp_src : natural;
112: cfg_ssp_offset : natural
113: );
114: port(
115: -----------------------------------------------------------------------
116: -- Test node connections
117: -----------------------------------------------------------------------
118: clk_sys : in std_logic;
119: rst_n : in std_logic;
120:
121: write_data : in std_logic_vector(31 DOWNTO 0);
122: read_data : out std_logic_vector(31 DOWNTO 0);
123: adress : in std_logic_vector(15 DOWNTO 0);
124: scs : in std_logic;
125: srd : in std_logic;
126: swr : in std_logic;
127: sbe : in std_logic_vector(3 DOWNTO 0);
128:
129: -- CAN bus from/to DUT
130: dut_can_tx : in std_logic;
131: dut_can_rx : out std_logic;
132:
133: -- Test Nodes test probe output
134: test_node_test_probe : out t_ctu_can_fd_test_probe;
135: test_node_scan_enable : in std_logic
136: );
137: end entity;
138:
139:
140: architecture tb of feature_test_agent is
141:
142: signal bus_level : std_logic;
143:
144: -- Test node signals
145: signal test_node_can_tx : std_logic;
146: signal test_node_can_rx : std_logic;
147:
148: -- Signals with 1 ps delay (close to delta celay only)
149: signal dut_can_tx_delta_delay : std_logic;
150: signal test_node_can_tx_delta_delay : std_logic;
151:
152: -- Delayed CAN bus signals
153: signal dut_can_tx_delayed : std_logic := '1';
154: signal test_node_can_tx_delayed : std_logic := '1';
155:
156: -- Forcing bus level value (ANDed bus level)
157: signal force_bus_level_i : boolean := false;
158: signal force_bus_level_value : std_logic := '0';
159:
160: -- Inverting bus value compared
161: signal flip_bus_level_i : boolean := false;
162:
163: -- Forcing CAN RX of only single node
164: signal force_can_rx_dut : boolean := false;
165: signal force_can_rx_test_node : boolean := false;
166: signal force_can_rx_value : std_logic := '0';
167:
168: -- Transceiver delays (on can_tx signal)
169: signal can_tx_delay_dut : time := 1 ns;
170: signal can_tx_delay_test_node : time := 1 ns;
171:
172: -- ANDed TX (expected bus level upon regular transmission)
173: signal anded_tx : std_logic;
174:
175: begin
176:
177: ---------------------------------------------------------------------------
178: -- Test node
179: ---------------------------------------------------------------------------
180: i_test_node : entity ctu_can_fd_rtl.ctu_can_fd_top
181: generic map(
182: -- Keep config hard-coded, it is enough that DUT is configurable!
183: -- Everything is tested at the "DUT" instance!
184: G_RX_BUF_SIZE => 256,
185: G_TXT_BUF_COUNT => 4,
186: G_FILT_A_EN => false,
187: G_FILT_B_EN => false,
188: G_FILT_C_EN => false,
189: G_FILT_RANGE_EN => false,
190: G_TRAFFIC_CTRS_EN => true,
191: G_PARITY_EN => false,
192: G_TECHNOLOGY => C_TECH_ASIC
193: )
194: port map(
195: -- Clock and Asynchronous reset
196: clk_sys => clk_sys,
197: rst_n => rst_n,
198:
199: -- DFT support
200: scan_mode => test_node_scan_enable,
201:
202: -- Memory interface
203: data_in => write_data,
204: data_out => read_data,
205: adress => adress,
206: scs => scs,
207: srd => srd,
208: swr => swr,
209: sbe => sbe,
210:
211: -- Interrupt Interface - not needed for test node
212: int => open,
213:
214: -- CAN Bus Interface
215: can_tx => test_node_can_tx,
216: can_rx => test_node_can_rx,
217:
218: -- Test probe, timestamp, not needed for test node!
219: test_probe => test_node_test_probe,
220: timestamp => (OTHERS => '1')
221: );
222:
223: ---------------------------------------------------------------------------
224: -- Comunication receiver process
225: ---------------------------------------------------------------------------
226: p_receiver : process
227: variable cmd : integer;
228: variable reply_code : integer;
229: variable tmp : integer;
230: variable tmp_logic : std_logic;
231: begin
232: receive_start(default_channel, C_FEATURE_TEST_AGENT_ID);
233:
234: -- Command is sent as message type
235: cmd := com_channel_data.get_msg_code;
236: reply_code := C_REPLY_CODE_OK;
237:
238: case cmd is
239: when FEATURE_TEST_AGNT_FORCE_BUS =>
240: force_bus_level_value <= com_channel_data.get_param;
241: force_bus_level_i <= true;
242:
243: when FEATURE_TEST_AGNT_RELEASE_BUS =>
244: force_bus_level_i <= false;
245: flip_bus_level_i <= false;
246:
247: when FEATURE_TEST_AGNT_FORCE_CAN_RX =>
248: tmp := com_channel_data.get_param;
249: force_can_rx_value <= com_channel_data.get_param;
250: if (tmp = 0) then
251: force_can_rx_dut <= true;
252: else
253: force_can_rx_test_node <= true;
254: end if;
255:
256: when FEATURE_TEST_AGNT_RELEASE_CAN_RX =>
257: force_can_rx_dut <= false;
258: force_can_rx_test_node <= false;
259:
260: when FEATURE_TEST_AGNT_SET_TRV_DELAY =>
261: tmp := com_channel_data.get_param;
262: if (tmp = 0) then
263: can_tx_delay_dut <= com_channel_data.get_param;
264: else
265: can_tx_delay_test_node <= com_channel_data.get_param;
266: end if;
267:
268: when FEATURE_TEST_AGNT_CHECK_BUS_LEVEL =>
269: tmp_logic := com_channel_data.get_param;
270: check_m(tmp_logic = bus_level, FEATURE_TEST_AGENT_TAG &
271: "Bus level value shoul be:" & std_logic'image(tmp_logic));
272:
273: when FEATURE_TEST_AGNT_CHECK_CAN_TX =>
274: tmp := com_channel_data.get_param;
275: tmp_logic := com_channel_data.get_param;
276: if (tmp = 0) then
277: check_m(tmp_logic = dut_can_tx, "DUT CAN TX");
278: else
279: check_m(tmp_logic = test_node_can_tx, "Test node CAN TX");
280: end if;
281:
282: when FEATURE_TEST_AGNT_GET_CAN_TX =>
283: tmp := com_channel_data.get_param;
284: if (tmp = 0) then
285: com_channel_data.set_param(dut_can_tx);
286: else
287: com_channel_data.set_param(test_node_can_tx);
288: end if;
289:
290: when FEATURE_TEST_AGNT_GET_CAN_RX =>
291: tmp := com_channel_data.get_param;
292: if (tmp = 0) then
293: com_channel_data.set_param(dut_can_rx);
294: else
295: com_channel_data.set_param(test_node_can_rx);
296: end if;
297:
298: when FEATURE_TEST_AGNT_FLIP_BUS =>
299: flip_bus_level_i <= true;
300:
301: when others =>
302: info_m("Invalid message type: " & integer'image(cmd));
303: reply_code := C_REPLY_CODE_ERR;
304:
305: end case;
306: receive_finish(default_channel, reply_code);
307: end process;
308:
309: ---------------------------------------------------------------------------
310: -- Signal delaying
311: ---------------------------------------------------------------------------
312: i_tx_delay_dut : entity ctu_can_fd_tb.signal_delayer
313: generic map (
314: NSAMPLES => 32
315: )
316: port map (
317: input => dut_can_tx_delta_delay,
318: delay => can_tx_delay_dut,
319: delayed => dut_can_tx_delayed
320: );
321:
322: i_tx_delay_test_node : entity ctu_can_fd_tb.signal_delayer
323: generic map (
324: NSAMPLES => 32
325: )
326: port map (
327: input => test_node_can_tx_delta_delay,
328: delay => can_tx_delay_test_node,
329: delayed => test_node_can_tx_delayed
330: );
331:
332: ---------------------------------------------------------------------------
333: -- On RTL, can_tx is 'U' at time zero, and it gets defined value when
334: -- rst_n is asserted. Thus 'U' -> 1 event occurs in non-zero time.
335: -- On Xilinx gate level sims, having rst_n = 'U' first few nanoseconds of
336: -- simulation does cause output of flop in reset synchronizer to be '0',
337: -- not 'U'. Thus synchronized reset is '0' from time 0, and there is no
338: -- event on it when rst_n input gets asserted non-'U' value! This causes
339: -- can_tx to be set to '1' from time 0 of simulation. As consequence of
340: -- this, signal delayer will ignore the first event on can_tx in time 0,
341: -- and will keep its output at 0!
342: ---------------------------------------------------------------------------
343: dut_can_tx_delta_delay <= dut_can_tx after 1 ps;
344: test_node_can_tx_delta_delay <= test_node_can_tx after 1 ps;
345:
346: ---------------------------------------------------------------------------
347: -- Bus level and RX signal of each node
348: ---------------------------------------------------------------------------
349: anded_tx <= dut_can_tx_delayed and test_node_can_tx_delayed;
350:
351: bus_level <= force_bus_level_value when force_bus_level_i else
352: not (anded_tx) when flip_bus_level_i else
353: anded_tx;
354:
355: dut_can_rx <= force_can_rx_value when force_can_rx_dut else
356: bus_level;
357:
358: test_node_can_rx <= force_can_rx_value when force_can_rx_test_node else
359: bus_level;
360:
361: ---------------------------------------------------------------------------
362: ---------------------------------------------------------------------------
363: -- Test control process
364: --
365: -- Waits on start request from Test controller agent and runs a test.
366: ---------------------------------------------------------------------------
367: ---------------------------------------------------------------------------
368: p_test : process
369: variable bus_timing : t_ctu_bit_time_cfg :=(
370: tq_nbt => cfg_brp,
371: tq_dbt => cfg_brp_fd,
372: prop_nbt => cfg_prop,
373: ph1_nbt => cfg_ph_1,
374: ph2_nbt => cfg_ph_2,
375: sjw_nbt => cfg_sjw,
376: prop_dbt => cfg_prop_fd,
377: ph1_dbt => cfg_ph_1_fd,
378: ph2_dbt => cfg_ph_2_fd,
379: sjw_dbt => cfg_sjw_fd
380: );
381: begin
382: wait until feature_start = '1';
383:
384: -- Pre-set test to be "passed", any error will make it fail
385: ctu_vip_test_result.set_result(true);
386:
387: -- Initialize TXT Buffer memories
388: info_m("***************************************************************");
389: info_m("Clearing TXT Buffer memories!");
390: info_m("***************************************************************");
391: info_m("DUT node:");
392: ctu_init_txtb_mems(DUT_NODE, default_channel);
393: info_m("Test node:");
394: ctu_init_txtb_mems(TEST_NODE, default_channel);
395:
396: -- Configure bit timing
397: ctu_set_bit_time_cfg(bus_timing, DUT_NODE, default_channel);
398: ctu_set_bit_time_cfg(bus_timing, TEST_NODE, default_channel);
399:
400: -- Configure secondary sample point
401: ctu_set_ssp(t_ctu_ssp_kind'val(cfg_ssp_src),
402: std_logic_vector(to_unsigned(cfg_ssp_offset, 8)),
403: DUT_NODE, default_channel);
404:
405: ctu_set_ssp(t_ctu_ssp_kind'val(cfg_ssp_src),
406: std_logic_vector(to_unsigned(cfg_ssp_offset, 8)),
407: TEST_NODE, default_channel);
408:
409: -- Set default retransmitt limit to 0 (Failed frames are not retransmited)
410: ctu_set_retr_limit(true, 0, DUT_NODE, default_channel);
411: ctu_set_retr_limit(true, 0, TEST_NODE, default_channel);
412:
413: -- Enable CAN controllers
414: ctu_turn(true, DUT_NODE, default_channel);
415: ctu_turn(true, TEST_NODE, default_channel);
416: info_m("Controllers are ON");
417:
418: -- Wait till integration is over in both nodes
419: ctu_wait_err_active(DUT_NODE, default_channel);
420: ctu_wait_err_active(TEST_NODE, default_channel);
421: info_m("Bus integration finished");
422:
423: -- Execute feature test
424: exec_feature_test(test_name, default_channel);
425:
426: -- Signal test is done.
427: feature_result <= ctu_vip_test_result.get_result;
428: wait for 0 ns;
429: feature_done <= '1';
430: wait until feature_start = '0';
431: feature_done <= '0';
432: wait for 0 ns;
433:
434: end process;
435:
436: end architecture;